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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/dsa/ocelot.h>
8#include <linux/if_bridge.h>
9#include <linux/iopoll.h>
10#include <linux/phy/phy.h>
11#include <net/pkt_sched.h>
12#include <soc/mscc/ocelot_hsio.h>
13#include <soc/mscc/ocelot_vcap.h>
14#include "ocelot.h"
15#include "ocelot_vcap.h"
16
17#define TABLE_UPDATE_SLEEP_US 10
18#define TABLE_UPDATE_TIMEOUT_US 100000
19#define MEM_INIT_SLEEP_US 1000
20#define MEM_INIT_TIMEOUT_US 100000
21
22#define OCELOT_RSV_VLAN_RANGE_START 4000
23
24struct ocelot_mact_entry {
25 u8 mac[ETH_ALEN];
26 u16 vid;
27 enum macaccess_entry_type type;
28};
29
30/* Caller must hold &ocelot->mact_lock */
31static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
32{
33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
34}
35
36/* Caller must hold &ocelot->mact_lock */
37static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
38{
39 u32 val;
40
41 return readx_poll_timeout(ocelot_mact_read_macaccess,
42 ocelot, val,
43 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
44 MACACCESS_CMD_IDLE,
45 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
46}
47
48/* Caller must hold &ocelot->mact_lock */
49static void ocelot_mact_select(struct ocelot *ocelot,
50 const unsigned char mac[ETH_ALEN],
51 unsigned int vid)
52{
53 u32 macl = 0, mach = 0;
54
55 /* Set the MAC address to handle and the vlan associated in a format
56 * understood by the hardware.
57 */
58 mach |= vid << 16;
59 mach |= mac[0] << 8;
60 mach |= mac[1] << 0;
61 macl |= mac[2] << 24;
62 macl |= mac[3] << 16;
63 macl |= mac[4] << 8;
64 macl |= mac[5] << 0;
65
66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
68
69}
70
71static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
72 const unsigned char mac[ETH_ALEN],
73 unsigned int vid, enum macaccess_entry_type type)
74{
75 u32 cmd = ANA_TABLES_MACACCESS_VALID |
76 ANA_TABLES_MACACCESS_DEST_IDX(port) |
77 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
78 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
79 unsigned int mc_ports;
80 int err;
81
82 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
83 if (type == ENTRYTYPE_MACv4)
84 mc_ports = (mac[1] << 8) | mac[2];
85 else if (type == ENTRYTYPE_MACv6)
86 mc_ports = (mac[0] << 8) | mac[1];
87 else
88 mc_ports = 0;
89
90 if (mc_ports & BIT(ocelot->num_phys_ports))
91 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
92
93 ocelot_mact_select(ocelot, mac, vid);
94
95 /* Issue a write command */
96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
97
98 err = ocelot_mact_wait_for_completion(ocelot);
99
100 return err;
101}
102
103int ocelot_mact_learn(struct ocelot *ocelot, int port,
104 const unsigned char mac[ETH_ALEN],
105 unsigned int vid, enum macaccess_entry_type type)
106{
107 int ret;
108
109 mutex_lock(&ocelot->mact_lock);
110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
111 mutex_unlock(&ocelot->mact_lock);
112
113 return ret;
114}
115EXPORT_SYMBOL(ocelot_mact_learn);
116
117int ocelot_mact_forget(struct ocelot *ocelot,
118 const unsigned char mac[ETH_ALEN], unsigned int vid)
119{
120 int err;
121
122 mutex_lock(&ocelot->mact_lock);
123
124 ocelot_mact_select(ocelot, mac, vid);
125
126 /* Issue a forget command */
127 ocelot_write(ocelot,
128 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
129 ANA_TABLES_MACACCESS);
130
131 err = ocelot_mact_wait_for_completion(ocelot);
132
133 mutex_unlock(&ocelot->mact_lock);
134
135 return err;
136}
137EXPORT_SYMBOL(ocelot_mact_forget);
138
139int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
140 const unsigned char mac[ETH_ALEN],
141 unsigned int vid, enum macaccess_entry_type *type)
142{
143 int val;
144
145 mutex_lock(&ocelot->mact_lock);
146
147 ocelot_mact_select(ocelot, mac, vid);
148
149 /* Issue a read command with MACACCESS_VALID=1. */
150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
151 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
152 ANA_TABLES_MACACCESS);
153
154 if (ocelot_mact_wait_for_completion(ocelot)) {
155 mutex_unlock(&ocelot->mact_lock);
156 return -ETIMEDOUT;
157 }
158
159 /* Read back the entry flags */
160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
161
162 mutex_unlock(&ocelot->mact_lock);
163
164 if (!(val & ANA_TABLES_MACACCESS_VALID))
165 return -ENOENT;
166
167 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
168 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
169
170 return 0;
171}
172EXPORT_SYMBOL(ocelot_mact_lookup);
173
174int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
175 const unsigned char mac[ETH_ALEN],
176 unsigned int vid,
177 enum macaccess_entry_type type,
178 int sfid, int ssid)
179{
180 int ret;
181
182 mutex_lock(&ocelot->mact_lock);
183
184 ocelot_write(ocelot,
185 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
186 ANA_TABLES_STREAMDATA_SFID(sfid) |
187 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
188 ANA_TABLES_STREAMDATA_SSID(ssid),
189 ANA_TABLES_STREAMDATA);
190
191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
192
193 mutex_unlock(&ocelot->mact_lock);
194
195 return ret;
196}
197EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
198
199static void ocelot_mact_init(struct ocelot *ocelot)
200{
201 /* Configure the learning mode entries attributes:
202 * - Do not copy the frame to the CPU extraction queues.
203 * - Use the vlan and mac_cpoy for dmac lookup.
204 */
205 ocelot_rmw(ocelot, 0,
206 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
207 | ANA_AGENCTRL_LEARN_FWD_KILL
208 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
209 ANA_AGENCTRL);
210
211 /* Clear the MAC table. We are not concurrent with anyone, so
212 * holding &ocelot->mact_lock is pointless.
213 */
214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
215}
216
217void ocelot_pll5_init(struct ocelot *ocelot)
218{
219 /* Configure PLL5. This will need a proper CCF driver
220 * The values are coming from the VTSS API for Ocelot
221 */
222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
223 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
224 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
226 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
227 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
228 HSIO_PLL5G_CFG0_ENA_BIAS |
229 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
230 HSIO_PLL5G_CFG0_ENA_CP1 |
231 HSIO_PLL5G_CFG0_SELCPI(2) |
232 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
233 HSIO_PLL5G_CFG0_SELBGV820(4) |
234 HSIO_PLL5G_CFG0_DIV4 |
235 HSIO_PLL5G_CFG0_ENA_CLKTREE |
236 HSIO_PLL5G_CFG0_ENA_LANE);
237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
238 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
239 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
240 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
241 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
242 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
243 HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
244}
245EXPORT_SYMBOL(ocelot_pll5_init);
246
247static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
248{
249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
250 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
251 ANA_PORT_VCAP_S2_CFG, port);
252
253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
254 ANA_PORT_VCAP_CFG, port);
255
256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
257 REW_PORT_CFG_ES0_EN,
258 REW_PORT_CFG, port);
259}
260
261static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
262 struct netlink_ext_ack *extack)
263{
264 struct net_device *bridge = NULL;
265 int port;
266
267 for (port = 0; port < ocelot->num_phys_ports; port++) {
268 struct ocelot_port *ocelot_port = ocelot->ports[port];
269
270 if (!ocelot_port || !ocelot_port->bridge ||
271 !br_vlan_enabled(ocelot_port->bridge))
272 continue;
273
274 if (!bridge) {
275 bridge = ocelot_port->bridge;
276 continue;
277 }
278
279 if (bridge == ocelot_port->bridge)
280 continue;
281
282 NL_SET_ERR_MSG_MOD(extack,
283 "Only one VLAN-aware bridge is supported");
284 return -EBUSY;
285 }
286
287 return 0;
288}
289
290static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
291{
292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
293}
294
295static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
296{
297 u32 val;
298
299 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
300 ocelot,
301 val,
302 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
303 ANA_TABLES_VLANACCESS_CMD_IDLE,
304 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
305}
306
307static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
308{
309 /* Select the VID to configure */
310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
311 ANA_TABLES_VLANTIDX);
312 /* Set the vlan port members mask and issue a write command */
313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
314 ANA_TABLES_VLANACCESS_CMD_WRITE,
315 ANA_TABLES_VLANACCESS);
316
317 return ocelot_vlant_wait_for_completion(ocelot);
318}
319
320static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
321{
322 struct ocelot_bridge_vlan *vlan;
323 int num_untagged = 0;
324
325 list_for_each_entry(vlan, &ocelot->vlans, list) {
326 if (!(vlan->portmask & BIT(port)))
327 continue;
328
329 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(),
330 * because this is never active in hardware at the same time as
331 * the bridge VLANs, which only matter in VLAN-aware mode.
332 */
333 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START)
334 continue;
335
336 if (vlan->untagged & BIT(port))
337 num_untagged++;
338 }
339
340 return num_untagged;
341}
342
343static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
344{
345 struct ocelot_bridge_vlan *vlan;
346 int num_tagged = 0;
347
348 list_for_each_entry(vlan, &ocelot->vlans, list) {
349 if (!(vlan->portmask & BIT(port)))
350 continue;
351
352 if (!(vlan->untagged & BIT(port)))
353 num_tagged++;
354 }
355
356 return num_tagged;
357}
358
359/* We use native VLAN when we have to mix egress-tagged VLANs with exactly
360 * _one_ egress-untagged VLAN (_the_ native VLAN)
361 */
362static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
363{
364 return ocelot_port_num_tagged_vlans(ocelot, port) &&
365 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
366}
367
368static struct ocelot_bridge_vlan *
369ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
370{
371 struct ocelot_bridge_vlan *vlan;
372
373 list_for_each_entry(vlan, &ocelot->vlans, list)
374 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
375 return vlan;
376
377 return NULL;
378}
379
380/* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
381 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
382 * state of the port.
383 */
384static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
385{
386 struct ocelot_port *ocelot_port = ocelot->ports[port];
387 enum ocelot_port_tag_config tag_cfg;
388 bool uses_native_vlan = false;
389
390 if (ocelot_port->vlan_aware) {
391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
392
393 if (uses_native_vlan)
394 tag_cfg = OCELOT_PORT_TAG_NATIVE;
395 else if (ocelot_port_num_untagged_vlans(ocelot, port))
396 tag_cfg = OCELOT_PORT_TAG_DISABLED;
397 else
398 tag_cfg = OCELOT_PORT_TAG_TRUNK;
399 } else {
400 tag_cfg = OCELOT_PORT_TAG_DISABLED;
401 }
402
403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
404 REW_TAG_CFG_TAG_CFG_M,
405 REW_TAG_CFG, port);
406
407 if (uses_native_vlan) {
408 struct ocelot_bridge_vlan *native_vlan;
409
410 /* Not having a native VLAN is impossible, because
411 * ocelot_port_num_untagged_vlans has returned 1.
412 * So there is no use in checking for NULL here.
413 */
414 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
415
416 ocelot_rmw_gix(ocelot,
417 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
418 REW_PORT_VLAN_CFG_PORT_VID_M,
419 REW_PORT_VLAN_CFG, port);
420 }
421}
422
423int ocelot_bridge_num_find(struct ocelot *ocelot,
424 const struct net_device *bridge)
425{
426 int port;
427
428 for (port = 0; port < ocelot->num_phys_ports; port++) {
429 struct ocelot_port *ocelot_port = ocelot->ports[port];
430
431 if (ocelot_port && ocelot_port->bridge == bridge)
432 return ocelot_port->bridge_num;
433 }
434
435 return -1;
436}
437EXPORT_SYMBOL_GPL(ocelot_bridge_num_find);
438
439static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
440 const struct net_device *bridge)
441{
442 int bridge_num;
443
444 /* Standalone ports use VID 0 */
445 if (!bridge)
446 return 0;
447
448 bridge_num = ocelot_bridge_num_find(ocelot, bridge);
449 if (WARN_ON(bridge_num < 0))
450 return 0;
451
452 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */
453 return VLAN_N_VID - bridge_num - 1;
454}
455
456/**
457 * ocelot_update_vlan_reclassify_rule() - Make switch aware only to bridge VLAN TPID
458 *
459 * @ocelot: Switch private data structure
460 * @port: Index of ingress port
461 *
462 * IEEE 802.1Q-2018 clauses "5.5 C-VLAN component conformance" and "5.6 S-VLAN
463 * component conformance" suggest that a C-VLAN component should only recognize
464 * and filter on C-Tags, and an S-VLAN component should only recognize and
465 * process based on C-Tags.
466 *
467 * In Linux, as per commit 1a0b20b25732 ("Merge branch 'bridge-next'"), C-VLAN
468 * components are largely represented by a bridge with vlan_protocol 802.1Q,
469 * and S-VLAN components by a bridge with vlan_protocol 802.1ad.
470 *
471 * Currently the driver only offloads vlan_protocol 802.1Q, but the hardware
472 * design is non-conformant, because the switch assigns each frame to a VLAN
473 * based on an entirely different question, as detailed in figure "Basic VLAN
474 * Classification Flow" from its manual and reproduced below.
475 *
476 * Set TAG_TYPE, PCP, DEI, VID to port-default values in VLAN_CFG register
477 * if VLAN_AWARE_ENA[port] and frame has outer tag then:
478 * if VLAN_INNER_TAG_ENA[port] and frame has inner tag then:
479 * TAG_TYPE = (Frame.InnerTPID <> 0x8100)
480 * Set PCP, DEI, VID to values from inner VLAN header
481 * else:
482 * TAG_TYPE = (Frame.OuterTPID <> 0x8100)
483 * Set PCP, DEI, VID to values from outer VLAN header
484 * if VID == 0 then:
485 * VID = VLAN_CFG.VLAN_VID
486 *
487 * Summarized, the switch will recognize both 802.1Q and 802.1ad TPIDs as VLAN
488 * "with equal rights", and just set the TAG_TYPE bit to 0 (if 802.1Q) or to 1
489 * (if 802.1ad). It will classify based on whichever of the tags is "outer", no
490 * matter what TPID that may have (or "inner", if VLAN_INNER_TAG_ENA[port]).
491 *
492 * In the VLAN Table, the TAG_TYPE information is not accessible - just the
493 * classified VID is - so it is as if each VLAN Table entry is for 2 VLANs:
494 * C-VLAN X, and S-VLAN X.
495 *
496 * Whereas the Linux bridge behavior is to only filter on frames with a TPID
497 * equal to the vlan_protocol, and treat everything else as VLAN-untagged.
498 *
499 * Consider an ingress packet tagged with 802.1ad VID=3 and 802.1Q VID=5,
500 * received on a bridge vlan_filtering=1 vlan_protocol=802.1Q port. This frame
501 * should be treated as 802.1Q-untagged, and classified to the PVID of that
502 * bridge port. Not to VID=3, and not to VID=5.
503 *
504 * The VCAP IS1 TCAM has everything we need to overwrite the choices made in
505 * the basic VLAN classification pipeline: it can match on TAG_TYPE in the key,
506 * and it can modify the classified VID in the action. Thus, for each port
507 * under a vlan_filtering bridge, we can insert a rule in VCAP IS1 lookup 0 to
508 * match on 802.1ad tagged frames and modify their classified VID to the 802.1Q
509 * PVID of the port. This effectively makes it appear to the outside world as
510 * if those packets were processed as VLAN-untagged.
511 *
512 * The rule needs to be updated each time the bridge PVID changes, and needs
513 * to be deleted if the bridge PVID is deleted, or if the port becomes
514 * VLAN-unaware.
515 */
516static int ocelot_update_vlan_reclassify_rule(struct ocelot *ocelot, int port)
517{
518 unsigned long cookie = OCELOT_VCAP_IS1_VLAN_RECLASSIFY(ocelot, port);
519 struct ocelot_vcap_block *block_vcap_is1 = &ocelot->block[VCAP_IS1];
520 struct ocelot_port *ocelot_port = ocelot->ports[port];
521 const struct ocelot_bridge_vlan *pvid_vlan;
522 struct ocelot_vcap_filter *filter;
523 int err, val, pcp, dei;
524 bool vid_replace_ena;
525 u16 vid;
526
527 pvid_vlan = ocelot_port->pvid_vlan;
528 vid_replace_ena = ocelot_port->vlan_aware && pvid_vlan;
529
530 filter = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, cookie,
531 false);
532 if (!vid_replace_ena) {
533 /* If the reclassification filter doesn't need to exist, delete
534 * it if it was previously installed, and exit doing nothing
535 * otherwise.
536 */
537 if (filter)
538 return ocelot_vcap_filter_del(ocelot, filter);
539
540 return 0;
541 }
542
543 /* The reclassification rule must apply. See if it already exists
544 * or if it must be created.
545 */
546
547 /* Treating as VLAN-untagged means using as classified VID equal to
548 * the bridge PVID, and PCP/DEI set to the port default QoS values.
549 */
550 vid = pvid_vlan->vid;
551 val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
552 pcp = ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
553 dei = !!(val & ANA_PORT_QOS_CFG_DP_DEFAULT_VAL);
554
555 if (filter) {
556 bool changed = false;
557
558 /* Filter exists, just update it */
559 if (filter->action.vid != vid) {
560 filter->action.vid = vid;
561 changed = true;
562 }
563 if (filter->action.pcp != pcp) {
564 filter->action.pcp = pcp;
565 changed = true;
566 }
567 if (filter->action.dei != dei) {
568 filter->action.dei = dei;
569 changed = true;
570 }
571
572 if (!changed)
573 return 0;
574
575 return ocelot_vcap_filter_replace(ocelot, filter);
576 }
577
578 /* Filter doesn't exist, create it */
579 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
580 if (!filter)
581 return -ENOMEM;
582
583 filter->key_type = OCELOT_VCAP_KEY_ANY;
584 filter->ingress_port_mask = BIT(port);
585 filter->vlan.tpid = OCELOT_VCAP_BIT_1;
586 filter->prio = 1;
587 filter->id.cookie = cookie;
588 filter->id.tc_offload = false;
589 filter->block_id = VCAP_IS1;
590 filter->type = OCELOT_VCAP_FILTER_OFFLOAD;
591 filter->lookup = 0;
592 filter->action.vid_replace_ena = true;
593 filter->action.pcp_dei_ena = true;
594 filter->action.vid = vid;
595 filter->action.pcp = pcp;
596 filter->action.dei = dei;
597
598 err = ocelot_vcap_filter_add(ocelot, filter, NULL);
599 if (err)
600 kfree(filter);
601
602 return err;
603}
604
605/* Default vlan to clasify for untagged frames (may be zero) */
606static int ocelot_port_set_pvid(struct ocelot *ocelot, int port,
607 const struct ocelot_bridge_vlan *pvid_vlan)
608{
609 struct ocelot_port *ocelot_port = ocelot->ports[port];
610 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
611 u32 val = 0;
612
613 ocelot_port->pvid_vlan = pvid_vlan;
614
615 if (ocelot_port->vlan_aware && pvid_vlan)
616 pvid = pvid_vlan->vid;
617
618 ocelot_rmw_gix(ocelot,
619 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
620 ANA_PORT_VLAN_CFG_VLAN_VID_M,
621 ANA_PORT_VLAN_CFG, port);
622
623 /* If there's no pvid, we should drop not only untagged traffic (which
624 * happens automatically), but also 802.1p traffic which gets
625 * classified to VLAN 0, but that is always in our RX filter, so it
626 * would get accepted were it not for this setting.
627 *
628 * Also, we only support the bridge 802.1Q VLAN protocol, so
629 * 802.1ad-tagged frames (carrying S-Tags) should be considered
630 * 802.1Q-untagged, and also dropped.
631 */
632 if (!pvid_vlan && ocelot_port->vlan_aware)
633 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
634 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA |
635 ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA;
636
637 ocelot_rmw_gix(ocelot, val,
638 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
639 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA |
640 ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA,
641 ANA_PORT_DROP_CFG, port);
642
643 return ocelot_update_vlan_reclassify_rule(ocelot, port);
644}
645
646static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
647 u16 vid)
648{
649 struct ocelot_bridge_vlan *vlan;
650
651 list_for_each_entry(vlan, &ocelot->vlans, list)
652 if (vlan->vid == vid)
653 return vlan;
654
655 return NULL;
656}
657
658static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
659 bool untagged)
660{
661 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
662 unsigned long portmask;
663 int err;
664
665 if (vlan) {
666 portmask = vlan->portmask | BIT(port);
667
668 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
669 if (err)
670 return err;
671
672 vlan->portmask = portmask;
673 /* Bridge VLANs can be overwritten with a different
674 * egress-tagging setting, so make sure to override an untagged
675 * with a tagged VID if that's going on.
676 */
677 if (untagged)
678 vlan->untagged |= BIT(port);
679 else
680 vlan->untagged &= ~BIT(port);
681
682 return 0;
683 }
684
685 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
686 if (!vlan)
687 return -ENOMEM;
688
689 portmask = BIT(port);
690
691 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
692 if (err) {
693 kfree(vlan);
694 return err;
695 }
696
697 vlan->vid = vid;
698 vlan->portmask = portmask;
699 if (untagged)
700 vlan->untagged = BIT(port);
701 INIT_LIST_HEAD(&vlan->list);
702 list_add_tail(&vlan->list, &ocelot->vlans);
703
704 return 0;
705}
706
707static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
708{
709 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
710 unsigned long portmask;
711 int err;
712
713 if (!vlan)
714 return 0;
715
716 portmask = vlan->portmask & ~BIT(port);
717
718 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
719 if (err)
720 return err;
721
722 vlan->portmask = portmask;
723 if (vlan->portmask)
724 return 0;
725
726 list_del(&vlan->list);
727 kfree(vlan);
728
729 return 0;
730}
731
732static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
733 const struct net_device *bridge)
734{
735 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
736
737 return ocelot_vlan_member_add(ocelot, port, vid, true);
738}
739
740static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
741 const struct net_device *bridge)
742{
743 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
744
745 return ocelot_vlan_member_del(ocelot, port, vid);
746}
747
748int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
749 bool vlan_aware, struct netlink_ext_ack *extack)
750{
751 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
752 struct ocelot_port *ocelot_port = ocelot->ports[port];
753 struct ocelot_vcap_filter *filter;
754 int err = 0;
755 u32 val;
756
757 list_for_each_entry(filter, &block->rules, list) {
758 if (filter->ingress_port_mask & BIT(port) &&
759 filter->action.vid_replace_ena) {
760 NL_SET_ERR_MSG_MOD(extack,
761 "Cannot change VLAN state with vlan modify rules active");
762 return -EBUSY;
763 }
764 }
765
766 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
767 if (err)
768 return err;
769
770 if (vlan_aware)
771 err = ocelot_del_vlan_unaware_pvid(ocelot, port,
772 ocelot_port->bridge);
773 else if (ocelot_port->bridge)
774 err = ocelot_add_vlan_unaware_pvid(ocelot, port,
775 ocelot_port->bridge);
776 if (err)
777 return err;
778
779 ocelot_port->vlan_aware = vlan_aware;
780
781 if (vlan_aware)
782 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
783 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
784 else
785 val = 0;
786 ocelot_rmw_gix(ocelot, val,
787 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
788 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
789 ANA_PORT_VLAN_CFG, port);
790
791 err = ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
792 if (err)
793 return err;
794
795 ocelot_port_manage_port_tag(ocelot, port);
796
797 return 0;
798}
799EXPORT_SYMBOL(ocelot_port_vlan_filtering);
800
801int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
802 bool untagged, struct netlink_ext_ack *extack)
803{
804 if (untagged) {
805 /* We are adding an egress-tagged VLAN */
806 if (ocelot_port_uses_native_vlan(ocelot, port)) {
807 NL_SET_ERR_MSG_MOD(extack,
808 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
809 return -EBUSY;
810 }
811 } else {
812 /* We are adding an egress-tagged VLAN */
813 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
814 NL_SET_ERR_MSG_MOD(extack,
815 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
816 return -EBUSY;
817 }
818 }
819
820 if (vid > OCELOT_RSV_VLAN_RANGE_START) {
821 NL_SET_ERR_MSG_MOD(extack,
822 "VLAN range 4000-4095 reserved for VLAN-unaware bridging");
823 return -EBUSY;
824 }
825
826 return 0;
827}
828EXPORT_SYMBOL(ocelot_vlan_prepare);
829
830int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
831 bool untagged)
832{
833 int err;
834
835 /* Ignore VID 0 added to our RX filter by the 8021q module, since
836 * that collides with OCELOT_STANDALONE_PVID and changes it from
837 * egress-untagged to egress-tagged.
838 */
839 if (!vid)
840 return 0;
841
842 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
843 if (err)
844 return err;
845
846 /* Default ingress vlan classification */
847 if (pvid) {
848 err = ocelot_port_set_pvid(ocelot, port,
849 ocelot_bridge_vlan_find(ocelot, vid));
850 if (err)
851 return err;
852 }
853
854 /* Untagged egress vlan clasification */
855 ocelot_port_manage_port_tag(ocelot, port);
856
857 return 0;
858}
859EXPORT_SYMBOL(ocelot_vlan_add);
860
861int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
862{
863 struct ocelot_port *ocelot_port = ocelot->ports[port];
864 bool del_pvid = false;
865 int err;
866
867 if (!vid)
868 return 0;
869
870 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
871 del_pvid = true;
872
873 err = ocelot_vlan_member_del(ocelot, port, vid);
874 if (err)
875 return err;
876
877 /* Ingress */
878 if (del_pvid) {
879 err = ocelot_port_set_pvid(ocelot, port, NULL);
880 if (err)
881 return err;
882 }
883
884 /* Egress */
885 ocelot_port_manage_port_tag(ocelot, port);
886
887 return 0;
888}
889EXPORT_SYMBOL(ocelot_vlan_del);
890
891static void ocelot_vlan_init(struct ocelot *ocelot)
892{
893 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
894 u16 port, vid;
895
896 /* Clear VLAN table, by default all ports are members of all VLANs */
897 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
898 ANA_TABLES_VLANACCESS);
899 ocelot_vlant_wait_for_completion(ocelot);
900
901 /* Configure the port VLAN memberships */
902 for (vid = 1; vid < VLAN_N_VID; vid++)
903 ocelot_vlant_set_mask(ocelot, vid, 0);
904
905 /* We need VID 0 to get traffic on standalone ports.
906 * It is added automatically if the 8021q module is loaded, but we
907 * can't rely on that since it might not be.
908 */
909 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
910
911 /* Set vlan ingress filter mask to all ports but the CPU port by
912 * default.
913 */
914 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
915
916 for (port = 0; port < ocelot->num_phys_ports; port++) {
917 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
918 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
919 }
920}
921
922static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
923{
924 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
925}
926
927static int ocelot_port_flush(struct ocelot *ocelot, int port)
928{
929 unsigned int pause_ena;
930 int err, val;
931
932 /* Disable dequeuing from the egress queues */
933 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
934 QSYS_PORT_MODE_DEQUEUE_DIS,
935 QSYS_PORT_MODE, port);
936
937 /* Disable flow control */
938 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
939 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
940
941 /* Disable priority flow control */
942 ocelot_fields_write(ocelot, port,
943 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
944
945 /* Wait at least the time it takes to receive a frame of maximum length
946 * at the port.
947 * Worst-case delays for 10 kilobyte jumbo frames are:
948 * 8 ms on a 10M port
949 * 800 μs on a 100M port
950 * 80 μs on a 1G port
951 * 32 μs on a 2.5G port
952 */
953 usleep_range(8000, 10000);
954
955 /* Disable half duplex backpressure. */
956 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
957 SYS_FRONT_PORT_MODE, port);
958
959 /* Flush the queues associated with the port. */
960 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
961 REW_PORT_CFG, port);
962
963 /* Enable dequeuing from the egress queues. */
964 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
965 port);
966
967 /* Wait until flushing is complete. */
968 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
969 100, 2000000, false, ocelot, port);
970
971 /* Clear flushing again. */
972 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
973
974 /* Re-enable flow control */
975 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
976
977 return err;
978}
979
980int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
981 struct device_node *portnp)
982{
983 struct ocelot_port *ocelot_port = ocelot->ports[port];
984 struct device *dev = ocelot->dev;
985 int err;
986
987 /* Ensure clock signals and speed are set on all QSGMII links */
988 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII)
989 ocelot_port_rmwl(ocelot_port, 0,
990 DEV_CLOCK_CFG_MAC_TX_RST |
991 DEV_CLOCK_CFG_MAC_RX_RST,
992 DEV_CLOCK_CFG);
993
994 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) {
995 struct phy *serdes = of_phy_get(portnp, NULL);
996
997 if (IS_ERR(serdes)) {
998 err = PTR_ERR(serdes);
999 dev_err_probe(dev, err,
1000 "missing SerDes phys for port %d\n",
1001 port);
1002 return err;
1003 }
1004
1005 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET,
1006 ocelot_port->phy_mode);
1007 of_phy_put(serdes);
1008 if (err) {
1009 dev_err(dev, "Could not SerDes mode on port %d: %pe\n",
1010 port, ERR_PTR(err));
1011 return err;
1012 }
1013 }
1014
1015 return 0;
1016}
1017EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes);
1018
1019void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
1020 unsigned int link_an_mode,
1021 const struct phylink_link_state *state)
1022{
1023 struct ocelot_port *ocelot_port = ocelot->ports[port];
1024
1025 /* Disable HDX fast control */
1026 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
1027 DEV_PORT_MISC);
1028
1029 /* SGMII only for now */
1030 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
1031 PCS1G_MODE_CFG);
1032 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
1033
1034 /* Enable PCS */
1035 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
1036
1037 /* No aneg on SGMII */
1038 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
1039
1040 /* No loopback */
1041 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
1042}
1043EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config);
1044
1045void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1046 unsigned int link_an_mode,
1047 phy_interface_t interface,
1048 unsigned long quirks)
1049{
1050 struct ocelot_port *ocelot_port = ocelot->ports[port];
1051 int err;
1052
1053 ocelot_port->speed = SPEED_UNKNOWN;
1054
1055 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
1056 DEV_MAC_ENA_CFG);
1057
1058 if (ocelot->ops->cut_through_fwd) {
1059 mutex_lock(&ocelot->fwd_domain_lock);
1060 ocelot->ops->cut_through_fwd(ocelot);
1061 mutex_unlock(&ocelot->fwd_domain_lock);
1062 }
1063
1064 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
1065
1066 err = ocelot_port_flush(ocelot, port);
1067 if (err)
1068 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
1069 port, err);
1070
1071 /* Put the port in reset. */
1072 if (interface != PHY_INTERFACE_MODE_QSGMII ||
1073 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
1074 ocelot_port_rmwl(ocelot_port,
1075 DEV_CLOCK_CFG_MAC_TX_RST |
1076 DEV_CLOCK_CFG_MAC_RX_RST,
1077 DEV_CLOCK_CFG_MAC_TX_RST |
1078 DEV_CLOCK_CFG_MAC_RX_RST,
1079 DEV_CLOCK_CFG);
1080}
1081EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
1082
1083void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1084 struct phy_device *phydev,
1085 unsigned int link_an_mode,
1086 phy_interface_t interface,
1087 int speed, int duplex,
1088 bool tx_pause, bool rx_pause,
1089 unsigned long quirks)
1090{
1091 struct ocelot_port *ocelot_port = ocelot->ports[port];
1092 int mac_speed, mode = 0;
1093 u32 mac_fc_cfg;
1094
1095 ocelot_port->speed = speed;
1096
1097 /* The MAC might be integrated in systems where the MAC speed is fixed
1098 * and it's the PCS who is performing the rate adaptation, so we have
1099 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
1100 * (which is also its default value).
1101 */
1102 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
1103 speed == SPEED_1000) {
1104 mac_speed = OCELOT_SPEED_1000;
1105 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
1106 } else if (speed == SPEED_2500) {
1107 mac_speed = OCELOT_SPEED_2500;
1108 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
1109 } else if (speed == SPEED_100) {
1110 mac_speed = OCELOT_SPEED_100;
1111 } else {
1112 mac_speed = OCELOT_SPEED_10;
1113 }
1114
1115 if (duplex == DUPLEX_FULL)
1116 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
1117
1118 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
1119
1120 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
1121 * PORT_RST bits in DEV_CLOCK_CFG.
1122 */
1123 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
1124 DEV_CLOCK_CFG);
1125
1126 switch (speed) {
1127 case SPEED_10:
1128 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
1129 break;
1130 case SPEED_100:
1131 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
1132 break;
1133 case SPEED_1000:
1134 case SPEED_2500:
1135 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
1136 break;
1137 default:
1138 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
1139 port, speed);
1140 return;
1141 }
1142
1143 if (rx_pause)
1144 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
1145
1146 if (tx_pause)
1147 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
1148 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
1149 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
1150 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
1151
1152 /* Flow control. Link speed is only used here to evaluate the time
1153 * specification in incoming pause frames.
1154 */
1155 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
1156
1157 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
1158
1159 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */
1160 if (port != ocelot->npi)
1161 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
1162 tx_pause);
1163
1164 /* Undo the effects of ocelot_phylink_mac_link_down:
1165 * enable MAC module
1166 */
1167 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
1168 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
1169
1170 /* If the port supports cut-through forwarding, update the masks before
1171 * enabling forwarding on the port.
1172 */
1173 if (ocelot->ops->cut_through_fwd) {
1174 mutex_lock(&ocelot->fwd_domain_lock);
1175 /* Workaround for hardware bug - FP doesn't work
1176 * at all link speeds for all PHY modes. The function
1177 * below also calls ocelot->ops->cut_through_fwd(),
1178 * so we don't need to do it twice.
1179 */
1180 ocelot_port_update_active_preemptible_tcs(ocelot, port);
1181 mutex_unlock(&ocelot->fwd_domain_lock);
1182 }
1183
1184 /* Core: Enable port for frame transfer */
1185 ocelot_fields_write(ocelot, port,
1186 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1187}
1188EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
1189
1190static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
1191 u32 *rval)
1192{
1193 u32 bytes_valid, val;
1194
1195 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1196 if (val == XTR_NOT_READY) {
1197 if (ifh)
1198 return -EIO;
1199
1200 do {
1201 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1202 } while (val == XTR_NOT_READY);
1203 }
1204
1205 switch (val) {
1206 case XTR_ABORT:
1207 return -EIO;
1208 case XTR_EOF_0:
1209 case XTR_EOF_1:
1210 case XTR_EOF_2:
1211 case XTR_EOF_3:
1212 case XTR_PRUNED:
1213 bytes_valid = XTR_VALID_BYTES(val);
1214 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1215 if (val == XTR_ESCAPE)
1216 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1217 else
1218 *rval = val;
1219
1220 return bytes_valid;
1221 case XTR_ESCAPE:
1222 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1223
1224 return 4;
1225 default:
1226 *rval = val;
1227
1228 return 4;
1229 }
1230}
1231
1232static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
1233{
1234 int i, err = 0;
1235
1236 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
1237 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
1238 if (err != 4)
1239 return (err < 0) ? err : -EIO;
1240 }
1241
1242 return 0;
1243}
1244
1245void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1246 u64 timestamp)
1247{
1248 struct skb_shared_hwtstamps *shhwtstamps;
1249 u64 tod_in_ns, full_ts_in_ns;
1250 struct timespec64 ts;
1251
1252 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1253
1254 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
1255 if ((tod_in_ns & 0xffffffff) < timestamp)
1256 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
1257 timestamp;
1258 else
1259 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
1260 timestamp;
1261
1262 shhwtstamps = skb_hwtstamps(skb);
1263 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1264 shhwtstamps->hwtstamp = full_ts_in_ns;
1265}
1266EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
1267
1268void ocelot_lock_inj_grp(struct ocelot *ocelot, int grp)
1269 __acquires(&ocelot->inj_lock)
1270{
1271 spin_lock(&ocelot->inj_lock);
1272}
1273EXPORT_SYMBOL_GPL(ocelot_lock_inj_grp);
1274
1275void ocelot_unlock_inj_grp(struct ocelot *ocelot, int grp)
1276 __releases(&ocelot->inj_lock)
1277{
1278 spin_unlock(&ocelot->inj_lock);
1279}
1280EXPORT_SYMBOL_GPL(ocelot_unlock_inj_grp);
1281
1282void ocelot_lock_xtr_grp(struct ocelot *ocelot, int grp)
1283 __acquires(&ocelot->inj_lock)
1284{
1285 spin_lock(&ocelot->inj_lock);
1286}
1287EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp);
1288
1289void ocelot_unlock_xtr_grp(struct ocelot *ocelot, int grp)
1290 __releases(&ocelot->inj_lock)
1291{
1292 spin_unlock(&ocelot->inj_lock);
1293}
1294EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp);
1295
1296void ocelot_lock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1297 __acquires(&ocelot->xtr_lock)
1298{
1299 spin_lock_bh(&ocelot->xtr_lock);
1300}
1301EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp_bh);
1302
1303void ocelot_unlock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1304 __releases(&ocelot->xtr_lock)
1305{
1306 spin_unlock_bh(&ocelot->xtr_lock);
1307}
1308EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp_bh);
1309
1310int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
1311{
1312 u64 timestamp, src_port, len;
1313 u32 xfh[OCELOT_TAG_LEN / 4];
1314 struct net_device *dev;
1315 struct sk_buff *skb;
1316 int sz, buf_len;
1317 u32 val, *buf;
1318 int err;
1319
1320 lockdep_assert_held(&ocelot->xtr_lock);
1321
1322 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1323 if (err)
1324 return err;
1325
1326 ocelot_xfh_get_src_port(xfh, &src_port);
1327 ocelot_xfh_get_len(xfh, &len);
1328 ocelot_xfh_get_rew_val(xfh, ×tamp);
1329
1330 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1331 return -EINVAL;
1332
1333 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1334 if (!dev)
1335 return -EINVAL;
1336
1337 skb = netdev_alloc_skb(dev, len);
1338 if (unlikely(!skb)) {
1339 netdev_err(dev, "Unable to allocate sk_buff\n");
1340 return -ENOMEM;
1341 }
1342
1343 buf_len = len - ETH_FCS_LEN;
1344 buf = (u32 *)skb_put(skb, buf_len);
1345
1346 len = 0;
1347 do {
1348 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1349 if (sz < 0) {
1350 err = sz;
1351 goto out_free_skb;
1352 }
1353 *buf++ = val;
1354 len += sz;
1355 } while (len < buf_len);
1356
1357 /* Read the FCS */
1358 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1359 if (sz < 0) {
1360 err = sz;
1361 goto out_free_skb;
1362 }
1363
1364 /* Update the statistics if part of the FCS was read before */
1365 len -= ETH_FCS_LEN - sz;
1366
1367 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1368 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1369 *buf = val;
1370 }
1371
1372 if (ocelot->ptp)
1373 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1374
1375 /* Everything we see on an interface that is in the HW bridge
1376 * has already been forwarded.
1377 */
1378 if (ocelot->ports[src_port]->bridge)
1379 skb->offload_fwd_mark = 1;
1380
1381 skb->protocol = eth_type_trans(skb, dev);
1382
1383 *nskb = skb;
1384
1385 return 0;
1386
1387out_free_skb:
1388 kfree_skb(skb);
1389 return err;
1390}
1391EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1392
1393bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1394{
1395 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1396
1397 lockdep_assert_held(&ocelot->inj_lock);
1398
1399 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1400 return false;
1401 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1402 return false;
1403
1404 return true;
1405}
1406EXPORT_SYMBOL(ocelot_can_inject);
1407
1408/**
1409 * ocelot_ifh_set_basic - Set basic information in Injection Frame Header
1410 * @ifh: Pointer to Injection Frame Header memory
1411 * @ocelot: Switch private data structure
1412 * @port: Egress port number
1413 * @rew_op: Egress rewriter operation for PTP
1414 * @skb: Pointer to socket buffer (packet)
1415 *
1416 * Populate the Injection Frame Header with basic information for this skb: the
1417 * analyzer bypass bit, destination port, VLAN info, egress rewriter info.
1418 */
1419void ocelot_ifh_set_basic(void *ifh, struct ocelot *ocelot, int port,
1420 u32 rew_op, struct sk_buff *skb)
1421{
1422 struct ocelot_port *ocelot_port = ocelot->ports[port];
1423 struct net_device *dev = skb->dev;
1424 u64 vlan_tci, tag_type;
1425 int qos_class;
1426
1427 ocelot_xmit_get_vlan_info(skb, ocelot_port->bridge, &vlan_tci,
1428 &tag_type);
1429
1430 qos_class = netdev_get_num_tc(dev) ?
1431 netdev_get_prio_tc_map(dev, skb->priority) : skb->priority;
1432
1433 memset(ifh, 0, OCELOT_TAG_LEN);
1434 ocelot_ifh_set_bypass(ifh, 1);
1435 ocelot_ifh_set_src(ifh, ocelot->num_phys_ports);
1436 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1437 ocelot_ifh_set_qos_class(ifh, qos_class);
1438 ocelot_ifh_set_tag_type(ifh, tag_type);
1439 ocelot_ifh_set_vlan_tci(ifh, vlan_tci);
1440 if (rew_op)
1441 ocelot_ifh_set_rew_op(ifh, rew_op);
1442}
1443EXPORT_SYMBOL(ocelot_ifh_set_basic);
1444
1445void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1446 u32 rew_op, struct sk_buff *skb)
1447{
1448 u32 ifh[OCELOT_TAG_LEN / 4];
1449 unsigned int i, count, last;
1450
1451 lockdep_assert_held(&ocelot->inj_lock);
1452
1453 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1454 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1455
1456 ocelot_ifh_set_basic(ifh, ocelot, port, rew_op, skb);
1457
1458 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1459 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1460
1461 count = DIV_ROUND_UP(skb->len, 4);
1462 last = skb->len % 4;
1463 for (i = 0; i < count; i++)
1464 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1465
1466 /* Add padding */
1467 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1468 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1469 i++;
1470 }
1471
1472 /* Indicate EOF and valid bytes in last word */
1473 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1474 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1475 QS_INJ_CTRL_EOF,
1476 QS_INJ_CTRL, grp);
1477
1478 /* Add dummy CRC */
1479 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1480 skb_tx_timestamp(skb);
1481
1482 skb->dev->stats.tx_packets++;
1483 skb->dev->stats.tx_bytes += skb->len;
1484}
1485EXPORT_SYMBOL(ocelot_port_inject_frame);
1486
1487void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1488{
1489 lockdep_assert_held(&ocelot->xtr_lock);
1490
1491 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1492 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1493}
1494EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1495
1496int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1497 u16 vid, const struct net_device *bridge)
1498{
1499 if (!vid)
1500 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1501
1502 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1503}
1504EXPORT_SYMBOL(ocelot_fdb_add);
1505
1506int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1507 u16 vid, const struct net_device *bridge)
1508{
1509 if (!vid)
1510 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1511
1512 return ocelot_mact_forget(ocelot, addr, vid);
1513}
1514EXPORT_SYMBOL(ocelot_fdb_del);
1515
1516/* Caller must hold &ocelot->mact_lock */
1517static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1518 struct ocelot_mact_entry *entry)
1519{
1520 u32 val, dst, macl, mach;
1521 char mac[ETH_ALEN];
1522
1523 /* Set row and column to read from */
1524 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1525 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1526
1527 /* Issue a read command */
1528 ocelot_write(ocelot,
1529 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1530 ANA_TABLES_MACACCESS);
1531
1532 if (ocelot_mact_wait_for_completion(ocelot))
1533 return -ETIMEDOUT;
1534
1535 /* Read the entry flags */
1536 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1537 if (!(val & ANA_TABLES_MACACCESS_VALID))
1538 return -EINVAL;
1539
1540 /* If the entry read has another port configured as its destination,
1541 * do not report it.
1542 */
1543 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1544 if (dst != port)
1545 return -EINVAL;
1546
1547 /* Get the entry's MAC address and VLAN id */
1548 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1549 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1550
1551 mac[0] = (mach >> 8) & 0xff;
1552 mac[1] = (mach >> 0) & 0xff;
1553 mac[2] = (macl >> 24) & 0xff;
1554 mac[3] = (macl >> 16) & 0xff;
1555 mac[4] = (macl >> 8) & 0xff;
1556 mac[5] = (macl >> 0) & 0xff;
1557
1558 entry->vid = (mach >> 16) & 0xfff;
1559 ether_addr_copy(entry->mac, mac);
1560
1561 return 0;
1562}
1563
1564int ocelot_mact_flush(struct ocelot *ocelot, int port)
1565{
1566 int err;
1567
1568 mutex_lock(&ocelot->mact_lock);
1569
1570 /* Program ageing filter for a single port */
1571 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1572 ANA_ANAGEFIL);
1573
1574 /* Flushing dynamic FDB entries requires two successive age scans */
1575 ocelot_write(ocelot,
1576 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1577 ANA_TABLES_MACACCESS);
1578
1579 err = ocelot_mact_wait_for_completion(ocelot);
1580 if (err) {
1581 mutex_unlock(&ocelot->mact_lock);
1582 return err;
1583 }
1584
1585 /* And second... */
1586 ocelot_write(ocelot,
1587 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1588 ANA_TABLES_MACACCESS);
1589
1590 err = ocelot_mact_wait_for_completion(ocelot);
1591
1592 /* Restore ageing filter */
1593 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1594
1595 mutex_unlock(&ocelot->mact_lock);
1596
1597 return err;
1598}
1599EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1600
1601int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1602 dsa_fdb_dump_cb_t *cb, void *data)
1603{
1604 int err = 0;
1605 int i, j;
1606
1607 /* We could take the lock just around ocelot_mact_read, but doing so
1608 * thousands of times in a row seems rather pointless and inefficient.
1609 */
1610 mutex_lock(&ocelot->mact_lock);
1611
1612 /* Loop through all the mac tables entries. */
1613 for (i = 0; i < ocelot->num_mact_rows; i++) {
1614 for (j = 0; j < 4; j++) {
1615 struct ocelot_mact_entry entry;
1616 bool is_static;
1617
1618 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1619 /* If the entry is invalid (wrong port, invalid...),
1620 * skip it.
1621 */
1622 if (err == -EINVAL)
1623 continue;
1624 else if (err)
1625 break;
1626
1627 is_static = (entry.type == ENTRYTYPE_LOCKED);
1628
1629 /* Hide the reserved VLANs used for
1630 * VLAN-unaware bridging.
1631 */
1632 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START)
1633 entry.vid = 0;
1634
1635 err = cb(entry.mac, entry.vid, is_static, data);
1636 if (err)
1637 break;
1638 }
1639 }
1640
1641 mutex_unlock(&ocelot->mact_lock);
1642
1643 return err;
1644}
1645EXPORT_SYMBOL(ocelot_fdb_dump);
1646
1647int ocelot_trap_add(struct ocelot *ocelot, int port,
1648 unsigned long cookie, bool take_ts,
1649 void (*populate)(struct ocelot_vcap_filter *f))
1650{
1651 struct ocelot_vcap_block *block_vcap_is2;
1652 struct ocelot_vcap_filter *trap;
1653 bool new = false;
1654 int err;
1655
1656 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1657
1658 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1659 false);
1660 if (!trap) {
1661 trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1662 if (!trap)
1663 return -ENOMEM;
1664
1665 populate(trap);
1666 trap->prio = 1;
1667 trap->id.cookie = cookie;
1668 trap->id.tc_offload = false;
1669 trap->block_id = VCAP_IS2;
1670 trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1671 trap->lookup = 0;
1672 trap->action.cpu_copy_ena = true;
1673 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1674 trap->action.port_mask = 0;
1675 trap->take_ts = take_ts;
1676 trap->is_trap = true;
1677 new = true;
1678 }
1679
1680 trap->ingress_port_mask |= BIT(port);
1681
1682 if (new)
1683 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1684 else
1685 err = ocelot_vcap_filter_replace(ocelot, trap);
1686 if (err) {
1687 trap->ingress_port_mask &= ~BIT(port);
1688 if (!trap->ingress_port_mask)
1689 kfree(trap);
1690 return err;
1691 }
1692
1693 return 0;
1694}
1695
1696int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1697{
1698 struct ocelot_vcap_block *block_vcap_is2;
1699 struct ocelot_vcap_filter *trap;
1700
1701 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1702
1703 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1704 false);
1705 if (!trap)
1706 return 0;
1707
1708 trap->ingress_port_mask &= ~BIT(port);
1709 if (!trap->ingress_port_mask)
1710 return ocelot_vcap_filter_del(ocelot, trap);
1711
1712 return ocelot_vcap_filter_replace(ocelot, trap);
1713}
1714
1715static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1716{
1717 u32 mask = 0;
1718 int port;
1719
1720 lockdep_assert_held(&ocelot->fwd_domain_lock);
1721
1722 for (port = 0; port < ocelot->num_phys_ports; port++) {
1723 struct ocelot_port *ocelot_port = ocelot->ports[port];
1724
1725 if (!ocelot_port)
1726 continue;
1727
1728 if (ocelot_port->bond == bond)
1729 mask |= BIT(port);
1730 }
1731
1732 return mask;
1733}
1734
1735/* The logical port number of a LAG is equal to the lowest numbered physical
1736 * port ID present in that LAG. It may change if that port ever leaves the LAG.
1737 */
1738int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
1739{
1740 int bond_mask = ocelot_get_bond_mask(ocelot, bond);
1741
1742 if (!bond_mask)
1743 return -ENOENT;
1744
1745 return __ffs(bond_mask);
1746}
1747EXPORT_SYMBOL_GPL(ocelot_bond_get_id);
1748
1749/* Returns the mask of user ports assigned to this DSA tag_8021q CPU port.
1750 * Note that when CPU ports are in a LAG, the user ports are assigned to the
1751 * 'primary' CPU port, the one whose physical port number gives the logical
1752 * port number of the LAG.
1753 *
1754 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG
1755 * (to which no user port is assigned), but it appears that forwarding from
1756 * this secondary CPU port looks at the PGID_SRC associated with the logical
1757 * port ID that it's assigned to, which *is* configured properly.
1758 */
1759static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
1760 struct ocelot_port *cpu)
1761{
1762 u32 mask = 0;
1763 int port;
1764
1765 for (port = 0; port < ocelot->num_phys_ports; port++) {
1766 struct ocelot_port *ocelot_port = ocelot->ports[port];
1767
1768 if (!ocelot_port)
1769 continue;
1770
1771 if (ocelot_port->dsa_8021q_cpu == cpu)
1772 mask |= BIT(port);
1773 }
1774
1775 if (cpu->bond)
1776 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond);
1777
1778 return mask;
1779}
1780
1781/* Returns the DSA tag_8021q CPU port that the given port is assigned to,
1782 * or the bit mask of CPU ports if said CPU port is in a LAG.
1783 */
1784u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
1785{
1786 struct ocelot_port *ocelot_port = ocelot->ports[port];
1787 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
1788
1789 if (!cpu_port)
1790 return 0;
1791
1792 if (cpu_port->bond)
1793 return ocelot_get_bond_mask(ocelot, cpu_port->bond);
1794
1795 return BIT(cpu_port->index);
1796}
1797EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
1798
1799u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1800{
1801 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1802 const struct net_device *bridge;
1803 u32 mask = 0;
1804 int port;
1805
1806 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
1807 return 0;
1808
1809 bridge = ocelot_port->bridge;
1810 if (!bridge)
1811 return 0;
1812
1813 for (port = 0; port < ocelot->num_phys_ports; port++) {
1814 ocelot_port = ocelot->ports[port];
1815
1816 if (!ocelot_port)
1817 continue;
1818
1819 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1820 ocelot_port->bridge == bridge)
1821 mask |= BIT(port);
1822 }
1823
1824 return mask;
1825}
1826EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
1827
1828static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1829{
1830 int port;
1831
1832 lockdep_assert_held(&ocelot->fwd_domain_lock);
1833
1834 /* If cut-through forwarding is supported, update the masks before a
1835 * port joins the forwarding domain, to avoid potential underruns if it
1836 * has the highest speed from the new domain.
1837 */
1838 if (joining && ocelot->ops->cut_through_fwd)
1839 ocelot->ops->cut_through_fwd(ocelot);
1840
1841 /* Apply FWD mask. The loop is needed to add/remove the current port as
1842 * a source for the other ports.
1843 */
1844 for (port = 0; port < ocelot->num_phys_ports; port++) {
1845 struct ocelot_port *ocelot_port = ocelot->ports[port];
1846 unsigned long mask;
1847
1848 if (!ocelot_port) {
1849 /* Unused ports can't send anywhere */
1850 mask = 0;
1851 } else if (ocelot_port->is_dsa_8021q_cpu) {
1852 /* The DSA tag_8021q CPU ports need to be able to
1853 * forward packets to all ports assigned to them.
1854 */
1855 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
1856 ocelot_port);
1857 } else if (ocelot_port->bridge) {
1858 struct net_device *bond = ocelot_port->bond;
1859
1860 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1861 mask &= ~BIT(port);
1862
1863 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1864 port);
1865
1866 if (bond)
1867 mask &= ~ocelot_get_bond_mask(ocelot, bond);
1868 } else {
1869 /* Standalone ports forward only to DSA tag_8021q CPU
1870 * ports (if those exist), or to the hardware CPU port
1871 * module otherwise.
1872 */
1873 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1874 port);
1875 }
1876
1877 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1878 }
1879
1880 /* If cut-through forwarding is supported and a port is leaving, there
1881 * is a chance that cut-through was disabled on the other ports due to
1882 * the port which is leaving (it has a higher link speed). We need to
1883 * update the cut-through masks of the remaining ports no earlier than
1884 * after the port has left, to prevent underruns from happening between
1885 * the cut-through update and the forwarding domain update.
1886 */
1887 if (!joining && ocelot->ops->cut_through_fwd)
1888 ocelot->ops->cut_through_fwd(ocelot);
1889}
1890
1891/* Update PGID_CPU which is the destination port mask used for whitelisting
1892 * unicast addresses filtered towards the host. In the normal and NPI modes,
1893 * this points to the analyzer entry for the CPU port module, while in DSA
1894 * tag_8021q mode, it is a bit mask of all active CPU ports.
1895 * PGID_SRC will take care of forwarding a packet from one user port to
1896 * no more than a single CPU port.
1897 */
1898static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
1899{
1900 int pgid_cpu = 0;
1901 int port;
1902
1903 for (port = 0; port < ocelot->num_phys_ports; port++) {
1904 struct ocelot_port *ocelot_port = ocelot->ports[port];
1905
1906 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu)
1907 continue;
1908
1909 pgid_cpu |= BIT(port);
1910 }
1911
1912 if (!pgid_cpu)
1913 pgid_cpu = BIT(ocelot->num_phys_ports);
1914
1915 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
1916}
1917
1918void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1919{
1920 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1921 u16 vid;
1922
1923 mutex_lock(&ocelot->fwd_domain_lock);
1924
1925 cpu_port->is_dsa_8021q_cpu = true;
1926
1927 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1928 ocelot_vlan_member_add(ocelot, cpu, vid, true);
1929
1930 ocelot_update_pgid_cpu(ocelot);
1931
1932 mutex_unlock(&ocelot->fwd_domain_lock);
1933}
1934EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu);
1935
1936void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1937{
1938 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1939 u16 vid;
1940
1941 mutex_lock(&ocelot->fwd_domain_lock);
1942
1943 cpu_port->is_dsa_8021q_cpu = false;
1944
1945 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1946 ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
1947
1948 ocelot_update_pgid_cpu(ocelot);
1949
1950 mutex_unlock(&ocelot->fwd_domain_lock);
1951}
1952EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu);
1953
1954void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
1955 int cpu)
1956{
1957 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1958
1959 mutex_lock(&ocelot->fwd_domain_lock);
1960
1961 ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
1962 ocelot_apply_bridge_fwd_mask(ocelot, true);
1963
1964 mutex_unlock(&ocelot->fwd_domain_lock);
1965}
1966EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
1967
1968void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
1969{
1970 mutex_lock(&ocelot->fwd_domain_lock);
1971
1972 ocelot->ports[port]->dsa_8021q_cpu = NULL;
1973 ocelot_apply_bridge_fwd_mask(ocelot, true);
1974
1975 mutex_unlock(&ocelot->fwd_domain_lock);
1976}
1977EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
1978
1979void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1980{
1981 struct ocelot_port *ocelot_port = ocelot->ports[port];
1982 u32 learn_ena = 0;
1983
1984 mutex_lock(&ocelot->fwd_domain_lock);
1985
1986 ocelot_port->stp_state = state;
1987
1988 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1989 ocelot_port->learn_ena)
1990 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1991
1992 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1993 ANA_PORT_PORT_CFG, port);
1994
1995 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
1996
1997 mutex_unlock(&ocelot->fwd_domain_lock);
1998}
1999EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
2000
2001void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
2002{
2003 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
2004
2005 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
2006 * which is clearly not what our intention is. So avoid that.
2007 */
2008 if (!age_period)
2009 age_period = 1;
2010
2011 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
2012}
2013EXPORT_SYMBOL(ocelot_set_ageing_time);
2014
2015static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
2016 const unsigned char *addr,
2017 u16 vid)
2018{
2019 struct ocelot_multicast *mc;
2020
2021 list_for_each_entry(mc, &ocelot->multicast, list) {
2022 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
2023 return mc;
2024 }
2025
2026 return NULL;
2027}
2028
2029static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
2030{
2031 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
2032 return ENTRYTYPE_MACv4;
2033 if (addr[0] == 0x33 && addr[1] == 0x33)
2034 return ENTRYTYPE_MACv6;
2035 return ENTRYTYPE_LOCKED;
2036}
2037
2038static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
2039 unsigned long ports)
2040{
2041 struct ocelot_pgid *pgid;
2042
2043 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
2044 if (!pgid)
2045 return ERR_PTR(-ENOMEM);
2046
2047 pgid->ports = ports;
2048 pgid->index = index;
2049 refcount_set(&pgid->refcount, 1);
2050 list_add_tail(&pgid->list, &ocelot->pgids);
2051
2052 return pgid;
2053}
2054
2055static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
2056{
2057 if (!refcount_dec_and_test(&pgid->refcount))
2058 return;
2059
2060 list_del(&pgid->list);
2061 kfree(pgid);
2062}
2063
2064static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
2065 const struct ocelot_multicast *mc)
2066{
2067 struct ocelot_pgid *pgid;
2068 int index;
2069
2070 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
2071 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
2072 * destination mask table (PGID), the destination set is programmed as
2073 * part of the entry MAC address.", and the DEST_IDX is set to 0.
2074 */
2075 if (mc->entry_type == ENTRYTYPE_MACv4 ||
2076 mc->entry_type == ENTRYTYPE_MACv6)
2077 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
2078
2079 list_for_each_entry(pgid, &ocelot->pgids, list) {
2080 /* When searching for a nonreserved multicast PGID, ignore the
2081 * dummy PGID of zero that we have for MACv4/MACv6 entries
2082 */
2083 if (pgid->index && pgid->ports == mc->ports) {
2084 refcount_inc(&pgid->refcount);
2085 return pgid;
2086 }
2087 }
2088
2089 /* Search for a free index in the nonreserved multicast PGID area */
2090 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
2091 bool used = false;
2092
2093 list_for_each_entry(pgid, &ocelot->pgids, list) {
2094 if (pgid->index == index) {
2095 used = true;
2096 break;
2097 }
2098 }
2099
2100 if (!used)
2101 return ocelot_pgid_alloc(ocelot, index, mc->ports);
2102 }
2103
2104 return ERR_PTR(-ENOSPC);
2105}
2106
2107static void ocelot_encode_ports_to_mdb(unsigned char *addr,
2108 struct ocelot_multicast *mc)
2109{
2110 ether_addr_copy(addr, mc->addr);
2111
2112 if (mc->entry_type == ENTRYTYPE_MACv4) {
2113 addr[0] = 0;
2114 addr[1] = mc->ports >> 8;
2115 addr[2] = mc->ports & 0xff;
2116 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
2117 addr[0] = mc->ports >> 8;
2118 addr[1] = mc->ports & 0xff;
2119 }
2120}
2121
2122int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
2123 const struct switchdev_obj_port_mdb *mdb,
2124 const struct net_device *bridge)
2125{
2126 unsigned char addr[ETH_ALEN];
2127 struct ocelot_multicast *mc;
2128 struct ocelot_pgid *pgid;
2129 u16 vid = mdb->vid;
2130
2131 if (!vid)
2132 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2133
2134 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2135 if (!mc) {
2136 /* New entry */
2137 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
2138 if (!mc)
2139 return -ENOMEM;
2140
2141 mc->entry_type = ocelot_classify_mdb(mdb->addr);
2142 ether_addr_copy(mc->addr, mdb->addr);
2143 mc->vid = vid;
2144
2145 list_add_tail(&mc->list, &ocelot->multicast);
2146 } else {
2147 /* Existing entry. Clean up the current port mask from
2148 * hardware now, because we'll be modifying it.
2149 */
2150 ocelot_pgid_free(ocelot, mc->pgid);
2151 ocelot_encode_ports_to_mdb(addr, mc);
2152 ocelot_mact_forget(ocelot, addr, vid);
2153 }
2154
2155 mc->ports |= BIT(port);
2156
2157 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2158 if (IS_ERR(pgid)) {
2159 dev_err(ocelot->dev,
2160 "Cannot allocate PGID for mdb %pM vid %d\n",
2161 mc->addr, mc->vid);
2162 devm_kfree(ocelot->dev, mc);
2163 return PTR_ERR(pgid);
2164 }
2165 mc->pgid = pgid;
2166
2167 ocelot_encode_ports_to_mdb(addr, mc);
2168
2169 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2170 mc->entry_type != ENTRYTYPE_MACv6)
2171 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2172 pgid->index);
2173
2174 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2175 mc->entry_type);
2176}
2177EXPORT_SYMBOL(ocelot_port_mdb_add);
2178
2179int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
2180 const struct switchdev_obj_port_mdb *mdb,
2181 const struct net_device *bridge)
2182{
2183 unsigned char addr[ETH_ALEN];
2184 struct ocelot_multicast *mc;
2185 struct ocelot_pgid *pgid;
2186 u16 vid = mdb->vid;
2187
2188 if (!vid)
2189 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2190
2191 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2192 if (!mc)
2193 return -ENOENT;
2194
2195 ocelot_encode_ports_to_mdb(addr, mc);
2196 ocelot_mact_forget(ocelot, addr, vid);
2197
2198 ocelot_pgid_free(ocelot, mc->pgid);
2199 mc->ports &= ~BIT(port);
2200 if (!mc->ports) {
2201 list_del(&mc->list);
2202 devm_kfree(ocelot->dev, mc);
2203 return 0;
2204 }
2205
2206 /* We have a PGID with fewer ports now */
2207 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2208 if (IS_ERR(pgid))
2209 return PTR_ERR(pgid);
2210 mc->pgid = pgid;
2211
2212 ocelot_encode_ports_to_mdb(addr, mc);
2213
2214 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2215 mc->entry_type != ENTRYTYPE_MACv6)
2216 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2217 pgid->index);
2218
2219 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2220 mc->entry_type);
2221}
2222EXPORT_SYMBOL(ocelot_port_mdb_del);
2223
2224int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
2225 struct net_device *bridge, int bridge_num,
2226 struct netlink_ext_ack *extack)
2227{
2228 struct ocelot_port *ocelot_port = ocelot->ports[port];
2229 int err;
2230
2231 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
2232 if (err)
2233 return err;
2234
2235 mutex_lock(&ocelot->fwd_domain_lock);
2236
2237 ocelot_port->bridge = bridge;
2238 ocelot_port->bridge_num = bridge_num;
2239
2240 ocelot_apply_bridge_fwd_mask(ocelot, true);
2241
2242 mutex_unlock(&ocelot->fwd_domain_lock);
2243
2244 if (br_vlan_enabled(bridge))
2245 return 0;
2246
2247 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
2248}
2249EXPORT_SYMBOL(ocelot_port_bridge_join);
2250
2251void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
2252 struct net_device *bridge)
2253{
2254 struct ocelot_port *ocelot_port = ocelot->ports[port];
2255
2256 mutex_lock(&ocelot->fwd_domain_lock);
2257
2258 if (!br_vlan_enabled(bridge))
2259 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
2260
2261 ocelot_port->bridge = NULL;
2262 ocelot_port->bridge_num = -1;
2263
2264 ocelot_port_set_pvid(ocelot, port, NULL);
2265 ocelot_port_manage_port_tag(ocelot, port);
2266 ocelot_apply_bridge_fwd_mask(ocelot, false);
2267
2268 mutex_unlock(&ocelot->fwd_domain_lock);
2269}
2270EXPORT_SYMBOL(ocelot_port_bridge_leave);
2271
2272static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
2273{
2274 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
2275 int i, port, lag;
2276
2277 /* Reset destination and aggregation PGIDS */
2278 for_each_unicast_dest_pgid(ocelot, port)
2279 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2280
2281 for_each_aggr_pgid(ocelot, i)
2282 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
2283 ANA_PGID_PGID, i);
2284
2285 /* The visited ports bitmask holds the list of ports offloading any
2286 * bonding interface. Initially we mark all these ports as unvisited,
2287 * then every time we visit a port in this bitmask, we know that it is
2288 * the lowest numbered port, i.e. the one whose logical ID == physical
2289 * port ID == LAG ID. So we mark as visited all further ports in the
2290 * bitmask that are offloading the same bonding interface. This way,
2291 * we set up the aggregation PGIDs only once per bonding interface.
2292 */
2293 for (port = 0; port < ocelot->num_phys_ports; port++) {
2294 struct ocelot_port *ocelot_port = ocelot->ports[port];
2295
2296 if (!ocelot_port || !ocelot_port->bond)
2297 continue;
2298
2299 visited &= ~BIT(port);
2300 }
2301
2302 /* Now, set PGIDs for each active LAG */
2303 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
2304 struct net_device *bond = ocelot->ports[lag]->bond;
2305 int num_active_ports = 0;
2306 unsigned long bond_mask;
2307 u8 aggr_idx[16];
2308
2309 if (!bond || (visited & BIT(lag)))
2310 continue;
2311
2312 bond_mask = ocelot_get_bond_mask(ocelot, bond);
2313
2314 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
2315 struct ocelot_port *ocelot_port = ocelot->ports[port];
2316
2317 // Destination mask
2318 ocelot_write_rix(ocelot, bond_mask,
2319 ANA_PGID_PGID, port);
2320
2321 if (ocelot_port->lag_tx_active)
2322 aggr_idx[num_active_ports++] = port;
2323 }
2324
2325 for_each_aggr_pgid(ocelot, i) {
2326 u32 ac;
2327
2328 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
2329 ac &= ~bond_mask;
2330 /* Don't do division by zero if there was no active
2331 * port. Just make all aggregation codes zero.
2332 */
2333 if (num_active_ports)
2334 ac |= BIT(aggr_idx[i % num_active_ports]);
2335 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
2336 }
2337
2338 /* Mark all ports in the same LAG as visited to avoid applying
2339 * the same config again.
2340 */
2341 for (port = lag; port < ocelot->num_phys_ports; port++) {
2342 struct ocelot_port *ocelot_port = ocelot->ports[port];
2343
2344 if (!ocelot_port)
2345 continue;
2346
2347 if (ocelot_port->bond == bond)
2348 visited |= BIT(port);
2349 }
2350 }
2351}
2352
2353/* When offloading a bonding interface, the switch ports configured under the
2354 * same bond must have the same logical port ID, equal to the physical port ID
2355 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2356 * bridged mode, each port has a logical port ID equal to its physical port ID.
2357 */
2358static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2359{
2360 int port;
2361
2362 for (port = 0; port < ocelot->num_phys_ports; port++) {
2363 struct ocelot_port *ocelot_port = ocelot->ports[port];
2364 struct net_device *bond;
2365
2366 if (!ocelot_port)
2367 continue;
2368
2369 bond = ocelot_port->bond;
2370 if (bond) {
2371 int lag = ocelot_bond_get_id(ocelot, bond);
2372
2373 ocelot_rmw_gix(ocelot,
2374 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2375 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2376 ANA_PORT_PORT_CFG, port);
2377 } else {
2378 ocelot_rmw_gix(ocelot,
2379 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2380 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2381 ANA_PORT_PORT_CFG, port);
2382 }
2383 }
2384}
2385
2386static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2387 unsigned long from_mask, unsigned long to_mask)
2388{
2389 unsigned char addr[ETH_ALEN];
2390 struct ocelot_pgid *pgid;
2391 u16 vid = mc->vid;
2392
2393 dev_dbg(ocelot->dev,
2394 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n",
2395 mc->addr, mc->vid, from_mask, to_mask);
2396
2397 /* First clean up the current port mask from hardware, because
2398 * we'll be modifying it.
2399 */
2400 ocelot_pgid_free(ocelot, mc->pgid);
2401 ocelot_encode_ports_to_mdb(addr, mc);
2402 ocelot_mact_forget(ocelot, addr, vid);
2403
2404 mc->ports &= ~from_mask;
2405 mc->ports |= to_mask;
2406
2407 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2408 if (IS_ERR(pgid)) {
2409 dev_err(ocelot->dev,
2410 "Cannot allocate PGID for mdb %pM vid %d\n",
2411 mc->addr, mc->vid);
2412 devm_kfree(ocelot->dev, mc);
2413 return PTR_ERR(pgid);
2414 }
2415 mc->pgid = pgid;
2416
2417 ocelot_encode_ports_to_mdb(addr, mc);
2418
2419 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2420 mc->entry_type != ENTRYTYPE_MACv6)
2421 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2422 pgid->index);
2423
2424 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2425 mc->entry_type);
2426}
2427
2428int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2429 unsigned long to_mask)
2430{
2431 struct ocelot_multicast *mc;
2432 int err;
2433
2434 list_for_each_entry(mc, &ocelot->multicast, list) {
2435 if (!(mc->ports & from_mask))
2436 continue;
2437
2438 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2439 if (err)
2440 return err;
2441 }
2442
2443 return 0;
2444}
2445EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs);
2446
2447/* Documentation for PORTID_VAL says:
2448 * Logical port number for front port. If port is not a member of a LLAG,
2449 * then PORTID must be set to the physical port number.
2450 * If port is a member of a LLAG, then PORTID must be set to the common
2451 * PORTID_VAL used for all member ports of the LLAG.
2452 * The value must not exceed the number of physical ports on the device.
2453 *
2454 * This means we have little choice but to migrate FDB entries pointing towards
2455 * a logical port when that changes.
2456 */
2457static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2458 struct net_device *bond,
2459 int lag)
2460{
2461 struct ocelot_lag_fdb *fdb;
2462 int err;
2463
2464 lockdep_assert_held(&ocelot->fwd_domain_lock);
2465
2466 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2467 if (fdb->bond != bond)
2468 continue;
2469
2470 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2471 if (err) {
2472 dev_err(ocelot->dev,
2473 "failed to delete LAG %s FDB %pM vid %d: %pe\n",
2474 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2475 }
2476
2477 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2478 ENTRYTYPE_LOCKED);
2479 if (err) {
2480 dev_err(ocelot->dev,
2481 "failed to migrate LAG %s FDB %pM vid %d: %pe\n",
2482 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2483 }
2484 }
2485}
2486
2487int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2488 struct net_device *bond,
2489 struct netdev_lag_upper_info *info,
2490 struct netlink_ext_ack *extack)
2491{
2492 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2493 NL_SET_ERR_MSG_MOD(extack,
2494 "Can only offload LAG using hash TX type");
2495 return -EOPNOTSUPP;
2496 }
2497
2498 mutex_lock(&ocelot->fwd_domain_lock);
2499
2500 ocelot->ports[port]->bond = bond;
2501
2502 ocelot_setup_logical_port_ids(ocelot);
2503 ocelot_apply_bridge_fwd_mask(ocelot, true);
2504 ocelot_set_aggr_pgids(ocelot);
2505
2506 mutex_unlock(&ocelot->fwd_domain_lock);
2507
2508 return 0;
2509}
2510EXPORT_SYMBOL(ocelot_port_lag_join);
2511
2512void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2513 struct net_device *bond)
2514{
2515 int old_lag_id, new_lag_id;
2516
2517 mutex_lock(&ocelot->fwd_domain_lock);
2518
2519 old_lag_id = ocelot_bond_get_id(ocelot, bond);
2520
2521 ocelot->ports[port]->bond = NULL;
2522
2523 ocelot_setup_logical_port_ids(ocelot);
2524 ocelot_apply_bridge_fwd_mask(ocelot, false);
2525 ocelot_set_aggr_pgids(ocelot);
2526
2527 new_lag_id = ocelot_bond_get_id(ocelot, bond);
2528
2529 if (new_lag_id >= 0 && old_lag_id != new_lag_id)
2530 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2531
2532 mutex_unlock(&ocelot->fwd_domain_lock);
2533}
2534EXPORT_SYMBOL(ocelot_port_lag_leave);
2535
2536void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2537{
2538 struct ocelot_port *ocelot_port = ocelot->ports[port];
2539
2540 mutex_lock(&ocelot->fwd_domain_lock);
2541
2542 ocelot_port->lag_tx_active = lag_tx_active;
2543
2544 /* Rebalance the LAGs */
2545 ocelot_set_aggr_pgids(ocelot);
2546
2547 mutex_unlock(&ocelot->fwd_domain_lock);
2548}
2549EXPORT_SYMBOL(ocelot_port_lag_change);
2550
2551int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2552 const unsigned char *addr, u16 vid,
2553 const struct net_device *bridge)
2554{
2555 struct ocelot_lag_fdb *fdb;
2556 int lag, err;
2557
2558 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL);
2559 if (!fdb)
2560 return -ENOMEM;
2561
2562 mutex_lock(&ocelot->fwd_domain_lock);
2563
2564 if (!vid)
2565 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2566
2567 ether_addr_copy(fdb->addr, addr);
2568 fdb->vid = vid;
2569 fdb->bond = bond;
2570
2571 lag = ocelot_bond_get_id(ocelot, bond);
2572
2573 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2574 if (err) {
2575 mutex_unlock(&ocelot->fwd_domain_lock);
2576 kfree(fdb);
2577 return err;
2578 }
2579
2580 list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2581 mutex_unlock(&ocelot->fwd_domain_lock);
2582
2583 return 0;
2584}
2585EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add);
2586
2587int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2588 const unsigned char *addr, u16 vid,
2589 const struct net_device *bridge)
2590{
2591 struct ocelot_lag_fdb *fdb, *tmp;
2592
2593 mutex_lock(&ocelot->fwd_domain_lock);
2594
2595 if (!vid)
2596 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2597
2598 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2599 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid ||
2600 fdb->bond != bond)
2601 continue;
2602
2603 ocelot_mact_forget(ocelot, addr, vid);
2604 list_del(&fdb->list);
2605 mutex_unlock(&ocelot->fwd_domain_lock);
2606 kfree(fdb);
2607
2608 return 0;
2609 }
2610
2611 mutex_unlock(&ocelot->fwd_domain_lock);
2612
2613 return -ENOENT;
2614}
2615EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del);
2616
2617/* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2618 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2619 * In the special case that it's the NPI port that we're configuring, the
2620 * length of the tag and optional prefix needs to be accounted for privately,
2621 * in order to be able to sustain communication at the requested @sdu.
2622 */
2623void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2624{
2625 struct ocelot_port *ocelot_port = ocelot->ports[port];
2626 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2627 int pause_start, pause_stop;
2628 int atop, atop_tot;
2629
2630 if (port == ocelot->npi) {
2631 maxlen += OCELOT_TAG_LEN;
2632
2633 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2634 maxlen += OCELOT_SHORT_PREFIX_LEN;
2635 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2636 maxlen += OCELOT_LONG_PREFIX_LEN;
2637 }
2638
2639 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2640
2641 /* Set Pause watermark hysteresis */
2642 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2643 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2644 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2645 pause_start);
2646 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2647 pause_stop);
2648
2649 /* Tail dropping watermarks */
2650 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2651 OCELOT_BUFFER_CELL_SZ;
2652 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2653 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2654 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2655}
2656EXPORT_SYMBOL(ocelot_port_set_maxlen);
2657
2658int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2659{
2660 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2661
2662 if (port == ocelot->npi) {
2663 max_mtu -= OCELOT_TAG_LEN;
2664
2665 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2666 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2667 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2668 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2669 }
2670
2671 return max_mtu;
2672}
2673EXPORT_SYMBOL(ocelot_get_max_mtu);
2674
2675static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2676 bool enabled)
2677{
2678 struct ocelot_port *ocelot_port = ocelot->ports[port];
2679 u32 val = 0;
2680
2681 if (enabled)
2682 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2683
2684 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2685 ANA_PORT_PORT_CFG, port);
2686
2687 ocelot_port->learn_ena = enabled;
2688}
2689
2690static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2691 bool enabled)
2692{
2693 u32 val = 0;
2694
2695 if (enabled)
2696 val = BIT(port);
2697
2698 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2699}
2700
2701static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2702 bool enabled)
2703{
2704 u32 val = 0;
2705
2706 if (enabled)
2707 val = BIT(port);
2708
2709 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2710 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
2711 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
2712}
2713
2714static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2715 bool enabled)
2716{
2717 u32 val = 0;
2718
2719 if (enabled)
2720 val = BIT(port);
2721
2722 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2723}
2724
2725int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2726 struct switchdev_brport_flags flags)
2727{
2728 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2729 BR_BCAST_FLOOD))
2730 return -EINVAL;
2731
2732 return 0;
2733}
2734EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2735
2736void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2737 struct switchdev_brport_flags flags)
2738{
2739 if (flags.mask & BR_LEARNING)
2740 ocelot_port_set_learning(ocelot, port,
2741 !!(flags.val & BR_LEARNING));
2742
2743 if (flags.mask & BR_FLOOD)
2744 ocelot_port_set_ucast_flood(ocelot, port,
2745 !!(flags.val & BR_FLOOD));
2746
2747 if (flags.mask & BR_MCAST_FLOOD)
2748 ocelot_port_set_mcast_flood(ocelot, port,
2749 !!(flags.val & BR_MCAST_FLOOD));
2750
2751 if (flags.mask & BR_BCAST_FLOOD)
2752 ocelot_port_set_bcast_flood(ocelot, port,
2753 !!(flags.val & BR_BCAST_FLOOD));
2754}
2755EXPORT_SYMBOL(ocelot_port_bridge_flags);
2756
2757int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
2758{
2759 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2760
2761 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
2762}
2763EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio);
2764
2765int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
2766{
2767 if (prio >= OCELOT_NUM_TC)
2768 return -ERANGE;
2769
2770 ocelot_rmw_gix(ocelot,
2771 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio),
2772 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M,
2773 ANA_PORT_QOS_CFG,
2774 port);
2775
2776 return ocelot_update_vlan_reclassify_rule(ocelot, port);
2777}
2778EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio);
2779
2780int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
2781{
2782 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2783 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2784
2785 /* Return error if DSCP prioritization isn't enabled */
2786 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA))
2787 return -EOPNOTSUPP;
2788
2789 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) {
2790 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg);
2791 /* Re-read ANA_DSCP_CFG for the translated DSCP */
2792 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2793 }
2794
2795 /* If the DSCP value is not trusted, the QoS classification falls back
2796 * to VLAN PCP or port-based default.
2797 */
2798 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA))
2799 return -EOPNOTSUPP;
2800
2801 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg);
2802}
2803EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio);
2804
2805int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2806{
2807 int mask, val;
2808
2809 if (prio >= OCELOT_NUM_TC)
2810 return -ERANGE;
2811
2812 /* There is at least one app table priority (this one), so we need to
2813 * make sure DSCP prioritization is enabled on the port.
2814 * Also make sure DSCP translation is disabled
2815 * (dcbnl doesn't support it).
2816 */
2817 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2818 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2819
2820 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
2821 ANA_PORT_QOS_CFG, port);
2822
2823 /* Trust this DSCP value and map it to the given QoS class */
2824 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio);
2825
2826 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
2827
2828 return 0;
2829}
2830EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio);
2831
2832int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2833{
2834 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2835 int mask, i;
2836
2837 /* During a "dcb app replace" command, the new app table entry will be
2838 * added first, then the old one will be deleted. But the hardware only
2839 * supports one QoS class per DSCP value (duh), so if we blindly delete
2840 * the app table entry for this DSCP value, we end up deleting the
2841 * entry with the new priority. Avoid that by checking whether user
2842 * space wants to delete the priority which is currently configured, or
2843 * something else which is no longer current.
2844 */
2845 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio)
2846 return 0;
2847
2848 /* Untrust this DSCP value */
2849 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
2850
2851 for (i = 0; i < 64; i++) {
2852 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
2853
2854 /* There are still app table entries on the port, so we need to
2855 * keep DSCP enabled, nothing to do.
2856 */
2857 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)
2858 return 0;
2859 }
2860
2861 /* Disable DSCP QoS classification if there isn't any trusted
2862 * DSCP value left.
2863 */
2864 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2865 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2866
2867 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
2868
2869 return 0;
2870}
2871EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio);
2872
2873struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
2874 struct netlink_ext_ack *extack)
2875{
2876 struct ocelot_mirror *m = ocelot->mirror;
2877
2878 if (m) {
2879 if (m->to != to) {
2880 NL_SET_ERR_MSG_MOD(extack,
2881 "Mirroring already configured towards different egress port");
2882 return ERR_PTR(-EBUSY);
2883 }
2884
2885 refcount_inc(&m->refcount);
2886 return m;
2887 }
2888
2889 m = kzalloc(sizeof(*m), GFP_KERNEL);
2890 if (!m)
2891 return ERR_PTR(-ENOMEM);
2892
2893 m->to = to;
2894 refcount_set(&m->refcount, 1);
2895 ocelot->mirror = m;
2896
2897 /* Program the mirror port to hardware */
2898 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
2899
2900 return m;
2901}
2902
2903void ocelot_mirror_put(struct ocelot *ocelot)
2904{
2905 struct ocelot_mirror *m = ocelot->mirror;
2906
2907 if (!refcount_dec_and_test(&m->refcount))
2908 return;
2909
2910 ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
2911 ocelot->mirror = NULL;
2912 kfree(m);
2913}
2914
2915int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
2916 bool ingress, struct netlink_ext_ack *extack)
2917{
2918 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
2919
2920 if (IS_ERR(m))
2921 return PTR_ERR(m);
2922
2923 if (ingress) {
2924 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2925 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2926 ANA_PORT_PORT_CFG, from);
2927 } else {
2928 ocelot_rmw(ocelot, BIT(from), BIT(from),
2929 ANA_EMIRRORPORTS);
2930 }
2931
2932 return 0;
2933}
2934EXPORT_SYMBOL_GPL(ocelot_port_mirror_add);
2935
2936void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
2937{
2938 if (ingress) {
2939 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2940 ANA_PORT_PORT_CFG, from);
2941 } else {
2942 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
2943 }
2944
2945 ocelot_mirror_put(ocelot);
2946}
2947EXPORT_SYMBOL_GPL(ocelot_port_mirror_del);
2948
2949static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port)
2950{
2951 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2952
2953 netdev_reset_tc(dev);
2954 ocelot_port_change_fp(ocelot, port, 0);
2955}
2956
2957int ocelot_port_mqprio(struct ocelot *ocelot, int port,
2958 struct tc_mqprio_qopt_offload *mqprio)
2959{
2960 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2961 struct netlink_ext_ack *extack = mqprio->extack;
2962 struct tc_mqprio_qopt *qopt = &mqprio->qopt;
2963 int num_tc = qopt->num_tc;
2964 int tc, err;
2965
2966 if (!num_tc) {
2967 ocelot_port_reset_mqprio(ocelot, port);
2968 return 0;
2969 }
2970
2971 err = netdev_set_num_tc(dev, num_tc);
2972 if (err)
2973 return err;
2974
2975 for (tc = 0; tc < num_tc; tc++) {
2976 if (qopt->count[tc] != 1) {
2977 NL_SET_ERR_MSG_MOD(extack,
2978 "Only one TXQ per TC supported");
2979 return -EINVAL;
2980 }
2981
2982 err = netdev_set_tc_queue(dev, tc, 1, qopt->offset[tc]);
2983 if (err)
2984 goto err_reset_tc;
2985 }
2986
2987 err = netif_set_real_num_tx_queues(dev, num_tc);
2988 if (err)
2989 goto err_reset_tc;
2990
2991 ocelot_port_change_fp(ocelot, port, mqprio->preemptible_tcs);
2992
2993 return 0;
2994
2995err_reset_tc:
2996 ocelot_port_reset_mqprio(ocelot, port);
2997 return err;
2998}
2999EXPORT_SYMBOL_GPL(ocelot_port_mqprio);
3000
3001void ocelot_init_port(struct ocelot *ocelot, int port)
3002{
3003 struct ocelot_port *ocelot_port = ocelot->ports[port];
3004
3005 skb_queue_head_init(&ocelot_port->tx_skbs);
3006
3007 /* Basic L2 initialization */
3008
3009 /* Set MAC IFG Gaps
3010 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
3011 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
3012 */
3013 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
3014 DEV_MAC_IFG_CFG);
3015
3016 /* Load seed (0) and set MAC HDX late collision */
3017 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
3018 DEV_MAC_HDX_CFG_SEED_LOAD,
3019 DEV_MAC_HDX_CFG);
3020 mdelay(1);
3021 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
3022 DEV_MAC_HDX_CFG);
3023
3024 /* Set Max Length and maximum tags allowed */
3025 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
3026 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
3027 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
3028 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
3029 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
3030 DEV_MAC_TAGS_CFG);
3031
3032 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
3033 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
3034 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
3035
3036 /* Enable transmission of pause frames */
3037 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
3038
3039 /* Drop frames with multicast source address */
3040 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
3041 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
3042 ANA_PORT_DROP_CFG, port);
3043
3044 /* Set default VLAN and tag type to 8021Q. */
3045 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
3046 REW_PORT_VLAN_CFG_PORT_TPID_M,
3047 REW_PORT_VLAN_CFG, port);
3048
3049 /* Disable source address learning for standalone mode */
3050 ocelot_port_set_learning(ocelot, port, false);
3051
3052 /* Set the port's initial logical port ID value, enable receiving
3053 * frames on it, and configure the MAC address learning type to
3054 * automatic.
3055 */
3056 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
3057 ANA_PORT_PORT_CFG_RECV_ENA |
3058 ANA_PORT_PORT_CFG_PORTID_VAL(port),
3059 ANA_PORT_PORT_CFG, port);
3060
3061 /* Enable vcap lookups */
3062 ocelot_vcap_enable(ocelot, port);
3063}
3064EXPORT_SYMBOL(ocelot_init_port);
3065
3066/* Configure and enable the CPU port module, which is a set of queues
3067 * accessible through register MMIO, frame DMA or Ethernet (in case
3068 * NPI mode is used).
3069 */
3070static void ocelot_cpu_port_init(struct ocelot *ocelot)
3071{
3072 int cpu = ocelot->num_phys_ports;
3073
3074 /* The unicast destination PGID for the CPU port module is unused */
3075 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
3076 /* Instead set up a multicast destination PGID for traffic copied to
3077 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
3078 * addresses will be copied to the CPU via this PGID.
3079 */
3080 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
3081 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
3082 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
3083 ANA_PORT_PORT_CFG, cpu);
3084
3085 /* Enable CPU port module */
3086 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
3087 /* CPU port Injection/Extraction configuration */
3088 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
3089 OCELOT_TAG_PREFIX_NONE);
3090 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
3091 OCELOT_TAG_PREFIX_NONE);
3092
3093 /* Configure the CPU port to be VLAN aware */
3094 ocelot_write_gix(ocelot,
3095 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) |
3096 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
3097 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
3098 ANA_PORT_VLAN_CFG, cpu);
3099}
3100
3101static void ocelot_detect_features(struct ocelot *ocelot)
3102{
3103 int mmgt, eq_ctrl;
3104
3105 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
3106 * the number of 240-byte free memory words (aka 4-cell chunks) and not
3107 * 192 bytes as the documentation incorrectly says.
3108 */
3109 mmgt = ocelot_read(ocelot, SYS_MMGT);
3110 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
3111
3112 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
3113 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
3114}
3115
3116static int ocelot_mem_init_status(struct ocelot *ocelot)
3117{
3118 unsigned int val;
3119 int err;
3120
3121 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
3122 &val);
3123
3124 return err ?: val;
3125}
3126
3127int ocelot_reset(struct ocelot *ocelot)
3128{
3129 int err;
3130 u32 val;
3131
3132 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
3133 if (err)
3134 return err;
3135
3136 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
3137 if (err)
3138 return err;
3139
3140 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be
3141 * 100us) before enabling the switch core.
3142 */
3143 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val,
3144 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US);
3145 if (err)
3146 return err;
3147
3148 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
3149 if (err)
3150 return err;
3151
3152 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
3153}
3154EXPORT_SYMBOL(ocelot_reset);
3155
3156int ocelot_init(struct ocelot *ocelot)
3157{
3158 int i, ret;
3159 u32 port;
3160
3161 if (ocelot->ops->reset) {
3162 ret = ocelot->ops->reset(ocelot);
3163 if (ret) {
3164 dev_err(ocelot->dev, "Switch reset failed\n");
3165 return ret;
3166 }
3167 }
3168
3169 mutex_init(&ocelot->mact_lock);
3170 mutex_init(&ocelot->fwd_domain_lock);
3171 spin_lock_init(&ocelot->ptp_clock_lock);
3172 spin_lock_init(&ocelot->ts_id_lock);
3173 spin_lock_init(&ocelot->inj_lock);
3174 spin_lock_init(&ocelot->xtr_lock);
3175
3176 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
3177 if (!ocelot->owq)
3178 return -ENOMEM;
3179
3180 ret = ocelot_stats_init(ocelot);
3181 if (ret)
3182 goto err_stats_init;
3183
3184 INIT_LIST_HEAD(&ocelot->multicast);
3185 INIT_LIST_HEAD(&ocelot->pgids);
3186 INIT_LIST_HEAD(&ocelot->vlans);
3187 INIT_LIST_HEAD(&ocelot->lag_fdbs);
3188 ocelot_detect_features(ocelot);
3189 ocelot_mact_init(ocelot);
3190 ocelot_vlan_init(ocelot);
3191 ocelot_vcap_init(ocelot);
3192 ocelot_cpu_port_init(ocelot);
3193
3194 if (ocelot->ops->psfp_init)
3195 ocelot->ops->psfp_init(ocelot);
3196
3197 if (ocelot->mm_supported) {
3198 ret = ocelot_mm_init(ocelot);
3199 if (ret)
3200 goto err_mm_init;
3201 }
3202
3203 for (port = 0; port < ocelot->num_phys_ports; port++) {
3204 /* Clear all counters (5 groups) */
3205 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
3206 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
3207 SYS_STAT_CFG);
3208 }
3209
3210 /* Only use S-Tag */
3211 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
3212
3213 /* Aggregation mode */
3214 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
3215 ANA_AGGR_CFG_AC_DMAC_ENA |
3216 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
3217 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
3218 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
3219 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
3220 ANA_AGGR_CFG);
3221
3222 /* Set MAC age time to default value. The entry is aged after
3223 * 2*AGE_PERIOD
3224 */
3225 ocelot_write(ocelot,
3226 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
3227 ANA_AUTOAGE);
3228
3229 /* Disable learning for frames discarded by VLAN ingress filtering */
3230 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
3231
3232 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
3233 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
3234 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
3235
3236 /* Setup flooding PGIDs */
3237 for (i = 0; i < ocelot->num_flooding_pgids; i++)
3238 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
3239 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
3240 ANA_FLOODING_FLD_UNICAST(PGID_UC),
3241 ANA_FLOODING, i);
3242 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
3243 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
3244 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
3245 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
3246 ANA_FLOODING_IPMC);
3247
3248 for (port = 0; port < ocelot->num_phys_ports; port++) {
3249 /* Transmit the frame to the local port. */
3250 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
3251 /* Do not forward BPDU frames to the front ports. */
3252 ocelot_write_gix(ocelot,
3253 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
3254 ANA_PORT_CPU_FWD_BPDU_CFG,
3255 port);
3256 /* Ensure bridging is disabled */
3257 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
3258 }
3259
3260 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
3261 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
3262
3263 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
3264 }
3265
3266 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
3267
3268 /* Allow broadcast and unknown L2 multicast to the CPU. */
3269 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3270 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3271 ANA_PGID_PGID, PGID_MC);
3272 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3273 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3274 ANA_PGID_PGID, PGID_BC);
3275 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
3276 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
3277
3278 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
3279 * registers endianness.
3280 */
3281 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
3282 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
3283 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
3284 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
3285 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
3286 ANA_CPUQ_CFG_CPUQ_LRN(2) |
3287 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
3288 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
3289 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
3290 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
3291 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
3292 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
3293 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
3294 for (i = 0; i < 16; i++)
3295 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
3296 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
3297 ANA_CPUQ_8021_CFG, i);
3298
3299 return 0;
3300
3301err_mm_init:
3302 ocelot_stats_deinit(ocelot);
3303err_stats_init:
3304 destroy_workqueue(ocelot->owq);
3305 return ret;
3306}
3307EXPORT_SYMBOL(ocelot_init);
3308
3309void ocelot_deinit(struct ocelot *ocelot)
3310{
3311 ocelot_stats_deinit(ocelot);
3312 destroy_workqueue(ocelot->owq);
3313}
3314EXPORT_SYMBOL(ocelot_deinit);
3315
3316void ocelot_deinit_port(struct ocelot *ocelot, int port)
3317{
3318 struct ocelot_port *ocelot_port = ocelot->ports[port];
3319
3320 skb_queue_purge(&ocelot_port->tx_skbs);
3321}
3322EXPORT_SYMBOL(ocelot_deinit_port);
3323
3324MODULE_DESCRIPTION("Microsemi Ocelot switch family library");
3325MODULE_LICENSE("Dual MIT/GPL");
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/etherdevice.h>
8#include <linux/ethtool.h>
9#include <linux/if_bridge.h>
10#include <linux/if_ether.h>
11#include <linux/if_vlan.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/netdevice.h>
16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/skbuff.h>
19#include <linux/iopoll.h>
20#include <net/arp.h>
21#include <net/netevent.h>
22#include <net/rtnetlink.h>
23#include <net/switchdev.h>
24
25#include "ocelot.h"
26#include "ocelot_ace.h"
27
28#define TABLE_UPDATE_SLEEP_US 10
29#define TABLE_UPDATE_TIMEOUT_US 100000
30
31/* MAC table entry types.
32 * ENTRYTYPE_NORMAL is subject to aging.
33 * ENTRYTYPE_LOCKED is not subject to aging.
34 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
35 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
36 */
37enum macaccess_entry_type {
38 ENTRYTYPE_NORMAL = 0,
39 ENTRYTYPE_LOCKED,
40 ENTRYTYPE_MACv4,
41 ENTRYTYPE_MACv6,
42};
43
44struct ocelot_mact_entry {
45 u8 mac[ETH_ALEN];
46 u16 vid;
47 enum macaccess_entry_type type;
48};
49
50static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
51{
52 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
53}
54
55static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
56{
57 u32 val;
58
59 return readx_poll_timeout(ocelot_mact_read_macaccess,
60 ocelot, val,
61 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
62 MACACCESS_CMD_IDLE,
63 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
64}
65
66static void ocelot_mact_select(struct ocelot *ocelot,
67 const unsigned char mac[ETH_ALEN],
68 unsigned int vid)
69{
70 u32 macl = 0, mach = 0;
71
72 /* Set the MAC address to handle and the vlan associated in a format
73 * understood by the hardware.
74 */
75 mach |= vid << 16;
76 mach |= mac[0] << 8;
77 mach |= mac[1] << 0;
78 macl |= mac[2] << 24;
79 macl |= mac[3] << 16;
80 macl |= mac[4] << 8;
81 macl |= mac[5] << 0;
82
83 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
84 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
85
86}
87
88static int ocelot_mact_learn(struct ocelot *ocelot, int port,
89 const unsigned char mac[ETH_ALEN],
90 unsigned int vid,
91 enum macaccess_entry_type type)
92{
93 ocelot_mact_select(ocelot, mac, vid);
94
95 /* Issue a write command */
96 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
97 ANA_TABLES_MACACCESS_DEST_IDX(port) |
98 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
99 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
100 ANA_TABLES_MACACCESS);
101
102 return ocelot_mact_wait_for_completion(ocelot);
103}
104
105static int ocelot_mact_forget(struct ocelot *ocelot,
106 const unsigned char mac[ETH_ALEN],
107 unsigned int vid)
108{
109 ocelot_mact_select(ocelot, mac, vid);
110
111 /* Issue a forget command */
112 ocelot_write(ocelot,
113 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
114 ANA_TABLES_MACACCESS);
115
116 return ocelot_mact_wait_for_completion(ocelot);
117}
118
119static void ocelot_mact_init(struct ocelot *ocelot)
120{
121 /* Configure the learning mode entries attributes:
122 * - Do not copy the frame to the CPU extraction queues.
123 * - Use the vlan and mac_cpoy for dmac lookup.
124 */
125 ocelot_rmw(ocelot, 0,
126 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
127 | ANA_AGENCTRL_LEARN_FWD_KILL
128 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
129 ANA_AGENCTRL);
130
131 /* Clear the MAC table */
132 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
133}
134
135static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port)
136{
137 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
138 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
139 ANA_PORT_VCAP_S2_CFG, port->chip_port);
140}
141
142static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
143{
144 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
145}
146
147static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
148{
149 u32 val;
150
151 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
152 ocelot,
153 val,
154 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
155 ANA_TABLES_VLANACCESS_CMD_IDLE,
156 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
157}
158
159static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
160{
161 /* Select the VID to configure */
162 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
163 ANA_TABLES_VLANTIDX);
164 /* Set the vlan port members mask and issue a write command */
165 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
166 ANA_TABLES_VLANACCESS_CMD_WRITE,
167 ANA_TABLES_VLANACCESS);
168
169 return ocelot_vlant_wait_for_completion(ocelot);
170}
171
172static void ocelot_vlan_mode(struct ocelot_port *port,
173 netdev_features_t features)
174{
175 struct ocelot *ocelot = port->ocelot;
176 u8 p = port->chip_port;
177 u32 val;
178
179 /* Filtering */
180 val = ocelot_read(ocelot, ANA_VLANMASK);
181 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
182 val |= BIT(p);
183 else
184 val &= ~BIT(p);
185 ocelot_write(ocelot, val, ANA_VLANMASK);
186}
187
188static void ocelot_vlan_port_apply(struct ocelot *ocelot,
189 struct ocelot_port *port)
190{
191 u32 val;
192
193 /* Ingress clasification (ANA_PORT_VLAN_CFG) */
194 /* Default vlan to clasify for untagged frames (may be zero) */
195 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid);
196 if (port->vlan_aware)
197 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
198 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
199
200 ocelot_rmw_gix(ocelot, val,
201 ANA_PORT_VLAN_CFG_VLAN_VID_M |
202 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
203 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
204 ANA_PORT_VLAN_CFG, port->chip_port);
205
206 /* Drop frames with multicast source address */
207 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA;
208 if (port->vlan_aware && !port->vid)
209 /* If port is vlan-aware and tagged, drop untagged and priority
210 * tagged frames.
211 */
212 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
213 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
214 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
215 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port);
216
217 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */
218 val = REW_TAG_CFG_TAG_TPID_CFG(0);
219
220 if (port->vlan_aware) {
221 if (port->vid)
222 /* Tag all frames except when VID == DEFAULT_VLAN */
223 val |= REW_TAG_CFG_TAG_CFG(1);
224 else
225 /* Tag all frames */
226 val |= REW_TAG_CFG_TAG_CFG(3);
227 }
228 ocelot_rmw_gix(ocelot, val,
229 REW_TAG_CFG_TAG_TPID_CFG_M |
230 REW_TAG_CFG_TAG_CFG_M,
231 REW_TAG_CFG, port->chip_port);
232
233 /* Set default VLAN and tag type to 8021Q. */
234 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) |
235 REW_PORT_VLAN_CFG_PORT_VID(port->vid);
236 ocelot_rmw_gix(ocelot, val,
237 REW_PORT_VLAN_CFG_PORT_TPID_M |
238 REW_PORT_VLAN_CFG_PORT_VID_M,
239 REW_PORT_VLAN_CFG, port->chip_port);
240}
241
242static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
243 bool untagged)
244{
245 struct ocelot_port *port = netdev_priv(dev);
246 struct ocelot *ocelot = port->ocelot;
247 int ret;
248
249 /* Add the port MAC address to with the right VLAN information */
250 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
251 ENTRYTYPE_LOCKED);
252
253 /* Make the port a member of the VLAN */
254 ocelot->vlan_mask[vid] |= BIT(port->chip_port);
255 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
256 if (ret)
257 return ret;
258
259 /* Default ingress vlan classification */
260 if (pvid)
261 port->pvid = vid;
262
263 /* Untagged egress vlan clasification */
264 if (untagged && port->vid != vid) {
265 if (port->vid) {
266 dev_err(ocelot->dev,
267 "Port already has a native VLAN: %d\n",
268 port->vid);
269 return -EBUSY;
270 }
271 port->vid = vid;
272 }
273
274 ocelot_vlan_port_apply(ocelot, port);
275
276 return 0;
277}
278
279static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
280{
281 struct ocelot_port *port = netdev_priv(dev);
282 struct ocelot *ocelot = port->ocelot;
283 int ret;
284
285 /* 8021q removes VID 0 on module unload for all interfaces
286 * with VLAN filtering feature. We need to keep it to receive
287 * untagged traffic.
288 */
289 if (vid == 0)
290 return 0;
291
292 /* Del the port MAC address to with the right VLAN information */
293 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
294
295 /* Stop the port from being a member of the vlan */
296 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port);
297 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
298 if (ret)
299 return ret;
300
301 /* Ingress */
302 if (port->pvid == vid)
303 port->pvid = 0;
304
305 /* Egress */
306 if (port->vid == vid)
307 port->vid = 0;
308
309 ocelot_vlan_port_apply(ocelot, port);
310
311 return 0;
312}
313
314static void ocelot_vlan_init(struct ocelot *ocelot)
315{
316 u16 port, vid;
317
318 /* Clear VLAN table, by default all ports are members of all VLANs */
319 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
320 ANA_TABLES_VLANACCESS);
321 ocelot_vlant_wait_for_completion(ocelot);
322
323 /* Configure the port VLAN memberships */
324 for (vid = 1; vid < VLAN_N_VID; vid++) {
325 ocelot->vlan_mask[vid] = 0;
326 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
327 }
328
329 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
330 * traffic. It is added automatically if 8021q module is loaded, but
331 * we can't rely on it since module may be not loaded.
332 */
333 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
334 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
335
336 /* Configure the CPU port to be VLAN aware */
337 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
338 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
339 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
340 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
341
342 /* Set vlan ingress filter mask to all ports but the CPU port by
343 * default.
344 */
345 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK);
346
347 for (port = 0; port < ocelot->num_phys_ports; port++) {
348 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
349 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
350 }
351}
352
353/* Watermark encode
354 * Bit 8: Unit; 0:1, 1:16
355 * Bit 7-0: Value to be multiplied with unit
356 */
357static u16 ocelot_wm_enc(u16 value)
358{
359 if (value >= BIT(8))
360 return BIT(8) | (value / 16);
361
362 return value;
363}
364
365static void ocelot_port_adjust_link(struct net_device *dev)
366{
367 struct ocelot_port *port = netdev_priv(dev);
368 struct ocelot *ocelot = port->ocelot;
369 u8 p = port->chip_port;
370 int speed, atop_wm, mode = 0;
371
372 switch (dev->phydev->speed) {
373 case SPEED_10:
374 speed = OCELOT_SPEED_10;
375 break;
376 case SPEED_100:
377 speed = OCELOT_SPEED_100;
378 break;
379 case SPEED_1000:
380 speed = OCELOT_SPEED_1000;
381 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
382 break;
383 case SPEED_2500:
384 speed = OCELOT_SPEED_2500;
385 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
386 break;
387 default:
388 netdev_err(dev, "Unsupported PHY speed: %d\n",
389 dev->phydev->speed);
390 return;
391 }
392
393 phy_print_status(dev->phydev);
394
395 if (!dev->phydev->link)
396 return;
397
398 /* Only full duplex supported for now */
399 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA |
400 mode, DEV_MAC_MODE_CFG);
401
402 /* Set MAC IFG Gaps
403 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
404 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
405 */
406 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG);
407
408 /* Load seed (0) and set MAC HDX late collision */
409 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
410 DEV_MAC_HDX_CFG_SEED_LOAD,
411 DEV_MAC_HDX_CFG);
412 mdelay(1);
413 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
414 DEV_MAC_HDX_CFG);
415
416 /* Disable HDX fast control */
417 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
418
419 /* SGMII only for now */
420 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
421 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
422
423 /* Enable PCS */
424 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
425
426 /* No aneg on SGMII */
427 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
428
429 /* No loopback */
430 ocelot_port_writel(port, 0, PCS1G_LB_CFG);
431
432 /* Set Max Length and maximum tags allowed */
433 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
434 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
435 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
436 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
437 DEV_MAC_TAGS_CFG);
438
439 /* Enable MAC module */
440 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA |
441 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
442
443 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
444 * reset */
445 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed),
446 DEV_CLOCK_CFG);
447
448 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
449 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
450 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG);
451
452 /* No PFC */
453 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
454 ANA_PFC_PFC_CFG, p);
455
456 /* Set Pause WM hysteresis
457 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
458 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
459 */
460 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
461 SYS_PAUSE_CFG_PAUSE_STOP(101) |
462 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p);
463
464 /* Core: Enable port for frame transfer */
465 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
466 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
467 QSYS_SWITCH_PORT_MODE_PORT_ENA,
468 QSYS_SWITCH_PORT_MODE, p);
469
470 /* Flow control */
471 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
472 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
473 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
474 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
475 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
476 SYS_MAC_FC_CFG, p);
477 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p);
478
479 /* Tail dropping watermark */
480 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
481 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
482 SYS_ATOP, p);
483 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
484}
485
486static int ocelot_port_open(struct net_device *dev)
487{
488 struct ocelot_port *port = netdev_priv(dev);
489 struct ocelot *ocelot = port->ocelot;
490 int err;
491
492 /* Enable receiving frames on the port, and activate auto-learning of
493 * MAC addresses.
494 */
495 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
496 ANA_PORT_PORT_CFG_RECV_ENA |
497 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port),
498 ANA_PORT_PORT_CFG, port->chip_port);
499
500 if (port->serdes) {
501 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET,
502 port->phy_mode);
503 if (err) {
504 netdev_err(dev, "Could not set mode of SerDes\n");
505 return err;
506 }
507 }
508
509 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link,
510 port->phy_mode);
511 if (err) {
512 netdev_err(dev, "Could not attach to PHY\n");
513 return err;
514 }
515
516 dev->phydev = port->phy;
517
518 phy_attached_info(port->phy);
519 phy_start(port->phy);
520 return 0;
521}
522
523static int ocelot_port_stop(struct net_device *dev)
524{
525 struct ocelot_port *port = netdev_priv(dev);
526
527 phy_disconnect(port->phy);
528
529 dev->phydev = NULL;
530
531 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG);
532 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
533 QSYS_SWITCH_PORT_MODE, port->chip_port);
534 return 0;
535}
536
537/* Generate the IFH for frame injection
538 *
539 * The IFH is a 128bit-value
540 * bit 127: bypass the analyzer processing
541 * bit 56-67: destination mask
542 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
543 * bit 20-27: cpu extraction queue mask
544 * bit 16: tag type 0: C-tag, 1: S-tag
545 * bit 0-11: VID
546 */
547static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
548{
549 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21);
550 ifh[1] = (0xf00 & info->port) >> 8;
551 ifh[2] = (0xff & info->port) << 24;
552 ifh[3] = (info->tag_type << 16) | info->vid;
553
554 return 0;
555}
556
557static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
558{
559 struct skb_shared_info *shinfo = skb_shinfo(skb);
560 struct ocelot_port *port = netdev_priv(dev);
561 struct ocelot *ocelot = port->ocelot;
562 u32 val, ifh[IFH_LEN];
563 struct frame_info info = {};
564 u8 grp = 0; /* Send everything on CPU group 0 */
565 unsigned int i, count, last;
566
567 val = ocelot_read(ocelot, QS_INJ_STATUS);
568 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
569 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
570 return NETDEV_TX_BUSY;
571
572 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
573 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
574
575 info.port = BIT(port->chip_port);
576 info.tag_type = IFH_TAG_TYPE_C;
577 info.vid = skb_vlan_tag_get(skb);
578
579 /* Check if timestamping is needed */
580 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) {
581 info.rew_op = port->ptp_cmd;
582 if (port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP)
583 info.rew_op |= (port->ts_id % 4) << 3;
584 }
585
586 ocelot_gen_ifh(ifh, &info);
587
588 for (i = 0; i < IFH_LEN; i++)
589 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
590 QS_INJ_WR, grp);
591
592 count = (skb->len + 3) / 4;
593 last = skb->len % 4;
594 for (i = 0; i < count; i++) {
595 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
596 }
597
598 /* Add padding */
599 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
600 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
601 i++;
602 }
603
604 /* Indicate EOF and valid bytes in last word */
605 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
606 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
607 QS_INJ_CTRL_EOF,
608 QS_INJ_CTRL, grp);
609
610 /* Add dummy CRC */
611 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
612 skb_tx_timestamp(skb);
613
614 dev->stats.tx_packets++;
615 dev->stats.tx_bytes += skb->len;
616
617 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP &&
618 port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
619 struct ocelot_skb *oskb =
620 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC);
621
622 if (unlikely(!oskb))
623 goto out;
624
625 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
626
627 oskb->skb = skb;
628 oskb->id = port->ts_id % 4;
629 port->ts_id++;
630
631 list_add_tail(&oskb->head, &port->skbs);
632
633 return NETDEV_TX_OK;
634 }
635
636out:
637 dev_kfree_skb_any(skb);
638 return NETDEV_TX_OK;
639}
640
641void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts)
642{
643 unsigned long flags;
644 u32 val;
645
646 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
647
648 /* Read current PTP time to get seconds */
649 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
650
651 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
652 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
653 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
654 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
655
656 /* Read packet HW timestamp from FIFO */
657 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
658 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
659
660 /* Sec has incremented since the ts was registered */
661 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
662 ts->tv_sec--;
663
664 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
665}
666EXPORT_SYMBOL(ocelot_get_hwtimestamp);
667
668static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr)
669{
670 struct ocelot_port *port = netdev_priv(dev);
671
672 return ocelot_mact_forget(port->ocelot, addr, port->pvid);
673}
674
675static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr)
676{
677 struct ocelot_port *port = netdev_priv(dev);
678
679 return ocelot_mact_learn(port->ocelot, PGID_CPU, addr, port->pvid,
680 ENTRYTYPE_LOCKED);
681}
682
683static void ocelot_set_rx_mode(struct net_device *dev)
684{
685 struct ocelot_port *port = netdev_priv(dev);
686 struct ocelot *ocelot = port->ocelot;
687 int i;
688 u32 val;
689
690 /* This doesn't handle promiscuous mode because the bridge core is
691 * setting IFF_PROMISC on all slave interfaces and all frames would be
692 * forwarded to the CPU port.
693 */
694 val = GENMASK(ocelot->num_phys_ports - 1, 0);
695 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
696 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
697
698 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync);
699}
700
701static int ocelot_port_get_phys_port_name(struct net_device *dev,
702 char *buf, size_t len)
703{
704 struct ocelot_port *port = netdev_priv(dev);
705 int ret;
706
707 ret = snprintf(buf, len, "p%d", port->chip_port);
708 if (ret >= len)
709 return -EINVAL;
710
711 return 0;
712}
713
714static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
715{
716 struct ocelot_port *port = netdev_priv(dev);
717 struct ocelot *ocelot = port->ocelot;
718 const struct sockaddr *addr = p;
719
720 /* Learn the new net device MAC address in the mac table. */
721 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid,
722 ENTRYTYPE_LOCKED);
723 /* Then forget the previous one. */
724 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid);
725
726 ether_addr_copy(dev->dev_addr, addr->sa_data);
727 return 0;
728}
729
730static void ocelot_get_stats64(struct net_device *dev,
731 struct rtnl_link_stats64 *stats)
732{
733 struct ocelot_port *port = netdev_priv(dev);
734 struct ocelot *ocelot = port->ocelot;
735
736 /* Configure the port to read the stats from */
737 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port),
738 SYS_STAT_CFG);
739
740 /* Get Rx stats */
741 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
742 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
743 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
744 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
745 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
746 ocelot_read(ocelot, SYS_COUNT_RX_64) +
747 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
748 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
749 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
750 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
751 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
752 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
753 stats->rx_dropped = dev->stats.rx_dropped;
754
755 /* Get Tx stats */
756 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
757 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
758 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
759 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
760 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
761 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
762 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
763 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
764 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
765 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
766}
767
768static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
769 struct net_device *dev, const unsigned char *addr,
770 u16 vid, u16 flags,
771 struct netlink_ext_ack *extack)
772{
773 struct ocelot_port *port = netdev_priv(dev);
774 struct ocelot *ocelot = port->ocelot;
775
776 if (!vid) {
777 if (!port->vlan_aware)
778 /* If the bridge is not VLAN aware and no VID was
779 * provided, set it to pvid to ensure the MAC entry
780 * matches incoming untagged packets
781 */
782 vid = port->pvid;
783 else
784 /* If the bridge is VLAN aware a VID must be provided as
785 * otherwise the learnt entry wouldn't match any frame.
786 */
787 return -EINVAL;
788 }
789
790 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid,
791 ENTRYTYPE_LOCKED);
792}
793
794static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
795 struct net_device *dev,
796 const unsigned char *addr, u16 vid)
797{
798 struct ocelot_port *port = netdev_priv(dev);
799 struct ocelot *ocelot = port->ocelot;
800
801 return ocelot_mact_forget(ocelot, addr, vid);
802}
803
804struct ocelot_dump_ctx {
805 struct net_device *dev;
806 struct sk_buff *skb;
807 struct netlink_callback *cb;
808 int idx;
809};
810
811static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry,
812 struct ocelot_dump_ctx *dump)
813{
814 u32 portid = NETLINK_CB(dump->cb->skb).portid;
815 u32 seq = dump->cb->nlh->nlmsg_seq;
816 struct nlmsghdr *nlh;
817 struct ndmsg *ndm;
818
819 if (dump->idx < dump->cb->args[2])
820 goto skip;
821
822 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
823 sizeof(*ndm), NLM_F_MULTI);
824 if (!nlh)
825 return -EMSGSIZE;
826
827 ndm = nlmsg_data(nlh);
828 ndm->ndm_family = AF_BRIDGE;
829 ndm->ndm_pad1 = 0;
830 ndm->ndm_pad2 = 0;
831 ndm->ndm_flags = NTF_SELF;
832 ndm->ndm_type = 0;
833 ndm->ndm_ifindex = dump->dev->ifindex;
834 ndm->ndm_state = NUD_REACHABLE;
835
836 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac))
837 goto nla_put_failure;
838
839 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid))
840 goto nla_put_failure;
841
842 nlmsg_end(dump->skb, nlh);
843
844skip:
845 dump->idx++;
846 return 0;
847
848nla_put_failure:
849 nlmsg_cancel(dump->skb, nlh);
850 return -EMSGSIZE;
851}
852
853static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col,
854 struct ocelot_mact_entry *entry)
855{
856 struct ocelot *ocelot = port->ocelot;
857 char mac[ETH_ALEN];
858 u32 val, dst, macl, mach;
859
860 /* Set row and column to read from */
861 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
862 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
863
864 /* Issue a read command */
865 ocelot_write(ocelot,
866 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
867 ANA_TABLES_MACACCESS);
868
869 if (ocelot_mact_wait_for_completion(ocelot))
870 return -ETIMEDOUT;
871
872 /* Read the entry flags */
873 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
874 if (!(val & ANA_TABLES_MACACCESS_VALID))
875 return -EINVAL;
876
877 /* If the entry read has another port configured as its destination,
878 * do not report it.
879 */
880 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
881 if (dst != port->chip_port)
882 return -EINVAL;
883
884 /* Get the entry's MAC address and VLAN id */
885 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
886 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
887
888 mac[0] = (mach >> 8) & 0xff;
889 mac[1] = (mach >> 0) & 0xff;
890 mac[2] = (macl >> 24) & 0xff;
891 mac[3] = (macl >> 16) & 0xff;
892 mac[4] = (macl >> 8) & 0xff;
893 mac[5] = (macl >> 0) & 0xff;
894
895 entry->vid = (mach >> 16) & 0xfff;
896 ether_addr_copy(entry->mac, mac);
897
898 return 0;
899}
900
901static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
902 struct net_device *dev,
903 struct net_device *filter_dev, int *idx)
904{
905 struct ocelot_port *port = netdev_priv(dev);
906 int i, j, ret = 0;
907 struct ocelot_dump_ctx dump = {
908 .dev = dev,
909 .skb = skb,
910 .cb = cb,
911 .idx = *idx,
912 };
913
914 struct ocelot_mact_entry entry;
915
916 /* Loop through all the mac tables entries. There are 1024 rows of 4
917 * entries.
918 */
919 for (i = 0; i < 1024; i++) {
920 for (j = 0; j < 4; j++) {
921 ret = ocelot_mact_read(port, i, j, &entry);
922 /* If the entry is invalid (wrong port, invalid...),
923 * skip it.
924 */
925 if (ret == -EINVAL)
926 continue;
927 else if (ret)
928 goto end;
929
930 ret = ocelot_fdb_do_dump(&entry, &dump);
931 if (ret)
932 goto end;
933 }
934 }
935
936end:
937 *idx = dump.idx;
938 return ret;
939}
940
941static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
942 u16 vid)
943{
944 return ocelot_vlan_vid_add(dev, vid, false, false);
945}
946
947static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
948 u16 vid)
949{
950 return ocelot_vlan_vid_del(dev, vid);
951}
952
953static int ocelot_set_features(struct net_device *dev,
954 netdev_features_t features)
955{
956 struct ocelot_port *port = netdev_priv(dev);
957 netdev_features_t changed = dev->features ^ features;
958
959 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
960 port->tc.offload_cnt) {
961 netdev_err(dev,
962 "Cannot disable HW TC offload while offloads active\n");
963 return -EBUSY;
964 }
965
966 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
967 ocelot_vlan_mode(port, features);
968
969 return 0;
970}
971
972static int ocelot_get_port_parent_id(struct net_device *dev,
973 struct netdev_phys_item_id *ppid)
974{
975 struct ocelot_port *ocelot_port = netdev_priv(dev);
976 struct ocelot *ocelot = ocelot_port->ocelot;
977
978 ppid->id_len = sizeof(ocelot->base_mac);
979 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len);
980
981 return 0;
982}
983
984static int ocelot_hwstamp_get(struct ocelot_port *port, struct ifreq *ifr)
985{
986 struct ocelot *ocelot = port->ocelot;
987
988 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
989 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
990}
991
992static int ocelot_hwstamp_set(struct ocelot_port *port, struct ifreq *ifr)
993{
994 struct ocelot *ocelot = port->ocelot;
995 struct hwtstamp_config cfg;
996
997 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
998 return -EFAULT;
999
1000 /* reserved for future extensions */
1001 if (cfg.flags)
1002 return -EINVAL;
1003
1004 /* Tx type sanity check */
1005 switch (cfg.tx_type) {
1006 case HWTSTAMP_TX_ON:
1007 port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1008 break;
1009 case HWTSTAMP_TX_ONESTEP_SYNC:
1010 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1011 * need to update the origin time.
1012 */
1013 port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1014 break;
1015 case HWTSTAMP_TX_OFF:
1016 port->ptp_cmd = 0;
1017 break;
1018 default:
1019 return -ERANGE;
1020 }
1021
1022 mutex_lock(&ocelot->ptp_lock);
1023
1024 switch (cfg.rx_filter) {
1025 case HWTSTAMP_FILTER_NONE:
1026 break;
1027 case HWTSTAMP_FILTER_ALL:
1028 case HWTSTAMP_FILTER_SOME:
1029 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1030 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1031 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1032 case HWTSTAMP_FILTER_NTP_ALL:
1033 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1034 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1035 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1036 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1037 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1038 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1039 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1040 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1041 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1042 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1043 break;
1044 default:
1045 mutex_unlock(&ocelot->ptp_lock);
1046 return -ERANGE;
1047 }
1048
1049 /* Commit back the result & save it */
1050 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1051 mutex_unlock(&ocelot->ptp_lock);
1052
1053 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1054}
1055
1056static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1057{
1058 struct ocelot_port *port = netdev_priv(dev);
1059 struct ocelot *ocelot = port->ocelot;
1060
1061 /* The function is only used for PTP operations for now */
1062 if (!ocelot->ptp)
1063 return -EOPNOTSUPP;
1064
1065 switch (cmd) {
1066 case SIOCSHWTSTAMP:
1067 return ocelot_hwstamp_set(port, ifr);
1068 case SIOCGHWTSTAMP:
1069 return ocelot_hwstamp_get(port, ifr);
1070 default:
1071 return -EOPNOTSUPP;
1072 }
1073}
1074
1075static const struct net_device_ops ocelot_port_netdev_ops = {
1076 .ndo_open = ocelot_port_open,
1077 .ndo_stop = ocelot_port_stop,
1078 .ndo_start_xmit = ocelot_port_xmit,
1079 .ndo_set_rx_mode = ocelot_set_rx_mode,
1080 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
1081 .ndo_set_mac_address = ocelot_port_set_mac_address,
1082 .ndo_get_stats64 = ocelot_get_stats64,
1083 .ndo_fdb_add = ocelot_fdb_add,
1084 .ndo_fdb_del = ocelot_fdb_del,
1085 .ndo_fdb_dump = ocelot_fdb_dump,
1086 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
1087 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
1088 .ndo_set_features = ocelot_set_features,
1089 .ndo_get_port_parent_id = ocelot_get_port_parent_id,
1090 .ndo_setup_tc = ocelot_setup_tc,
1091 .ndo_do_ioctl = ocelot_ioctl,
1092};
1093
1094static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data)
1095{
1096 struct ocelot_port *port = netdev_priv(netdev);
1097 struct ocelot *ocelot = port->ocelot;
1098 int i;
1099
1100 if (sset != ETH_SS_STATS)
1101 return;
1102
1103 for (i = 0; i < ocelot->num_stats; i++)
1104 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1105 ETH_GSTRING_LEN);
1106}
1107
1108static void ocelot_update_stats(struct ocelot *ocelot)
1109{
1110 int i, j;
1111
1112 mutex_lock(&ocelot->stats_lock);
1113
1114 for (i = 0; i < ocelot->num_phys_ports; i++) {
1115 /* Configure the port to read the stats from */
1116 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1117
1118 for (j = 0; j < ocelot->num_stats; j++) {
1119 u32 val;
1120 unsigned int idx = i * ocelot->num_stats + j;
1121
1122 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1123 ocelot->stats_layout[j].offset);
1124
1125 if (val < (ocelot->stats[idx] & U32_MAX))
1126 ocelot->stats[idx] += (u64)1 << 32;
1127
1128 ocelot->stats[idx] = (ocelot->stats[idx] &
1129 ~(u64)U32_MAX) + val;
1130 }
1131 }
1132
1133 mutex_unlock(&ocelot->stats_lock);
1134}
1135
1136static void ocelot_check_stats_work(struct work_struct *work)
1137{
1138 struct delayed_work *del_work = to_delayed_work(work);
1139 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1140 stats_work);
1141
1142 ocelot_update_stats(ocelot);
1143
1144 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1145 OCELOT_STATS_CHECK_DELAY);
1146}
1147
1148static void ocelot_get_ethtool_stats(struct net_device *dev,
1149 struct ethtool_stats *stats, u64 *data)
1150{
1151 struct ocelot_port *port = netdev_priv(dev);
1152 struct ocelot *ocelot = port->ocelot;
1153 int i;
1154
1155 /* check and update now */
1156 ocelot_update_stats(ocelot);
1157
1158 /* Copy all counters */
1159 for (i = 0; i < ocelot->num_stats; i++)
1160 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i];
1161}
1162
1163static int ocelot_get_sset_count(struct net_device *dev, int sset)
1164{
1165 struct ocelot_port *port = netdev_priv(dev);
1166 struct ocelot *ocelot = port->ocelot;
1167
1168 if (sset != ETH_SS_STATS)
1169 return -EOPNOTSUPP;
1170 return ocelot->num_stats;
1171}
1172
1173static int ocelot_get_ts_info(struct net_device *dev,
1174 struct ethtool_ts_info *info)
1175{
1176 struct ocelot_port *ocelot_port = netdev_priv(dev);
1177 struct ocelot *ocelot = ocelot_port->ocelot;
1178
1179 if (!ocelot->ptp)
1180 return ethtool_op_get_ts_info(dev, info);
1181
1182 info->phc_index = ocelot->ptp_clock ?
1183 ptp_clock_index(ocelot->ptp_clock) : -1;
1184 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1185 SOF_TIMESTAMPING_RX_SOFTWARE |
1186 SOF_TIMESTAMPING_SOFTWARE |
1187 SOF_TIMESTAMPING_TX_HARDWARE |
1188 SOF_TIMESTAMPING_RX_HARDWARE |
1189 SOF_TIMESTAMPING_RAW_HARDWARE;
1190 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1191 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1192 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1193
1194 return 0;
1195}
1196
1197static const struct ethtool_ops ocelot_ethtool_ops = {
1198 .get_strings = ocelot_get_strings,
1199 .get_ethtool_stats = ocelot_get_ethtool_stats,
1200 .get_sset_count = ocelot_get_sset_count,
1201 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1202 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1203 .get_ts_info = ocelot_get_ts_info,
1204};
1205
1206static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
1207 struct switchdev_trans *trans,
1208 u8 state)
1209{
1210 struct ocelot *ocelot = ocelot_port->ocelot;
1211 u32 port_cfg;
1212 int port, i;
1213
1214 if (switchdev_trans_ph_prepare(trans))
1215 return 0;
1216
1217 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
1218 return 0;
1219
1220 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
1221 ocelot_port->chip_port);
1222
1223 switch (state) {
1224 case BR_STATE_FORWARDING:
1225 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
1226 /* Fallthrough */
1227 case BR_STATE_LEARNING:
1228 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1229 break;
1230
1231 default:
1232 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1233 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
1234 break;
1235 }
1236
1237 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
1238 ocelot_port->chip_port);
1239
1240 /* Apply FWD mask. The loop is needed to add/remove the current port as
1241 * a source for the other ports.
1242 */
1243 for (port = 0; port < ocelot->num_phys_ports; port++) {
1244 if (ocelot->bridge_fwd_mask & BIT(port)) {
1245 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
1246
1247 for (i = 0; i < ocelot->num_phys_ports; i++) {
1248 unsigned long bond_mask = ocelot->lags[i];
1249
1250 if (!bond_mask)
1251 continue;
1252
1253 if (bond_mask & BIT(port)) {
1254 mask &= ~bond_mask;
1255 break;
1256 }
1257 }
1258
1259 ocelot_write_rix(ocelot,
1260 BIT(ocelot->num_phys_ports) | mask,
1261 ANA_PGID_PGID, PGID_SRC + port);
1262 } else {
1263 /* Only the CPU port, this is compatible with link
1264 * aggregation.
1265 */
1266 ocelot_write_rix(ocelot,
1267 BIT(ocelot->num_phys_ports),
1268 ANA_PGID_PGID, PGID_SRC + port);
1269 }
1270 }
1271
1272 return 0;
1273}
1274
1275static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
1276 unsigned long ageing_clock_t)
1277{
1278 struct ocelot *ocelot = ocelot_port->ocelot;
1279 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1280 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1281
1282 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
1283 ANA_AUTOAGE);
1284}
1285
1286static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
1287{
1288 struct ocelot *ocelot = port->ocelot;
1289 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
1290 port->chip_port);
1291
1292 if (mc)
1293 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1294 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1295 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1296 else
1297 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1298 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1299 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
1300
1301 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
1302}
1303
1304static int ocelot_port_attr_set(struct net_device *dev,
1305 const struct switchdev_attr *attr,
1306 struct switchdev_trans *trans)
1307{
1308 struct ocelot_port *ocelot_port = netdev_priv(dev);
1309 int err = 0;
1310
1311 switch (attr->id) {
1312 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1313 ocelot_port_attr_stp_state_set(ocelot_port, trans,
1314 attr->u.stp_state);
1315 break;
1316 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1317 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
1318 break;
1319 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1320 ocelot_port->vlan_aware = attr->u.vlan_filtering;
1321 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port);
1322 break;
1323 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1324 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
1325 break;
1326 default:
1327 err = -EOPNOTSUPP;
1328 break;
1329 }
1330
1331 return err;
1332}
1333
1334static int ocelot_port_obj_add_vlan(struct net_device *dev,
1335 const struct switchdev_obj_port_vlan *vlan,
1336 struct switchdev_trans *trans)
1337{
1338 int ret;
1339 u16 vid;
1340
1341 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1342 ret = ocelot_vlan_vid_add(dev, vid,
1343 vlan->flags & BRIDGE_VLAN_INFO_PVID,
1344 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
1345 if (ret)
1346 return ret;
1347 }
1348
1349 return 0;
1350}
1351
1352static int ocelot_port_vlan_del_vlan(struct net_device *dev,
1353 const struct switchdev_obj_port_vlan *vlan)
1354{
1355 int ret;
1356 u16 vid;
1357
1358 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1359 ret = ocelot_vlan_vid_del(dev, vid);
1360
1361 if (ret)
1362 return ret;
1363 }
1364
1365 return 0;
1366}
1367
1368static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1369 const unsigned char *addr,
1370 u16 vid)
1371{
1372 struct ocelot_multicast *mc;
1373
1374 list_for_each_entry(mc, &ocelot->multicast, list) {
1375 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1376 return mc;
1377 }
1378
1379 return NULL;
1380}
1381
1382static int ocelot_port_obj_add_mdb(struct net_device *dev,
1383 const struct switchdev_obj_port_mdb *mdb,
1384 struct switchdev_trans *trans)
1385{
1386 struct ocelot_port *port = netdev_priv(dev);
1387 struct ocelot *ocelot = port->ocelot;
1388 struct ocelot_multicast *mc;
1389 unsigned char addr[ETH_ALEN];
1390 u16 vid = mdb->vid;
1391 bool new = false;
1392
1393 if (!vid)
1394 vid = port->pvid;
1395
1396 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1397 if (!mc) {
1398 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1399 if (!mc)
1400 return -ENOMEM;
1401
1402 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1403 mc->vid = vid;
1404
1405 list_add_tail(&mc->list, &ocelot->multicast);
1406 new = true;
1407 }
1408
1409 memcpy(addr, mc->addr, ETH_ALEN);
1410 addr[0] = 0;
1411
1412 if (!new) {
1413 addr[2] = mc->ports << 0;
1414 addr[1] = mc->ports << 8;
1415 ocelot_mact_forget(ocelot, addr, vid);
1416 }
1417
1418 mc->ports |= BIT(port->chip_port);
1419 addr[2] = mc->ports << 0;
1420 addr[1] = mc->ports << 8;
1421
1422 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1423}
1424
1425static int ocelot_port_obj_del_mdb(struct net_device *dev,
1426 const struct switchdev_obj_port_mdb *mdb)
1427{
1428 struct ocelot_port *port = netdev_priv(dev);
1429 struct ocelot *ocelot = port->ocelot;
1430 struct ocelot_multicast *mc;
1431 unsigned char addr[ETH_ALEN];
1432 u16 vid = mdb->vid;
1433
1434 if (!vid)
1435 vid = port->pvid;
1436
1437 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1438 if (!mc)
1439 return -ENOENT;
1440
1441 memcpy(addr, mc->addr, ETH_ALEN);
1442 addr[2] = mc->ports << 0;
1443 addr[1] = mc->ports << 8;
1444 addr[0] = 0;
1445 ocelot_mact_forget(ocelot, addr, vid);
1446
1447 mc->ports &= ~BIT(port->chip_port);
1448 if (!mc->ports) {
1449 list_del(&mc->list);
1450 devm_kfree(ocelot->dev, mc);
1451 return 0;
1452 }
1453
1454 addr[2] = mc->ports << 0;
1455 addr[1] = mc->ports << 8;
1456
1457 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1458}
1459
1460static int ocelot_port_obj_add(struct net_device *dev,
1461 const struct switchdev_obj *obj,
1462 struct switchdev_trans *trans,
1463 struct netlink_ext_ack *extack)
1464{
1465 int ret = 0;
1466
1467 switch (obj->id) {
1468 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1469 ret = ocelot_port_obj_add_vlan(dev,
1470 SWITCHDEV_OBJ_PORT_VLAN(obj),
1471 trans);
1472 break;
1473 case SWITCHDEV_OBJ_ID_PORT_MDB:
1474 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1475 trans);
1476 break;
1477 default:
1478 return -EOPNOTSUPP;
1479 }
1480
1481 return ret;
1482}
1483
1484static int ocelot_port_obj_del(struct net_device *dev,
1485 const struct switchdev_obj *obj)
1486{
1487 int ret = 0;
1488
1489 switch (obj->id) {
1490 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1491 ret = ocelot_port_vlan_del_vlan(dev,
1492 SWITCHDEV_OBJ_PORT_VLAN(obj));
1493 break;
1494 case SWITCHDEV_OBJ_ID_PORT_MDB:
1495 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1496 break;
1497 default:
1498 return -EOPNOTSUPP;
1499 }
1500
1501 return ret;
1502}
1503
1504static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port,
1505 struct net_device *bridge)
1506{
1507 struct ocelot *ocelot = ocelot_port->ocelot;
1508
1509 if (!ocelot->bridge_mask) {
1510 ocelot->hw_bridge_dev = bridge;
1511 } else {
1512 if (ocelot->hw_bridge_dev != bridge)
1513 /* This is adding the port to a second bridge, this is
1514 * unsupported */
1515 return -ENODEV;
1516 }
1517
1518 ocelot->bridge_mask |= BIT(ocelot_port->chip_port);
1519
1520 return 0;
1521}
1522
1523static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port,
1524 struct net_device *bridge)
1525{
1526 struct ocelot *ocelot = ocelot_port->ocelot;
1527
1528 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port);
1529
1530 if (!ocelot->bridge_mask)
1531 ocelot->hw_bridge_dev = NULL;
1532
1533 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */
1534 ocelot_port->vlan_aware = 0;
1535 ocelot_port->pvid = 0;
1536 ocelot_port->vid = 0;
1537}
1538
1539static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1540{
1541 int i, port, lag;
1542
1543 /* Reset destination and aggregation PGIDS */
1544 for (port = 0; port < ocelot->num_phys_ports; port++)
1545 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1546
1547 for (i = PGID_AGGR; i < PGID_SRC; i++)
1548 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1549 ANA_PGID_PGID, i);
1550
1551 /* Now, set PGIDs for each LAG */
1552 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1553 unsigned long bond_mask;
1554 int aggr_count = 0;
1555 u8 aggr_idx[16];
1556
1557 bond_mask = ocelot->lags[lag];
1558 if (!bond_mask)
1559 continue;
1560
1561 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1562 // Destination mask
1563 ocelot_write_rix(ocelot, bond_mask,
1564 ANA_PGID_PGID, port);
1565 aggr_idx[aggr_count] = port;
1566 aggr_count++;
1567 }
1568
1569 for (i = PGID_AGGR; i < PGID_SRC; i++) {
1570 u32 ac;
1571
1572 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1573 ac &= ~bond_mask;
1574 ac |= BIT(aggr_idx[i % aggr_count]);
1575 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1576 }
1577 }
1578}
1579
1580static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1581{
1582 unsigned long bond_mask = ocelot->lags[lag];
1583 unsigned int p;
1584
1585 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1586 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1587
1588 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1589
1590 /* Use lag port as logical port for port i */
1591 ocelot_write_gix(ocelot, port_cfg |
1592 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1593 ANA_PORT_PORT_CFG, p);
1594 }
1595}
1596
1597static int ocelot_port_lag_join(struct ocelot_port *ocelot_port,
1598 struct net_device *bond)
1599{
1600 struct ocelot *ocelot = ocelot_port->ocelot;
1601 int p = ocelot_port->chip_port;
1602 int lag, lp;
1603 struct net_device *ndev;
1604 u32 bond_mask = 0;
1605
1606 rcu_read_lock();
1607 for_each_netdev_in_bond_rcu(bond, ndev) {
1608 struct ocelot_port *port = netdev_priv(ndev);
1609
1610 bond_mask |= BIT(port->chip_port);
1611 }
1612 rcu_read_unlock();
1613
1614 lp = __ffs(bond_mask);
1615
1616 /* If the new port is the lowest one, use it as the logical port from
1617 * now on
1618 */
1619 if (p == lp) {
1620 lag = p;
1621 ocelot->lags[p] = bond_mask;
1622 bond_mask &= ~BIT(p);
1623 if (bond_mask) {
1624 lp = __ffs(bond_mask);
1625 ocelot->lags[lp] = 0;
1626 }
1627 } else {
1628 lag = lp;
1629 ocelot->lags[lp] |= BIT(p);
1630 }
1631
1632 ocelot_setup_lag(ocelot, lag);
1633 ocelot_set_aggr_pgids(ocelot);
1634
1635 return 0;
1636}
1637
1638static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port,
1639 struct net_device *bond)
1640{
1641 struct ocelot *ocelot = ocelot_port->ocelot;
1642 int p = ocelot_port->chip_port;
1643 u32 port_cfg;
1644 int i;
1645
1646 /* Remove port from any lag */
1647 for (i = 0; i < ocelot->num_phys_ports; i++)
1648 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port);
1649
1650 /* if it was the logical port of the lag, move the lag config to the
1651 * next port
1652 */
1653 if (ocelot->lags[p]) {
1654 int n = __ffs(ocelot->lags[p]);
1655
1656 ocelot->lags[n] = ocelot->lags[p];
1657 ocelot->lags[p] = 0;
1658
1659 ocelot_setup_lag(ocelot, n);
1660 }
1661
1662 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1663 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1664 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p),
1665 ANA_PORT_PORT_CFG, p);
1666
1667 ocelot_set_aggr_pgids(ocelot);
1668}
1669
1670/* Checks if the net_device instance given to us originate from our driver. */
1671static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1672{
1673 return dev->netdev_ops == &ocelot_port_netdev_ops;
1674}
1675
1676static int ocelot_netdevice_port_event(struct net_device *dev,
1677 unsigned long event,
1678 struct netdev_notifier_changeupper_info *info)
1679{
1680 struct ocelot_port *ocelot_port = netdev_priv(dev);
1681 int err = 0;
1682
1683 switch (event) {
1684 case NETDEV_CHANGEUPPER:
1685 if (netif_is_bridge_master(info->upper_dev)) {
1686 if (info->linking)
1687 err = ocelot_port_bridge_join(ocelot_port,
1688 info->upper_dev);
1689 else
1690 ocelot_port_bridge_leave(ocelot_port,
1691 info->upper_dev);
1692
1693 ocelot_vlan_port_apply(ocelot_port->ocelot,
1694 ocelot_port);
1695 }
1696 if (netif_is_lag_master(info->upper_dev)) {
1697 if (info->linking)
1698 err = ocelot_port_lag_join(ocelot_port,
1699 info->upper_dev);
1700 else
1701 ocelot_port_lag_leave(ocelot_port,
1702 info->upper_dev);
1703 }
1704 break;
1705 default:
1706 break;
1707 }
1708
1709 return err;
1710}
1711
1712static int ocelot_netdevice_event(struct notifier_block *unused,
1713 unsigned long event, void *ptr)
1714{
1715 struct netdev_notifier_changeupper_info *info = ptr;
1716 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1717 int ret = 0;
1718
1719 if (!ocelot_netdevice_dev_check(dev))
1720 return 0;
1721
1722 if (event == NETDEV_PRECHANGEUPPER &&
1723 netif_is_lag_master(info->upper_dev)) {
1724 struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
1725 struct netlink_ext_ack *extack;
1726
1727 if (lag_upper_info &&
1728 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1729 extack = netdev_notifier_info_to_extack(&info->info);
1730 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
1731
1732 ret = -EINVAL;
1733 goto notify;
1734 }
1735 }
1736
1737 if (netif_is_lag_master(dev)) {
1738 struct net_device *slave;
1739 struct list_head *iter;
1740
1741 netdev_for_each_lower_dev(dev, slave, iter) {
1742 ret = ocelot_netdevice_port_event(slave, event, info);
1743 if (ret)
1744 goto notify;
1745 }
1746 } else {
1747 ret = ocelot_netdevice_port_event(dev, event, info);
1748 }
1749
1750notify:
1751 return notifier_from_errno(ret);
1752}
1753
1754struct notifier_block ocelot_netdevice_nb __read_mostly = {
1755 .notifier_call = ocelot_netdevice_event,
1756};
1757EXPORT_SYMBOL(ocelot_netdevice_nb);
1758
1759static int ocelot_switchdev_event(struct notifier_block *unused,
1760 unsigned long event, void *ptr)
1761{
1762 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1763 int err;
1764
1765 switch (event) {
1766 case SWITCHDEV_PORT_ATTR_SET:
1767 err = switchdev_handle_port_attr_set(dev, ptr,
1768 ocelot_netdevice_dev_check,
1769 ocelot_port_attr_set);
1770 return notifier_from_errno(err);
1771 }
1772
1773 return NOTIFY_DONE;
1774}
1775
1776struct notifier_block ocelot_switchdev_nb __read_mostly = {
1777 .notifier_call = ocelot_switchdev_event,
1778};
1779EXPORT_SYMBOL(ocelot_switchdev_nb);
1780
1781static int ocelot_switchdev_blocking_event(struct notifier_block *unused,
1782 unsigned long event, void *ptr)
1783{
1784 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1785 int err;
1786
1787 switch (event) {
1788 /* Blocking events. */
1789 case SWITCHDEV_PORT_OBJ_ADD:
1790 err = switchdev_handle_port_obj_add(dev, ptr,
1791 ocelot_netdevice_dev_check,
1792 ocelot_port_obj_add);
1793 return notifier_from_errno(err);
1794 case SWITCHDEV_PORT_OBJ_DEL:
1795 err = switchdev_handle_port_obj_del(dev, ptr,
1796 ocelot_netdevice_dev_check,
1797 ocelot_port_obj_del);
1798 return notifier_from_errno(err);
1799 case SWITCHDEV_PORT_ATTR_SET:
1800 err = switchdev_handle_port_attr_set(dev, ptr,
1801 ocelot_netdevice_dev_check,
1802 ocelot_port_attr_set);
1803 return notifier_from_errno(err);
1804 }
1805
1806 return NOTIFY_DONE;
1807}
1808
1809struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = {
1810 .notifier_call = ocelot_switchdev_blocking_event,
1811};
1812EXPORT_SYMBOL(ocelot_switchdev_blocking_nb);
1813
1814int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts)
1815{
1816 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1817 unsigned long flags;
1818 time64_t s;
1819 u32 val;
1820 s64 ns;
1821
1822 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1823
1824 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1825 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1826 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
1827 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1828
1829 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff;
1830 s <<= 32;
1831 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
1832 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
1833
1834 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1835
1836 /* Deal with negative values */
1837 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) {
1838 s--;
1839 ns &= 0xf;
1840 ns += 999999984;
1841 }
1842
1843 set_normalized_timespec64(ts, s, ns);
1844 return 0;
1845}
1846EXPORT_SYMBOL(ocelot_ptp_gettime64);
1847
1848static int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
1849 const struct timespec64 *ts)
1850{
1851 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1852 unsigned long flags;
1853 u32 val;
1854
1855 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1856
1857 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1858 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1859 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
1860
1861 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1862
1863 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB,
1864 TOD_ACC_PIN);
1865 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB,
1866 TOD_ACC_PIN);
1867 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
1868
1869 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1870 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1871 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD);
1872
1873 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1874
1875 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1876 return 0;
1877}
1878
1879static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
1880{
1881 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) {
1882 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1883 unsigned long flags;
1884 u32 val;
1885
1886 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1887
1888 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1889 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1890 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
1891
1892 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1893
1894 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
1895 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN);
1896 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
1897
1898 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1899 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1900 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA);
1901
1902 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1903
1904 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1905 } else {
1906 /* Fall back using ocelot_ptp_settime64 which is not exact. */
1907 struct timespec64 ts;
1908 u64 now;
1909
1910 ocelot_ptp_gettime64(ptp, &ts);
1911
1912 now = ktime_to_ns(timespec64_to_ktime(ts));
1913 ts = ns_to_timespec64(now + delta);
1914
1915 ocelot_ptp_settime64(ptp, &ts);
1916 }
1917 return 0;
1918}
1919
1920static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1921{
1922 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1923 u32 unit = 0, direction = 0;
1924 unsigned long flags;
1925 u64 adj = 0;
1926
1927 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1928
1929 if (!scaled_ppm)
1930 goto disable_adj;
1931
1932 if (scaled_ppm < 0) {
1933 direction = PTP_CFG_CLK_ADJ_CFG_DIR;
1934 scaled_ppm = -scaled_ppm;
1935 }
1936
1937 adj = PSEC_PER_SEC << 16;
1938 do_div(adj, scaled_ppm);
1939 do_div(adj, 1000);
1940
1941 /* If the adjustment value is too large, use ns instead */
1942 if (adj >= (1L << 30)) {
1943 unit = PTP_CFG_CLK_ADJ_FREQ_NS;
1944 do_div(adj, 1000);
1945 }
1946
1947 /* Still too big */
1948 if (adj >= (1L << 30))
1949 goto disable_adj;
1950
1951 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ);
1952 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction,
1953 PTP_CLK_CFG_ADJ_CFG);
1954
1955 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1956 return 0;
1957
1958disable_adj:
1959 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG);
1960
1961 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1962 return 0;
1963}
1964
1965static struct ptp_clock_info ocelot_ptp_clock_info = {
1966 .owner = THIS_MODULE,
1967 .name = "ocelot ptp",
1968 .max_adj = 0x7fffffff,
1969 .n_alarm = 0,
1970 .n_ext_ts = 0,
1971 .n_per_out = 0,
1972 .n_pins = 0,
1973 .pps = 0,
1974 .gettime64 = ocelot_ptp_gettime64,
1975 .settime64 = ocelot_ptp_settime64,
1976 .adjtime = ocelot_ptp_adjtime,
1977 .adjfine = ocelot_ptp_adjfine,
1978};
1979
1980static int ocelot_init_timestamp(struct ocelot *ocelot)
1981{
1982 ocelot->ptp_info = ocelot_ptp_clock_info;
1983 ocelot->ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev);
1984 if (IS_ERR(ocelot->ptp_clock))
1985 return PTR_ERR(ocelot->ptp_clock);
1986 /* Check if PHC support is missing at the configuration level */
1987 if (!ocelot->ptp_clock)
1988 return 0;
1989
1990 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG);
1991 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW);
1992 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH);
1993
1994 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC);
1995
1996 /* There is no device reconfiguration, PTP Rx stamping is always
1997 * enabled.
1998 */
1999 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2000
2001 return 0;
2002}
2003
2004int ocelot_probe_port(struct ocelot *ocelot, u8 port,
2005 void __iomem *regs,
2006 struct phy_device *phy)
2007{
2008 struct ocelot_port *ocelot_port;
2009 struct net_device *dev;
2010 int err;
2011
2012 dev = alloc_etherdev(sizeof(struct ocelot_port));
2013 if (!dev)
2014 return -ENOMEM;
2015 SET_NETDEV_DEV(dev, ocelot->dev);
2016 ocelot_port = netdev_priv(dev);
2017 ocelot_port->dev = dev;
2018 ocelot_port->ocelot = ocelot;
2019 ocelot_port->regs = regs;
2020 ocelot_port->chip_port = port;
2021 ocelot_port->phy = phy;
2022 ocelot->ports[port] = ocelot_port;
2023
2024 dev->netdev_ops = &ocelot_port_netdev_ops;
2025 dev->ethtool_ops = &ocelot_ethtool_ops;
2026
2027 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS |
2028 NETIF_F_HW_TC;
2029 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2030
2031 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
2032 dev->dev_addr[ETH_ALEN - 1] += port;
2033 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
2034 ENTRYTYPE_LOCKED);
2035
2036 INIT_LIST_HEAD(&ocelot_port->skbs);
2037
2038 err = register_netdev(dev);
2039 if (err) {
2040 dev_err(ocelot->dev, "register_netdev failed\n");
2041 goto err_register_netdev;
2042 }
2043
2044 /* Basic L2 initialization */
2045 ocelot_vlan_port_apply(ocelot, ocelot_port);
2046
2047 /* Enable vcap lookups */
2048 ocelot_vcap_enable(ocelot, ocelot_port);
2049
2050 return 0;
2051
2052err_register_netdev:
2053 free_netdev(dev);
2054 return err;
2055}
2056EXPORT_SYMBOL(ocelot_probe_port);
2057
2058int ocelot_init(struct ocelot *ocelot)
2059{
2060 u32 port;
2061 int i, ret, cpu = ocelot->num_phys_ports;
2062 char queue_name[32];
2063
2064 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
2065 sizeof(u32), GFP_KERNEL);
2066 if (!ocelot->lags)
2067 return -ENOMEM;
2068
2069 ocelot->stats = devm_kcalloc(ocelot->dev,
2070 ocelot->num_phys_ports * ocelot->num_stats,
2071 sizeof(u64), GFP_KERNEL);
2072 if (!ocelot->stats)
2073 return -ENOMEM;
2074
2075 mutex_init(&ocelot->stats_lock);
2076 mutex_init(&ocelot->ptp_lock);
2077 spin_lock_init(&ocelot->ptp_clock_lock);
2078 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2079 dev_name(ocelot->dev));
2080 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2081 if (!ocelot->stats_queue)
2082 return -ENOMEM;
2083
2084 ocelot_mact_init(ocelot);
2085 ocelot_vlan_init(ocelot);
2086 ocelot_ace_init(ocelot);
2087
2088 for (port = 0; port < ocelot->num_phys_ports; port++) {
2089 /* Clear all counters (5 groups) */
2090 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2091 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2092 SYS_STAT_CFG);
2093 }
2094
2095 /* Only use S-Tag */
2096 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2097
2098 /* Aggregation mode */
2099 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2100 ANA_AGGR_CFG_AC_DMAC_ENA |
2101 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2102 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
2103
2104 /* Set MAC age time to default value. The entry is aged after
2105 * 2*AGE_PERIOD
2106 */
2107 ocelot_write(ocelot,
2108 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2109 ANA_AUTOAGE);
2110
2111 /* Disable learning for frames discarded by VLAN ingress filtering */
2112 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2113
2114 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2115 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2116 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2117
2118 /* Setup flooding PGIDs */
2119 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2120 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
2121 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2122 ANA_FLOODING, 0);
2123 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2124 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2125 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2126 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2127 ANA_FLOODING_IPMC);
2128
2129 for (port = 0; port < ocelot->num_phys_ports; port++) {
2130 /* Transmit the frame to the local port. */
2131 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2132 /* Do not forward BPDU frames to the front ports. */
2133 ocelot_write_gix(ocelot,
2134 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2135 ANA_PORT_CPU_FWD_BPDU_CFG,
2136 port);
2137 /* Ensure bridging is disabled */
2138 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2139 }
2140
2141 /* Configure and enable the CPU port. */
2142 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2143 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2144 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2145 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2146 ANA_PORT_PORT_CFG, cpu);
2147
2148 /* Allow broadcast MAC frames. */
2149 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
2150 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2151
2152 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2153 }
2154 ocelot_write_rix(ocelot,
2155 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
2156 ANA_PGID_PGID, PGID_MC);
2157 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2158 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2159
2160 /* CPU port Injection/Extraction configuration */
2161 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
2162 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2163 QSYS_SWITCH_PORT_MODE_PORT_ENA,
2164 QSYS_SWITCH_PORT_MODE, cpu);
2165 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
2166 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
2167 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2168 * registers endianness.
2169 */
2170 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2171 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2172 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2173 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2174 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2175 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2176 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2177 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2178 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2179 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2180 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2181 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2182 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2183 for (i = 0; i < 16; i++)
2184 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2185 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2186 ANA_CPUQ_8021_CFG, i);
2187
2188 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2189 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2190 OCELOT_STATS_CHECK_DELAY);
2191
2192 if (ocelot->ptp) {
2193 ret = ocelot_init_timestamp(ocelot);
2194 if (ret) {
2195 dev_err(ocelot->dev,
2196 "Timestamp initialization failed\n");
2197 return ret;
2198 }
2199 }
2200
2201 return 0;
2202}
2203EXPORT_SYMBOL(ocelot_init);
2204
2205void ocelot_deinit(struct ocelot *ocelot)
2206{
2207 struct list_head *pos, *tmp;
2208 struct ocelot_port *port;
2209 struct ocelot_skb *entry;
2210 int i;
2211
2212 cancel_delayed_work(&ocelot->stats_work);
2213 destroy_workqueue(ocelot->stats_queue);
2214 mutex_destroy(&ocelot->stats_lock);
2215 ocelot_ace_deinit();
2216
2217 for (i = 0; i < ocelot->num_phys_ports; i++) {
2218 port = ocelot->ports[i];
2219
2220 list_for_each_safe(pos, tmp, &port->skbs) {
2221 entry = list_entry(pos, struct ocelot_skb, head);
2222
2223 list_del(pos);
2224 dev_kfree_skb_any(entry->skb);
2225 kfree(entry);
2226 }
2227 }
2228}
2229EXPORT_SYMBOL(ocelot_deinit);
2230
2231MODULE_LICENSE("Dual MIT/GPL");