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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_DEFINES_H_
5#define _IGC_DEFINES_H_
6
7#include <linux/bitfield.h>
8
9/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
10#define REQ_TX_DESCRIPTOR_MULTIPLE 8
11#define REQ_RX_DESCRIPTOR_MULTIPLE 8
12
13#define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
14#define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */
15#define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
16
17/* Definitions for power management and wakeup registers */
18/* Wake Up Control */
19#define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
20
21/* Wake Up Filter Control */
22#define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
23#define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
24#define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
25#define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
26#define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
27#define IGC_WUFC_FLEX_HQ BIT(14) /* Flex Filters Host Queuing */
28#define IGC_WUFC_FLX0 BIT(16) /* Flexible Filter 0 Enable */
29#define IGC_WUFC_FLX1 BIT(17) /* Flexible Filter 1 Enable */
30#define IGC_WUFC_FLX2 BIT(18) /* Flexible Filter 2 Enable */
31#define IGC_WUFC_FLX3 BIT(19) /* Flexible Filter 3 Enable */
32#define IGC_WUFC_FLX4 BIT(20) /* Flexible Filter 4 Enable */
33#define IGC_WUFC_FLX5 BIT(21) /* Flexible Filter 5 Enable */
34#define IGC_WUFC_FLX6 BIT(22) /* Flexible Filter 6 Enable */
35#define IGC_WUFC_FLX7 BIT(23) /* Flexible Filter 7 Enable */
36
37#define IGC_WUFC_FILTER_MASK GENMASK(23, 14)
38
39#define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
40
41/* Wake Up Status */
42#define IGC_WUS_EX 0x00000004 /* Directed Exact */
43#define IGC_WUS_ARPD 0x00000020 /* Directed ARP Request */
44#define IGC_WUS_IPV4 0x00000040 /* Directed IPv4 */
45#define IGC_WUS_IPV6 0x00000080 /* Directed IPv6 */
46#define IGC_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */
47
48/* Packet types that are enabled for wake packet delivery */
49#define WAKE_PKT_WUS ( \
50 IGC_WUS_EX | \
51 IGC_WUS_ARPD | \
52 IGC_WUS_IPV4 | \
53 IGC_WUS_IPV6 | \
54 IGC_WUS_NSD)
55
56/* Wake Up Packet Length */
57#define IGC_WUPL_MASK 0x00000FFF
58
59/* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
60#define IGC_WUPM_BYTES 128
61
62/* Wakeup Filter Control Extended */
63#define IGC_WUFC_EXT_FLX8 BIT(8) /* Flexible Filter 8 Enable */
64#define IGC_WUFC_EXT_FLX9 BIT(9) /* Flexible Filter 9 Enable */
65#define IGC_WUFC_EXT_FLX10 BIT(10) /* Flexible Filter 10 Enable */
66#define IGC_WUFC_EXT_FLX11 BIT(11) /* Flexible Filter 11 Enable */
67#define IGC_WUFC_EXT_FLX12 BIT(12) /* Flexible Filter 12 Enable */
68#define IGC_WUFC_EXT_FLX13 BIT(13) /* Flexible Filter 13 Enable */
69#define IGC_WUFC_EXT_FLX14 BIT(14) /* Flexible Filter 14 Enable */
70#define IGC_WUFC_EXT_FLX15 BIT(15) /* Flexible Filter 15 Enable */
71#define IGC_WUFC_EXT_FLX16 BIT(16) /* Flexible Filter 16 Enable */
72#define IGC_WUFC_EXT_FLX17 BIT(17) /* Flexible Filter 17 Enable */
73#define IGC_WUFC_EXT_FLX18 BIT(18) /* Flexible Filter 18 Enable */
74#define IGC_WUFC_EXT_FLX19 BIT(19) /* Flexible Filter 19 Enable */
75#define IGC_WUFC_EXT_FLX20 BIT(20) /* Flexible Filter 20 Enable */
76#define IGC_WUFC_EXT_FLX21 BIT(21) /* Flexible Filter 21 Enable */
77#define IGC_WUFC_EXT_FLX22 BIT(22) /* Flexible Filter 22 Enable */
78#define IGC_WUFC_EXT_FLX23 BIT(23) /* Flexible Filter 23 Enable */
79#define IGC_WUFC_EXT_FLX24 BIT(24) /* Flexible Filter 24 Enable */
80#define IGC_WUFC_EXT_FLX25 BIT(25) /* Flexible Filter 25 Enable */
81#define IGC_WUFC_EXT_FLX26 BIT(26) /* Flexible Filter 26 Enable */
82#define IGC_WUFC_EXT_FLX27 BIT(27) /* Flexible Filter 27 Enable */
83#define IGC_WUFC_EXT_FLX28 BIT(28) /* Flexible Filter 28 Enable */
84#define IGC_WUFC_EXT_FLX29 BIT(29) /* Flexible Filter 29 Enable */
85#define IGC_WUFC_EXT_FLX30 BIT(30) /* Flexible Filter 30 Enable */
86#define IGC_WUFC_EXT_FLX31 BIT(31) /* Flexible Filter 31 Enable */
87
88#define IGC_WUFC_EXT_FILTER_MASK GENMASK(31, 8)
89
90/* Loop limit on how long we wait for auto-negotiation to complete */
91#define COPPER_LINK_UP_LIMIT 10
92#define PHY_AUTO_NEG_LIMIT 45
93
94/* Number of 100 microseconds we wait for PCI Express master disable */
95#define MASTER_DISABLE_TIMEOUT 800
96/*Blocks new Master requests */
97#define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004
98/* Status of Master requests. */
99#define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000
100
101/* Receive Address
102 * Number of high/low register pairs in the RAR. The RAR (Receive Address
103 * Registers) holds the directed and multicast addresses that we monitor.
104 * Technically, we have 16 spots. However, we reserve one of these spots
105 * (RAR[15]) for our directed address used by controllers with
106 * manageability enabled, allowing us room for 15 multicast addresses.
107 */
108#define IGC_RAH_RAH_MASK 0x0000FFFF
109#define IGC_RAH_ASEL_MASK 0x00030000
110#define IGC_RAH_ASEL_SRC_ADDR BIT(16)
111#define IGC_RAH_QSEL_MASK 0x000C0000
112#define IGC_RAH_QSEL_SHIFT 18
113#define IGC_RAH_QSEL_ENABLE BIT(28)
114#define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
115
116#define IGC_RAL_MAC_ADDR_LEN 4
117#define IGC_RAH_MAC_ADDR_LEN 2
118
119/* Error Codes */
120#define IGC_SUCCESS 0
121#define IGC_ERR_NVM 1
122#define IGC_ERR_PHY 2
123#define IGC_ERR_CONFIG 3
124#define IGC_ERR_PARAM 4
125#define IGC_ERR_MAC_INIT 5
126#define IGC_ERR_RESET 9
127#define IGC_ERR_MASTER_REQUESTS_PENDING 10
128#define IGC_ERR_BLK_PHY_RESET 12
129#define IGC_ERR_SWFW_SYNC 13
130
131/* Device Control */
132#define IGC_CTRL_RST 0x04000000 /* Global reset */
133
134#define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
135#define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
136#define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */
137#define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */
138#define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
139
140#define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
141#define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
142
143#define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
144#define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
145
146/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
147#define MAX_JUMBO_FRAME_SIZE 0x2600
148
149/* PBA constants */
150#define IGC_PBA_34K 0x0022
151
152/* SW Semaphore Register */
153#define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
154#define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
155
156/* SWFW_SYNC Definitions */
157#define IGC_SWFW_EEP_SM 0x1
158#define IGC_SWFW_PHY0_SM 0x2
159
160/* Autoneg Advertisement Register */
161#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
162#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
163#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
164#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
165#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
166#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
167
168/* Link Partner Ability Register (Base Page) */
169#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
170#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
171
172/* 1000BASE-T Control Register */
173#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
174#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
175
176/* 1000BASE-T Status Register */
177#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
178
179/* PHY GPY 211 registers */
180#define STANDARD_AN_REG_MASK 0x0007 /* MMD */
181#define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
182#define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */
183
184/* NVM Control */
185/* Number of milliseconds for NVM auto read done after MAC reset. */
186#define AUTO_READ_DONE_TIMEOUT 10
187#define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
188#define IGC_EECD_REQ 0x00000040 /* NVM Access Request */
189#define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */
190/* NVM Addressing bits based on type 0=small, 1=large */
191#define IGC_EECD_ADDR_BITS 0x00000400
192#define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
193#define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
194#define IGC_EECD_SIZE_EX_SHIFT 11
195#define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
196#define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/
197#define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */
198#define IGC_FLUDONE_ATTEMPTS 20000
199#define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
200
201/* Offset to data in NVM read/write registers */
202#define IGC_NVM_RW_REG_DATA 16
203#define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
204#define IGC_NVM_RW_REG_START 1 /* Start operation */
205#define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
206#define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */
207#define IGC_NVM_DEV_STARTER 5 /* Dev_starter Version */
208
209/* NVM Word Offsets */
210#define NVM_CHECKSUM_REG 0x003F
211
212/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
213#define NVM_SUM 0xBABA
214#define NVM_WORD_SIZE_BASE_SHIFT 6
215
216/* Collision related configuration parameters */
217#define IGC_COLLISION_THRESHOLD 15
218#define IGC_CT_SHIFT 4
219#define IGC_COLLISION_DISTANCE 63
220#define IGC_COLD_SHIFT 12
221
222/* Device Status */
223#define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
224#define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
225#define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
226#define IGC_STATUS_FUNC_SHIFT 2
227#define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */
228#define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
229#define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
230#define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */
231
232#define SPEED_10 10
233#define SPEED_100 100
234#define SPEED_1000 1000
235#define SPEED_2500 2500
236#define HALF_DUPLEX 1
237#define FULL_DUPLEX 2
238
239/* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
240#define ADVERTISE_10_HALF 0x0001
241#define ADVERTISE_10_FULL 0x0002
242#define ADVERTISE_100_HALF 0x0004
243#define ADVERTISE_100_FULL 0x0008
244#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
245#define ADVERTISE_1000_FULL 0x0020
246#define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */
247#define ADVERTISE_2500_FULL 0x0080
248
249#define IGC_ALL_SPEED_DUPLEX_2500 ( \
250 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
251 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
252
253#define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500
254
255/* Interrupt Cause Read */
256#define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
257#define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
258#define IGC_ICR_LSC BIT(2) /* Link Status Change */
259#define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
260#define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
261#define IGC_ICR_RXO BIT(6) /* Rx overrun */
262#define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
263#define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */
264#define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */
265
266/* If this bit asserted, the driver should claim the interrupt */
267#define IGC_ICR_INT_ASSERTED BIT(31)
268
269#define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
270
271#define IMS_ENABLE_MASK ( \
272 IGC_IMS_RXT0 | \
273 IGC_IMS_TXDW | \
274 IGC_IMS_RXDMT0 | \
275 IGC_IMS_RXSEQ | \
276 IGC_IMS_LSC)
277
278/* Interrupt Mask Set */
279#define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
280#define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
281#define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */
282#define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
283#define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
284#define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
285#define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
286#define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */
287
288#define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
289#define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
290
291/* Interrupt Cause Set */
292#define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */
293#define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */
294
295#define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
296#define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
297#define IGC_IVAR_VALID 0x80
298#define IGC_GPIE_NSICR 0x00000001
299#define IGC_GPIE_MSIX_MODE 0x00000010
300#define IGC_GPIE_EIAME 0x40000000
301#define IGC_GPIE_PBA 0x80000000
302
303/* Receive Descriptor bit definitions */
304#define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */
305
306/* Transmit Descriptor bit definitions */
307#define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */
308#define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */
309#define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
310#define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
311#define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */
312#define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */
313#define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
314#define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
315#define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */
316#define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */
317#define IGC_TXD_CMD_IP 0x02000000 /* IP packet */
318#define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
319#define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
320
321#define IGC_TXD_PTP2_TIMER_1 0x00000020
322
323/* IPSec Encrypt Enable */
324#define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
325#define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
326
327#define IGC_ADVTXD_TSN_CNTX_FIRST 0x00000080
328
329/* Transmit Control */
330#define IGC_TCTL_EN 0x00000002 /* enable Tx */
331#define IGC_TCTL_PSP 0x00000008 /* pad short packets */
332#define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
333#define IGC_TCTL_COLD 0x003ff000 /* collision distance */
334#define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
335
336/* Flow Control Constants */
337#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
338#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
339#define FLOW_CONTROL_TYPE 0x8808
340/* Enable XON frame transmission */
341#define IGC_FCRTL_XONE 0x80000000
342
343/* Management Control */
344#define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
345#define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
346
347/* Receive Control */
348#define IGC_RCTL_RST 0x00000001 /* Software reset */
349#define IGC_RCTL_EN 0x00000002 /* enable */
350#define IGC_RCTL_SBP 0x00000004 /* store bad packet */
351#define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
352#define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
353#define IGC_RCTL_LPE 0x00000020 /* long packet enable */
354#define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
355#define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
356
357#define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
358#define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
359
360/* Split Replication Receive Control */
361#define IGC_SRRCTL_TIMESTAMP 0x40000000
362#define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14)
363#define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17)
364
365/* Receive Descriptor bit definitions */
366#define IGC_RXD_STAT_EOP 0x02 /* End of Packet */
367#define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */
368#define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
369#define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
370#define IGC_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
371
372#define IGC_RXDEXT_STATERR_LB 0x00040000
373
374/* Advanced Receive Descriptor bit definitions */
375#define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
376
377#define IGC_RXDEXT_STATERR_L4E 0x20000000
378#define IGC_RXDEXT_STATERR_IPE 0x40000000
379#define IGC_RXDEXT_STATERR_RXE 0x80000000
380
381#define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
382#define IGC_MRQC_RSS_FIELD_IPV4 0x00020000
383#define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
384#define IGC_MRQC_RSS_FIELD_IPV6 0x00100000
385#define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
386
387/* Header split receive */
388#define IGC_RFCTL_IPV6_EX_DIS 0x00010000
389#define IGC_RFCTL_LEF 0x00040000
390
391#define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
392
393#define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */
394#define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
395#define IGC_RCTL_DPF 0x00400000 /* discard pause frames */
396#define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */
397#define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
398
399#define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
400#define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
401#define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
402
403#define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */
404
405#define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */
406#define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
407
408/* Retry Buffer Control */
409#define IGC_RETX_CTL 0x041C
410#define IGC_RETX_CTL_WATERMARK_MASK 0xF
411#define IGC_RETX_CTL_QBVFULLTH_SHIFT 8 /* QBV Retry Buffer Full Threshold */
412#define IGC_RETX_CTL_QBVFULLEN 0x1000 /* Enable QBV Retry Buffer Full Threshold */
413
414/* Transmit Scheduling Latency */
415/* Latency between transmission scheduling (LaunchTime) and the time
416 * the packet is transmitted to the network in nanosecond.
417 */
418#define IGC_TXOFFSET_SPEED_10 0x000034BC
419#define IGC_TXOFFSET_SPEED_100 0x00000578
420#define IGC_TXOFFSET_SPEED_1000 0x0000012C
421#define IGC_TXOFFSET_SPEED_2500 0x00000578
422
423/* Time Sync Interrupt Causes */
424#define IGC_TSICR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
425#define IGC_TSICR_TXTS BIT(1) /* Transmit Timestamp. */
426#define IGC_TSICR_TT0 BIT(3) /* Target Time 0 Trigger. */
427#define IGC_TSICR_TT1 BIT(4) /* Target Time 1 Trigger. */
428#define IGC_TSICR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */
429#define IGC_TSICR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
430
431#define IGC_TSICR_INTERRUPTS IGC_TSICR_TXTS
432
433#define IGC_FTQF_VF_BP 0x00008000
434#define IGC_FTQF_1588_TIME_STAMP 0x08000000
435#define IGC_FTQF_MASK 0xF0000000
436#define IGC_FTQF_MASK_PROTO_BP 0x10000000
437
438/* Time Sync Receive Control bit definitions */
439#define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
440#define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00
441#define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02
442#define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
443#define IGC_TSYNCRXCTL_TYPE_ALL 0x08
444#define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
445#define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
446#define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
447#define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 /* Sample RX tstamp in PHY sop */
448
449/* Time Sync Receive Configuration */
450#define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
451#define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
452#define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
453
454/* Immediate Interrupt Receive */
455#define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
456#define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
457#define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
458#define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
459
460/* Immediate Interrupt Receive Extended */
461#define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
462#define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
463
464/* Time Sync Transmit Control bit definitions */
465#define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
466#define IGC_TSYNCTXCTL_TXTT_1 0x00000002 /* Tx timestamp reg 1 valid */
467#define IGC_TSYNCTXCTL_TXTT_2 0x00000004 /* Tx timestamp reg 2 valid */
468#define IGC_TSYNCTXCTL_TXTT_3 0x00000008 /* Tx timestamp reg 3 valid */
469#define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
470#define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
471#define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
472#define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
473#define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
474#define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */
475
476#define IGC_TSYNCTXCTL_TXTT_ANY ( \
477 IGC_TSYNCTXCTL_TXTT_0 | IGC_TSYNCTXCTL_TXTT_1 | \
478 IGC_TSYNCTXCTL_TXTT_2 | IGC_TSYNCTXCTL_TXTT_3)
479
480/* Timer selection bits */
481#define IGC_AUX_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for auxiliary time stamp */
482#define IGC_AUX_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for auxiliary time stamp */
483#define IGC_AUX_IO_TIMER_SEL_SYSTIM2 (2u << 30) /* Select SYSTIM2 for auxiliary time stamp */
484#define IGC_AUX_IO_TIMER_SEL_SYSTIM3 (3u << 30) /* Select SYSTIM3 for auxiliary time stamp */
485#define IGC_TT_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for target time stamp */
486#define IGC_TT_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for target time stamp */
487#define IGC_TT_IO_TIMER_SEL_SYSTIM2 (2u << 30) /* Select SYSTIM2 for target time stamp */
488#define IGC_TT_IO_TIMER_SEL_SYSTIM3 (3u << 30) /* Select SYSTIM3 for target time stamp */
489
490/* TSAUXC Configuration Bits */
491#define IGC_TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
492#define IGC_TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
493#define IGC_TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
494#define IGC_TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */
495#define IGC_TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
496#define IGC_TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
497#define IGC_TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
498#define IGC_TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */
499#define IGC_TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
500#define IGC_TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */
501#define IGC_TSAUXC_PLSG BIT(17) /* Generate a pulse. */
502#define IGC_TSAUXC_DISABLE1 BIT(27) /* Disable SYSTIM0 Count Operation. */
503#define IGC_TSAUXC_DISABLE2 BIT(28) /* Disable SYSTIM1 Count Operation. */
504#define IGC_TSAUXC_DISABLE3 BIT(29) /* Disable SYSTIM2 Count Operation. */
505#define IGC_TSAUXC_DIS_TS_CLEAR BIT(30) /* Disable EN_TT0/1 auto clear. */
506#define IGC_TSAUXC_DISABLE0 BIT(31) /* Disable SYSTIM0 Count Operation. */
507
508/* SDP Configuration Bits */
509#define IGC_AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
510#define IGC_AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
511#define IGC_AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
512#define IGC_AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
513#define IGC_AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
514#define IGC_AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
515#define IGC_AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
516#define IGC_AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
517#define IGC_AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
518#define IGC_AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
519#define IGC_TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
520#define IGC_TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
521#define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
522#define IGC_TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
523#define IGC_TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
524#define IGC_TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
525#define IGC_TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
526#define IGC_TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
527#define IGC_TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
528#define IGC_TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
529#define IGC_TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
530#define IGC_TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
531#define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
532#define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
533#define IGC_TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
534#define IGC_TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
535#define IGC_TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
536#define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
537#define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
538#define IGC_TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
539
540/* Transmit Scheduling */
541#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001
542#define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008
543#define IGC_TQAVCTRL_FUTSCDDIS 0x00000080
544
545#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001
546#define IGC_TXQCTL_STRICT_CYCLE 0x00000002
547#define IGC_TXQCTL_STRICT_END 0x00000004
548#define IGC_TXQCTL_QAV_SEL_MASK 0x000000C0
549#define IGC_TXQCTL_QAV_SEL_CBS0 0x00000080
550#define IGC_TXQCTL_QAV_SEL_CBS1 0x000000C0
551
552#define IGC_TQAVCC_IDLESLOPE_MASK 0xFFFF
553#define IGC_TQAVCC_KEEP_CREDITS BIT(30)
554
555#define IGC_MAX_SR_QUEUES 2
556
557#define IGC_TXARB_TXQ_PRIO_0_MASK GENMASK(1, 0)
558#define IGC_TXARB_TXQ_PRIO_1_MASK GENMASK(3, 2)
559#define IGC_TXARB_TXQ_PRIO_2_MASK GENMASK(5, 4)
560#define IGC_TXARB_TXQ_PRIO_3_MASK GENMASK(7, 6)
561#define IGC_TXARB_TXQ_PRIO_0(x) FIELD_PREP(IGC_TXARB_TXQ_PRIO_0_MASK, (x))
562#define IGC_TXARB_TXQ_PRIO_1(x) FIELD_PREP(IGC_TXARB_TXQ_PRIO_1_MASK, (x))
563#define IGC_TXARB_TXQ_PRIO_2(x) FIELD_PREP(IGC_TXARB_TXQ_PRIO_2_MASK, (x))
564#define IGC_TXARB_TXQ_PRIO_3(x) FIELD_PREP(IGC_TXARB_TXQ_PRIO_3_MASK, (x))
565
566/* Receive Checksum Control */
567#define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
568#define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
569
570/* PCIe PTM Control */
571#define IGC_PTM_CTRL_START_NOW BIT(29) /* Start PTM Now */
572#define IGC_PTM_CTRL_EN BIT(30) /* Enable PTM */
573#define IGC_PTM_CTRL_TRIG BIT(31) /* PTM Cycle trigger */
574#define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2)
575#define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8)
576
577#define IGC_PTM_SHORT_CYC_DEFAULT 1 /* Default short cycle interval */
578#define IGC_PTM_CYC_TIME_DEFAULT 5 /* Default PTM cycle time */
579#define IGC_PTM_TIMEOUT_DEFAULT 255 /* Default timeout for PTM errors */
580
581/* PCIe Digital Delay */
582#define IGC_PCIE_DIG_DELAY_DEFAULT 0x01440000
583
584/* PCIe PHY Delay */
585#define IGC_PCIE_PHY_DELAY_DEFAULT 0x40900000
586
587#define IGC_TIMADJ_ADJUST_METH 0x40000000
588
589/* PCIe PTM Status */
590#define IGC_PTM_STAT_VALID BIT(0) /* PTM Status */
591#define IGC_PTM_STAT_RET_ERR BIT(1) /* Root port timeout */
592#define IGC_PTM_STAT_BAD_PTM_RES BIT(2) /* PTM Response msg instead of PTM Response Data */
593#define IGC_PTM_STAT_T4M1_OVFL BIT(3) /* T4 minus T1 overflow */
594#define IGC_PTM_STAT_ADJUST_1ST BIT(4) /* 1588 timer adjusted during 1st PTM cycle */
595#define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
596
597/* PCIe PTM Cycle Control */
598#define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec) ((msec) & 0x3ff) /* PTM Cycle Time (msec) */
599#define IGC_PTM_CYCLE_CTRL_AUTO_CYC_EN BIT(31) /* PTM Cycle Control */
600
601/* GPY211 - I225 defines */
602#define GPY_MMD_MASK 0xFFFF0000
603#define GPY_MMD_SHIFT 16
604#define GPY_REG_MASK 0x0000FFFF
605
606#define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
607
608/* MAC definitions */
609#define IGC_FACTPS_MNGCG 0x20000000
610#define IGC_FWSM_MODE_MASK 0xE
611#define IGC_FWSM_MODE_SHIFT 1
612
613/* Management Control */
614#define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
615#define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
616
617/* PHY */
618#define PHY_REVISION_MASK 0xFFFFFFF0
619#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
620#define IGC_GEN_POLL_TIMEOUT 1920
621
622/* PHY Control Register */
623#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
624#define MII_CR_POWER_DOWN 0x0800 /* Power down */
625#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
626
627/* PHY Status Register */
628#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
629#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
630#define IGC_PHY_RST_COMP 0x0100 /* Internal PHY reset completion */
631
632/* PHY 1000 MII Register/Bit Definitions */
633/* PHY Registers defined by IEEE */
634#define PHY_CONTROL 0x00 /* Control Register */
635#define PHY_STATUS 0x01 /* Status Register */
636#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
637#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
638#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
639#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
640#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
641#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
642
643/* MDI Control */
644#define IGC_MDIC_DATA_MASK 0x0000FFFF
645#define IGC_MDIC_REG_MASK 0x001F0000
646#define IGC_MDIC_REG_SHIFT 16
647#define IGC_MDIC_PHY_MASK 0x03E00000
648#define IGC_MDIC_PHY_SHIFT 21
649#define IGC_MDIC_OP_WRITE 0x04000000
650#define IGC_MDIC_OP_READ 0x08000000
651#define IGC_MDIC_READY 0x10000000
652#define IGC_MDIC_ERROR 0x40000000
653
654/* EEE Link Ability */
655#define IGC_EEE_2500BT_MASK BIT(0)
656#define IGC_EEE_1000BT_MASK BIT(2)
657#define IGC_EEE_100BT_MASK BIT(1)
658
659/* EEE Link-Partner Ability */
660#define IGC_LP_EEE_2500BT_MASK BIT(0)
661#define IGC_LP_EEE_1000BT_MASK BIT(2)
662#define IGC_LP_EEE_100BT_MASK BIT(1)
663
664#define IGC_N0_QUEUE -1
665
666#define IGC_MAX_MAC_HDR_LEN 127
667#define IGC_MAX_NETWORK_HDR_LEN 511
668
669#define IGC_VLANPQF_QSEL(_n, q_idx) ((q_idx) << ((_n) * 4))
670#define IGC_VLANPQF_VALID(_n) (0x1 << (3 + (_n) * 4))
671#define IGC_VLANPQF_QUEUE_MASK 0x03
672
673#define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
674#define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */
675#define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet Type of TCP */
676#define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
677
678/* Maximum size of the MTA register table in all supported adapters */
679#define MAX_MTA_REG 128
680
681/* EEE defines */
682#define IGC_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */
683#define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
684#define IGC_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
685#define IGC_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
686#define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
687#define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
688#define IGC_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
689#define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
690
691/* LTR defines */
692#define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */
693#define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */
694#define IGC_TW_SYSTEM_1000_MASK 0x000000FF
695/* Minimum time for 100BASE-T where no data will be transmit following move out
696 * of EEE LPI Tx state
697 */
698#define IGC_TW_SYSTEM_100_MASK 0x0000FF00
699#define IGC_TW_SYSTEM_100_SHIFT 8
700/* Reg val to set scale to 1024 nsec */
701#define IGC_LTRMINV_SCALE_1024 2
702/* Reg val to set scale to 32768 nsec */
703#define IGC_LTRMINV_SCALE_32768 3
704/* Reg val to set scale to 1024 nsec */
705#define IGC_LTRMAXV_SCALE_1024 2
706/* Reg val to set scale to 32768 nsec */
707#define IGC_LTRMAXV_SCALE_32768 3
708#define IGC_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */
709#define IGC_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */
710#define IGC_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */
711#define IGC_LTRMINV_SCALE_SHIFT 10
712#define IGC_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */
713#define IGC_LTRMAXV_SCALE_SHIFT 10
714
715#endif /* _IGC_DEFINES_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_DEFINES_H_
5#define _IGC_DEFINES_H_
6
7/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
8#define REQ_TX_DESCRIPTOR_MULTIPLE 8
9#define REQ_RX_DESCRIPTOR_MULTIPLE 8
10
11#define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
12
13/* Physical Func Reset Done Indication */
14#define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000
15
16/* Loop limit on how long we wait for auto-negotiation to complete */
17#define COPPER_LINK_UP_LIMIT 10
18#define PHY_AUTO_NEG_LIMIT 45
19#define PHY_FORCE_LIMIT 20
20
21/* Number of 100 microseconds we wait for PCI Express master disable */
22#define MASTER_DISABLE_TIMEOUT 800
23/*Blocks new Master requests */
24#define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004
25/* Status of Master requests. */
26#define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000
27
28/* Receive Address
29 * Number of high/low register pairs in the RAR. The RAR (Receive Address
30 * Registers) holds the directed and multicast addresses that we monitor.
31 * Technically, we have 16 spots. However, we reserve one of these spots
32 * (RAR[15]) for our directed address used by controllers with
33 * manageability enabled, allowing us room for 15 multicast addresses.
34 */
35#define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
36#define IGC_RAH_POOL_1 0x00040000
37#define IGC_RAL_MAC_ADDR_LEN 4
38#define IGC_RAH_MAC_ADDR_LEN 2
39
40/* Error Codes */
41#define IGC_SUCCESS 0
42#define IGC_ERR_NVM 1
43#define IGC_ERR_PHY 2
44#define IGC_ERR_CONFIG 3
45#define IGC_ERR_PARAM 4
46#define IGC_ERR_MAC_INIT 5
47#define IGC_ERR_RESET 9
48#define IGC_ERR_MASTER_REQUESTS_PENDING 10
49#define IGC_ERR_BLK_PHY_RESET 12
50#define IGC_ERR_SWFW_SYNC 13
51
52/* Device Control */
53#define IGC_CTRL_DEV_RST 0x20000000 /* Device reset */
54
55#define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
56#define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
57#define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */
58#define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */
59
60#define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
61#define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
62
63#define IGC_CONNSW_AUTOSENSE_EN 0x1
64
65/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
66#define MAX_JUMBO_FRAME_SIZE 0x2600
67
68/* PBA constants */
69#define IGC_PBA_34K 0x0022
70
71/* SW Semaphore Register */
72#define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
73#define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
74
75/* SWFW_SYNC Definitions */
76#define IGC_SWFW_EEP_SM 0x1
77#define IGC_SWFW_PHY0_SM 0x2
78
79/* Autoneg Advertisement Register */
80#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
81#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
82#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
83#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
84#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
85#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
86
87/* Link Partner Ability Register (Base Page) */
88#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
89#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
90
91/* 1000BASE-T Control Register */
92#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
93#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
94#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
95
96/* 1000BASE-T Status Register */
97#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
98#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
99
100/* PHY GPY 211 registers */
101#define STANDARD_AN_REG_MASK 0x0007 /* MMD */
102#define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */
103#define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
104#define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */
105
106/* NVM Control */
107/* Number of milliseconds for NVM auto read done after MAC reset. */
108#define AUTO_READ_DONE_TIMEOUT 10
109#define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
110#define IGC_EECD_REQ 0x00000040 /* NVM Access Request */
111#define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */
112/* NVM Addressing bits based on type 0=small, 1=large */
113#define IGC_EECD_ADDR_BITS 0x00000400
114#define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
115#define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
116#define IGC_EECD_SIZE_EX_SHIFT 11
117#define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
118#define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/
119#define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */
120#define IGC_FLUDONE_ATTEMPTS 20000
121#define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
122
123/* Offset to data in NVM read/write registers */
124#define IGC_NVM_RW_REG_DATA 16
125#define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
126#define IGC_NVM_RW_REG_START 1 /* Start operation */
127#define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
128#define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */
129
130/* NVM Word Offsets */
131#define NVM_CHECKSUM_REG 0x003F
132
133/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
134#define NVM_SUM 0xBABA
135
136#define NVM_PBA_OFFSET_0 8
137#define NVM_PBA_OFFSET_1 9
138#define NVM_RESERVED_WORD 0xFFFF
139#define NVM_PBA_PTR_GUARD 0xFAFA
140#define NVM_WORD_SIZE_BASE_SHIFT 6
141
142/* Collision related configuration parameters */
143#define IGC_COLLISION_THRESHOLD 15
144#define IGC_CT_SHIFT 4
145#define IGC_COLLISION_DISTANCE 63
146#define IGC_COLD_SHIFT 12
147
148/* Device Status */
149#define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
150#define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
151#define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
152#define IGC_STATUS_FUNC_SHIFT 2
153#define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */
154#define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */
155#define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
156#define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
157#define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */
158
159#define SPEED_10 10
160#define SPEED_100 100
161#define SPEED_1000 1000
162#define SPEED_2500 2500
163#define HALF_DUPLEX 1
164#define FULL_DUPLEX 2
165
166/* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
167#define ADVERTISE_10_HALF 0x0001
168#define ADVERTISE_10_FULL 0x0002
169#define ADVERTISE_100_HALF 0x0004
170#define ADVERTISE_100_FULL 0x0008
171#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
172#define ADVERTISE_1000_FULL 0x0020
173#define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */
174#define ADVERTISE_2500_FULL 0x0080
175
176#define IGC_ALL_SPEED_DUPLEX_2500 ( \
177 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
178 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
179
180#define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500
181
182/* Interrupt Cause Read */
183#define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
184#define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
185#define IGC_ICR_LSC BIT(2) /* Link Status Change */
186#define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
187#define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
188#define IGC_ICR_RXO BIT(6) /* Rx overrun */
189#define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
190#define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */
191
192/* If this bit asserted, the driver should claim the interrupt */
193#define IGC_ICR_INT_ASSERTED BIT(31)
194
195#define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
196
197#define IMS_ENABLE_MASK ( \
198 IGC_IMS_RXT0 | \
199 IGC_IMS_TXDW | \
200 IGC_IMS_RXDMT0 | \
201 IGC_IMS_RXSEQ | \
202 IGC_IMS_LSC)
203
204/* Interrupt Mask Set */
205#define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
206#define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
207#define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */
208#define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
209#define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
210#define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
211#define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
212
213#define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
214#define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
215
216/* Interrupt Cause Set */
217#define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */
218#define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */
219#define IGC_ICS_DRSTA IGC_ICR_DRSTA /* Device Reset Aserted */
220
221#define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
222#define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
223#define IGC_IVAR_VALID 0x80
224#define IGC_GPIE_NSICR 0x00000001
225#define IGC_GPIE_MSIX_MODE 0x00000010
226#define IGC_GPIE_EIAME 0x40000000
227#define IGC_GPIE_PBA 0x80000000
228
229/* Transmit Descriptor bit definitions */
230#define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */
231#define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */
232#define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
233#define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
234#define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */
235#define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
236#define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */
237#define IGC_TXD_CMD_RS 0x08000000 /* Report Status */
238#define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
239#define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
240#define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
241#define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
242#define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */
243#define IGC_TXD_STAT_EC 0x00000002 /* Excess Collisions */
244#define IGC_TXD_STAT_LC 0x00000004 /* Late Collisions */
245#define IGC_TXD_STAT_TU 0x00000008 /* Transmit underrun */
246#define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */
247#define IGC_TXD_CMD_IP 0x02000000 /* IP packet */
248#define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
249#define IGC_TXD_STAT_TC 0x00000004 /* Tx Underrun */
250#define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
251
252/* Transmit Control */
253#define IGC_TCTL_EN 0x00000002 /* enable Tx */
254#define IGC_TCTL_PSP 0x00000008 /* pad short packets */
255#define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
256#define IGC_TCTL_COLD 0x003ff000 /* collision distance */
257#define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
258#define IGC_TCTL_MULR 0x10000000 /* Multiple request support */
259
260/* Flow Control Constants */
261#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
262#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
263#define FLOW_CONTROL_TYPE 0x8808
264/* Enable XON frame transmission */
265#define IGC_FCRTL_XONE 0x80000000
266
267/* Management Control */
268#define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
269#define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
270
271/* Receive Control */
272#define IGC_RCTL_RST 0x00000001 /* Software reset */
273#define IGC_RCTL_EN 0x00000002 /* enable */
274#define IGC_RCTL_SBP 0x00000004 /* store bad packet */
275#define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
276#define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
277#define IGC_RCTL_LPE 0x00000020 /* long packet enable */
278#define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
279#define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
280
281#define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
282#define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
283
284/* Receive Descriptor bit definitions */
285#define IGC_RXD_STAT_EOP 0x02 /* End of Packet */
286
287#define IGC_RXDEXT_STATERR_CE 0x01000000
288#define IGC_RXDEXT_STATERR_SE 0x02000000
289#define IGC_RXDEXT_STATERR_SEQ 0x04000000
290#define IGC_RXDEXT_STATERR_CXE 0x10000000
291#define IGC_RXDEXT_STATERR_TCPE 0x20000000
292#define IGC_RXDEXT_STATERR_IPE 0x40000000
293#define IGC_RXDEXT_STATERR_RXE 0x80000000
294
295/* Same mask, but for extended and packet split descriptors */
296#define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \
297 IGC_RXDEXT_STATERR_CE | \
298 IGC_RXDEXT_STATERR_SE | \
299 IGC_RXDEXT_STATERR_SEQ | \
300 IGC_RXDEXT_STATERR_CXE | \
301 IGC_RXDEXT_STATERR_RXE)
302
303#define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
304#define IGC_MRQC_RSS_FIELD_IPV4 0x00020000
305#define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
306#define IGC_MRQC_RSS_FIELD_IPV6 0x00100000
307#define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
308
309/* Header split receive */
310#define IGC_RFCTL_IPV6_EX_DIS 0x00010000
311#define IGC_RFCTL_LEF 0x00040000
312
313#define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
314
315#define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */
316#define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
317#define IGC_RCTL_DPF 0x00400000 /* discard pause frames */
318#define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */
319#define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
320
321#define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
322#define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
323
324/* Receive Checksum Control */
325#define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
326#define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
327
328/* GPY211 - I225 defines */
329#define GPY_MMD_MASK 0xFFFF0000
330#define GPY_MMD_SHIFT 16
331#define GPY_REG_MASK 0x0000FFFF
332
333#define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
334
335/* MAC definitions */
336#define IGC_FACTPS_MNGCG 0x20000000
337#define IGC_FWSM_MODE_MASK 0xE
338#define IGC_FWSM_MODE_SHIFT 1
339
340/* Management Control */
341#define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
342#define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
343
344/* PHY */
345#define PHY_REVISION_MASK 0xFFFFFFF0
346#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
347#define IGC_GEN_POLL_TIMEOUT 1920
348
349/* PHY Control Register */
350#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
351#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
352#define MII_CR_POWER_DOWN 0x0800 /* Power down */
353#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
354#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
355#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
356#define MII_CR_SPEED_1000 0x0040
357#define MII_CR_SPEED_100 0x2000
358#define MII_CR_SPEED_10 0x0000
359
360/* PHY Status Register */
361#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
362#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
363
364/* PHY 1000 MII Register/Bit Definitions */
365/* PHY Registers defined by IEEE */
366#define PHY_CONTROL 0x00 /* Control Register */
367#define PHY_STATUS 0x01 /* Status Register */
368#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
369#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
370#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
371#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
372#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
373#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
374
375/* Bit definitions for valid PHY IDs. I = Integrated E = External */
376#define I225_I_PHY_ID 0x67C9DC00
377
378/* MDI Control */
379#define IGC_MDIC_DATA_MASK 0x0000FFFF
380#define IGC_MDIC_REG_MASK 0x001F0000
381#define IGC_MDIC_REG_SHIFT 16
382#define IGC_MDIC_PHY_MASK 0x03E00000
383#define IGC_MDIC_PHY_SHIFT 21
384#define IGC_MDIC_OP_WRITE 0x04000000
385#define IGC_MDIC_OP_READ 0x08000000
386#define IGC_MDIC_READY 0x10000000
387#define IGC_MDIC_INT_EN 0x20000000
388#define IGC_MDIC_ERROR 0x40000000
389#define IGC_MDIC_DEST 0x80000000
390
391#define IGC_N0_QUEUE -1
392
393#define IGC_MAX_MAC_HDR_LEN 127
394#define IGC_MAX_NETWORK_HDR_LEN 511
395
396#define IGC_VLAPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4))
397#define IGC_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4))
398#define IGC_VLAPQF_QUEUE_MASK 0x03
399
400#define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
401#define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */
402#define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet Type of TCP */
403#define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
404
405#endif /* _IGC_DEFINES_H_ */