Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 */
4#ifndef LINUX_MMC_CQHCI_H
5#define LINUX_MMC_CQHCI_H
6
7#include <linux/compiler.h>
8#include <linux/bitfield.h>
9#include <linux/bitops.h>
10#include <linux/spinlock_types.h>
11#include <linux/types.h>
12#include <linux/completion.h>
13#include <linux/wait.h>
14#include <linux/irqreturn.h>
15#include <asm/io.h>
16
17/* registers */
18/* version */
19#define CQHCI_VER 0x00
20#define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)
21#define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)
22#define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))
23
24/* capabilities */
25#define CQHCI_CAP 0x04
26#define CQHCI_CAP_CS 0x10000000 /* Crypto Support */
27#define CQHCI_CAP_ITCFMUL GENMASK(15, 12)
28#define CQHCI_ITCFMUL(x) FIELD_GET(CQHCI_CAP_ITCFMUL, (x))
29
30/* configuration */
31#define CQHCI_CFG 0x08
32#define CQHCI_DCMD 0x00001000
33#define CQHCI_TASK_DESC_SZ 0x00000100
34#define CQHCI_CRYPTO_GENERAL_ENABLE 0x00000002
35#define CQHCI_ENABLE 0x00000001
36
37/* control */
38#define CQHCI_CTL 0x0C
39#define CQHCI_CLEAR_ALL_TASKS 0x00000100
40#define CQHCI_HALT 0x00000001
41
42/* interrupt status */
43#define CQHCI_IS 0x10
44#define CQHCI_IS_HAC BIT(0)
45#define CQHCI_IS_TCC BIT(1)
46#define CQHCI_IS_RED BIT(2)
47#define CQHCI_IS_TCL BIT(3)
48#define CQHCI_IS_GCE BIT(4) /* General Crypto Error */
49#define CQHCI_IS_ICCE BIT(5) /* Invalid Crypto Config Error */
50
51#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
52 CQHCI_IS_GCE | CQHCI_IS_ICCE)
53
54/* interrupt status enable */
55#define CQHCI_ISTE 0x14
56
57/* interrupt signal enable */
58#define CQHCI_ISGE 0x18
59
60/* interrupt coalescing */
61#define CQHCI_IC 0x1C
62#define CQHCI_IC_ENABLE BIT(31)
63#define CQHCI_IC_RESET BIT(16)
64#define CQHCI_IC_ICCTHWEN BIT(15)
65#define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8)
66#define CQHCI_IC_ICTOVALWEN BIT(7)
67#define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F)
68
69/* task list base address */
70#define CQHCI_TDLBA 0x20
71
72/* task list base address upper */
73#define CQHCI_TDLBAU 0x24
74
75/* door-bell */
76#define CQHCI_TDBR 0x28
77
78/* task completion notification */
79#define CQHCI_TCN 0x2C
80
81/* device queue status */
82#define CQHCI_DQS 0x30
83
84/* device pending tasks */
85#define CQHCI_DPT 0x34
86
87/* task clear */
88#define CQHCI_TCLR 0x38
89
90/* task descriptor processing error */
91#define CQHCI_TDPE 0x3c
92
93/* send status config 1 */
94#define CQHCI_SSC1 0x40
95#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
96
97/* send status config 2 */
98#define CQHCI_SSC2 0x44
99
100/* response for dcmd */
101#define CQHCI_CRDCT 0x48
102
103/* response mode error mask */
104#define CQHCI_RMEM 0x50
105
106/* task error info */
107#define CQHCI_TERRI 0x54
108
109#define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))
110#define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)
111#define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15))
112#define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)
113#define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)
114#define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31))
115
116/* command response index */
117#define CQHCI_CRI 0x58
118
119/* command response argument */
120#define CQHCI_CRA 0x5C
121
122/* crypto capabilities */
123#define CQHCI_CCAP 0x100
124#define CQHCI_CRYPTOCAP 0x104
125
126#define CQHCI_INT_ALL 0xF
127#define CQHCI_IC_DEFAULT_ICCTH 31
128#define CQHCI_IC_DEFAULT_ICTOVAL 1
129
130/* attribute fields */
131#define CQHCI_VALID(x) (((x) & 1) << 0)
132#define CQHCI_END(x) (((x) & 1) << 1)
133#define CQHCI_INT(x) (((x) & 1) << 2)
134#define CQHCI_ACT(x) (((x) & 0x7) << 3)
135
136/* data command task descriptor fields */
137#define CQHCI_FORCED_PROG(x) (((x) & 1) << 6)
138#define CQHCI_CONTEXT(x) (((x) & 0xF) << 7)
139#define CQHCI_DATA_TAG(x) (((x) & 1) << 11)
140#define CQHCI_DATA_DIR(x) (((x) & 1) << 12)
141#define CQHCI_PRIORITY(x) (((x) & 1) << 13)
142#define CQHCI_QBAR(x) (((x) & 1) << 14)
143#define CQHCI_REL_WRITE(x) (((x) & 1) << 15)
144#define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16)
145#define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32)
146
147/* direct command task descriptor fields */
148#define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16)
149#define CQHCI_CMD_TIMING(x) (((x) & 1) << 22)
150#define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23)
151
152/* crypto task descriptor fields (for bits 64-127 of task descriptor) */
153#define CQHCI_CRYPTO_ENABLE_BIT (1ULL << 47)
154#define CQHCI_CRYPTO_KEYSLOT(x) ((u64)(x) << 32)
155
156/* transfer descriptor fields */
157#define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16)
158#define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
159#define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
160
161/* CCAP - Crypto Capability 100h */
162union cqhci_crypto_capabilities {
163 __le32 reg_val;
164 struct {
165 u8 num_crypto_cap;
166 u8 config_count;
167 u8 reserved;
168 u8 config_array_ptr;
169 };
170};
171
172enum cqhci_crypto_key_size {
173 CQHCI_CRYPTO_KEY_SIZE_INVALID = 0,
174 CQHCI_CRYPTO_KEY_SIZE_128 = 1,
175 CQHCI_CRYPTO_KEY_SIZE_192 = 2,
176 CQHCI_CRYPTO_KEY_SIZE_256 = 3,
177 CQHCI_CRYPTO_KEY_SIZE_512 = 4,
178};
179
180enum cqhci_crypto_alg {
181 CQHCI_CRYPTO_ALG_AES_XTS = 0,
182 CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC = 1,
183 CQHCI_CRYPTO_ALG_AES_ECB = 2,
184 CQHCI_CRYPTO_ALG_ESSIV_AES_CBC = 3,
185};
186
187/* x-CRYPTOCAP - Crypto Capability X */
188union cqhci_crypto_cap_entry {
189 __le32 reg_val;
190 struct {
191 u8 algorithm_id;
192 u8 sdus_mask; /* Supported data unit size mask */
193 u8 key_size;
194 u8 reserved;
195 };
196};
197
198#define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
199#define CQHCI_CRYPTO_KEY_MAX_SIZE 64
200/* x-CRYPTOCFG - Crypto Configuration X */
201union cqhci_crypto_cfg_entry {
202 __le32 reg_val[32];
203 struct {
204 u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
205 u8 data_unit_size;
206 u8 crypto_cap_idx;
207 u8 reserved_1;
208 u8 config_enable;
209 u8 reserved_multi_host;
210 u8 reserved_2;
211 u8 vsb[2];
212 u8 reserved_3[56];
213 };
214};
215
216struct cqhci_host_ops;
217struct mmc_host;
218struct mmc_request;
219struct cqhci_slot;
220
221struct cqhci_host {
222 const struct cqhci_host_ops *ops;
223 void __iomem *mmio;
224 struct mmc_host *mmc;
225
226 spinlock_t lock;
227
228 /* relative card address of device */
229 unsigned int rca;
230
231 /* 64 bit DMA */
232 bool dma64;
233 int num_slots;
234 int qcnt;
235
236 u32 dcmd_slot;
237 u32 caps;
238#define CQHCI_TASK_DESC_SZ_128 0x1
239
240 u32 quirks;
241#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
242
243 bool enabled;
244 bool halted;
245 bool init_done;
246 bool activated;
247 bool waiting_for_idle;
248 bool recovery_halt;
249
250 size_t desc_size;
251 size_t data_size;
252
253 u8 *desc_base;
254
255 /* total descriptor size */
256 u8 slot_sz;
257
258 /* 64/128 bit depends on CQHCI_CFG */
259 u8 task_desc_len;
260
261 /* 64 bit on 32-bit arch, 128 bit on 64-bit */
262 u8 link_desc_len;
263
264 u8 *trans_desc_base;
265 /* same length as transfer descriptor */
266 u8 trans_desc_len;
267
268 dma_addr_t desc_dma_base;
269 dma_addr_t trans_desc_dma_base;
270
271 struct completion halt_comp;
272 wait_queue_head_t wait_queue;
273 struct cqhci_slot *slot;
274
275#ifdef CONFIG_MMC_CRYPTO
276 union cqhci_crypto_capabilities crypto_capabilities;
277 union cqhci_crypto_cap_entry *crypto_cap_array;
278 u32 crypto_cfg_register;
279#endif
280};
281
282struct cqhci_host_ops {
283 void (*dumpregs)(struct mmc_host *mmc);
284 void (*write_l)(struct cqhci_host *host, u32 val, int reg);
285 u32 (*read_l)(struct cqhci_host *host, int reg);
286 void (*enable)(struct mmc_host *mmc);
287 void (*disable)(struct mmc_host *mmc, bool recovery);
288 void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
289 u64 *data);
290 void (*pre_enable)(struct mmc_host *mmc);
291 void (*post_disable)(struct mmc_host *mmc);
292#ifdef CONFIG_MMC_CRYPTO
293 int (*program_key)(struct cqhci_host *cq_host,
294 const union cqhci_crypto_cfg_entry *cfg, int slot);
295#endif
296 void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc,
297 dma_addr_t addr, int len, bool end, bool dma64);
298
299};
300
301static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
302{
303 if (unlikely(host->ops->write_l))
304 host->ops->write_l(host, val, reg);
305 else
306 writel_relaxed(val, host->mmio + reg);
307}
308
309static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
310{
311 if (unlikely(host->ops->read_l))
312 return host->ops->read_l(host, reg);
313 else
314 return readl_relaxed(host->mmio + reg);
315}
316
317struct platform_device;
318
319irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
320 int data_error);
321int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
322struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
323int cqhci_deactivate(struct mmc_host *mmc);
324void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, bool dma64);
325static inline int cqhci_suspend(struct mmc_host *mmc)
326{
327 return cqhci_deactivate(mmc);
328}
329int cqhci_resume(struct mmc_host *mmc);
330
331#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 */
4#ifndef LINUX_MMC_CQHCI_H
5#define LINUX_MMC_CQHCI_H
6
7#include <linux/compiler.h>
8#include <linux/bitops.h>
9#include <linux/spinlock_types.h>
10#include <linux/types.h>
11#include <linux/completion.h>
12#include <linux/wait.h>
13#include <linux/irqreturn.h>
14#include <asm/io.h>
15
16/* registers */
17/* version */
18#define CQHCI_VER 0x00
19#define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)
20#define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)
21#define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))
22
23/* capabilities */
24#define CQHCI_CAP 0x04
25/* configuration */
26#define CQHCI_CFG 0x08
27#define CQHCI_DCMD 0x00001000
28#define CQHCI_TASK_DESC_SZ 0x00000100
29#define CQHCI_ENABLE 0x00000001
30
31/* control */
32#define CQHCI_CTL 0x0C
33#define CQHCI_CLEAR_ALL_TASKS 0x00000100
34#define CQHCI_HALT 0x00000001
35
36/* interrupt status */
37#define CQHCI_IS 0x10
38#define CQHCI_IS_HAC BIT(0)
39#define CQHCI_IS_TCC BIT(1)
40#define CQHCI_IS_RED BIT(2)
41#define CQHCI_IS_TCL BIT(3)
42
43#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED)
44
45/* interrupt status enable */
46#define CQHCI_ISTE 0x14
47
48/* interrupt signal enable */
49#define CQHCI_ISGE 0x18
50
51/* interrupt coalescing */
52#define CQHCI_IC 0x1C
53#define CQHCI_IC_ENABLE BIT(31)
54#define CQHCI_IC_RESET BIT(16)
55#define CQHCI_IC_ICCTHWEN BIT(15)
56#define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8)
57#define CQHCI_IC_ICTOVALWEN BIT(7)
58#define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F)
59
60/* task list base address */
61#define CQHCI_TDLBA 0x20
62
63/* task list base address upper */
64#define CQHCI_TDLBAU 0x24
65
66/* door-bell */
67#define CQHCI_TDBR 0x28
68
69/* task completion notification */
70#define CQHCI_TCN 0x2C
71
72/* device queue status */
73#define CQHCI_DQS 0x30
74
75/* device pending tasks */
76#define CQHCI_DPT 0x34
77
78/* task clear */
79#define CQHCI_TCLR 0x38
80
81/* send status config 1 */
82#define CQHCI_SSC1 0x40
83#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
84
85/* send status config 2 */
86#define CQHCI_SSC2 0x44
87
88/* response for dcmd */
89#define CQHCI_CRDCT 0x48
90
91/* response mode error mask */
92#define CQHCI_RMEM 0x50
93
94/* task error info */
95#define CQHCI_TERRI 0x54
96
97#define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))
98#define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)
99#define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15))
100#define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)
101#define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)
102#define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31))
103
104/* command response index */
105#define CQHCI_CRI 0x58
106
107/* command response argument */
108#define CQHCI_CRA 0x5C
109
110#define CQHCI_INT_ALL 0xF
111#define CQHCI_IC_DEFAULT_ICCTH 31
112#define CQHCI_IC_DEFAULT_ICTOVAL 1
113
114/* attribute fields */
115#define CQHCI_VALID(x) (((x) & 1) << 0)
116#define CQHCI_END(x) (((x) & 1) << 1)
117#define CQHCI_INT(x) (((x) & 1) << 2)
118#define CQHCI_ACT(x) (((x) & 0x7) << 3)
119
120/* data command task descriptor fields */
121#define CQHCI_FORCED_PROG(x) (((x) & 1) << 6)
122#define CQHCI_CONTEXT(x) (((x) & 0xF) << 7)
123#define CQHCI_DATA_TAG(x) (((x) & 1) << 11)
124#define CQHCI_DATA_DIR(x) (((x) & 1) << 12)
125#define CQHCI_PRIORITY(x) (((x) & 1) << 13)
126#define CQHCI_QBAR(x) (((x) & 1) << 14)
127#define CQHCI_REL_WRITE(x) (((x) & 1) << 15)
128#define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16)
129#define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32)
130
131/* direct command task descriptor fields */
132#define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16)
133#define CQHCI_CMD_TIMING(x) (((x) & 1) << 22)
134#define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23)
135
136/* transfer descriptor fields */
137#define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16)
138#define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
139#define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
140
141struct cqhci_host_ops;
142struct mmc_host;
143struct mmc_request;
144struct cqhci_slot;
145
146struct cqhci_host {
147 const struct cqhci_host_ops *ops;
148 void __iomem *mmio;
149 struct mmc_host *mmc;
150
151 spinlock_t lock;
152
153 /* relative card address of device */
154 unsigned int rca;
155
156 /* 64 bit DMA */
157 bool dma64;
158 int num_slots;
159 int qcnt;
160
161 u32 dcmd_slot;
162 u32 caps;
163#define CQHCI_TASK_DESC_SZ_128 0x1
164
165 u32 quirks;
166#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
167
168 bool enabled;
169 bool halted;
170 bool init_done;
171 bool activated;
172 bool waiting_for_idle;
173 bool recovery_halt;
174
175 size_t desc_size;
176 size_t data_size;
177
178 u8 *desc_base;
179
180 /* total descriptor size */
181 u8 slot_sz;
182
183 /* 64/128 bit depends on CQHCI_CFG */
184 u8 task_desc_len;
185
186 /* 64 bit on 32-bit arch, 128 bit on 64-bit */
187 u8 link_desc_len;
188
189 u8 *trans_desc_base;
190 /* same length as transfer descriptor */
191 u8 trans_desc_len;
192
193 dma_addr_t desc_dma_base;
194 dma_addr_t trans_desc_dma_base;
195
196 struct completion halt_comp;
197 wait_queue_head_t wait_queue;
198 struct cqhci_slot *slot;
199};
200
201struct cqhci_host_ops {
202 void (*dumpregs)(struct mmc_host *mmc);
203 void (*write_l)(struct cqhci_host *host, u32 val, int reg);
204 u32 (*read_l)(struct cqhci_host *host, int reg);
205 void (*enable)(struct mmc_host *mmc);
206 void (*disable)(struct mmc_host *mmc, bool recovery);
207 void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
208 u64 *data);
209};
210
211static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
212{
213 if (unlikely(host->ops->write_l))
214 host->ops->write_l(host, val, reg);
215 else
216 writel_relaxed(val, host->mmio + reg);
217}
218
219static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
220{
221 if (unlikely(host->ops->read_l))
222 return host->ops->read_l(host, reg);
223 else
224 return readl_relaxed(host->mmio + reg);
225}
226
227struct platform_device;
228
229irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
230 int data_error);
231int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
232struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
233int cqhci_suspend(struct mmc_host *mmc);
234int cqhci_resume(struct mmc_host *mmc);
235
236#endif