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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2014, Sony Mobile Communications AB.
5 *
6 */
7
8#include <linux/acpi.h>
9#include <linux/atomic.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/dmapool.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/property.h>
23#include <linux/scatterlist.h>
24
25/* QUP Registers */
26#define QUP_CONFIG 0x000
27#define QUP_STATE 0x004
28#define QUP_IO_MODE 0x008
29#define QUP_SW_RESET 0x00c
30#define QUP_OPERATIONAL 0x018
31#define QUP_ERROR_FLAGS 0x01c
32#define QUP_ERROR_FLAGS_EN 0x020
33#define QUP_OPERATIONAL_MASK 0x028
34#define QUP_HW_VERSION 0x030
35#define QUP_MX_OUTPUT_CNT 0x100
36#define QUP_OUT_FIFO_BASE 0x110
37#define QUP_MX_WRITE_CNT 0x150
38#define QUP_MX_INPUT_CNT 0x200
39#define QUP_MX_READ_CNT 0x208
40#define QUP_IN_FIFO_BASE 0x218
41#define QUP_I2C_CLK_CTL 0x400
42#define QUP_I2C_STATUS 0x404
43#define QUP_I2C_MASTER_GEN 0x408
44
45/* QUP States and reset values */
46#define QUP_RESET_STATE 0
47#define QUP_RUN_STATE 1
48#define QUP_PAUSE_STATE 3
49#define QUP_STATE_MASK 3
50
51#define QUP_STATE_VALID BIT(2)
52#define QUP_I2C_MAST_GEN BIT(4)
53#define QUP_I2C_FLUSH BIT(6)
54
55#define QUP_OPERATIONAL_RESET 0x000ff0
56#define QUP_I2C_STATUS_RESET 0xfffffc
57
58/* QUP OPERATIONAL FLAGS */
59#define QUP_I2C_NACK_FLAG BIT(3)
60#define QUP_OUT_NOT_EMPTY BIT(4)
61#define QUP_IN_NOT_EMPTY BIT(5)
62#define QUP_OUT_FULL BIT(6)
63#define QUP_OUT_SVC_FLAG BIT(8)
64#define QUP_IN_SVC_FLAG BIT(9)
65#define QUP_MX_OUTPUT_DONE BIT(10)
66#define QUP_MX_INPUT_DONE BIT(11)
67#define OUT_BLOCK_WRITE_REQ BIT(12)
68#define IN_BLOCK_READ_REQ BIT(13)
69
70/* I2C mini core related values */
71#define QUP_NO_INPUT BIT(7)
72#define QUP_CLOCK_AUTO_GATE BIT(13)
73#define I2C_MINI_CORE (2 << 8)
74#define I2C_N_VAL 15
75#define I2C_N_VAL_V2 7
76
77/* Most significant word offset in FIFO port */
78#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
79
80/* Packing/Unpacking words in FIFOs, and IO modes */
81#define QUP_OUTPUT_BLK_MODE (1 << 10)
82#define QUP_OUTPUT_BAM_MODE (3 << 10)
83#define QUP_INPUT_BLK_MODE (1 << 12)
84#define QUP_INPUT_BAM_MODE (3 << 12)
85#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
86#define QUP_UNPACK_EN BIT(14)
87#define QUP_PACK_EN BIT(15)
88
89#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
90#define QUP_V2_TAGS_EN 1
91
92#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
93#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
94#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
95#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
96
97/* QUP tags */
98#define QUP_TAG_START (1 << 8)
99#define QUP_TAG_DATA (2 << 8)
100#define QUP_TAG_STOP (3 << 8)
101#define QUP_TAG_REC (4 << 8)
102#define QUP_BAM_INPUT_EOT 0x93
103#define QUP_BAM_FLUSH_STOP 0x96
104
105/* QUP v2 tags */
106#define QUP_TAG_V2_START 0x81
107#define QUP_TAG_V2_DATAWR 0x82
108#define QUP_TAG_V2_DATAWR_STOP 0x83
109#define QUP_TAG_V2_DATARD 0x85
110#define QUP_TAG_V2_DATARD_NACK 0x86
111#define QUP_TAG_V2_DATARD_STOP 0x87
112
113/* Status, Error flags */
114#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
115#define I2C_STATUS_BUS_ACTIVE BIT(8)
116#define I2C_STATUS_ERROR_MASK 0x38000fc
117#define QUP_STATUS_ERROR_FLAGS 0x7c
118
119#define QUP_READ_LIMIT 256
120#define SET_BIT 0x1
121#define RESET_BIT 0x0
122#define ONE_BYTE 0x1
123#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
124
125/* Maximum transfer length for single DMA descriptor */
126#define MX_TX_RX_LEN SZ_64K
127#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
128/* Maximum transfer length for all DMA descriptors */
129#define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
130#define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
131
132/*
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
135 * the overheads.
136 */
137#define TOUT_MIN 2
138
139/* Default values. Use these if FW query fails */
140#define DEFAULT_CLK_FREQ I2C_MAX_STANDARD_MODE_FREQ
141#define DEFAULT_SRC_CLK 20000000
142
143/*
144 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
145 * data transfer
146 */
147#define QUP_MAX_TAGS_LEN 4
148/* Max data length for each DATARD tags */
149#define RECV_MAX_DATA_LEN 254
150/* TAG length for DATA READ in RX FIFO */
151#define READ_RX_TAGS_LEN 2
152
153static unsigned int scl_freq;
154module_param_named(scl_freq, scl_freq, uint, 0444);
155MODULE_PARM_DESC(scl_freq, "SCL frequency override");
156
157/*
158 * count: no of blocks
159 * pos: current block number
160 * tx_tag_len: tx tag length for current block
161 * rx_tag_len: rx tag length for current block
162 * data_len: remaining data length for current message
163 * cur_blk_len: data length for current block
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
165 * total_rx_len: total rx length including tag bytes for current QUP transfer
166 * tx_fifo_data_pos: current byte number in TX FIFO word
167 * tx_fifo_free: number of free bytes in current QUP block write.
168 * rx_fifo_data_pos: current byte number in RX FIFO word
169 * fifo_available: number of available bytes in RX FIFO for current
170 * QUP block read
171 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
172 * to TX FIFO will be appended in this data and will be written to
173 * TX FIFO when all the 4 bytes are available.
174 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
175 * contains the 4 bytes of RX data.
176 * cur_data: pointer to tell cur data position for current message
177 * cur_tx_tags: pointer to tell cur position in tags
178 * tx_tags_sent: all tx tag bytes have been written in FIFO word
179 * send_last_word: for tx FIFO, last word send is pending in current block
180 * rx_bytes_read: if all the bytes have been read from rx FIFO.
181 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
182 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
183 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
184 * tags: contains tx tag bytes for current QUP transfer
185 */
186struct qup_i2c_block {
187 int count;
188 int pos;
189 int tx_tag_len;
190 int rx_tag_len;
191 int data_len;
192 int cur_blk_len;
193 int total_tx_len;
194 int total_rx_len;
195 int tx_fifo_data_pos;
196 int tx_fifo_free;
197 int rx_fifo_data_pos;
198 int fifo_available;
199 u32 tx_fifo_data;
200 u32 rx_fifo_data;
201 u8 *cur_data;
202 u8 *cur_tx_tags;
203 bool tx_tags_sent;
204 bool send_last_word;
205 bool rx_tags_fetched;
206 bool rx_bytes_read;
207 bool is_tx_blk_mode;
208 bool is_rx_blk_mode;
209 u8 tags[6];
210};
211
212struct qup_i2c_tag {
213 u8 *start;
214 dma_addr_t addr;
215};
216
217struct qup_i2c_bam {
218 struct qup_i2c_tag tag;
219 struct dma_chan *dma;
220 struct scatterlist *sg;
221 unsigned int sg_cnt;
222};
223
224struct qup_i2c_dev {
225 struct device *dev;
226 void __iomem *base;
227 int irq;
228 struct clk *clk;
229 struct clk *pclk;
230 struct i2c_adapter adap;
231
232 int clk_ctl;
233 int out_fifo_sz;
234 int in_fifo_sz;
235 int out_blk_sz;
236 int in_blk_sz;
237
238 int blk_xfer_limit;
239 unsigned long one_byte_t;
240 unsigned long xfer_timeout;
241 struct qup_i2c_block blk;
242
243 struct i2c_msg *msg;
244 /* Current posion in user message buffer */
245 int pos;
246 /* I2C protocol errors */
247 u32 bus_err;
248 /* QUP core errors */
249 u32 qup_err;
250
251 /* To check if this is the last msg */
252 bool is_last;
253 bool is_smbus_read;
254
255 /* To configure when bus is in run state */
256 u32 config_run;
257
258 /* dma parameters */
259 bool is_dma;
260 /* To check if the current transfer is using DMA */
261 bool use_dma;
262 unsigned int max_xfer_sg_len;
263 unsigned int tag_buf_pos;
264 /* The threshold length above which block mode will be used */
265 unsigned int blk_mode_threshold;
266 struct dma_pool *dpool;
267 struct qup_i2c_tag start_tag;
268 struct qup_i2c_bam brx;
269 struct qup_i2c_bam btx;
270
271 struct completion xfer;
272 /* function to write data in tx fifo */
273 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
274 /* function to read data from rx fifo */
275 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
276 /* function to write tags in tx fifo for i2c read transfer */
277 void (*write_rx_tags)(struct qup_i2c_dev *qup);
278};
279
280static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
281{
282 struct qup_i2c_dev *qup = dev;
283 struct qup_i2c_block *blk = &qup->blk;
284 u32 bus_err;
285 u32 qup_err;
286 u32 opflags;
287
288 bus_err = readl(qup->base + QUP_I2C_STATUS);
289 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
290 opflags = readl(qup->base + QUP_OPERATIONAL);
291
292 if (!qup->msg) {
293 /* Clear Error interrupt */
294 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
295 return IRQ_HANDLED;
296 }
297
298 bus_err &= I2C_STATUS_ERROR_MASK;
299 qup_err &= QUP_STATUS_ERROR_FLAGS;
300
301 /* Clear the error bits in QUP_ERROR_FLAGS */
302 if (qup_err)
303 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
304
305 /* Clear the error bits in QUP_I2C_STATUS */
306 if (bus_err)
307 writel(bus_err, qup->base + QUP_I2C_STATUS);
308
309 /*
310 * Check for BAM mode and returns if already error has come for current
311 * transfer. In Error case, sometimes, QUP generates more than one
312 * interrupt.
313 */
314 if (qup->use_dma && (qup->qup_err || qup->bus_err))
315 return IRQ_HANDLED;
316
317 /* Reset the QUP State in case of error */
318 if (qup_err || bus_err) {
319 /*
320 * Don’t reset the QUP state in case of BAM mode. The BAM
321 * flush operation needs to be scheduled in transfer function
322 * which will clear the remaining schedule descriptors in BAM
323 * HW FIFO and generates the BAM interrupt.
324 */
325 if (!qup->use_dma)
326 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
327 goto done;
328 }
329
330 if (opflags & QUP_OUT_SVC_FLAG) {
331 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
332
333 if (opflags & OUT_BLOCK_WRITE_REQ) {
334 blk->tx_fifo_free += qup->out_blk_sz;
335 if (qup->msg->flags & I2C_M_RD)
336 qup->write_rx_tags(qup);
337 else
338 qup->write_tx_fifo(qup);
339 }
340 }
341
342 if (opflags & QUP_IN_SVC_FLAG) {
343 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
344
345 if (!blk->is_rx_blk_mode) {
346 blk->fifo_available += qup->in_fifo_sz;
347 qup->read_rx_fifo(qup);
348 } else if (opflags & IN_BLOCK_READ_REQ) {
349 blk->fifo_available += qup->in_blk_sz;
350 qup->read_rx_fifo(qup);
351 }
352 }
353
354 if (qup->msg->flags & I2C_M_RD) {
355 if (!blk->rx_bytes_read)
356 return IRQ_HANDLED;
357 } else {
358 /*
359 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
360 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
361 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
362 * of interrupt for write message in FIFO mode is
363 * QUP_MAX_OUTPUT_DONE_FLAG condition.
364 */
365 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
366 return IRQ_HANDLED;
367 }
368
369done:
370 qup->qup_err = qup_err;
371 qup->bus_err = bus_err;
372 complete(&qup->xfer);
373 return IRQ_HANDLED;
374}
375
376static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
377 u32 req_state, u32 req_mask)
378{
379 int retries = 1;
380 u32 state;
381
382 /*
383 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
384 * cycles. So retry once after a 1uS delay.
385 */
386 do {
387 state = readl(qup->base + QUP_STATE);
388
389 if (state & QUP_STATE_VALID &&
390 (state & req_mask) == req_state)
391 return 0;
392
393 udelay(1);
394 } while (retries--);
395
396 return -ETIMEDOUT;
397}
398
399static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
400{
401 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
402}
403
404static void qup_i2c_flush(struct qup_i2c_dev *qup)
405{
406 u32 val = readl(qup->base + QUP_STATE);
407
408 val |= QUP_I2C_FLUSH;
409 writel(val, qup->base + QUP_STATE);
410}
411
412static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
413{
414 return qup_i2c_poll_state_mask(qup, 0, 0);
415}
416
417static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
418{
419 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
420}
421
422static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
423{
424 if (qup_i2c_poll_state_valid(qup) != 0)
425 return -EIO;
426
427 writel(state, qup->base + QUP_STATE);
428
429 if (qup_i2c_poll_state(qup, state) != 0)
430 return -EIO;
431 return 0;
432}
433
434/* Check if I2C bus returns to IDLE state */
435static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
436{
437 unsigned long timeout;
438 u32 status;
439 int ret = 0;
440
441 timeout = jiffies + len * 4;
442 for (;;) {
443 status = readl(qup->base + QUP_I2C_STATUS);
444 if (!(status & I2C_STATUS_BUS_ACTIVE))
445 break;
446
447 if (time_after(jiffies, timeout))
448 ret = -ETIMEDOUT;
449
450 usleep_range(len, len * 2);
451 }
452
453 return ret;
454}
455
456static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
457{
458 struct qup_i2c_block *blk = &qup->blk;
459 struct i2c_msg *msg = qup->msg;
460 u32 addr = i2c_8bit_addr_from_msg(msg);
461 u32 qup_tag;
462 int idx;
463 u32 val;
464
465 if (qup->pos == 0) {
466 val = QUP_TAG_START | addr;
467 idx = 1;
468 blk->tx_fifo_free--;
469 } else {
470 val = 0;
471 idx = 0;
472 }
473
474 while (blk->tx_fifo_free && qup->pos < msg->len) {
475 if (qup->pos == msg->len - 1)
476 qup_tag = QUP_TAG_STOP;
477 else
478 qup_tag = QUP_TAG_DATA;
479
480 if (idx & 1)
481 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
482 else
483 val = qup_tag | msg->buf[qup->pos];
484
485 /* Write out the pair and the last odd value */
486 if (idx & 1 || qup->pos == msg->len - 1)
487 writel(val, qup->base + QUP_OUT_FIFO_BASE);
488
489 qup->pos++;
490 idx++;
491 blk->tx_fifo_free--;
492 }
493}
494
495static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
496 struct i2c_msg *msg)
497{
498 qup->blk.pos = 0;
499 qup->blk.data_len = msg->len;
500 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
501}
502
503static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
504{
505 int data_len;
506
507 if (qup->blk.data_len > qup->blk_xfer_limit)
508 data_len = qup->blk_xfer_limit;
509 else
510 data_len = qup->blk.data_len;
511
512 return data_len;
513}
514
515static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
516{
517 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
518}
519
520static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
521 struct i2c_msg *msg)
522{
523 int len = 0;
524
525 if (qup->is_smbus_read) {
526 tags[len++] = QUP_TAG_V2_DATARD_STOP;
527 tags[len++] = qup_i2c_get_data_len(qup);
528 } else {
529 tags[len++] = QUP_TAG_V2_START;
530 tags[len++] = addr & 0xff;
531
532 if (msg->flags & I2C_M_TEN)
533 tags[len++] = addr >> 8;
534
535 tags[len++] = QUP_TAG_V2_DATARD;
536 /* Read 1 byte indicating the length of the SMBus message */
537 tags[len++] = 1;
538 }
539 return len;
540}
541
542static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
543 struct i2c_msg *msg)
544{
545 u16 addr = i2c_8bit_addr_from_msg(msg);
546 int len = 0;
547 int data_len;
548
549 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
550
551 /* Handle tags for SMBus block read */
552 if (qup_i2c_check_msg_len(msg))
553 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
554
555 if (qup->blk.pos == 0) {
556 tags[len++] = QUP_TAG_V2_START;
557 tags[len++] = addr & 0xff;
558
559 if (msg->flags & I2C_M_TEN)
560 tags[len++] = addr >> 8;
561 }
562
563 /* Send _STOP commands for the last block */
564 if (last) {
565 if (msg->flags & I2C_M_RD)
566 tags[len++] = QUP_TAG_V2_DATARD_STOP;
567 else
568 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
569 } else {
570 if (msg->flags & I2C_M_RD)
571 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
572 QUP_TAG_V2_DATARD_NACK :
573 QUP_TAG_V2_DATARD;
574 else
575 tags[len++] = QUP_TAG_V2_DATAWR;
576 }
577
578 data_len = qup_i2c_get_data_len(qup);
579
580 /* 0 implies 256 bytes */
581 if (data_len == QUP_READ_LIMIT)
582 tags[len++] = 0;
583 else
584 tags[len++] = data_len;
585
586 return len;
587}
588
589
590static void qup_i2c_bam_cb(void *data)
591{
592 struct qup_i2c_dev *qup = data;
593
594 complete(&qup->xfer);
595}
596
597static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
598 unsigned int buflen, struct qup_i2c_dev *qup,
599 int dir)
600{
601 int ret;
602
603 sg_set_buf(sg, buf, buflen);
604 ret = dma_map_sg(qup->dev, sg, 1, dir);
605 if (!ret)
606 return -EINVAL;
607
608 return 0;
609}
610
611static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
612{
613 if (qup->btx.dma)
614 dma_release_channel(qup->btx.dma);
615 if (qup->brx.dma)
616 dma_release_channel(qup->brx.dma);
617 qup->btx.dma = NULL;
618 qup->brx.dma = NULL;
619}
620
621static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
622{
623 int err;
624
625 if (!qup->btx.dma) {
626 qup->btx.dma = dma_request_chan(qup->dev, "tx");
627 if (IS_ERR(qup->btx.dma)) {
628 err = PTR_ERR(qup->btx.dma);
629 qup->btx.dma = NULL;
630 dev_err(qup->dev, "\n tx channel not available");
631 return err;
632 }
633 }
634
635 if (!qup->brx.dma) {
636 qup->brx.dma = dma_request_chan(qup->dev, "rx");
637 if (IS_ERR(qup->brx.dma)) {
638 dev_err(qup->dev, "\n rx channel not available");
639 err = PTR_ERR(qup->brx.dma);
640 qup->brx.dma = NULL;
641 qup_i2c_rel_dma(qup);
642 return err;
643 }
644 }
645 return 0;
646}
647
648static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
649{
650 int ret = 0, limit = QUP_READ_LIMIT;
651 u32 len = 0, blocks, rem;
652 u32 i = 0, tlen, tx_len = 0;
653 u8 *tags;
654
655 qup->blk_xfer_limit = QUP_READ_LIMIT;
656 qup_i2c_set_blk_data(qup, msg);
657
658 blocks = qup->blk.count;
659 rem = msg->len - (blocks - 1) * limit;
660
661 if (msg->flags & I2C_M_RD) {
662 while (qup->blk.pos < blocks) {
663 tlen = (i == (blocks - 1)) ? rem : limit;
664 tags = &qup->start_tag.start[qup->tag_buf_pos + len];
665 len += qup_i2c_set_tags(tags, qup, msg);
666 qup->blk.data_len -= tlen;
667
668 /* scratch buf to read the start and len tags */
669 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
670 &qup->brx.tag.start[0],
671 2, qup, DMA_FROM_DEVICE);
672
673 if (ret)
674 return ret;
675
676 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
677 &msg->buf[limit * i],
678 tlen, qup,
679 DMA_FROM_DEVICE);
680 if (ret)
681 return ret;
682
683 i++;
684 qup->blk.pos = i;
685 }
686 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
687 &qup->start_tag.start[qup->tag_buf_pos],
688 len, qup, DMA_TO_DEVICE);
689 if (ret)
690 return ret;
691
692 qup->tag_buf_pos += len;
693 } else {
694 while (qup->blk.pos < blocks) {
695 tlen = (i == (blocks - 1)) ? rem : limit;
696 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
697 len = qup_i2c_set_tags(tags, qup, msg);
698 qup->blk.data_len -= tlen;
699
700 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
701 tags, len,
702 qup, DMA_TO_DEVICE);
703 if (ret)
704 return ret;
705
706 tx_len += len;
707 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
708 &msg->buf[limit * i],
709 tlen, qup, DMA_TO_DEVICE);
710 if (ret)
711 return ret;
712 i++;
713 qup->blk.pos = i;
714 }
715
716 qup->tag_buf_pos += tx_len;
717 }
718
719 return 0;
720}
721
722static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
723{
724 struct dma_async_tx_descriptor *txd, *rxd = NULL;
725 int ret = 0;
726 dma_cookie_t cookie_rx, cookie_tx;
727 u32 len = 0;
728 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
729
730 /* schedule the EOT and FLUSH I2C tags */
731 len = 1;
732 if (rx_cnt) {
733 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
734 len++;
735
736 /* scratch buf to read the BAM EOT FLUSH tags */
737 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
738 &qup->brx.tag.start[0],
739 1, qup, DMA_FROM_DEVICE);
740 if (ret)
741 return ret;
742 }
743
744 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
745 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
746 len, qup, DMA_TO_DEVICE);
747 if (ret)
748 return ret;
749
750 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
751 DMA_MEM_TO_DEV,
752 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
753 if (!txd) {
754 dev_err(qup->dev, "failed to get tx desc\n");
755 ret = -EINVAL;
756 goto desc_err;
757 }
758
759 if (!rx_cnt) {
760 txd->callback = qup_i2c_bam_cb;
761 txd->callback_param = qup;
762 }
763
764 cookie_tx = dmaengine_submit(txd);
765 if (dma_submit_error(cookie_tx)) {
766 ret = -EINVAL;
767 goto desc_err;
768 }
769
770 dma_async_issue_pending(qup->btx.dma);
771
772 if (rx_cnt) {
773 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
774 rx_cnt, DMA_DEV_TO_MEM,
775 DMA_PREP_INTERRUPT);
776 if (!rxd) {
777 dev_err(qup->dev, "failed to get rx desc\n");
778 ret = -EINVAL;
779
780 /* abort TX descriptors */
781 dmaengine_terminate_sync(qup->btx.dma);
782 goto desc_err;
783 }
784
785 rxd->callback = qup_i2c_bam_cb;
786 rxd->callback_param = qup;
787 cookie_rx = dmaengine_submit(rxd);
788 if (dma_submit_error(cookie_rx)) {
789 ret = -EINVAL;
790 goto desc_err;
791 }
792
793 dma_async_issue_pending(qup->brx.dma);
794 }
795
796 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout))
797 ret = -ETIMEDOUT;
798
799 if (ret || qup->bus_err || qup->qup_err) {
800 reinit_completion(&qup->xfer);
801
802 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
803 if (ret) {
804 dev_err(qup->dev, "change to run state timed out");
805 goto desc_err;
806 }
807
808 qup_i2c_flush(qup);
809
810 /* wait for remaining interrupts to occur */
811 if (!wait_for_completion_timeout(&qup->xfer, HZ))
812 dev_err(qup->dev, "flush timed out\n");
813
814 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
815 }
816
817desc_err:
818 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
819
820 if (rx_cnt)
821 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
822 DMA_FROM_DEVICE);
823
824 return ret;
825}
826
827static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
828{
829 qup->btx.sg_cnt = 0;
830 qup->brx.sg_cnt = 0;
831 qup->tag_buf_pos = 0;
832}
833
834static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
835 int num)
836{
837 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
838 int ret = 0;
839 int idx = 0;
840
841 enable_irq(qup->irq);
842 ret = qup_i2c_req_dma(qup);
843
844 if (ret)
845 goto out;
846
847 writel(0, qup->base + QUP_MX_INPUT_CNT);
848 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
849
850 /* set BAM mode */
851 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
852
853 /* mask fifo irqs */
854 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
855
856 /* set RUN STATE */
857 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
858 if (ret)
859 goto out;
860
861 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
862 qup_i2c_bam_clear_tag_buffers(qup);
863
864 for (idx = 0; idx < num; idx++) {
865 qup->msg = msg + idx;
866 qup->is_last = idx == (num - 1);
867
868 ret = qup_i2c_bam_make_desc(qup, qup->msg);
869 if (ret)
870 break;
871
872 /*
873 * Make DMA descriptor and schedule the BAM transfer if its
874 * already crossed the maximum length. Since the memory for all
875 * tags buffers have been taken for 2 maximum possible
876 * transfers length so it will never cross the buffer actual
877 * length.
878 */
879 if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
880 qup->brx.sg_cnt > qup->max_xfer_sg_len ||
881 qup->is_last) {
882 ret = qup_i2c_bam_schedule_desc(qup);
883 if (ret)
884 break;
885
886 qup_i2c_bam_clear_tag_buffers(qup);
887 }
888 }
889
890out:
891 disable_irq(qup->irq);
892
893 qup->msg = NULL;
894 return ret;
895}
896
897static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
898 struct i2c_msg *msg)
899{
900 unsigned long left;
901 int ret = 0;
902
903 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
904 if (!left) {
905 writel(1, qup->base + QUP_SW_RESET);
906 ret = -ETIMEDOUT;
907 }
908
909 if (qup->bus_err || qup->qup_err)
910 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
911
912 return ret;
913}
914
915static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
916{
917 struct qup_i2c_block *blk = &qup->blk;
918 struct i2c_msg *msg = qup->msg;
919 u32 val = 0;
920 int idx = 0;
921
922 while (blk->fifo_available && qup->pos < msg->len) {
923 if ((idx & 1) == 0) {
924 /* Reading 2 words at time */
925 val = readl(qup->base + QUP_IN_FIFO_BASE);
926 msg->buf[qup->pos++] = val & 0xFF;
927 } else {
928 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
929 }
930 idx++;
931 blk->fifo_available--;
932 }
933
934 if (qup->pos == msg->len)
935 blk->rx_bytes_read = true;
936}
937
938static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
939{
940 struct i2c_msg *msg = qup->msg;
941 u32 addr, len, val;
942
943 addr = i2c_8bit_addr_from_msg(msg);
944
945 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
946 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
947
948 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
949 writel(val, qup->base + QUP_OUT_FIFO_BASE);
950}
951
952static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
953{
954 struct qup_i2c_block *blk = &qup->blk;
955 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
956 u32 io_mode = QUP_REPACK_EN;
957
958 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz;
959 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz;
960
961 if (blk->is_tx_blk_mode) {
962 io_mode |= QUP_OUTPUT_BLK_MODE;
963 writel(0, qup->base + QUP_MX_WRITE_CNT);
964 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
965 } else {
966 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
967 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
968 }
969
970 if (blk->total_rx_len) {
971 if (blk->is_rx_blk_mode) {
972 io_mode |= QUP_INPUT_BLK_MODE;
973 writel(0, qup->base + QUP_MX_READ_CNT);
974 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
975 } else {
976 writel(0, qup->base + QUP_MX_INPUT_CNT);
977 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
978 }
979 } else {
980 qup_config |= QUP_NO_INPUT;
981 }
982
983 writel(qup_config, qup->base + QUP_CONFIG);
984 writel(io_mode, qup->base + QUP_IO_MODE);
985}
986
987static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
988{
989 blk->tx_fifo_free = 0;
990 blk->fifo_available = 0;
991 blk->rx_bytes_read = false;
992}
993
994static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
995{
996 struct qup_i2c_block *blk = &qup->blk;
997 int ret;
998
999 qup_i2c_clear_blk_v1(blk);
1000 qup_i2c_conf_v1(qup);
1001 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1002 if (ret)
1003 return ret;
1004
1005 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1006
1007 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1008 if (ret)
1009 return ret;
1010
1011 reinit_completion(&qup->xfer);
1012 enable_irq(qup->irq);
1013 if (!blk->is_tx_blk_mode) {
1014 blk->tx_fifo_free = qup->out_fifo_sz;
1015
1016 if (is_rx)
1017 qup_i2c_write_rx_tags_v1(qup);
1018 else
1019 qup_i2c_write_tx_fifo_v1(qup);
1020 }
1021
1022 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1023 if (ret)
1024 goto err;
1025
1026 ret = qup_i2c_wait_for_complete(qup, qup->msg);
1027 if (ret)
1028 goto err;
1029
1030 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1031
1032err:
1033 disable_irq(qup->irq);
1034 return ret;
1035}
1036
1037static int qup_i2c_write_one(struct qup_i2c_dev *qup)
1038{
1039 struct i2c_msg *msg = qup->msg;
1040 struct qup_i2c_block *blk = &qup->blk;
1041
1042 qup->pos = 0;
1043 blk->total_tx_len = msg->len + 1;
1044 blk->total_rx_len = 0;
1045
1046 return qup_i2c_conf_xfer_v1(qup, false);
1047}
1048
1049static int qup_i2c_read_one(struct qup_i2c_dev *qup)
1050{
1051 struct qup_i2c_block *blk = &qup->blk;
1052
1053 qup->pos = 0;
1054 blk->total_tx_len = 2;
1055 blk->total_rx_len = qup->msg->len;
1056
1057 return qup_i2c_conf_xfer_v1(qup, true);
1058}
1059
1060static int qup_i2c_xfer(struct i2c_adapter *adap,
1061 struct i2c_msg msgs[],
1062 int num)
1063{
1064 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1065 int ret, idx;
1066
1067 ret = pm_runtime_get_sync(qup->dev);
1068 if (ret < 0)
1069 goto out;
1070
1071 qup->bus_err = 0;
1072 qup->qup_err = 0;
1073
1074 writel(1, qup->base + QUP_SW_RESET);
1075 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1076 if (ret)
1077 goto out;
1078
1079 /* Configure QUP as I2C mini core */
1080 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1081
1082 for (idx = 0; idx < num; idx++) {
1083 if (qup_i2c_poll_state_i2c_master(qup)) {
1084 ret = -EIO;
1085 goto out;
1086 }
1087
1088 if (qup_i2c_check_msg_len(&msgs[idx])) {
1089 ret = -EINVAL;
1090 goto out;
1091 }
1092
1093 qup->msg = &msgs[idx];
1094 if (msgs[idx].flags & I2C_M_RD)
1095 ret = qup_i2c_read_one(qup);
1096 else
1097 ret = qup_i2c_write_one(qup);
1098
1099 if (ret)
1100 break;
1101
1102 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1103 if (ret)
1104 break;
1105 }
1106
1107 if (ret == 0)
1108 ret = num;
1109out:
1110
1111 pm_runtime_mark_last_busy(qup->dev);
1112 pm_runtime_put_autosuspend(qup->dev);
1113
1114 return ret;
1115}
1116
1117/*
1118 * Configure registers related with reconfiguration during run and call it
1119 * before each i2c sub transfer.
1120 */
1121static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
1122{
1123 struct qup_i2c_block *blk = &qup->blk;
1124 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
1125
1126 if (blk->is_tx_blk_mode)
1127 writel(qup->config_run | blk->total_tx_len,
1128 qup->base + QUP_MX_OUTPUT_CNT);
1129 else
1130 writel(qup->config_run | blk->total_tx_len,
1131 qup->base + QUP_MX_WRITE_CNT);
1132
1133 if (blk->total_rx_len) {
1134 if (blk->is_rx_blk_mode)
1135 writel(qup->config_run | blk->total_rx_len,
1136 qup->base + QUP_MX_INPUT_CNT);
1137 else
1138 writel(qup->config_run | blk->total_rx_len,
1139 qup->base + QUP_MX_READ_CNT);
1140 } else {
1141 qup_config |= QUP_NO_INPUT;
1142 }
1143
1144 writel(qup_config, qup->base + QUP_CONFIG);
1145}
1146
1147/*
1148 * Configure registers related with transfer mode (FIFO/Block)
1149 * before starting of i2c transfer. It will be called only once in
1150 * QUP RESET state.
1151 */
1152static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
1153{
1154 struct qup_i2c_block *blk = &qup->blk;
1155 u32 io_mode = QUP_REPACK_EN;
1156
1157 if (blk->is_tx_blk_mode) {
1158 io_mode |= QUP_OUTPUT_BLK_MODE;
1159 writel(0, qup->base + QUP_MX_WRITE_CNT);
1160 } else {
1161 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1162 }
1163
1164 if (blk->is_rx_blk_mode) {
1165 io_mode |= QUP_INPUT_BLK_MODE;
1166 writel(0, qup->base + QUP_MX_READ_CNT);
1167 } else {
1168 writel(0, qup->base + QUP_MX_INPUT_CNT);
1169 }
1170
1171 writel(io_mode, qup->base + QUP_IO_MODE);
1172}
1173
1174/* Clear required variables before starting of any QUP v2 sub transfer. */
1175static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
1176{
1177 blk->send_last_word = false;
1178 blk->tx_tags_sent = false;
1179 blk->tx_fifo_data = 0;
1180 blk->tx_fifo_data_pos = 0;
1181 blk->tx_fifo_free = 0;
1182
1183 blk->rx_tags_fetched = false;
1184 blk->rx_bytes_read = false;
1185 blk->rx_fifo_data = 0;
1186 blk->rx_fifo_data_pos = 0;
1187 blk->fifo_available = 0;
1188}
1189
1190/* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1191static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
1192{
1193 struct qup_i2c_block *blk = &qup->blk;
1194 int j;
1195
1196 for (j = blk->rx_fifo_data_pos;
1197 blk->cur_blk_len && blk->fifo_available;
1198 blk->cur_blk_len--, blk->fifo_available--) {
1199 if (j == 0)
1200 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1201
1202 *(blk->cur_data++) = blk->rx_fifo_data;
1203 blk->rx_fifo_data >>= 8;
1204
1205 if (j == 3)
1206 j = 0;
1207 else
1208 j++;
1209 }
1210
1211 blk->rx_fifo_data_pos = j;
1212}
1213
1214/* Receive tags for read message in QUP v2 i2c transfer. */
1215static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
1216{
1217 struct qup_i2c_block *blk = &qup->blk;
1218
1219 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1220 blk->rx_fifo_data >>= blk->rx_tag_len * 8;
1221 blk->rx_fifo_data_pos = blk->rx_tag_len;
1222 blk->fifo_available -= blk->rx_tag_len;
1223}
1224
1225/*
1226 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1227 * preceded by received data bytes so
1228 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1229 * all tag bytes and discard that.
1230 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1231 * set rx_bytes_read to true.
1232 */
1233static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
1234{
1235 struct qup_i2c_block *blk = &qup->blk;
1236
1237 if (!blk->rx_tags_fetched) {
1238 qup_i2c_recv_tags(qup);
1239 blk->rx_tags_fetched = true;
1240 }
1241
1242 qup_i2c_recv_data(qup);
1243 if (!blk->cur_blk_len)
1244 blk->rx_bytes_read = true;
1245}
1246
1247/*
1248 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1249 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1250 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1251 */
1252static void
1253qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
1254{
1255 struct qup_i2c_block *blk = &qup->blk;
1256 unsigned int j;
1257
1258 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
1259 (*len)--, blk->tx_fifo_free--) {
1260 blk->tx_fifo_data |= *(*data)++ << (j * 8);
1261 if (j == 3) {
1262 writel(blk->tx_fifo_data,
1263 qup->base + QUP_OUT_FIFO_BASE);
1264 blk->tx_fifo_data = 0x0;
1265 j = 0;
1266 } else {
1267 j++;
1268 }
1269 }
1270
1271 blk->tx_fifo_data_pos = j;
1272}
1273
1274/* Transfer tags for read message in QUP v2 i2c transfer. */
1275static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
1276{
1277 struct qup_i2c_block *blk = &qup->blk;
1278
1279 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
1280 if (blk->tx_fifo_data_pos)
1281 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1282}
1283
1284/*
1285 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1286 * need to be written and QUP write tags can have maximum 256 data length, so
1287 *
1288 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1289 * tags to TX FIFO and set tx_tags_sent to true.
1290 * 2. Check if send_last_word is true. It will be set when last few data bytes
1291 * (less than 4 bytes) are remaining to be written in FIFO because of no FIFO
1292 * space. All this data bytes are available in tx_fifo_data so write this
1293 * in FIFO.
1294 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1295 * then more data is pending otherwise following 3 cases can be possible
1296 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
1297 * have been written in TX FIFO so nothing else is required.
1298 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1299 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1300 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1301 * will be always greater than or equal to 4 bytes.
1302 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
1303 * bytes) are copied to tx_fifo_data but couldn't be sent because of
1304 * FIFO full so make send_last_word true.
1305 */
1306static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
1307{
1308 struct qup_i2c_block *blk = &qup->blk;
1309
1310 if (!blk->tx_tags_sent) {
1311 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
1312 &blk->tx_tag_len);
1313 blk->tx_tags_sent = true;
1314 }
1315
1316 if (blk->send_last_word)
1317 goto send_last_word;
1318
1319 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
1320 if (!blk->cur_blk_len) {
1321 if (!blk->tx_fifo_data_pos)
1322 return;
1323
1324 if (blk->tx_fifo_free)
1325 goto send_last_word;
1326
1327 blk->send_last_word = true;
1328 }
1329
1330 return;
1331
1332send_last_word:
1333 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1334}
1335
1336/*
1337 * Main transfer function which read or write i2c data.
1338 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1339 * transfers can be scheduled.
1340 */
1341static int
1342qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
1343 bool change_pause_state)
1344{
1345 struct qup_i2c_block *blk = &qup->blk;
1346 struct i2c_msg *msg = qup->msg;
1347 int ret;
1348
1349 /*
1350 * Check if its SMBus Block read for which the top level read will be
1351 * done into 2 QUP reads. One with message length 1 while other one is
1352 * with actual length.
1353 */
1354 if (qup_i2c_check_msg_len(msg)) {
1355 if (qup->is_smbus_read) {
1356 /*
1357 * If the message length is already read in
1358 * the first byte of the buffer, account for
1359 * that by setting the offset
1360 */
1361 blk->cur_data += 1;
1362 is_first = false;
1363 } else {
1364 change_pause_state = false;
1365 }
1366 }
1367
1368 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
1369
1370 qup_i2c_clear_blk_v2(blk);
1371 qup_i2c_conf_count_v2(qup);
1372
1373 /* If it is first sub transfer, then configure i2c bus clocks */
1374 if (is_first) {
1375 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1376 if (ret)
1377 return ret;
1378
1379 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1380
1381 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1382 if (ret)
1383 return ret;
1384 }
1385
1386 reinit_completion(&qup->xfer);
1387 enable_irq(qup->irq);
1388 /*
1389 * In FIFO mode, tx FIFO can be written directly while in block mode the
1390 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
1391 */
1392 if (!blk->is_tx_blk_mode) {
1393 blk->tx_fifo_free = qup->out_fifo_sz;
1394
1395 if (is_rx)
1396 qup_i2c_write_rx_tags_v2(qup);
1397 else
1398 qup_i2c_write_tx_fifo_v2(qup);
1399 }
1400
1401 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1402 if (ret)
1403 goto err;
1404
1405 ret = qup_i2c_wait_for_complete(qup, msg);
1406 if (ret)
1407 goto err;
1408
1409 /* Move to pause state for all the transfers, except last one */
1410 if (change_pause_state) {
1411 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1412 if (ret)
1413 goto err;
1414 }
1415
1416err:
1417 disable_irq(qup->irq);
1418 return ret;
1419}
1420
1421/*
1422 * Transfer one read/write message in i2c transfer. It splits the message into
1423 * multiple of blk_xfer_limit data length blocks and schedule each
1424 * QUP block individually.
1425 */
1426static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
1427{
1428 int ret = 0;
1429 unsigned int data_len, i;
1430 struct i2c_msg *msg = qup->msg;
1431 struct qup_i2c_block *blk = &qup->blk;
1432 u8 *msg_buf = msg->buf;
1433
1434 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
1435 qup_i2c_set_blk_data(qup, msg);
1436
1437 for (i = 0; i < blk->count; i++) {
1438 data_len = qup_i2c_get_data_len(qup);
1439 blk->pos = i;
1440 blk->cur_tx_tags = blk->tags;
1441 blk->cur_blk_len = data_len;
1442 blk->tx_tag_len =
1443 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
1444
1445 blk->cur_data = msg_buf;
1446
1447 if (is_rx) {
1448 blk->total_tx_len = blk->tx_tag_len;
1449 blk->rx_tag_len = 2;
1450 blk->total_rx_len = blk->rx_tag_len + data_len;
1451 } else {
1452 blk->total_tx_len = blk->tx_tag_len + data_len;
1453 blk->total_rx_len = 0;
1454 }
1455
1456 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
1457 !qup->is_last || i < blk->count - 1);
1458 if (ret)
1459 return ret;
1460
1461 /* Handle SMBus block read length */
1462 if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
1463 !qup->is_smbus_read) {
1464 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
1465 return -EPROTO;
1466
1467 msg->len = msg->buf[0];
1468 qup->is_smbus_read = true;
1469 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
1470 qup->is_smbus_read = false;
1471 if (ret)
1472 return ret;
1473
1474 msg->len += 1;
1475 }
1476
1477 msg_buf += data_len;
1478 blk->data_len -= qup->blk_xfer_limit;
1479 }
1480
1481 return ret;
1482}
1483
1484/*
1485 * QUP v2 supports 3 modes
1486 * Programmed IO using FIFO mode : Less than FIFO size
1487 * Programmed IO using Block mode : Greater than FIFO size
1488 * DMA using BAM : Appropriate for any transaction size but the address should
1489 * be DMA applicable
1490 *
1491 * This function determines the mode which will be used for this transfer. An
1492 * i2c transfer contains multiple message. Following are the rules to determine
1493 * the mode used.
1494 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1495 * 2. If complete transfer length is greater than fifo size then use the DMA
1496 * mode.
1497 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1498 * for maximum tx and rx length to determine mode.
1499 */
1500static int
1501qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
1502 struct i2c_msg msgs[], int num)
1503{
1504 int idx;
1505 bool no_dma = false;
1506 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
1507
1508 /* All i2c_msgs should be transferred using either dma or cpu */
1509 for (idx = 0; idx < num; idx++) {
1510 if (msgs[idx].flags & I2C_M_RD)
1511 max_rx_len = max_t(unsigned int, max_rx_len,
1512 msgs[idx].len);
1513 else
1514 max_tx_len = max_t(unsigned int, max_tx_len,
1515 msgs[idx].len);
1516
1517 if (is_vmalloc_addr(msgs[idx].buf))
1518 no_dma = true;
1519
1520 total_len += msgs[idx].len;
1521 }
1522
1523 if (!no_dma && qup->is_dma &&
1524 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
1525 qup->use_dma = true;
1526 } else {
1527 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1528 QUP_MAX_TAGS_LEN;
1529 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1530 READ_RX_TAGS_LEN;
1531 }
1532
1533 return 0;
1534}
1535
1536static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1537 struct i2c_msg msgs[],
1538 int num)
1539{
1540 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1541 int ret, idx = 0;
1542
1543 qup->bus_err = 0;
1544 qup->qup_err = 0;
1545
1546 ret = pm_runtime_get_sync(qup->dev);
1547 if (ret < 0)
1548 goto out;
1549
1550 ret = qup_i2c_determine_mode_v2(qup, msgs, num);
1551 if (ret)
1552 goto out;
1553
1554 writel(1, qup->base + QUP_SW_RESET);
1555 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1556 if (ret)
1557 goto out;
1558
1559 /* Configure QUP as I2C mini core */
1560 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1561 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1562
1563 if (qup_i2c_poll_state_i2c_master(qup)) {
1564 ret = -EIO;
1565 goto out;
1566 }
1567
1568 if (qup->use_dma) {
1569 reinit_completion(&qup->xfer);
1570 ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
1571 qup->use_dma = false;
1572 } else {
1573 qup_i2c_conf_mode_v2(qup);
1574
1575 for (idx = 0; idx < num; idx++) {
1576 qup->msg = &msgs[idx];
1577 qup->is_last = idx == (num - 1);
1578
1579 ret = qup_i2c_xfer_v2_msg(qup, idx,
1580 !!(msgs[idx].flags & I2C_M_RD));
1581 if (ret)
1582 break;
1583 }
1584 qup->msg = NULL;
1585 }
1586
1587 if (!ret)
1588 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1589
1590 if (!ret)
1591 qup_i2c_change_state(qup, QUP_RESET_STATE);
1592
1593 if (ret == 0)
1594 ret = num;
1595out:
1596 pm_runtime_mark_last_busy(qup->dev);
1597 pm_runtime_put_autosuspend(qup->dev);
1598
1599 return ret;
1600}
1601
1602static u32 qup_i2c_func(struct i2c_adapter *adap)
1603{
1604 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1605}
1606
1607static const struct i2c_algorithm qup_i2c_algo = {
1608 .master_xfer = qup_i2c_xfer,
1609 .functionality = qup_i2c_func,
1610};
1611
1612static const struct i2c_algorithm qup_i2c_algo_v2 = {
1613 .master_xfer = qup_i2c_xfer_v2,
1614 .functionality = qup_i2c_func,
1615};
1616
1617/*
1618 * The QUP block will issue a NACK and STOP on the bus when reaching
1619 * the end of the read, the length of the read is specified as one byte
1620 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1621 */
1622static const struct i2c_adapter_quirks qup_i2c_quirks = {
1623 .flags = I2C_AQ_NO_ZERO_LEN,
1624 .max_read_len = QUP_READ_LIMIT,
1625};
1626
1627static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = {
1628 .flags = I2C_AQ_NO_ZERO_LEN,
1629};
1630
1631static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1632{
1633 clk_prepare_enable(qup->clk);
1634 clk_prepare_enable(qup->pclk);
1635}
1636
1637static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1638{
1639 u32 config;
1640
1641 qup_i2c_change_state(qup, QUP_RESET_STATE);
1642 clk_disable_unprepare(qup->clk);
1643 config = readl(qup->base + QUP_CONFIG);
1644 config |= QUP_CLOCK_AUTO_GATE;
1645 writel(config, qup->base + QUP_CONFIG);
1646 clk_disable_unprepare(qup->pclk);
1647}
1648
1649static const struct acpi_device_id qup_i2c_acpi_match[] = {
1650 { "QCOM8010"},
1651 { }
1652};
1653MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1654
1655static int qup_i2c_probe(struct platform_device *pdev)
1656{
1657 static const int blk_sizes[] = {4, 16, 32};
1658 struct qup_i2c_dev *qup;
1659 unsigned long one_bit_t;
1660 u32 io_mode, hw_ver, size;
1661 int ret, fs_div, hs_div;
1662 u32 src_clk_freq = DEFAULT_SRC_CLK;
1663 u32 clk_freq = DEFAULT_CLK_FREQ;
1664 int blocks;
1665 bool is_qup_v1;
1666
1667 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1668 if (!qup)
1669 return -ENOMEM;
1670
1671 qup->dev = &pdev->dev;
1672 init_completion(&qup->xfer);
1673 platform_set_drvdata(pdev, qup);
1674
1675 if (scl_freq) {
1676 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
1677 clk_freq = scl_freq;
1678 } else {
1679 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1680 if (ret) {
1681 dev_notice(qup->dev, "using default clock-frequency %d",
1682 DEFAULT_CLK_FREQ);
1683 }
1684 }
1685
1686 if (device_is_compatible(&pdev->dev, "qcom,i2c-qup-v1.1.1")) {
1687 qup->adap.algo = &qup_i2c_algo;
1688 qup->adap.quirks = &qup_i2c_quirks;
1689 is_qup_v1 = true;
1690 } else {
1691 qup->adap.algo = &qup_i2c_algo_v2;
1692 qup->adap.quirks = &qup_i2c_quirks_v2;
1693 is_qup_v1 = false;
1694 if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
1695 goto nodma;
1696 else
1697 ret = qup_i2c_req_dma(qup);
1698
1699 if (ret == -EPROBE_DEFER)
1700 goto fail_dma;
1701 else if (ret != 0)
1702 goto nodma;
1703
1704 qup->max_xfer_sg_len = (MX_BLOCKS << 1);
1705 blocks = (MX_DMA_BLOCKS << 1) + 1;
1706 qup->btx.sg = devm_kcalloc(&pdev->dev,
1707 blocks, sizeof(*qup->btx.sg),
1708 GFP_KERNEL);
1709 if (!qup->btx.sg) {
1710 ret = -ENOMEM;
1711 goto fail_dma;
1712 }
1713 sg_init_table(qup->btx.sg, blocks);
1714
1715 qup->brx.sg = devm_kcalloc(&pdev->dev,
1716 blocks, sizeof(*qup->brx.sg),
1717 GFP_KERNEL);
1718 if (!qup->brx.sg) {
1719 ret = -ENOMEM;
1720 goto fail_dma;
1721 }
1722 sg_init_table(qup->brx.sg, blocks);
1723
1724 /* 2 tag bytes for each block + 5 for start, stop tags */
1725 size = blocks * 2 + 5;
1726
1727 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1728 size, GFP_KERNEL);
1729 if (!qup->start_tag.start) {
1730 ret = -ENOMEM;
1731 goto fail_dma;
1732 }
1733
1734 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1735 if (!qup->brx.tag.start) {
1736 ret = -ENOMEM;
1737 goto fail_dma;
1738 }
1739
1740 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1741 if (!qup->btx.tag.start) {
1742 ret = -ENOMEM;
1743 goto fail_dma;
1744 }
1745 qup->is_dma = true;
1746 }
1747
1748nodma:
1749 /* We support frequencies up to FAST Mode Plus (1MHz) */
1750 if (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) {
1751 dev_err(qup->dev, "clock frequency not supported %d\n",
1752 clk_freq);
1753 ret = -EINVAL;
1754 goto fail_dma;
1755 }
1756
1757 qup->base = devm_platform_ioremap_resource(pdev, 0);
1758 if (IS_ERR(qup->base)) {
1759 ret = PTR_ERR(qup->base);
1760 goto fail_dma;
1761 }
1762
1763 qup->irq = platform_get_irq(pdev, 0);
1764 if (qup->irq < 0) {
1765 ret = qup->irq;
1766 goto fail_dma;
1767 }
1768
1769 if (has_acpi_companion(qup->dev)) {
1770 ret = device_property_read_u32(qup->dev,
1771 "src-clock-hz", &src_clk_freq);
1772 if (ret) {
1773 dev_notice(qup->dev, "using default src-clock-hz %d",
1774 DEFAULT_SRC_CLK);
1775 }
1776 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1777 } else {
1778 qup->clk = devm_clk_get(qup->dev, "core");
1779 if (IS_ERR(qup->clk)) {
1780 dev_err(qup->dev, "Could not get core clock\n");
1781 ret = PTR_ERR(qup->clk);
1782 goto fail_dma;
1783 }
1784
1785 qup->pclk = devm_clk_get(qup->dev, "iface");
1786 if (IS_ERR(qup->pclk)) {
1787 dev_err(qup->dev, "Could not get iface clock\n");
1788 ret = PTR_ERR(qup->pclk);
1789 goto fail_dma;
1790 }
1791 qup_i2c_enable_clocks(qup);
1792 src_clk_freq = clk_get_rate(qup->clk);
1793 }
1794
1795 /*
1796 * Bootloaders might leave a pending interrupt on certain QUP's,
1797 * so we reset the core before registering for interrupts.
1798 */
1799 writel(1, qup->base + QUP_SW_RESET);
1800 ret = qup_i2c_poll_state_valid(qup);
1801 if (ret)
1802 goto fail;
1803
1804 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1805 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1806 "i2c_qup", qup);
1807 if (ret) {
1808 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1809 goto fail;
1810 }
1811
1812 hw_ver = readl(qup->base + QUP_HW_VERSION);
1813 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1814
1815 io_mode = readl(qup->base + QUP_IO_MODE);
1816
1817 /*
1818 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1819 * associated with each byte written/received
1820 */
1821 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1822 if (size >= ARRAY_SIZE(blk_sizes)) {
1823 ret = -EIO;
1824 goto fail;
1825 }
1826 qup->out_blk_sz = blk_sizes[size];
1827
1828 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1829 if (size >= ARRAY_SIZE(blk_sizes)) {
1830 ret = -EIO;
1831 goto fail;
1832 }
1833 qup->in_blk_sz = blk_sizes[size];
1834
1835 if (is_qup_v1) {
1836 /*
1837 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
1838 * single transfer but the block size is in bytes so divide the
1839 * in_blk_sz and out_blk_sz by 2
1840 */
1841 qup->in_blk_sz /= 2;
1842 qup->out_blk_sz /= 2;
1843 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
1844 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
1845 qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
1846 } else {
1847 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
1848 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
1849 qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
1850 }
1851
1852 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1853 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1854
1855 size = QUP_INPUT_FIFO_SIZE(io_mode);
1856 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1857
1858 hs_div = 3;
1859 if (clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) {
1860 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1861 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1862 } else {
1863 /* 33%/66% duty cycle */
1864 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
1865 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
1866 }
1867
1868 /*
1869 * Time it takes for a byte to be clocked out on the bus.
1870 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1871 */
1872 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1873 qup->one_byte_t = one_bit_t * 9;
1874 qup->xfer_timeout = TOUT_MIN * HZ +
1875 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
1876
1877 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1878 qup->in_blk_sz, qup->in_fifo_sz,
1879 qup->out_blk_sz, qup->out_fifo_sz);
1880
1881 i2c_set_adapdata(&qup->adap, qup);
1882 qup->adap.dev.parent = qup->dev;
1883 qup->adap.dev.of_node = pdev->dev.of_node;
1884 qup->is_last = true;
1885
1886 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1887
1888 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1889 pm_runtime_use_autosuspend(qup->dev);
1890 pm_runtime_set_active(qup->dev);
1891 pm_runtime_enable(qup->dev);
1892
1893 ret = i2c_add_adapter(&qup->adap);
1894 if (ret)
1895 goto fail_runtime;
1896
1897 return 0;
1898
1899fail_runtime:
1900 pm_runtime_disable(qup->dev);
1901 pm_runtime_set_suspended(qup->dev);
1902fail:
1903 qup_i2c_disable_clocks(qup);
1904fail_dma:
1905 if (qup->btx.dma)
1906 dma_release_channel(qup->btx.dma);
1907 if (qup->brx.dma)
1908 dma_release_channel(qup->brx.dma);
1909 return ret;
1910}
1911
1912static void qup_i2c_remove(struct platform_device *pdev)
1913{
1914 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1915
1916 if (qup->is_dma) {
1917 dma_release_channel(qup->btx.dma);
1918 dma_release_channel(qup->brx.dma);
1919 }
1920
1921 disable_irq(qup->irq);
1922 qup_i2c_disable_clocks(qup);
1923 i2c_del_adapter(&qup->adap);
1924 pm_runtime_disable(qup->dev);
1925 pm_runtime_set_suspended(qup->dev);
1926}
1927
1928static int qup_i2c_pm_suspend_runtime(struct device *device)
1929{
1930 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1931
1932 dev_dbg(device, "pm_runtime: suspending...\n");
1933 qup_i2c_disable_clocks(qup);
1934 return 0;
1935}
1936
1937static int qup_i2c_pm_resume_runtime(struct device *device)
1938{
1939 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1940
1941 dev_dbg(device, "pm_runtime: resuming...\n");
1942 qup_i2c_enable_clocks(qup);
1943 return 0;
1944}
1945
1946static int qup_i2c_suspend(struct device *device)
1947{
1948 if (!pm_runtime_suspended(device))
1949 return qup_i2c_pm_suspend_runtime(device);
1950 return 0;
1951}
1952
1953static int qup_i2c_resume(struct device *device)
1954{
1955 qup_i2c_pm_resume_runtime(device);
1956 pm_runtime_mark_last_busy(device);
1957 pm_request_autosuspend(device);
1958 return 0;
1959}
1960
1961static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1962 SYSTEM_SLEEP_PM_OPS(qup_i2c_suspend, qup_i2c_resume)
1963 RUNTIME_PM_OPS(qup_i2c_pm_suspend_runtime,
1964 qup_i2c_pm_resume_runtime, NULL)
1965};
1966
1967static const struct of_device_id qup_i2c_dt_match[] = {
1968 { .compatible = "qcom,i2c-qup-v1.1.1" },
1969 { .compatible = "qcom,i2c-qup-v2.1.1" },
1970 { .compatible = "qcom,i2c-qup-v2.2.1" },
1971 {}
1972};
1973MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1974
1975static struct platform_driver qup_i2c_driver = {
1976 .probe = qup_i2c_probe,
1977 .remove = qup_i2c_remove,
1978 .driver = {
1979 .name = "i2c_qup",
1980 .pm = pm_ptr(&qup_i2c_qup_pm_ops),
1981 .of_match_table = qup_i2c_dt_match,
1982 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
1983 },
1984};
1985
1986module_platform_driver(qup_i2c_driver);
1987
1988MODULE_DESCRIPTION("Qualcomm QUP based I2C controller");
1989MODULE_LICENSE("GPL v2");
1990MODULE_ALIAS("platform:i2c_qup");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2014, Sony Mobile Communications AB.
5 *
6 */
7
8#include <linux/acpi.h>
9#include <linux/atomic.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/dmapool.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/scatterlist.h>
24
25/* QUP Registers */
26#define QUP_CONFIG 0x000
27#define QUP_STATE 0x004
28#define QUP_IO_MODE 0x008
29#define QUP_SW_RESET 0x00c
30#define QUP_OPERATIONAL 0x018
31#define QUP_ERROR_FLAGS 0x01c
32#define QUP_ERROR_FLAGS_EN 0x020
33#define QUP_OPERATIONAL_MASK 0x028
34#define QUP_HW_VERSION 0x030
35#define QUP_MX_OUTPUT_CNT 0x100
36#define QUP_OUT_FIFO_BASE 0x110
37#define QUP_MX_WRITE_CNT 0x150
38#define QUP_MX_INPUT_CNT 0x200
39#define QUP_MX_READ_CNT 0x208
40#define QUP_IN_FIFO_BASE 0x218
41#define QUP_I2C_CLK_CTL 0x400
42#define QUP_I2C_STATUS 0x404
43#define QUP_I2C_MASTER_GEN 0x408
44
45/* QUP States and reset values */
46#define QUP_RESET_STATE 0
47#define QUP_RUN_STATE 1
48#define QUP_PAUSE_STATE 3
49#define QUP_STATE_MASK 3
50
51#define QUP_STATE_VALID BIT(2)
52#define QUP_I2C_MAST_GEN BIT(4)
53#define QUP_I2C_FLUSH BIT(6)
54
55#define QUP_OPERATIONAL_RESET 0x000ff0
56#define QUP_I2C_STATUS_RESET 0xfffffc
57
58/* QUP OPERATIONAL FLAGS */
59#define QUP_I2C_NACK_FLAG BIT(3)
60#define QUP_OUT_NOT_EMPTY BIT(4)
61#define QUP_IN_NOT_EMPTY BIT(5)
62#define QUP_OUT_FULL BIT(6)
63#define QUP_OUT_SVC_FLAG BIT(8)
64#define QUP_IN_SVC_FLAG BIT(9)
65#define QUP_MX_OUTPUT_DONE BIT(10)
66#define QUP_MX_INPUT_DONE BIT(11)
67#define OUT_BLOCK_WRITE_REQ BIT(12)
68#define IN_BLOCK_READ_REQ BIT(13)
69
70/* I2C mini core related values */
71#define QUP_NO_INPUT BIT(7)
72#define QUP_CLOCK_AUTO_GATE BIT(13)
73#define I2C_MINI_CORE (2 << 8)
74#define I2C_N_VAL 15
75#define I2C_N_VAL_V2 7
76
77/* Most significant word offset in FIFO port */
78#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
79
80/* Packing/Unpacking words in FIFOs, and IO modes */
81#define QUP_OUTPUT_BLK_MODE (1 << 10)
82#define QUP_OUTPUT_BAM_MODE (3 << 10)
83#define QUP_INPUT_BLK_MODE (1 << 12)
84#define QUP_INPUT_BAM_MODE (3 << 12)
85#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
86#define QUP_UNPACK_EN BIT(14)
87#define QUP_PACK_EN BIT(15)
88
89#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
90#define QUP_V2_TAGS_EN 1
91
92#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
93#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
94#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
95#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
96
97/* QUP tags */
98#define QUP_TAG_START (1 << 8)
99#define QUP_TAG_DATA (2 << 8)
100#define QUP_TAG_STOP (3 << 8)
101#define QUP_TAG_REC (4 << 8)
102#define QUP_BAM_INPUT_EOT 0x93
103#define QUP_BAM_FLUSH_STOP 0x96
104
105/* QUP v2 tags */
106#define QUP_TAG_V2_START 0x81
107#define QUP_TAG_V2_DATAWR 0x82
108#define QUP_TAG_V2_DATAWR_STOP 0x83
109#define QUP_TAG_V2_DATARD 0x85
110#define QUP_TAG_V2_DATARD_NACK 0x86
111#define QUP_TAG_V2_DATARD_STOP 0x87
112
113/* Status, Error flags */
114#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
115#define I2C_STATUS_BUS_ACTIVE BIT(8)
116#define I2C_STATUS_ERROR_MASK 0x38000fc
117#define QUP_STATUS_ERROR_FLAGS 0x7c
118
119#define QUP_READ_LIMIT 256
120#define SET_BIT 0x1
121#define RESET_BIT 0x0
122#define ONE_BYTE 0x1
123#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
124
125/* Maximum transfer length for single DMA descriptor */
126#define MX_TX_RX_LEN SZ_64K
127#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
128/* Maximum transfer length for all DMA descriptors */
129#define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
130#define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
131
132/*
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
135 * the overheads.
136 */
137#define TOUT_MIN 2
138
139/* I2C Frequency Modes */
140#define I2C_STANDARD_FREQ 100000
141#define I2C_FAST_MODE_FREQ 400000
142#define I2C_FAST_MODE_PLUS_FREQ 1000000
143
144/* Default values. Use these if FW query fails */
145#define DEFAULT_CLK_FREQ I2C_STANDARD_FREQ
146#define DEFAULT_SRC_CLK 20000000
147
148/*
149 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
150 * data transfer
151 */
152#define QUP_MAX_TAGS_LEN 4
153/* Max data length for each DATARD tags */
154#define RECV_MAX_DATA_LEN 254
155/* TAG length for DATA READ in RX FIFO */
156#define READ_RX_TAGS_LEN 2
157
158static unsigned int scl_freq;
159module_param_named(scl_freq, scl_freq, uint, 0444);
160MODULE_PARM_DESC(scl_freq, "SCL frequency override");
161
162/*
163 * count: no of blocks
164 * pos: current block number
165 * tx_tag_len: tx tag length for current block
166 * rx_tag_len: rx tag length for current block
167 * data_len: remaining data length for current message
168 * cur_blk_len: data length for current block
169 * total_tx_len: total tx length including tag bytes for current QUP transfer
170 * total_rx_len: total rx length including tag bytes for current QUP transfer
171 * tx_fifo_data_pos: current byte number in TX FIFO word
172 * tx_fifo_free: number of free bytes in current QUP block write.
173 * rx_fifo_data_pos: current byte number in RX FIFO word
174 * fifo_available: number of available bytes in RX FIFO for current
175 * QUP block read
176 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
177 * to TX FIFO will be appended in this data and will be written to
178 * TX FIFO when all the 4 bytes are available.
179 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
180 * contains the 4 bytes of RX data.
181 * cur_data: pointer to tell cur data position for current message
182 * cur_tx_tags: pointer to tell cur position in tags
183 * tx_tags_sent: all tx tag bytes have been written in FIFO word
184 * send_last_word: for tx FIFO, last word send is pending in current block
185 * rx_bytes_read: if all the bytes have been read from rx FIFO.
186 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
187 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
188 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
189 * tags: contains tx tag bytes for current QUP transfer
190 */
191struct qup_i2c_block {
192 int count;
193 int pos;
194 int tx_tag_len;
195 int rx_tag_len;
196 int data_len;
197 int cur_blk_len;
198 int total_tx_len;
199 int total_rx_len;
200 int tx_fifo_data_pos;
201 int tx_fifo_free;
202 int rx_fifo_data_pos;
203 int fifo_available;
204 u32 tx_fifo_data;
205 u32 rx_fifo_data;
206 u8 *cur_data;
207 u8 *cur_tx_tags;
208 bool tx_tags_sent;
209 bool send_last_word;
210 bool rx_tags_fetched;
211 bool rx_bytes_read;
212 bool is_tx_blk_mode;
213 bool is_rx_blk_mode;
214 u8 tags[6];
215};
216
217struct qup_i2c_tag {
218 u8 *start;
219 dma_addr_t addr;
220};
221
222struct qup_i2c_bam {
223 struct qup_i2c_tag tag;
224 struct dma_chan *dma;
225 struct scatterlist *sg;
226 unsigned int sg_cnt;
227};
228
229struct qup_i2c_dev {
230 struct device *dev;
231 void __iomem *base;
232 int irq;
233 struct clk *clk;
234 struct clk *pclk;
235 struct i2c_adapter adap;
236
237 int clk_ctl;
238 int out_fifo_sz;
239 int in_fifo_sz;
240 int out_blk_sz;
241 int in_blk_sz;
242
243 int blk_xfer_limit;
244 unsigned long one_byte_t;
245 unsigned long xfer_timeout;
246 struct qup_i2c_block blk;
247
248 struct i2c_msg *msg;
249 /* Current posion in user message buffer */
250 int pos;
251 /* I2C protocol errors */
252 u32 bus_err;
253 /* QUP core errors */
254 u32 qup_err;
255
256 /* To check if this is the last msg */
257 bool is_last;
258 bool is_smbus_read;
259
260 /* To configure when bus is in run state */
261 u32 config_run;
262
263 /* dma parameters */
264 bool is_dma;
265 /* To check if the current transfer is using DMA */
266 bool use_dma;
267 unsigned int max_xfer_sg_len;
268 unsigned int tag_buf_pos;
269 /* The threshold length above which block mode will be used */
270 unsigned int blk_mode_threshold;
271 struct dma_pool *dpool;
272 struct qup_i2c_tag start_tag;
273 struct qup_i2c_bam brx;
274 struct qup_i2c_bam btx;
275
276 struct completion xfer;
277 /* function to write data in tx fifo */
278 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
279 /* function to read data from rx fifo */
280 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
281 /* function to write tags in tx fifo for i2c read transfer */
282 void (*write_rx_tags)(struct qup_i2c_dev *qup);
283};
284
285static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
286{
287 struct qup_i2c_dev *qup = dev;
288 struct qup_i2c_block *blk = &qup->blk;
289 u32 bus_err;
290 u32 qup_err;
291 u32 opflags;
292
293 bus_err = readl(qup->base + QUP_I2C_STATUS);
294 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
295 opflags = readl(qup->base + QUP_OPERATIONAL);
296
297 if (!qup->msg) {
298 /* Clear Error interrupt */
299 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
300 return IRQ_HANDLED;
301 }
302
303 bus_err &= I2C_STATUS_ERROR_MASK;
304 qup_err &= QUP_STATUS_ERROR_FLAGS;
305
306 /* Clear the error bits in QUP_ERROR_FLAGS */
307 if (qup_err)
308 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
309
310 /* Clear the error bits in QUP_I2C_STATUS */
311 if (bus_err)
312 writel(bus_err, qup->base + QUP_I2C_STATUS);
313
314 /*
315 * Check for BAM mode and returns if already error has come for current
316 * transfer. In Error case, sometimes, QUP generates more than one
317 * interrupt.
318 */
319 if (qup->use_dma && (qup->qup_err || qup->bus_err))
320 return IRQ_HANDLED;
321
322 /* Reset the QUP State in case of error */
323 if (qup_err || bus_err) {
324 /*
325 * Don’t reset the QUP state in case of BAM mode. The BAM
326 * flush operation needs to be scheduled in transfer function
327 * which will clear the remaining schedule descriptors in BAM
328 * HW FIFO and generates the BAM interrupt.
329 */
330 if (!qup->use_dma)
331 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
332 goto done;
333 }
334
335 if (opflags & QUP_OUT_SVC_FLAG) {
336 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
337
338 if (opflags & OUT_BLOCK_WRITE_REQ) {
339 blk->tx_fifo_free += qup->out_blk_sz;
340 if (qup->msg->flags & I2C_M_RD)
341 qup->write_rx_tags(qup);
342 else
343 qup->write_tx_fifo(qup);
344 }
345 }
346
347 if (opflags & QUP_IN_SVC_FLAG) {
348 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
349
350 if (!blk->is_rx_blk_mode) {
351 blk->fifo_available += qup->in_fifo_sz;
352 qup->read_rx_fifo(qup);
353 } else if (opflags & IN_BLOCK_READ_REQ) {
354 blk->fifo_available += qup->in_blk_sz;
355 qup->read_rx_fifo(qup);
356 }
357 }
358
359 if (qup->msg->flags & I2C_M_RD) {
360 if (!blk->rx_bytes_read)
361 return IRQ_HANDLED;
362 } else {
363 /*
364 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
365 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
366 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
367 * of interrupt for write message in FIFO mode is
368 * QUP_MAX_OUTPUT_DONE_FLAG condition.
369 */
370 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
371 return IRQ_HANDLED;
372 }
373
374done:
375 qup->qup_err = qup_err;
376 qup->bus_err = bus_err;
377 complete(&qup->xfer);
378 return IRQ_HANDLED;
379}
380
381static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
382 u32 req_state, u32 req_mask)
383{
384 int retries = 1;
385 u32 state;
386
387 /*
388 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
389 * cycles. So retry once after a 1uS delay.
390 */
391 do {
392 state = readl(qup->base + QUP_STATE);
393
394 if (state & QUP_STATE_VALID &&
395 (state & req_mask) == req_state)
396 return 0;
397
398 udelay(1);
399 } while (retries--);
400
401 return -ETIMEDOUT;
402}
403
404static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
405{
406 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
407}
408
409static void qup_i2c_flush(struct qup_i2c_dev *qup)
410{
411 u32 val = readl(qup->base + QUP_STATE);
412
413 val |= QUP_I2C_FLUSH;
414 writel(val, qup->base + QUP_STATE);
415}
416
417static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
418{
419 return qup_i2c_poll_state_mask(qup, 0, 0);
420}
421
422static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
423{
424 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
425}
426
427static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
428{
429 if (qup_i2c_poll_state_valid(qup) != 0)
430 return -EIO;
431
432 writel(state, qup->base + QUP_STATE);
433
434 if (qup_i2c_poll_state(qup, state) != 0)
435 return -EIO;
436 return 0;
437}
438
439/* Check if I2C bus returns to IDLE state */
440static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
441{
442 unsigned long timeout;
443 u32 status;
444 int ret = 0;
445
446 timeout = jiffies + len * 4;
447 for (;;) {
448 status = readl(qup->base + QUP_I2C_STATUS);
449 if (!(status & I2C_STATUS_BUS_ACTIVE))
450 break;
451
452 if (time_after(jiffies, timeout))
453 ret = -ETIMEDOUT;
454
455 usleep_range(len, len * 2);
456 }
457
458 return ret;
459}
460
461static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
462{
463 struct qup_i2c_block *blk = &qup->blk;
464 struct i2c_msg *msg = qup->msg;
465 u32 addr = i2c_8bit_addr_from_msg(msg);
466 u32 qup_tag;
467 int idx;
468 u32 val;
469
470 if (qup->pos == 0) {
471 val = QUP_TAG_START | addr;
472 idx = 1;
473 blk->tx_fifo_free--;
474 } else {
475 val = 0;
476 idx = 0;
477 }
478
479 while (blk->tx_fifo_free && qup->pos < msg->len) {
480 if (qup->pos == msg->len - 1)
481 qup_tag = QUP_TAG_STOP;
482 else
483 qup_tag = QUP_TAG_DATA;
484
485 if (idx & 1)
486 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
487 else
488 val = qup_tag | msg->buf[qup->pos];
489
490 /* Write out the pair and the last odd value */
491 if (idx & 1 || qup->pos == msg->len - 1)
492 writel(val, qup->base + QUP_OUT_FIFO_BASE);
493
494 qup->pos++;
495 idx++;
496 blk->tx_fifo_free--;
497 }
498}
499
500static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
501 struct i2c_msg *msg)
502{
503 qup->blk.pos = 0;
504 qup->blk.data_len = msg->len;
505 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
506}
507
508static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
509{
510 int data_len;
511
512 if (qup->blk.data_len > qup->blk_xfer_limit)
513 data_len = qup->blk_xfer_limit;
514 else
515 data_len = qup->blk.data_len;
516
517 return data_len;
518}
519
520static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
521{
522 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
523}
524
525static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
526 struct i2c_msg *msg)
527{
528 int len = 0;
529
530 if (qup->is_smbus_read) {
531 tags[len++] = QUP_TAG_V2_DATARD_STOP;
532 tags[len++] = qup_i2c_get_data_len(qup);
533 } else {
534 tags[len++] = QUP_TAG_V2_START;
535 tags[len++] = addr & 0xff;
536
537 if (msg->flags & I2C_M_TEN)
538 tags[len++] = addr >> 8;
539
540 tags[len++] = QUP_TAG_V2_DATARD;
541 /* Read 1 byte indicating the length of the SMBus message */
542 tags[len++] = 1;
543 }
544 return len;
545}
546
547static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
548 struct i2c_msg *msg)
549{
550 u16 addr = i2c_8bit_addr_from_msg(msg);
551 int len = 0;
552 int data_len;
553
554 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
555
556 /* Handle tags for SMBus block read */
557 if (qup_i2c_check_msg_len(msg))
558 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
559
560 if (qup->blk.pos == 0) {
561 tags[len++] = QUP_TAG_V2_START;
562 tags[len++] = addr & 0xff;
563
564 if (msg->flags & I2C_M_TEN)
565 tags[len++] = addr >> 8;
566 }
567
568 /* Send _STOP commands for the last block */
569 if (last) {
570 if (msg->flags & I2C_M_RD)
571 tags[len++] = QUP_TAG_V2_DATARD_STOP;
572 else
573 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
574 } else {
575 if (msg->flags & I2C_M_RD)
576 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
577 QUP_TAG_V2_DATARD_NACK :
578 QUP_TAG_V2_DATARD;
579 else
580 tags[len++] = QUP_TAG_V2_DATAWR;
581 }
582
583 data_len = qup_i2c_get_data_len(qup);
584
585 /* 0 implies 256 bytes */
586 if (data_len == QUP_READ_LIMIT)
587 tags[len++] = 0;
588 else
589 tags[len++] = data_len;
590
591 return len;
592}
593
594
595static void qup_i2c_bam_cb(void *data)
596{
597 struct qup_i2c_dev *qup = data;
598
599 complete(&qup->xfer);
600}
601
602static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
603 unsigned int buflen, struct qup_i2c_dev *qup,
604 int dir)
605{
606 int ret;
607
608 sg_set_buf(sg, buf, buflen);
609 ret = dma_map_sg(qup->dev, sg, 1, dir);
610 if (!ret)
611 return -EINVAL;
612
613 return 0;
614}
615
616static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
617{
618 if (qup->btx.dma)
619 dma_release_channel(qup->btx.dma);
620 if (qup->brx.dma)
621 dma_release_channel(qup->brx.dma);
622 qup->btx.dma = NULL;
623 qup->brx.dma = NULL;
624}
625
626static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
627{
628 int err;
629
630 if (!qup->btx.dma) {
631 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
632 if (IS_ERR(qup->btx.dma)) {
633 err = PTR_ERR(qup->btx.dma);
634 qup->btx.dma = NULL;
635 dev_err(qup->dev, "\n tx channel not available");
636 return err;
637 }
638 }
639
640 if (!qup->brx.dma) {
641 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
642 if (IS_ERR(qup->brx.dma)) {
643 dev_err(qup->dev, "\n rx channel not available");
644 err = PTR_ERR(qup->brx.dma);
645 qup->brx.dma = NULL;
646 qup_i2c_rel_dma(qup);
647 return err;
648 }
649 }
650 return 0;
651}
652
653static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
654{
655 int ret = 0, limit = QUP_READ_LIMIT;
656 u32 len = 0, blocks, rem;
657 u32 i = 0, tlen, tx_len = 0;
658 u8 *tags;
659
660 qup->blk_xfer_limit = QUP_READ_LIMIT;
661 qup_i2c_set_blk_data(qup, msg);
662
663 blocks = qup->blk.count;
664 rem = msg->len - (blocks - 1) * limit;
665
666 if (msg->flags & I2C_M_RD) {
667 while (qup->blk.pos < blocks) {
668 tlen = (i == (blocks - 1)) ? rem : limit;
669 tags = &qup->start_tag.start[qup->tag_buf_pos + len];
670 len += qup_i2c_set_tags(tags, qup, msg);
671 qup->blk.data_len -= tlen;
672
673 /* scratch buf to read the start and len tags */
674 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
675 &qup->brx.tag.start[0],
676 2, qup, DMA_FROM_DEVICE);
677
678 if (ret)
679 return ret;
680
681 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
682 &msg->buf[limit * i],
683 tlen, qup,
684 DMA_FROM_DEVICE);
685 if (ret)
686 return ret;
687
688 i++;
689 qup->blk.pos = i;
690 }
691 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
692 &qup->start_tag.start[qup->tag_buf_pos],
693 len, qup, DMA_TO_DEVICE);
694 if (ret)
695 return ret;
696
697 qup->tag_buf_pos += len;
698 } else {
699 while (qup->blk.pos < blocks) {
700 tlen = (i == (blocks - 1)) ? rem : limit;
701 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
702 len = qup_i2c_set_tags(tags, qup, msg);
703 qup->blk.data_len -= tlen;
704
705 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
706 tags, len,
707 qup, DMA_TO_DEVICE);
708 if (ret)
709 return ret;
710
711 tx_len += len;
712 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
713 &msg->buf[limit * i],
714 tlen, qup, DMA_TO_DEVICE);
715 if (ret)
716 return ret;
717 i++;
718 qup->blk.pos = i;
719 }
720
721 qup->tag_buf_pos += tx_len;
722 }
723
724 return 0;
725}
726
727static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
728{
729 struct dma_async_tx_descriptor *txd, *rxd = NULL;
730 int ret = 0;
731 dma_cookie_t cookie_rx, cookie_tx;
732 u32 len = 0;
733 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
734
735 /* schedule the EOT and FLUSH I2C tags */
736 len = 1;
737 if (rx_cnt) {
738 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
739 len++;
740
741 /* scratch buf to read the BAM EOT FLUSH tags */
742 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
743 &qup->brx.tag.start[0],
744 1, qup, DMA_FROM_DEVICE);
745 if (ret)
746 return ret;
747 }
748
749 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
750 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
751 len, qup, DMA_TO_DEVICE);
752 if (ret)
753 return ret;
754
755 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
756 DMA_MEM_TO_DEV,
757 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
758 if (!txd) {
759 dev_err(qup->dev, "failed to get tx desc\n");
760 ret = -EINVAL;
761 goto desc_err;
762 }
763
764 if (!rx_cnt) {
765 txd->callback = qup_i2c_bam_cb;
766 txd->callback_param = qup;
767 }
768
769 cookie_tx = dmaengine_submit(txd);
770 if (dma_submit_error(cookie_tx)) {
771 ret = -EINVAL;
772 goto desc_err;
773 }
774
775 dma_async_issue_pending(qup->btx.dma);
776
777 if (rx_cnt) {
778 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
779 rx_cnt, DMA_DEV_TO_MEM,
780 DMA_PREP_INTERRUPT);
781 if (!rxd) {
782 dev_err(qup->dev, "failed to get rx desc\n");
783 ret = -EINVAL;
784
785 /* abort TX descriptors */
786 dmaengine_terminate_all(qup->btx.dma);
787 goto desc_err;
788 }
789
790 rxd->callback = qup_i2c_bam_cb;
791 rxd->callback_param = qup;
792 cookie_rx = dmaengine_submit(rxd);
793 if (dma_submit_error(cookie_rx)) {
794 ret = -EINVAL;
795 goto desc_err;
796 }
797
798 dma_async_issue_pending(qup->brx.dma);
799 }
800
801 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) {
802 dev_err(qup->dev, "normal trans timed out\n");
803 ret = -ETIMEDOUT;
804 }
805
806 if (ret || qup->bus_err || qup->qup_err) {
807 reinit_completion(&qup->xfer);
808
809 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
810 dev_err(qup->dev, "change to run state timed out");
811 goto desc_err;
812 }
813
814 qup_i2c_flush(qup);
815
816 /* wait for remaining interrupts to occur */
817 if (!wait_for_completion_timeout(&qup->xfer, HZ))
818 dev_err(qup->dev, "flush timed out\n");
819
820 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
821 }
822
823desc_err:
824 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
825
826 if (rx_cnt)
827 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
828 DMA_FROM_DEVICE);
829
830 return ret;
831}
832
833static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
834{
835 qup->btx.sg_cnt = 0;
836 qup->brx.sg_cnt = 0;
837 qup->tag_buf_pos = 0;
838}
839
840static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
841 int num)
842{
843 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
844 int ret = 0;
845 int idx = 0;
846
847 enable_irq(qup->irq);
848 ret = qup_i2c_req_dma(qup);
849
850 if (ret)
851 goto out;
852
853 writel(0, qup->base + QUP_MX_INPUT_CNT);
854 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
855
856 /* set BAM mode */
857 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
858
859 /* mask fifo irqs */
860 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
861
862 /* set RUN STATE */
863 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
864 if (ret)
865 goto out;
866
867 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
868 qup_i2c_bam_clear_tag_buffers(qup);
869
870 for (idx = 0; idx < num; idx++) {
871 qup->msg = msg + idx;
872 qup->is_last = idx == (num - 1);
873
874 ret = qup_i2c_bam_make_desc(qup, qup->msg);
875 if (ret)
876 break;
877
878 /*
879 * Make DMA descriptor and schedule the BAM transfer if its
880 * already crossed the maximum length. Since the memory for all
881 * tags buffers have been taken for 2 maximum possible
882 * transfers length so it will never cross the buffer actual
883 * length.
884 */
885 if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
886 qup->brx.sg_cnt > qup->max_xfer_sg_len ||
887 qup->is_last) {
888 ret = qup_i2c_bam_schedule_desc(qup);
889 if (ret)
890 break;
891
892 qup_i2c_bam_clear_tag_buffers(qup);
893 }
894 }
895
896out:
897 disable_irq(qup->irq);
898
899 qup->msg = NULL;
900 return ret;
901}
902
903static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
904 struct i2c_msg *msg)
905{
906 unsigned long left;
907 int ret = 0;
908
909 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
910 if (!left) {
911 writel(1, qup->base + QUP_SW_RESET);
912 ret = -ETIMEDOUT;
913 }
914
915 if (qup->bus_err || qup->qup_err)
916 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
917
918 return ret;
919}
920
921static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
922{
923 struct qup_i2c_block *blk = &qup->blk;
924 struct i2c_msg *msg = qup->msg;
925 u32 val = 0;
926 int idx = 0;
927
928 while (blk->fifo_available && qup->pos < msg->len) {
929 if ((idx & 1) == 0) {
930 /* Reading 2 words at time */
931 val = readl(qup->base + QUP_IN_FIFO_BASE);
932 msg->buf[qup->pos++] = val & 0xFF;
933 } else {
934 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
935 }
936 idx++;
937 blk->fifo_available--;
938 }
939
940 if (qup->pos == msg->len)
941 blk->rx_bytes_read = true;
942}
943
944static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
945{
946 struct i2c_msg *msg = qup->msg;
947 u32 addr, len, val;
948
949 addr = i2c_8bit_addr_from_msg(msg);
950
951 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
952 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
953
954 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
955 writel(val, qup->base + QUP_OUT_FIFO_BASE);
956}
957
958static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
959{
960 struct qup_i2c_block *blk = &qup->blk;
961 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
962 u32 io_mode = QUP_REPACK_EN;
963
964 blk->is_tx_blk_mode =
965 blk->total_tx_len > qup->out_fifo_sz ? true : false;
966 blk->is_rx_blk_mode =
967 blk->total_rx_len > qup->in_fifo_sz ? true : false;
968
969 if (blk->is_tx_blk_mode) {
970 io_mode |= QUP_OUTPUT_BLK_MODE;
971 writel(0, qup->base + QUP_MX_WRITE_CNT);
972 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
973 } else {
974 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
975 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
976 }
977
978 if (blk->total_rx_len) {
979 if (blk->is_rx_blk_mode) {
980 io_mode |= QUP_INPUT_BLK_MODE;
981 writel(0, qup->base + QUP_MX_READ_CNT);
982 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
983 } else {
984 writel(0, qup->base + QUP_MX_INPUT_CNT);
985 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
986 }
987 } else {
988 qup_config |= QUP_NO_INPUT;
989 }
990
991 writel(qup_config, qup->base + QUP_CONFIG);
992 writel(io_mode, qup->base + QUP_IO_MODE);
993}
994
995static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
996{
997 blk->tx_fifo_free = 0;
998 blk->fifo_available = 0;
999 blk->rx_bytes_read = false;
1000}
1001
1002static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
1003{
1004 struct qup_i2c_block *blk = &qup->blk;
1005 int ret;
1006
1007 qup_i2c_clear_blk_v1(blk);
1008 qup_i2c_conf_v1(qup);
1009 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1010 if (ret)
1011 return ret;
1012
1013 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1014
1015 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1016 if (ret)
1017 return ret;
1018
1019 reinit_completion(&qup->xfer);
1020 enable_irq(qup->irq);
1021 if (!blk->is_tx_blk_mode) {
1022 blk->tx_fifo_free = qup->out_fifo_sz;
1023
1024 if (is_rx)
1025 qup_i2c_write_rx_tags_v1(qup);
1026 else
1027 qup_i2c_write_tx_fifo_v1(qup);
1028 }
1029
1030 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1031 if (ret)
1032 goto err;
1033
1034 ret = qup_i2c_wait_for_complete(qup, qup->msg);
1035 if (ret)
1036 goto err;
1037
1038 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1039
1040err:
1041 disable_irq(qup->irq);
1042 return ret;
1043}
1044
1045static int qup_i2c_write_one(struct qup_i2c_dev *qup)
1046{
1047 struct i2c_msg *msg = qup->msg;
1048 struct qup_i2c_block *blk = &qup->blk;
1049
1050 qup->pos = 0;
1051 blk->total_tx_len = msg->len + 1;
1052 blk->total_rx_len = 0;
1053
1054 return qup_i2c_conf_xfer_v1(qup, false);
1055}
1056
1057static int qup_i2c_read_one(struct qup_i2c_dev *qup)
1058{
1059 struct qup_i2c_block *blk = &qup->blk;
1060
1061 qup->pos = 0;
1062 blk->total_tx_len = 2;
1063 blk->total_rx_len = qup->msg->len;
1064
1065 return qup_i2c_conf_xfer_v1(qup, true);
1066}
1067
1068static int qup_i2c_xfer(struct i2c_adapter *adap,
1069 struct i2c_msg msgs[],
1070 int num)
1071{
1072 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1073 int ret, idx;
1074
1075 ret = pm_runtime_get_sync(qup->dev);
1076 if (ret < 0)
1077 goto out;
1078
1079 qup->bus_err = 0;
1080 qup->qup_err = 0;
1081
1082 writel(1, qup->base + QUP_SW_RESET);
1083 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1084 if (ret)
1085 goto out;
1086
1087 /* Configure QUP as I2C mini core */
1088 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1089
1090 for (idx = 0; idx < num; idx++) {
1091 if (qup_i2c_poll_state_i2c_master(qup)) {
1092 ret = -EIO;
1093 goto out;
1094 }
1095
1096 if (qup_i2c_check_msg_len(&msgs[idx])) {
1097 ret = -EINVAL;
1098 goto out;
1099 }
1100
1101 qup->msg = &msgs[idx];
1102 if (msgs[idx].flags & I2C_M_RD)
1103 ret = qup_i2c_read_one(qup);
1104 else
1105 ret = qup_i2c_write_one(qup);
1106
1107 if (ret)
1108 break;
1109
1110 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1111 if (ret)
1112 break;
1113 }
1114
1115 if (ret == 0)
1116 ret = num;
1117out:
1118
1119 pm_runtime_mark_last_busy(qup->dev);
1120 pm_runtime_put_autosuspend(qup->dev);
1121
1122 return ret;
1123}
1124
1125/*
1126 * Configure registers related with reconfiguration during run and call it
1127 * before each i2c sub transfer.
1128 */
1129static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
1130{
1131 struct qup_i2c_block *blk = &qup->blk;
1132 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
1133
1134 if (blk->is_tx_blk_mode)
1135 writel(qup->config_run | blk->total_tx_len,
1136 qup->base + QUP_MX_OUTPUT_CNT);
1137 else
1138 writel(qup->config_run | blk->total_tx_len,
1139 qup->base + QUP_MX_WRITE_CNT);
1140
1141 if (blk->total_rx_len) {
1142 if (blk->is_rx_blk_mode)
1143 writel(qup->config_run | blk->total_rx_len,
1144 qup->base + QUP_MX_INPUT_CNT);
1145 else
1146 writel(qup->config_run | blk->total_rx_len,
1147 qup->base + QUP_MX_READ_CNT);
1148 } else {
1149 qup_config |= QUP_NO_INPUT;
1150 }
1151
1152 writel(qup_config, qup->base + QUP_CONFIG);
1153}
1154
1155/*
1156 * Configure registers related with transfer mode (FIFO/Block)
1157 * before starting of i2c transfer. It will be called only once in
1158 * QUP RESET state.
1159 */
1160static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
1161{
1162 struct qup_i2c_block *blk = &qup->blk;
1163 u32 io_mode = QUP_REPACK_EN;
1164
1165 if (blk->is_tx_blk_mode) {
1166 io_mode |= QUP_OUTPUT_BLK_MODE;
1167 writel(0, qup->base + QUP_MX_WRITE_CNT);
1168 } else {
1169 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1170 }
1171
1172 if (blk->is_rx_blk_mode) {
1173 io_mode |= QUP_INPUT_BLK_MODE;
1174 writel(0, qup->base + QUP_MX_READ_CNT);
1175 } else {
1176 writel(0, qup->base + QUP_MX_INPUT_CNT);
1177 }
1178
1179 writel(io_mode, qup->base + QUP_IO_MODE);
1180}
1181
1182/* Clear required variables before starting of any QUP v2 sub transfer. */
1183static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
1184{
1185 blk->send_last_word = false;
1186 blk->tx_tags_sent = false;
1187 blk->tx_fifo_data = 0;
1188 blk->tx_fifo_data_pos = 0;
1189 blk->tx_fifo_free = 0;
1190
1191 blk->rx_tags_fetched = false;
1192 blk->rx_bytes_read = false;
1193 blk->rx_fifo_data = 0;
1194 blk->rx_fifo_data_pos = 0;
1195 blk->fifo_available = 0;
1196}
1197
1198/* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1199static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
1200{
1201 struct qup_i2c_block *blk = &qup->blk;
1202 int j;
1203
1204 for (j = blk->rx_fifo_data_pos;
1205 blk->cur_blk_len && blk->fifo_available;
1206 blk->cur_blk_len--, blk->fifo_available--) {
1207 if (j == 0)
1208 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1209
1210 *(blk->cur_data++) = blk->rx_fifo_data;
1211 blk->rx_fifo_data >>= 8;
1212
1213 if (j == 3)
1214 j = 0;
1215 else
1216 j++;
1217 }
1218
1219 blk->rx_fifo_data_pos = j;
1220}
1221
1222/* Receive tags for read message in QUP v2 i2c transfer. */
1223static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
1224{
1225 struct qup_i2c_block *blk = &qup->blk;
1226
1227 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1228 blk->rx_fifo_data >>= blk->rx_tag_len * 8;
1229 blk->rx_fifo_data_pos = blk->rx_tag_len;
1230 blk->fifo_available -= blk->rx_tag_len;
1231}
1232
1233/*
1234 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1235 * preceded by received data bytes so
1236 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1237 * all tag bytes and discard that.
1238 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1239 * set rx_bytes_read to true.
1240 */
1241static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
1242{
1243 struct qup_i2c_block *blk = &qup->blk;
1244
1245 if (!blk->rx_tags_fetched) {
1246 qup_i2c_recv_tags(qup);
1247 blk->rx_tags_fetched = true;
1248 }
1249
1250 qup_i2c_recv_data(qup);
1251 if (!blk->cur_blk_len)
1252 blk->rx_bytes_read = true;
1253}
1254
1255/*
1256 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1257 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1258 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1259 */
1260static void
1261qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
1262{
1263 struct qup_i2c_block *blk = &qup->blk;
1264 unsigned int j;
1265
1266 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
1267 (*len)--, blk->tx_fifo_free--) {
1268 blk->tx_fifo_data |= *(*data)++ << (j * 8);
1269 if (j == 3) {
1270 writel(blk->tx_fifo_data,
1271 qup->base + QUP_OUT_FIFO_BASE);
1272 blk->tx_fifo_data = 0x0;
1273 j = 0;
1274 } else {
1275 j++;
1276 }
1277 }
1278
1279 blk->tx_fifo_data_pos = j;
1280}
1281
1282/* Transfer tags for read message in QUP v2 i2c transfer. */
1283static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
1284{
1285 struct qup_i2c_block *blk = &qup->blk;
1286
1287 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
1288 if (blk->tx_fifo_data_pos)
1289 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1290}
1291
1292/*
1293 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1294 * need to be written and QUP write tags can have maximum 256 data length, so
1295 *
1296 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1297 * tags to TX FIFO and set tx_tags_sent to true.
1298 * 2. Check if send_last_word is true. It will be set when last few data bytes
1299 * (less than 4 bytes) are reamining to be written in FIFO because of no FIFO
1300 * space. All this data bytes are available in tx_fifo_data so write this
1301 * in FIFO.
1302 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1303 * then more data is pending otherwise following 3 cases can be possible
1304 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
1305 * have been written in TX FIFO so nothing else is required.
1306 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1307 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1308 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1309 * will be always greater than or equal to 4 bytes.
1310 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
1311 * bytes) are copied to tx_fifo_data but couldn't be sent because of
1312 * FIFO full so make send_last_word true.
1313 */
1314static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
1315{
1316 struct qup_i2c_block *blk = &qup->blk;
1317
1318 if (!blk->tx_tags_sent) {
1319 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
1320 &blk->tx_tag_len);
1321 blk->tx_tags_sent = true;
1322 }
1323
1324 if (blk->send_last_word)
1325 goto send_last_word;
1326
1327 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
1328 if (!blk->cur_blk_len) {
1329 if (!blk->tx_fifo_data_pos)
1330 return;
1331
1332 if (blk->tx_fifo_free)
1333 goto send_last_word;
1334
1335 blk->send_last_word = true;
1336 }
1337
1338 return;
1339
1340send_last_word:
1341 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1342}
1343
1344/*
1345 * Main transfer function which read or write i2c data.
1346 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1347 * transfers can be scheduled.
1348 */
1349static int
1350qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
1351 bool change_pause_state)
1352{
1353 struct qup_i2c_block *blk = &qup->blk;
1354 struct i2c_msg *msg = qup->msg;
1355 int ret;
1356
1357 /*
1358 * Check if its SMBus Block read for which the top level read will be
1359 * done into 2 QUP reads. One with message length 1 while other one is
1360 * with actual length.
1361 */
1362 if (qup_i2c_check_msg_len(msg)) {
1363 if (qup->is_smbus_read) {
1364 /*
1365 * If the message length is already read in
1366 * the first byte of the buffer, account for
1367 * that by setting the offset
1368 */
1369 blk->cur_data += 1;
1370 is_first = false;
1371 } else {
1372 change_pause_state = false;
1373 }
1374 }
1375
1376 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
1377
1378 qup_i2c_clear_blk_v2(blk);
1379 qup_i2c_conf_count_v2(qup);
1380
1381 /* If it is first sub transfer, then configure i2c bus clocks */
1382 if (is_first) {
1383 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1384 if (ret)
1385 return ret;
1386
1387 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1388
1389 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1390 if (ret)
1391 return ret;
1392 }
1393
1394 reinit_completion(&qup->xfer);
1395 enable_irq(qup->irq);
1396 /*
1397 * In FIFO mode, tx FIFO can be written directly while in block mode the
1398 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
1399 */
1400 if (!blk->is_tx_blk_mode) {
1401 blk->tx_fifo_free = qup->out_fifo_sz;
1402
1403 if (is_rx)
1404 qup_i2c_write_rx_tags_v2(qup);
1405 else
1406 qup_i2c_write_tx_fifo_v2(qup);
1407 }
1408
1409 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1410 if (ret)
1411 goto err;
1412
1413 ret = qup_i2c_wait_for_complete(qup, msg);
1414 if (ret)
1415 goto err;
1416
1417 /* Move to pause state for all the transfers, except last one */
1418 if (change_pause_state) {
1419 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1420 if (ret)
1421 goto err;
1422 }
1423
1424err:
1425 disable_irq(qup->irq);
1426 return ret;
1427}
1428
1429/*
1430 * Transfer one read/write message in i2c transfer. It splits the message into
1431 * multiple of blk_xfer_limit data length blocks and schedule each
1432 * QUP block individually.
1433 */
1434static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
1435{
1436 int ret = 0;
1437 unsigned int data_len, i;
1438 struct i2c_msg *msg = qup->msg;
1439 struct qup_i2c_block *blk = &qup->blk;
1440 u8 *msg_buf = msg->buf;
1441
1442 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
1443 qup_i2c_set_blk_data(qup, msg);
1444
1445 for (i = 0; i < blk->count; i++) {
1446 data_len = qup_i2c_get_data_len(qup);
1447 blk->pos = i;
1448 blk->cur_tx_tags = blk->tags;
1449 blk->cur_blk_len = data_len;
1450 blk->tx_tag_len =
1451 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
1452
1453 blk->cur_data = msg_buf;
1454
1455 if (is_rx) {
1456 blk->total_tx_len = blk->tx_tag_len;
1457 blk->rx_tag_len = 2;
1458 blk->total_rx_len = blk->rx_tag_len + data_len;
1459 } else {
1460 blk->total_tx_len = blk->tx_tag_len + data_len;
1461 blk->total_rx_len = 0;
1462 }
1463
1464 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
1465 !qup->is_last || i < blk->count - 1);
1466 if (ret)
1467 return ret;
1468
1469 /* Handle SMBus block read length */
1470 if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
1471 !qup->is_smbus_read) {
1472 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
1473 return -EPROTO;
1474
1475 msg->len = msg->buf[0];
1476 qup->is_smbus_read = true;
1477 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
1478 qup->is_smbus_read = false;
1479 if (ret)
1480 return ret;
1481
1482 msg->len += 1;
1483 }
1484
1485 msg_buf += data_len;
1486 blk->data_len -= qup->blk_xfer_limit;
1487 }
1488
1489 return ret;
1490}
1491
1492/*
1493 * QUP v2 supports 3 modes
1494 * Programmed IO using FIFO mode : Less than FIFO size
1495 * Programmed IO using Block mode : Greater than FIFO size
1496 * DMA using BAM : Appropriate for any transaction size but the address should
1497 * be DMA applicable
1498 *
1499 * This function determines the mode which will be used for this transfer. An
1500 * i2c transfer contains multiple message. Following are the rules to determine
1501 * the mode used.
1502 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1503 * 2. If complete transfer length is greater than fifo size then use the DMA
1504 * mode.
1505 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1506 * for maximum tx and rx length to determine mode.
1507 */
1508static int
1509qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
1510 struct i2c_msg msgs[], int num)
1511{
1512 int idx;
1513 bool no_dma = false;
1514 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
1515
1516 /* All i2c_msgs should be transferred using either dma or cpu */
1517 for (idx = 0; idx < num; idx++) {
1518 if (msgs[idx].flags & I2C_M_RD)
1519 max_rx_len = max_t(unsigned int, max_rx_len,
1520 msgs[idx].len);
1521 else
1522 max_tx_len = max_t(unsigned int, max_tx_len,
1523 msgs[idx].len);
1524
1525 if (is_vmalloc_addr(msgs[idx].buf))
1526 no_dma = true;
1527
1528 total_len += msgs[idx].len;
1529 }
1530
1531 if (!no_dma && qup->is_dma &&
1532 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
1533 qup->use_dma = true;
1534 } else {
1535 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1536 QUP_MAX_TAGS_LEN ? true : false;
1537 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1538 READ_RX_TAGS_LEN ? true : false;
1539 }
1540
1541 return 0;
1542}
1543
1544static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1545 struct i2c_msg msgs[],
1546 int num)
1547{
1548 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1549 int ret, idx = 0;
1550
1551 qup->bus_err = 0;
1552 qup->qup_err = 0;
1553
1554 ret = pm_runtime_get_sync(qup->dev);
1555 if (ret < 0)
1556 goto out;
1557
1558 ret = qup_i2c_determine_mode_v2(qup, msgs, num);
1559 if (ret)
1560 goto out;
1561
1562 writel(1, qup->base + QUP_SW_RESET);
1563 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1564 if (ret)
1565 goto out;
1566
1567 /* Configure QUP as I2C mini core */
1568 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1569 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1570
1571 if (qup_i2c_poll_state_i2c_master(qup)) {
1572 ret = -EIO;
1573 goto out;
1574 }
1575
1576 if (qup->use_dma) {
1577 reinit_completion(&qup->xfer);
1578 ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
1579 qup->use_dma = false;
1580 } else {
1581 qup_i2c_conf_mode_v2(qup);
1582
1583 for (idx = 0; idx < num; idx++) {
1584 qup->msg = &msgs[idx];
1585 qup->is_last = idx == (num - 1);
1586
1587 ret = qup_i2c_xfer_v2_msg(qup, idx,
1588 !!(msgs[idx].flags & I2C_M_RD));
1589 if (ret)
1590 break;
1591 }
1592 qup->msg = NULL;
1593 }
1594
1595 if (!ret)
1596 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1597
1598 if (!ret)
1599 qup_i2c_change_state(qup, QUP_RESET_STATE);
1600
1601 if (ret == 0)
1602 ret = num;
1603out:
1604 pm_runtime_mark_last_busy(qup->dev);
1605 pm_runtime_put_autosuspend(qup->dev);
1606
1607 return ret;
1608}
1609
1610static u32 qup_i2c_func(struct i2c_adapter *adap)
1611{
1612 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1613}
1614
1615static const struct i2c_algorithm qup_i2c_algo = {
1616 .master_xfer = qup_i2c_xfer,
1617 .functionality = qup_i2c_func,
1618};
1619
1620static const struct i2c_algorithm qup_i2c_algo_v2 = {
1621 .master_xfer = qup_i2c_xfer_v2,
1622 .functionality = qup_i2c_func,
1623};
1624
1625/*
1626 * The QUP block will issue a NACK and STOP on the bus when reaching
1627 * the end of the read, the length of the read is specified as one byte
1628 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1629 */
1630static const struct i2c_adapter_quirks qup_i2c_quirks = {
1631 .flags = I2C_AQ_NO_ZERO_LEN,
1632 .max_read_len = QUP_READ_LIMIT,
1633};
1634
1635static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = {
1636 .flags = I2C_AQ_NO_ZERO_LEN,
1637};
1638
1639static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1640{
1641 clk_prepare_enable(qup->clk);
1642 clk_prepare_enable(qup->pclk);
1643}
1644
1645static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1646{
1647 u32 config;
1648
1649 qup_i2c_change_state(qup, QUP_RESET_STATE);
1650 clk_disable_unprepare(qup->clk);
1651 config = readl(qup->base + QUP_CONFIG);
1652 config |= QUP_CLOCK_AUTO_GATE;
1653 writel(config, qup->base + QUP_CONFIG);
1654 clk_disable_unprepare(qup->pclk);
1655}
1656
1657static const struct acpi_device_id qup_i2c_acpi_match[] = {
1658 { "QCOM8010"},
1659 { },
1660};
1661MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1662
1663static int qup_i2c_probe(struct platform_device *pdev)
1664{
1665 static const int blk_sizes[] = {4, 16, 32};
1666 struct qup_i2c_dev *qup;
1667 unsigned long one_bit_t;
1668 struct resource *res;
1669 u32 io_mode, hw_ver, size;
1670 int ret, fs_div, hs_div;
1671 u32 src_clk_freq = DEFAULT_SRC_CLK;
1672 u32 clk_freq = DEFAULT_CLK_FREQ;
1673 int blocks;
1674 bool is_qup_v1;
1675
1676 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1677 if (!qup)
1678 return -ENOMEM;
1679
1680 qup->dev = &pdev->dev;
1681 init_completion(&qup->xfer);
1682 platform_set_drvdata(pdev, qup);
1683
1684 if (scl_freq) {
1685 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
1686 clk_freq = scl_freq;
1687 } else {
1688 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1689 if (ret) {
1690 dev_notice(qup->dev, "using default clock-frequency %d",
1691 DEFAULT_CLK_FREQ);
1692 }
1693 }
1694
1695 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1696 qup->adap.algo = &qup_i2c_algo;
1697 qup->adap.quirks = &qup_i2c_quirks;
1698 is_qup_v1 = true;
1699 } else {
1700 qup->adap.algo = &qup_i2c_algo_v2;
1701 qup->adap.quirks = &qup_i2c_quirks_v2;
1702 is_qup_v1 = false;
1703 if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
1704 goto nodma;
1705 else
1706 ret = qup_i2c_req_dma(qup);
1707
1708 if (ret == -EPROBE_DEFER)
1709 goto fail_dma;
1710 else if (ret != 0)
1711 goto nodma;
1712
1713 qup->max_xfer_sg_len = (MX_BLOCKS << 1);
1714 blocks = (MX_DMA_BLOCKS << 1) + 1;
1715 qup->btx.sg = devm_kcalloc(&pdev->dev,
1716 blocks, sizeof(*qup->btx.sg),
1717 GFP_KERNEL);
1718 if (!qup->btx.sg) {
1719 ret = -ENOMEM;
1720 goto fail_dma;
1721 }
1722 sg_init_table(qup->btx.sg, blocks);
1723
1724 qup->brx.sg = devm_kcalloc(&pdev->dev,
1725 blocks, sizeof(*qup->brx.sg),
1726 GFP_KERNEL);
1727 if (!qup->brx.sg) {
1728 ret = -ENOMEM;
1729 goto fail_dma;
1730 }
1731 sg_init_table(qup->brx.sg, blocks);
1732
1733 /* 2 tag bytes for each block + 5 for start, stop tags */
1734 size = blocks * 2 + 5;
1735
1736 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1737 size, GFP_KERNEL);
1738 if (!qup->start_tag.start) {
1739 ret = -ENOMEM;
1740 goto fail_dma;
1741 }
1742
1743 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1744 if (!qup->brx.tag.start) {
1745 ret = -ENOMEM;
1746 goto fail_dma;
1747 }
1748
1749 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1750 if (!qup->btx.tag.start) {
1751 ret = -ENOMEM;
1752 goto fail_dma;
1753 }
1754 qup->is_dma = true;
1755 }
1756
1757nodma:
1758 /* We support frequencies up to FAST Mode Plus (1MHz) */
1759 if (!clk_freq || clk_freq > I2C_FAST_MODE_PLUS_FREQ) {
1760 dev_err(qup->dev, "clock frequency not supported %d\n",
1761 clk_freq);
1762 return -EINVAL;
1763 }
1764
1765 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1766 qup->base = devm_ioremap_resource(qup->dev, res);
1767 if (IS_ERR(qup->base))
1768 return PTR_ERR(qup->base);
1769
1770 qup->irq = platform_get_irq(pdev, 0);
1771 if (qup->irq < 0) {
1772 dev_err(qup->dev, "No IRQ defined\n");
1773 return qup->irq;
1774 }
1775
1776 if (has_acpi_companion(qup->dev)) {
1777 ret = device_property_read_u32(qup->dev,
1778 "src-clock-hz", &src_clk_freq);
1779 if (ret) {
1780 dev_notice(qup->dev, "using default src-clock-hz %d",
1781 DEFAULT_SRC_CLK);
1782 }
1783 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1784 } else {
1785 qup->clk = devm_clk_get(qup->dev, "core");
1786 if (IS_ERR(qup->clk)) {
1787 dev_err(qup->dev, "Could not get core clock\n");
1788 return PTR_ERR(qup->clk);
1789 }
1790
1791 qup->pclk = devm_clk_get(qup->dev, "iface");
1792 if (IS_ERR(qup->pclk)) {
1793 dev_err(qup->dev, "Could not get iface clock\n");
1794 return PTR_ERR(qup->pclk);
1795 }
1796 qup_i2c_enable_clocks(qup);
1797 src_clk_freq = clk_get_rate(qup->clk);
1798 }
1799
1800 /*
1801 * Bootloaders might leave a pending interrupt on certain QUP's,
1802 * so we reset the core before registering for interrupts.
1803 */
1804 writel(1, qup->base + QUP_SW_RESET);
1805 ret = qup_i2c_poll_state_valid(qup);
1806 if (ret)
1807 goto fail;
1808
1809 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1810 IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1811 if (ret) {
1812 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1813 goto fail;
1814 }
1815 disable_irq(qup->irq);
1816
1817 hw_ver = readl(qup->base + QUP_HW_VERSION);
1818 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1819
1820 io_mode = readl(qup->base + QUP_IO_MODE);
1821
1822 /*
1823 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1824 * associated with each byte written/received
1825 */
1826 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1827 if (size >= ARRAY_SIZE(blk_sizes)) {
1828 ret = -EIO;
1829 goto fail;
1830 }
1831 qup->out_blk_sz = blk_sizes[size];
1832
1833 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1834 if (size >= ARRAY_SIZE(blk_sizes)) {
1835 ret = -EIO;
1836 goto fail;
1837 }
1838 qup->in_blk_sz = blk_sizes[size];
1839
1840 if (is_qup_v1) {
1841 /*
1842 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
1843 * single transfer but the block size is in bytes so divide the
1844 * in_blk_sz and out_blk_sz by 2
1845 */
1846 qup->in_blk_sz /= 2;
1847 qup->out_blk_sz /= 2;
1848 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
1849 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
1850 qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
1851 } else {
1852 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
1853 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
1854 qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
1855 }
1856
1857 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1858 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1859
1860 size = QUP_INPUT_FIFO_SIZE(io_mode);
1861 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1862
1863 hs_div = 3;
1864 if (clk_freq <= I2C_STANDARD_FREQ) {
1865 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1866 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1867 } else {
1868 /* 33%/66% duty cycle */
1869 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
1870 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
1871 }
1872
1873 /*
1874 * Time it takes for a byte to be clocked out on the bus.
1875 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1876 */
1877 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1878 qup->one_byte_t = one_bit_t * 9;
1879 qup->xfer_timeout = TOUT_MIN * HZ +
1880 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
1881
1882 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1883 qup->in_blk_sz, qup->in_fifo_sz,
1884 qup->out_blk_sz, qup->out_fifo_sz);
1885
1886 i2c_set_adapdata(&qup->adap, qup);
1887 qup->adap.dev.parent = qup->dev;
1888 qup->adap.dev.of_node = pdev->dev.of_node;
1889 qup->is_last = true;
1890
1891 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1892
1893 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1894 pm_runtime_use_autosuspend(qup->dev);
1895 pm_runtime_set_active(qup->dev);
1896 pm_runtime_enable(qup->dev);
1897
1898 ret = i2c_add_adapter(&qup->adap);
1899 if (ret)
1900 goto fail_runtime;
1901
1902 return 0;
1903
1904fail_runtime:
1905 pm_runtime_disable(qup->dev);
1906 pm_runtime_set_suspended(qup->dev);
1907fail:
1908 qup_i2c_disable_clocks(qup);
1909fail_dma:
1910 if (qup->btx.dma)
1911 dma_release_channel(qup->btx.dma);
1912 if (qup->brx.dma)
1913 dma_release_channel(qup->brx.dma);
1914 return ret;
1915}
1916
1917static int qup_i2c_remove(struct platform_device *pdev)
1918{
1919 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1920
1921 if (qup->is_dma) {
1922 dma_release_channel(qup->btx.dma);
1923 dma_release_channel(qup->brx.dma);
1924 }
1925
1926 disable_irq(qup->irq);
1927 qup_i2c_disable_clocks(qup);
1928 i2c_del_adapter(&qup->adap);
1929 pm_runtime_disable(qup->dev);
1930 pm_runtime_set_suspended(qup->dev);
1931 return 0;
1932}
1933
1934#ifdef CONFIG_PM
1935static int qup_i2c_pm_suspend_runtime(struct device *device)
1936{
1937 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1938
1939 dev_dbg(device, "pm_runtime: suspending...\n");
1940 qup_i2c_disable_clocks(qup);
1941 return 0;
1942}
1943
1944static int qup_i2c_pm_resume_runtime(struct device *device)
1945{
1946 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1947
1948 dev_dbg(device, "pm_runtime: resuming...\n");
1949 qup_i2c_enable_clocks(qup);
1950 return 0;
1951}
1952#endif
1953
1954#ifdef CONFIG_PM_SLEEP
1955static int qup_i2c_suspend(struct device *device)
1956{
1957 if (!pm_runtime_suspended(device))
1958 return qup_i2c_pm_suspend_runtime(device);
1959 return 0;
1960}
1961
1962static int qup_i2c_resume(struct device *device)
1963{
1964 qup_i2c_pm_resume_runtime(device);
1965 pm_runtime_mark_last_busy(device);
1966 pm_request_autosuspend(device);
1967 return 0;
1968}
1969#endif
1970
1971static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1972 SET_SYSTEM_SLEEP_PM_OPS(
1973 qup_i2c_suspend,
1974 qup_i2c_resume)
1975 SET_RUNTIME_PM_OPS(
1976 qup_i2c_pm_suspend_runtime,
1977 qup_i2c_pm_resume_runtime,
1978 NULL)
1979};
1980
1981static const struct of_device_id qup_i2c_dt_match[] = {
1982 { .compatible = "qcom,i2c-qup-v1.1.1" },
1983 { .compatible = "qcom,i2c-qup-v2.1.1" },
1984 { .compatible = "qcom,i2c-qup-v2.2.1" },
1985 {}
1986};
1987MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1988
1989static struct platform_driver qup_i2c_driver = {
1990 .probe = qup_i2c_probe,
1991 .remove = qup_i2c_remove,
1992 .driver = {
1993 .name = "i2c_qup",
1994 .pm = &qup_i2c_qup_pm_ops,
1995 .of_match_table = qup_i2c_dt_match,
1996 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
1997 },
1998};
1999
2000module_platform_driver(qup_i2c_driver);
2001
2002MODULE_LICENSE("GPL v2");
2003MODULE_ALIAS("platform:i2c_qup");