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1/*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DISPLAY_H_
26#define _INTEL_DISPLAY_H_
27
28#include <drm/drm_util.h>
29
30#include "i915_reg_defs.h"
31#include "intel_display_limits.h"
32
33enum drm_scaling_filter;
34struct dpll;
35struct drm_atomic_state;
36struct drm_connector;
37struct drm_device;
38struct drm_display_mode;
39struct drm_encoder;
40struct drm_file;
41struct drm_format_info;
42struct drm_framebuffer;
43struct drm_i915_private;
44struct drm_mode_fb_cmd2;
45struct drm_modeset_acquire_ctx;
46struct drm_plane;
47struct drm_plane_state;
48struct i915_address_space;
49struct i915_gtt_view;
50struct intel_atomic_state;
51struct intel_crtc;
52struct intel_crtc_state;
53struct intel_digital_port;
54struct intel_display;
55struct intel_dp;
56struct intel_encoder;
57struct intel_initial_plane_config;
58struct intel_link_m_n;
59struct intel_plane;
60struct intel_plane_state;
61struct intel_power_domain_mask;
62struct intel_remapped_info;
63struct intel_rotation_info;
64struct pci_dev;
65struct work_struct;
66
67
68#define pipe_name(p) ((p) + 'A')
69
70static inline const char *transcoder_name(enum transcoder transcoder)
71{
72 switch (transcoder) {
73 case TRANSCODER_A:
74 return "A";
75 case TRANSCODER_B:
76 return "B";
77 case TRANSCODER_C:
78 return "C";
79 case TRANSCODER_D:
80 return "D";
81 case TRANSCODER_EDP:
82 return "EDP";
83 case TRANSCODER_DSI_A:
84 return "DSI A";
85 case TRANSCODER_DSI_C:
86 return "DSI C";
87 default:
88 return "<invalid>";
89 }
90}
91
92static inline bool transcoder_is_dsi(enum transcoder transcoder)
93{
94 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
95}
96
97#define plane_name(p) ((p) + 'A')
98
99#define for_each_plane_id_on_crtc(__crtc, __p) \
100 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
101 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
102
103#define for_each_dbuf_slice(__dev_priv, __slice) \
104 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
105 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
106
107#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
108 for_each_dbuf_slice((__dev_priv), (__slice)) \
109 for_each_if((__mask) & BIT(__slice))
110
111#define port_name(p) ((p) + 'A')
112
113/*
114 * Ports identifier referenced from other drivers.
115 * Expected to remain stable over time
116 */
117static inline const char *port_identifier(enum port port)
118{
119 switch (port) {
120 case PORT_A:
121 return "Port A";
122 case PORT_B:
123 return "Port B";
124 case PORT_C:
125 return "Port C";
126 case PORT_D:
127 return "Port D";
128 case PORT_E:
129 return "Port E";
130 case PORT_F:
131 return "Port F";
132 case PORT_G:
133 return "Port G";
134 case PORT_H:
135 return "Port H";
136 case PORT_I:
137 return "Port I";
138 default:
139 return "<invalid>";
140 }
141}
142
143enum tc_port {
144 TC_PORT_NONE = -1,
145
146 TC_PORT_1 = 0,
147 TC_PORT_2,
148 TC_PORT_3,
149 TC_PORT_4,
150 TC_PORT_5,
151 TC_PORT_6,
152
153 I915_MAX_TC_PORTS
154};
155
156enum aux_ch {
157 AUX_CH_NONE = -1,
158
159 AUX_CH_A,
160 AUX_CH_B,
161 AUX_CH_C,
162 AUX_CH_D,
163 AUX_CH_E, /* ICL+ */
164 AUX_CH_F,
165 AUX_CH_G,
166 AUX_CH_H,
167 AUX_CH_I,
168
169 /* tgl+ */
170 AUX_CH_USBC1 = AUX_CH_D,
171 AUX_CH_USBC2,
172 AUX_CH_USBC3,
173 AUX_CH_USBC4,
174 AUX_CH_USBC5,
175 AUX_CH_USBC6,
176
177 /* XE_LPD repositions D/E offsets and bitfields */
178 AUX_CH_D_XELPD = AUX_CH_USBC5,
179 AUX_CH_E_XELPD,
180};
181
182enum phy {
183 PHY_NONE = -1,
184
185 PHY_A = 0,
186 PHY_B,
187 PHY_C,
188 PHY_D,
189 PHY_E,
190 PHY_F,
191 PHY_G,
192 PHY_H,
193 PHY_I,
194
195 I915_MAX_PHYS
196};
197
198#define phy_name(a) ((a) + 'A')
199
200enum phy_fia {
201 FIA1,
202 FIA2,
203 FIA3,
204};
205
206#define for_each_hpd_pin(__pin) \
207 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
208
209#define for_each_pipe(__dev_priv, __p) \
210 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
211 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
212
213#define for_each_pipe_masked(__dev_priv, __p, __mask) \
214 for_each_pipe(__dev_priv, __p) \
215 for_each_if((__mask) & BIT(__p))
216
217#define for_each_cpu_transcoder(__dev_priv, __t) \
218 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
219 for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
220
221#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
222 for_each_cpu_transcoder(__dev_priv, __t) \
223 for_each_if ((__mask) & BIT(__t))
224
225#define for_each_sprite(__dev_priv, __p, __s) \
226 for ((__s) = 0; \
227 (__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
228 (__s)++)
229
230#define for_each_port(__port) \
231 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
232
233#define for_each_port_masked(__port, __ports_mask) \
234 for_each_port(__port) \
235 for_each_if((__ports_mask) & BIT(__port))
236
237#define for_each_phy_masked(__phy, __phys_mask) \
238 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
239 for_each_if((__phys_mask) & BIT(__phy))
240
241#define for_each_crtc(dev, crtc) \
242 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
243
244#define for_each_intel_plane(dev, intel_plane) \
245 list_for_each_entry(intel_plane, \
246 &(dev)->mode_config.plane_list, \
247 base.head)
248
249#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
250 list_for_each_entry(intel_plane, \
251 &(dev)->mode_config.plane_list, \
252 base.head) \
253 for_each_if((plane_mask) & \
254 drm_plane_mask(&intel_plane->base))
255
256#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
257 list_for_each_entry(intel_plane, \
258 &(dev)->mode_config.plane_list, \
259 base.head) \
260 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
261
262#define for_each_intel_crtc(dev, intel_crtc) \
263 list_for_each_entry(intel_crtc, \
264 &(dev)->mode_config.crtc_list, \
265 base.head)
266
267#define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
268 list_for_each_entry(intel_crtc, \
269 &(dev)->mode_config.crtc_list, \
270 base.head) \
271 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
272
273#define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \
274 list_for_each_entry_reverse((intel_crtc), \
275 &(dev)->mode_config.crtc_list, \
276 base.head) \
277 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
278
279#define for_each_intel_encoder(dev, intel_encoder) \
280 list_for_each_entry(intel_encoder, \
281 &(dev)->mode_config.encoder_list, \
282 base.head)
283
284#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
285 list_for_each_entry(intel_encoder, \
286 &(dev)->mode_config.encoder_list, \
287 base.head) \
288 for_each_if((encoder_mask) & \
289 drm_encoder_mask(&intel_encoder->base))
290
291#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
292 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
293 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
294 intel_encoder_can_psr(intel_encoder))
295
296#define for_each_intel_dp(dev, intel_encoder) \
297 for_each_intel_encoder(dev, intel_encoder) \
298 for_each_if(intel_encoder_is_dp(intel_encoder))
299
300#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
301 for_each_intel_encoder((dev), (intel_encoder)) \
302 for_each_if(intel_encoder_can_psr(intel_encoder))
303
304#define for_each_intel_connector_iter(intel_connector, iter) \
305 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
306
307#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
308 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
309 for_each_if((intel_encoder)->base.crtc == (__crtc))
310
311#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
312 for ((__i) = 0; \
313 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
314 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
315 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
316 (__i)++) \
317 for_each_if(plane)
318
319#define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
320 for ((__i) = 0; \
321 (__i) < (__state)->base.dev->mode_config.num_crtc && \
322 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
323 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
324 (__i)++) \
325 for_each_if(crtc)
326
327#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
328 for ((__i) = 0; \
329 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
330 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
331 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
332 (__i)++) \
333 for_each_if(plane)
334
335#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
336 for ((__i) = 0; \
337 (__i) < (__state)->base.dev->mode_config.num_crtc && \
338 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
339 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
340 (__i)++) \
341 for_each_if(crtc)
342
343#define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \
344 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
345 (__i) >= 0 && \
346 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
347 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
348 (__i)--) \
349 for_each_if(crtc)
350
351#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
352 for ((__i) = 0; \
353 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
354 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
355 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
356 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
357 (__i)++) \
358 for_each_if(plane)
359
360#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
361 for ((__i) = 0; \
362 (__i) < (__state)->base.dev->mode_config.num_crtc && \
363 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
364 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
365 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
366 (__i)++) \
367 for_each_if(crtc)
368
369#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
370 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
371 (__i) >= 0 && \
372 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
373 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
374 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
375 (__i)--) \
376 for_each_if(crtc)
377
378#define intel_atomic_crtc_state_for_each_plane_state( \
379 plane, plane_state, \
380 crtc_state) \
381 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
382 ((crtc_state)->uapi.plane_mask)) \
383 for_each_if ((plane_state = \
384 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
385
386#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
387 for ((__i) = 0; \
388 (__i) < (__state)->base.num_connector; \
389 (__i)++) \
390 for_each_if ((__state)->base.connectors[__i].ptr && \
391 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
392 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
393
394#define for_each_crtc_in_masks(display, crtc, first_pipes, second_pipes, i) \
395 for ((i) = 0; \
396 (i) < (I915_MAX_PIPES * 2) && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
397 (i)++) \
398 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
399
400#define for_each_crtc_in_masks_reverse(display, crtc, first_pipes, second_pipes, i) \
401 for ((i) = (I915_MAX_PIPES * 2 - 1); \
402 (i) >= 0 && ((crtc) = intel_crtc_for_pipe(display, (i) % I915_MAX_PIPES), 1); \
403 (i)--) \
404 for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
405
406#define for_each_pipe_crtc_modeset_disable(display, crtc, crtc_state, i) \
407 for_each_crtc_in_masks(display, crtc, \
408 _intel_modeset_primary_pipes(crtc_state), \
409 _intel_modeset_secondary_pipes(crtc_state), \
410 i)
411
412#define for_each_pipe_crtc_modeset_enable(display, crtc, crtc_state, i) \
413 for_each_crtc_in_masks_reverse(display, crtc, \
414 _intel_modeset_primary_pipes(crtc_state), \
415 _intel_modeset_secondary_pipes(crtc_state), \
416 i)
417
418int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
419int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
420 struct intel_crtc *crtc);
421u8 intel_calc_active_pipes(struct intel_atomic_state *state,
422 u8 active_pipes);
423void intel_link_compute_m_n(u16 bpp, int nlanes,
424 int pixel_clock, int link_clock,
425 int bw_overhead,
426 struct intel_link_m_n *m_n);
427u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
428 u32 pixel_format, u64 modifier);
429enum drm_mode_status
430intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
431 const struct drm_display_mode *mode,
432 int num_joined_pipes);
433enum drm_mode_status
434intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,
435 const struct drm_display_mode *mode);
436enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
437bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
438bool is_trans_port_sync_master(const struct intel_crtc_state *state);
439u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state);
440bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state);
441bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state);
442bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state);
443bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state);
444bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state);
445bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state);
446bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state);
447u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state);
448u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state);
449u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state);
450struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state);
451bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
452bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
453 const struct intel_crtc_state *pipe_config,
454 bool fastset);
455
456void intel_plane_destroy(struct drm_plane *plane);
457void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
458void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
459void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
460void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
461void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
462void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
463int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
464int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
465 const char *name, u32 reg, int ref_freq);
466int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
467 const char *name, u32 reg);
468void intel_init_display_hooks(struct drm_i915_private *dev_priv);
469unsigned int intel_fb_xy_to_linear(int x, int y,
470 const struct intel_plane_state *state,
471 int plane);
472void intel_add_fb_offsets(int *x, int *y,
473 const struct intel_plane_state *state, int plane);
474unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
475unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
476bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
477void intel_encoder_destroy(struct drm_encoder *encoder);
478struct drm_display_mode *
479intel_encoder_current_mode(struct intel_encoder *encoder);
480void intel_encoder_get_config(struct intel_encoder *encoder,
481 struct intel_crtc_state *crtc_state);
482bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
483bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
484bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
485enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
486 enum port port);
487
488enum phy intel_encoder_to_phy(struct intel_encoder *encoder);
489bool intel_encoder_is_combo(struct intel_encoder *encoder);
490bool intel_encoder_is_snps(struct intel_encoder *encoder);
491bool intel_encoder_is_tc(struct intel_encoder *encoder);
492enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
493
494int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
495void vlv_wait_port_ready(struct intel_display *display,
496 struct intel_digital_port *dig_port,
497 unsigned int expected_mask);
498
499bool intel_fuzzy_clock_check(int clock1, int clock2);
500
501void intel_zero_m_n(struct intel_link_m_n *m_n);
502void intel_set_m_n(struct drm_i915_private *i915,
503 const struct intel_link_m_n *m_n,
504 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
505 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
506void intel_get_m_n(struct drm_i915_private *i915,
507 struct intel_link_m_n *m_n,
508 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
509 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
510bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
511 enum transcoder transcoder);
512void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
513 enum transcoder cpu_transcoder,
514 const struct intel_link_m_n *m_n);
515void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
516 enum transcoder cpu_transcoder,
517 const struct intel_link_m_n *m_n);
518void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
519 enum transcoder cpu_transcoder,
520 struct intel_link_m_n *m_n);
521void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
522 enum transcoder cpu_transcoder,
523 struct intel_link_m_n *m_n);
524int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
525int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
526enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
527enum intel_display_power_domain
528intel_aux_power_domain(struct intel_digital_port *dig_port);
529void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
530 struct intel_crtc_state *crtc_state);
531void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
532
533int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
534unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
535
536bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
537
538struct intel_encoder *
539intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
540 const struct intel_crtc_state *crtc_state);
541void intel_plane_disable_noatomic(struct intel_crtc *crtc,
542 struct intel_plane *plane);
543void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
544 struct intel_plane_state *plane_state,
545 bool visible);
546void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
547
548void intel_update_watermarks(struct drm_i915_private *i915);
549
550bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
551 struct intel_crtc *crtc);
552
553/* modesetting */
554int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
555 const char *reason, u8 pipe_mask);
556int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
557 const char *reason);
558int intel_modeset_commit_pipes(struct drm_i915_private *i915,
559 u8 pipe_mask,
560 struct drm_modeset_acquire_ctx *ctx);
561void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
562 struct intel_power_domain_mask *old_domains);
563void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
564 struct intel_power_domain_mask *domains);
565
566/* interface for intel_display_driver.c */
567void intel_setup_outputs(struct drm_i915_private *i915);
568int intel_initial_commit(struct drm_device *dev);
569void intel_panel_sanitize_ssc(struct drm_i915_private *i915);
570void intel_update_czclk(struct drm_i915_private *i915);
571void intel_atomic_helper_free_state_worker(struct work_struct *work);
572enum drm_mode_status intel_mode_valid(struct drm_device *dev,
573 const struct drm_display_mode *mode);
574int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
575 bool nonblock);
576
577void intel_hpd_poll_fini(struct drm_i915_private *i915);
578
579/* modesetting asserts */
580void assert_transcoder(struct drm_i915_private *dev_priv,
581 enum transcoder cpu_transcoder, bool state);
582#define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
583#define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
584
585bool assert_port_valid(struct drm_i915_private *i915, enum port port);
586
587/*
588 * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw
589 * state sanity checks to check for unexpected conditions which may not
590 * necessarily be a user visible problem. This will either drm_WARN() or
591 * drm_err() depending on the verbose_state_checks module param, to enable
592 * distros and users to tailor their preferred amount of i915 abrt spam.
593 */
594#define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \
595 int __ret_warn_on = !!(condition); \
596 if (unlikely(__ret_warn_on)) \
597 if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \
598 drm_err((__display)->drm, format); \
599 unlikely(__ret_warn_on); \
600})
601
602bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
603int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
604
605#endif
1/*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DISPLAY_H_
26#define _INTEL_DISPLAY_H_
27
28#include <drm/drm_util.h>
29#include <drm/i915_drm.h>
30
31enum link_m_n_set;
32struct dpll;
33struct drm_connector;
34struct drm_device;
35struct drm_encoder;
36struct drm_file;
37struct drm_framebuffer;
38struct drm_i915_error_state_buf;
39struct drm_i915_gem_object;
40struct drm_i915_private;
41struct drm_modeset_acquire_ctx;
42struct drm_plane;
43struct drm_plane_state;
44struct i915_ggtt_view;
45struct intel_crtc;
46struct intel_crtc_state;
47struct intel_digital_port;
48struct intel_dp;
49struct intel_encoder;
50struct intel_load_detect_pipe;
51struct intel_plane;
52struct intel_plane_state;
53struct intel_remapped_info;
54struct intel_rotation_info;
55
56enum i915_gpio {
57 GPIOA,
58 GPIOB,
59 GPIOC,
60 GPIOD,
61 GPIOE,
62 GPIOF,
63 GPIOG,
64 GPIOH,
65 __GPIOI_UNUSED,
66 GPIOJ,
67 GPIOK,
68 GPIOL,
69 GPIOM,
70 GPION,
71 GPIOO,
72};
73
74/*
75 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
76 * rest have consecutive values and match the enum values of transcoders
77 * with a 1:1 transcoder -> pipe mapping.
78 */
79enum pipe {
80 INVALID_PIPE = -1,
81
82 PIPE_A = 0,
83 PIPE_B,
84 PIPE_C,
85 PIPE_D,
86 _PIPE_EDP,
87
88 I915_MAX_PIPES = _PIPE_EDP
89};
90
91#define pipe_name(p) ((p) + 'A')
92
93enum transcoder {
94 /*
95 * The following transcoders have a 1:1 transcoder -> pipe mapping,
96 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
97 * rest have consecutive values and match the enum values of the pipes
98 * they map to.
99 */
100 TRANSCODER_A = PIPE_A,
101 TRANSCODER_B = PIPE_B,
102 TRANSCODER_C = PIPE_C,
103 TRANSCODER_D = PIPE_D,
104
105 /*
106 * The following transcoders can map to any pipe, their enum value
107 * doesn't need to stay fixed.
108 */
109 TRANSCODER_EDP,
110 TRANSCODER_DSI_0,
111 TRANSCODER_DSI_1,
112 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
113 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
114
115 I915_MAX_TRANSCODERS
116};
117
118static inline const char *transcoder_name(enum transcoder transcoder)
119{
120 switch (transcoder) {
121 case TRANSCODER_A:
122 return "A";
123 case TRANSCODER_B:
124 return "B";
125 case TRANSCODER_C:
126 return "C";
127 case TRANSCODER_D:
128 return "D";
129 case TRANSCODER_EDP:
130 return "EDP";
131 case TRANSCODER_DSI_A:
132 return "DSI A";
133 case TRANSCODER_DSI_C:
134 return "DSI C";
135 default:
136 return "<invalid>";
137 }
138}
139
140static inline bool transcoder_is_dsi(enum transcoder transcoder)
141{
142 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
143}
144
145/*
146 * Global legacy plane identifier. Valid only for primary/sprite
147 * planes on pre-g4x, and only for primary planes on g4x-bdw.
148 */
149enum i9xx_plane_id {
150 PLANE_A,
151 PLANE_B,
152 PLANE_C,
153};
154
155#define plane_name(p) ((p) + 'A')
156#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
157
158/*
159 * Per-pipe plane identifier.
160 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
161 * number of planes per CRTC. Not all platforms really have this many planes,
162 * which means some arrays of size I915_MAX_PLANES may have unused entries
163 * between the topmost sprite plane and the cursor plane.
164 *
165 * This is expected to be passed to various register macros
166 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
167 */
168enum plane_id {
169 PLANE_PRIMARY,
170 PLANE_SPRITE0,
171 PLANE_SPRITE1,
172 PLANE_SPRITE2,
173 PLANE_SPRITE3,
174 PLANE_SPRITE4,
175 PLANE_SPRITE5,
176 PLANE_CURSOR,
177
178 I915_MAX_PLANES,
179};
180
181#define for_each_plane_id_on_crtc(__crtc, __p) \
182 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
183 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
184
185/*
186 * Ports identifier referenced from other drivers.
187 * Expected to remain stable over time
188 */
189static inline const char *port_identifier(enum port port)
190{
191 switch (port) {
192 case PORT_A:
193 return "Port A";
194 case PORT_B:
195 return "Port B";
196 case PORT_C:
197 return "Port C";
198 case PORT_D:
199 return "Port D";
200 case PORT_E:
201 return "Port E";
202 case PORT_F:
203 return "Port F";
204 case PORT_G:
205 return "Port G";
206 case PORT_H:
207 return "Port H";
208 case PORT_I:
209 return "Port I";
210 default:
211 return "<invalid>";
212 }
213}
214
215enum tc_port {
216 PORT_TC_NONE = -1,
217
218 PORT_TC1 = 0,
219 PORT_TC2,
220 PORT_TC3,
221 PORT_TC4,
222 PORT_TC5,
223 PORT_TC6,
224
225 I915_MAX_TC_PORTS
226};
227
228enum tc_port_mode {
229 TC_PORT_TBT_ALT,
230 TC_PORT_DP_ALT,
231 TC_PORT_LEGACY,
232};
233
234enum dpio_channel {
235 DPIO_CH0,
236 DPIO_CH1
237};
238
239enum dpio_phy {
240 DPIO_PHY0,
241 DPIO_PHY1,
242 DPIO_PHY2,
243};
244
245#define I915_NUM_PHYS_VLV 2
246
247enum aux_ch {
248 AUX_CH_A,
249 AUX_CH_B,
250 AUX_CH_C,
251 AUX_CH_D,
252 AUX_CH_E, /* ICL+ */
253 AUX_CH_F,
254};
255
256#define aux_ch_name(a) ((a) + 'A')
257
258/* Used by dp and fdi links */
259struct intel_link_m_n {
260 u32 tu;
261 u32 gmch_m;
262 u32 gmch_n;
263 u32 link_m;
264 u32 link_n;
265};
266
267enum phy {
268 PHY_NONE = -1,
269
270 PHY_A = 0,
271 PHY_B,
272 PHY_C,
273 PHY_D,
274 PHY_E,
275 PHY_F,
276 PHY_G,
277 PHY_H,
278 PHY_I,
279
280 I915_MAX_PHYS
281};
282
283#define phy_name(a) ((a) + 'A')
284
285enum phy_fia {
286 FIA1,
287 FIA2,
288 FIA3,
289};
290
291#define for_each_pipe(__dev_priv, __p) \
292 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
293
294#define for_each_pipe_masked(__dev_priv, __p, __mask) \
295 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
296 for_each_if((__mask) & BIT(__p))
297
298#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
299 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
300 for_each_if ((__mask) & (1 << (__t)))
301
302#define for_each_universal_plane(__dev_priv, __pipe, __p) \
303 for ((__p) = 0; \
304 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
305 (__p)++)
306
307#define for_each_sprite(__dev_priv, __p, __s) \
308 for ((__s) = 0; \
309 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
310 (__s)++)
311
312#define for_each_port_masked(__port, __ports_mask) \
313 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
314 for_each_if((__ports_mask) & BIT(__port))
315
316#define for_each_phy_masked(__phy, __phys_mask) \
317 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
318 for_each_if((__phys_mask) & BIT(__phy))
319
320#define for_each_crtc(dev, crtc) \
321 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
322
323#define for_each_intel_plane(dev, intel_plane) \
324 list_for_each_entry(intel_plane, \
325 &(dev)->mode_config.plane_list, \
326 base.head)
327
328#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
329 list_for_each_entry(intel_plane, \
330 &(dev)->mode_config.plane_list, \
331 base.head) \
332 for_each_if((plane_mask) & \
333 drm_plane_mask(&intel_plane->base)))
334
335#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
336 list_for_each_entry(intel_plane, \
337 &(dev)->mode_config.plane_list, \
338 base.head) \
339 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
340
341#define for_each_intel_crtc(dev, intel_crtc) \
342 list_for_each_entry(intel_crtc, \
343 &(dev)->mode_config.crtc_list, \
344 base.head)
345
346#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
347 list_for_each_entry(intel_crtc, \
348 &(dev)->mode_config.crtc_list, \
349 base.head) \
350 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
351
352#define for_each_intel_encoder(dev, intel_encoder) \
353 list_for_each_entry(intel_encoder, \
354 &(dev)->mode_config.encoder_list, \
355 base.head)
356
357#define for_each_intel_dp(dev, intel_encoder) \
358 for_each_intel_encoder(dev, intel_encoder) \
359 for_each_if(intel_encoder_is_dp(intel_encoder))
360
361#define for_each_intel_connector_iter(intel_connector, iter) \
362 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
363
364#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
365 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
366 for_each_if((intel_encoder)->base.crtc == (__crtc))
367
368#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
369 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
370 for_each_if((intel_connector)->base.encoder == (__encoder))
371
372#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
373 for ((__i) = 0; \
374 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
375 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
376 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
377 (__i)++) \
378 for_each_if(plane)
379
380#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
381 for ((__i) = 0; \
382 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
383 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
384 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
385 (__i)++) \
386 for_each_if(plane)
387
388#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
389 for ((__i) = 0; \
390 (__i) < (__state)->base.dev->mode_config.num_crtc && \
391 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
392 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
393 (__i)++) \
394 for_each_if(crtc)
395
396#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
397 for ((__i) = 0; \
398 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
399 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
400 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
401 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
402 (__i)++) \
403 for_each_if(plane)
404
405#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
406 for ((__i) = 0; \
407 (__i) < (__state)->base.dev->mode_config.num_crtc && \
408 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
409 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
410 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
411 (__i)++) \
412 for_each_if(crtc)
413
414void intel_link_compute_m_n(u16 bpp, int nlanes,
415 int pixel_clock, int link_clock,
416 struct intel_link_m_n *m_n,
417 bool constant_n, bool fec_enable);
418bool is_ccs_modifier(u64 modifier);
419void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
420u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
421 u32 pixel_format, u64 modifier);
422bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
423enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
424
425void intel_plane_destroy(struct drm_plane *plane);
426void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
427void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
428enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
429int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
430int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
431 const char *name, u32 reg, int ref_freq);
432int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
433 const char *name, u32 reg);
434void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
435void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
436void intel_init_display_hooks(struct drm_i915_private *dev_priv);
437unsigned int intel_fb_xy_to_linear(int x, int y,
438 const struct intel_plane_state *state,
439 int plane);
440unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
441 int color_plane, unsigned int height);
442void intel_add_fb_offsets(int *x, int *y,
443 const struct intel_plane_state *state, int plane);
444unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
445unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
446bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
447int intel_display_suspend(struct drm_device *dev);
448void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
449void intel_encoder_destroy(struct drm_encoder *encoder);
450struct drm_display_mode *
451intel_encoder_current_mode(struct intel_encoder *encoder);
452bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
453bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
454enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
455 enum port port);
456int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
457 struct drm_file *file_priv);
458enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
459 enum pipe pipe);
460u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
461
462int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
463void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
464 struct intel_digital_port *dport,
465 unsigned int expected_mask);
466int intel_get_load_detect_pipe(struct drm_connector *connector,
467 const struct drm_display_mode *mode,
468 struct intel_load_detect_pipe *old,
469 struct drm_modeset_acquire_ctx *ctx);
470void intel_release_load_detect_pipe(struct drm_connector *connector,
471 struct intel_load_detect_pipe *old,
472 struct drm_modeset_acquire_ctx *ctx);
473struct i915_vma *
474intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
475 const struct i915_ggtt_view *view,
476 bool uses_fence,
477 unsigned long *out_flags);
478void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
479struct drm_framebuffer *
480intel_framebuffer_create(struct drm_i915_gem_object *obj,
481 struct drm_mode_fb_cmd2 *mode_cmd);
482int intel_prepare_plane_fb(struct drm_plane *plane,
483 struct drm_plane_state *new_state);
484void intel_cleanup_plane_fb(struct drm_plane *plane,
485 struct drm_plane_state *old_state);
486
487void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
488 enum pipe pipe);
489
490int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
491 const struct dpll *dpll);
492void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
493int lpt_get_iclkip(struct drm_i915_private *dev_priv);
494bool intel_fuzzy_clock_check(int clock1, int clock2);
495
496void intel_prepare_reset(struct drm_i915_private *dev_priv);
497void intel_finish_reset(struct drm_i915_private *dev_priv);
498void intel_dp_get_m_n(struct intel_crtc *crtc,
499 struct intel_crtc_state *pipe_config);
500void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
501 enum link_m_n_set m_n);
502void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
503 const struct intel_crtc_state *crtc_state);
504int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
505bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
506 struct dpll *best_clock);
507int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
508
509bool intel_crtc_active(struct intel_crtc *crtc);
510bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
511void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
512void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
513enum intel_display_power_domain intel_port_to_power_domain(enum port port);
514enum intel_display_power_domain
515intel_aux_power_domain(struct intel_digital_port *dig_port);
516void intel_mode_from_pipe_config(struct drm_display_mode *mode,
517 struct intel_crtc_state *pipe_config);
518void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
519 struct intel_crtc_state *crtc_state);
520
521u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
522int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
523int skl_max_scale(const struct intel_crtc_state *crtc_state,
524 u32 pixel_format);
525u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
526 const struct intel_plane_state *plane_state);
527u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
528u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
529 const struct intel_plane_state *plane_state);
530u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
531u32 skl_plane_stride(const struct intel_plane_state *plane_state,
532 int plane);
533int skl_check_plane_surface(struct intel_plane_state *plane_state);
534int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
535int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
536unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
537 u32 pixel_format, u64 modifier,
538 unsigned int rotation);
539int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
540
541struct intel_display_error_state *
542intel_display_capture_error_state(struct drm_i915_private *dev_priv);
543void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
544 struct intel_display_error_state *error);
545
546/* modesetting */
547void intel_modeset_init_hw(struct drm_device *dev);
548int intel_modeset_init(struct drm_device *dev);
549void intel_modeset_driver_remove(struct drm_device *dev);
550int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state);
551void intel_display_resume(struct drm_device *dev);
552void i915_redisable_vga(struct drm_i915_private *dev_priv);
553void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
554void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
555
556/* modesetting asserts */
557void assert_panel_unlocked(struct drm_i915_private *dev_priv,
558 enum pipe pipe);
559void assert_pll(struct drm_i915_private *dev_priv,
560 enum pipe pipe, bool state);
561#define assert_pll_enabled(d, p) assert_pll(d, p, true)
562#define assert_pll_disabled(d, p) assert_pll(d, p, false)
563void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
564#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
565#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
566void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
567 enum pipe pipe, bool state);
568#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
569#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
570void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
571#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
572#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
573
574/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
575 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
576 * which may not necessarily be a user visible problem. This will either
577 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
578 * enable distros and users to tailor their preferred amount of i915 abrt
579 * spam.
580 */
581#define I915_STATE_WARN(condition, format...) ({ \
582 int __ret_warn_on = !!(condition); \
583 if (unlikely(__ret_warn_on)) \
584 if (!WARN(i915_modparams.verbose_state_checks, format)) \
585 DRM_ERROR(format); \
586 unlikely(__ret_warn_on); \
587})
588
589#define I915_STATE_WARN_ON(x) \
590 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
591
592#endif