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1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/ratelimit.h>
26#include <linux/printk.h>
27#include <linux/slab.h>
28#include <linux/list.h>
29#include <linux/types.h>
30#include <linux/bitops.h>
31#include <linux/sched.h>
32#include "kfd_priv.h"
33#include "kfd_device_queue_manager.h"
34#include "kfd_mqd_manager.h"
35#include "cik_regs.h"
36#include "kfd_kernel_queue.h"
37#include "amdgpu_amdkfd.h"
38#include "amdgpu_reset.h"
39#include "mes_v11_api_def.h"
40#include "kfd_debug.h"
41
42/* Size of the per-pipe EOP queue */
43#define CIK_HPD_EOP_BYTES_LOG2 11
44#define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
45
46static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
47 u32 pasid, unsigned int vmid);
48
49static int execute_queues_cpsch(struct device_queue_manager *dqm,
50 enum kfd_unmap_queues_filter filter,
51 uint32_t filter_param,
52 uint32_t grace_period);
53static int unmap_queues_cpsch(struct device_queue_manager *dqm,
54 enum kfd_unmap_queues_filter filter,
55 uint32_t filter_param,
56 uint32_t grace_period,
57 bool reset);
58
59static int map_queues_cpsch(struct device_queue_manager *dqm);
60
61static void deallocate_sdma_queue(struct device_queue_manager *dqm,
62 struct queue *q);
63
64static inline void deallocate_hqd(struct device_queue_manager *dqm,
65 struct queue *q);
66static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
67static int allocate_sdma_queue(struct device_queue_manager *dqm,
68 struct queue *q, const uint32_t *restore_sdma_id);
69static void kfd_process_hw_exception(struct work_struct *work);
70
71static inline
72enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
73{
74 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
75 return KFD_MQD_TYPE_SDMA;
76 return KFD_MQD_TYPE_CP;
77}
78
79static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
80{
81 int i;
82 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec
83 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe;
84
85 /* queue is available for KFD usage if bit is 1 */
86 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i)
87 if (test_bit(pipe_offset + i,
88 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
89 return true;
90 return false;
91}
92
93unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
94{
95 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap,
96 AMDGPU_MAX_QUEUES);
97}
98
99unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
100{
101 return dqm->dev->kfd->shared_resources.num_queue_per_pipe;
102}
103
104unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
105{
106 return dqm->dev->kfd->shared_resources.num_pipe_per_mec;
107}
108
109static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm)
110{
111 return kfd_get_num_sdma_engines(dqm->dev) +
112 kfd_get_num_xgmi_sdma_engines(dqm->dev);
113}
114
115unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
116{
117 return kfd_get_num_sdma_engines(dqm->dev) *
118 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
119}
120
121unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
122{
123 return kfd_get_num_xgmi_sdma_engines(dqm->dev) *
124 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
125}
126
127static void init_sdma_bitmaps(struct device_queue_manager *dqm)
128{
129 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
130 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm));
131
132 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
133 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
134
135 /* Mask out the reserved queues */
136 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap,
137 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap,
138 KFD_MAX_SDMA_QUEUES);
139}
140
141void program_sh_mem_settings(struct device_queue_manager *dqm,
142 struct qcm_process_device *qpd)
143{
144 uint32_t xcc_mask = dqm->dev->xcc_mask;
145 int xcc_id;
146
147 for_each_inst(xcc_id, xcc_mask)
148 dqm->dev->kfd2kgd->program_sh_mem_settings(
149 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config,
150 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit,
151 qpd->sh_mem_bases, xcc_id);
152}
153
154static void kfd_hws_hang(struct device_queue_manager *dqm)
155{
156 struct device_process_node *cur;
157 struct qcm_process_device *qpd;
158 struct queue *q;
159
160 /* Mark all device queues as reset. */
161 list_for_each_entry(cur, &dqm->queues, list) {
162 qpd = cur->qpd;
163 list_for_each_entry(q, &qpd->queues_list, list) {
164 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
165
166 pdd->has_reset_queue = true;
167 }
168 }
169
170 /*
171 * Issue a GPU reset if HWS is unresponsive
172 */
173 schedule_work(&dqm->hw_exception_work);
174}
175
176static int convert_to_mes_queue_type(int queue_type)
177{
178 int mes_queue_type;
179
180 switch (queue_type) {
181 case KFD_QUEUE_TYPE_COMPUTE:
182 mes_queue_type = MES_QUEUE_TYPE_COMPUTE;
183 break;
184 case KFD_QUEUE_TYPE_SDMA:
185 mes_queue_type = MES_QUEUE_TYPE_SDMA;
186 break;
187 default:
188 WARN(1, "Invalid queue type %d", queue_type);
189 mes_queue_type = -EINVAL;
190 break;
191 }
192
193 return mes_queue_type;
194}
195
196static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
197 struct qcm_process_device *qpd)
198{
199 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
200 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
201 struct mes_add_queue_input queue_input;
202 int r, queue_type;
203 uint64_t wptr_addr_off;
204
205 if (!dqm->sched_running || dqm->sched_halt)
206 return 0;
207 if (!down_read_trylock(&adev->reset_domain->sem))
208 return -EIO;
209
210 if (!pdd->proc_ctx_cpu_ptr) {
211 r = amdgpu_amdkfd_alloc_gtt_mem(adev,
212 AMDGPU_MES_PROC_CTX_SIZE,
213 &pdd->proc_ctx_bo,
214 &pdd->proc_ctx_gpu_addr,
215 &pdd->proc_ctx_cpu_ptr,
216 false);
217 if (r) {
218 dev_err(adev->dev,
219 "failed to allocate process context bo\n");
220 return r;
221 }
222 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);
223 }
224
225 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
226 queue_input.process_id = qpd->pqm->process->pasid;
227 queue_input.page_table_base_addr = qpd->page_table_base;
228 queue_input.process_va_start = 0;
229 queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
230 /* MES unit for quantum is 100ns */
231 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */
232 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr;
233 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */
234 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
235 queue_input.inprocess_gang_priority = q->properties.priority;
236 queue_input.gang_global_priority_level =
237 AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
238 queue_input.doorbell_offset = q->properties.doorbell_off;
239 queue_input.mqd_addr = q->gart_mqd_addr;
240 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
241
242 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
243 queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->properties.wptr_bo) + wptr_addr_off;
244
245 queue_input.is_kfd_process = 1;
246 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL);
247 queue_input.queue_size = q->properties.queue_size >> 2;
248
249 queue_input.paging = false;
250 queue_input.tba_addr = qpd->tba_addr;
251 queue_input.tma_addr = qpd->tma_addr;
252 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device);
253 queue_input.skip_process_ctx_clear =
254 qpd->pqm->process->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED &&
255 (qpd->pqm->process->debug_trap_enabled ||
256 kfd_dbg_has_ttmps_always_setup(q->device));
257
258 queue_type = convert_to_mes_queue_type(q->properties.type);
259 if (queue_type < 0) {
260 dev_err(adev->dev, "Queue type not supported with MES, queue:%d\n",
261 q->properties.type);
262 up_read(&adev->reset_domain->sem);
263 return -EINVAL;
264 }
265 queue_input.queue_type = (uint32_t)queue_type;
266
267 queue_input.exclusively_scheduled = q->properties.is_gws;
268
269 amdgpu_mes_lock(&adev->mes);
270 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
271 amdgpu_mes_unlock(&adev->mes);
272 up_read(&adev->reset_domain->sem);
273 if (r) {
274 dev_err(adev->dev, "failed to add hardware queue to MES, doorbell=0x%x\n",
275 q->properties.doorbell_off);
276 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n");
277 kfd_hws_hang(dqm);
278 }
279
280 return r;
281}
282
283static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,
284 struct qcm_process_device *qpd)
285{
286 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
287 int r;
288 struct mes_remove_queue_input queue_input;
289
290 if (!dqm->sched_running || dqm->sched_halt)
291 return 0;
292 if (!down_read_trylock(&adev->reset_domain->sem))
293 return -EIO;
294
295 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
296 queue_input.doorbell_offset = q->properties.doorbell_off;
297 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
298
299 amdgpu_mes_lock(&adev->mes);
300 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
301 amdgpu_mes_unlock(&adev->mes);
302 up_read(&adev->reset_domain->sem);
303
304 if (r) {
305 dev_err(adev->dev, "failed to remove hardware queue from MES, doorbell=0x%x\n",
306 q->properties.doorbell_off);
307 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n");
308 kfd_hws_hang(dqm);
309 }
310
311 return r;
312}
313
314static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm)
315{
316 struct device_process_node *cur;
317 struct device *dev = dqm->dev->adev->dev;
318 struct qcm_process_device *qpd;
319 struct queue *q;
320 int retval = 0;
321
322 list_for_each_entry(cur, &dqm->queues, list) {
323 qpd = cur->qpd;
324 list_for_each_entry(q, &qpd->queues_list, list) {
325 if (q->properties.is_active) {
326 retval = remove_queue_mes(dqm, q, qpd);
327 if (retval) {
328 dev_err(dev, "%s: Failed to remove queue %d for dev %d",
329 __func__,
330 q->properties.queue_id,
331 dqm->dev->id);
332 return retval;
333 }
334 }
335 }
336 }
337
338 return retval;
339}
340
341static int add_all_kfd_queues_mes(struct device_queue_manager *dqm)
342{
343 struct device_process_node *cur;
344 struct device *dev = dqm->dev->adev->dev;
345 struct qcm_process_device *qpd;
346 struct queue *q;
347 int retval = 0;
348
349 list_for_each_entry(cur, &dqm->queues, list) {
350 qpd = cur->qpd;
351 list_for_each_entry(q, &qpd->queues_list, list) {
352 if (!q->properties.is_active)
353 continue;
354 retval = add_queue_mes(dqm, q, qpd);
355 if (retval) {
356 dev_err(dev, "%s: Failed to add queue %d for dev %d",
357 __func__,
358 q->properties.queue_id,
359 dqm->dev->id);
360 return retval;
361 }
362 }
363 }
364
365 return retval;
366}
367
368static int suspend_all_queues_mes(struct device_queue_manager *dqm)
369{
370 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
371 int r = 0;
372
373 if (!down_read_trylock(&adev->reset_domain->sem))
374 return -EIO;
375
376 r = amdgpu_mes_suspend(adev);
377 up_read(&adev->reset_domain->sem);
378
379 if (r) {
380 dev_err(adev->dev, "failed to suspend gangs from MES\n");
381 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n");
382 kfd_hws_hang(dqm);
383 }
384
385 return r;
386}
387
388static int resume_all_queues_mes(struct device_queue_manager *dqm)
389{
390 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
391 int r = 0;
392
393 if (!down_read_trylock(&adev->reset_domain->sem))
394 return -EIO;
395
396 r = amdgpu_mes_resume(adev);
397 up_read(&adev->reset_domain->sem);
398
399 if (r) {
400 dev_err(adev->dev, "failed to resume gangs from MES\n");
401 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n");
402 kfd_hws_hang(dqm);
403 }
404
405 return r;
406}
407
408static void increment_queue_count(struct device_queue_manager *dqm,
409 struct qcm_process_device *qpd,
410 struct queue *q)
411{
412 dqm->active_queue_count++;
413 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
414 q->properties.type == KFD_QUEUE_TYPE_DIQ)
415 dqm->active_cp_queue_count++;
416
417 if (q->properties.is_gws) {
418 dqm->gws_queue_count++;
419 qpd->mapped_gws_queue = true;
420 }
421}
422
423static void decrement_queue_count(struct device_queue_manager *dqm,
424 struct qcm_process_device *qpd,
425 struct queue *q)
426{
427 dqm->active_queue_count--;
428 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
429 q->properties.type == KFD_QUEUE_TYPE_DIQ)
430 dqm->active_cp_queue_count--;
431
432 if (q->properties.is_gws) {
433 dqm->gws_queue_count--;
434 qpd->mapped_gws_queue = false;
435 }
436}
437
438/*
439 * Allocate a doorbell ID to this queue.
440 * If doorbell_id is passed in, make sure requested ID is valid then allocate it.
441 */
442static int allocate_doorbell(struct qcm_process_device *qpd,
443 struct queue *q,
444 uint32_t const *restore_id)
445{
446 struct kfd_node *dev = qpd->dqm->dev;
447
448 if (!KFD_IS_SOC15(dev)) {
449 /* On pre-SOC15 chips we need to use the queue ID to
450 * preserve the user mode ABI.
451 */
452
453 if (restore_id && *restore_id != q->properties.queue_id)
454 return -EINVAL;
455
456 q->doorbell_id = q->properties.queue_id;
457 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
458 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
459 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
460 * doorbell assignments based on the engine and queue id.
461 * The doobell index distance between RLC (2*i) and (2*i+1)
462 * for a SDMA engine is 512.
463 */
464
465 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx;
466
467 /*
468 * q->properties.sdma_engine_id corresponds to the virtual
469 * sdma engine number. However, for doorbell allocation,
470 * we need the physical sdma engine id in order to get the
471 * correct doorbell offset.
472 */
473 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id *
474 get_num_all_sdma_engines(qpd->dqm) +
475 q->properties.sdma_engine_id]
476 + (q->properties.sdma_queue_id & 1)
477 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
478 + (q->properties.sdma_queue_id >> 1);
479
480 if (restore_id && *restore_id != valid_id)
481 return -EINVAL;
482 q->doorbell_id = valid_id;
483 } else {
484 /* For CP queues on SOC15 */
485 if (restore_id) {
486 /* make sure that ID is free */
487 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap))
488 return -EINVAL;
489
490 q->doorbell_id = *restore_id;
491 } else {
492 /* or reserve a free doorbell ID */
493 unsigned int found;
494
495 found = find_first_zero_bit(qpd->doorbell_bitmap,
496 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
497 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
498 pr_debug("No doorbells available");
499 return -EBUSY;
500 }
501 set_bit(found, qpd->doorbell_bitmap);
502 q->doorbell_id = found;
503 }
504 }
505
506 q->properties.doorbell_off = amdgpu_doorbell_index_on_bar(dev->adev,
507 qpd->proc_doorbells,
508 q->doorbell_id,
509 dev->kfd->device_info.doorbell_size);
510 return 0;
511}
512
513static void deallocate_doorbell(struct qcm_process_device *qpd,
514 struct queue *q)
515{
516 unsigned int old;
517 struct kfd_node *dev = qpd->dqm->dev;
518
519 if (!KFD_IS_SOC15(dev) ||
520 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
521 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
522 return;
523
524 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
525 WARN_ON(!old);
526}
527
528static void program_trap_handler_settings(struct device_queue_manager *dqm,
529 struct qcm_process_device *qpd)
530{
531 uint32_t xcc_mask = dqm->dev->xcc_mask;
532 int xcc_id;
533
534 if (dqm->dev->kfd2kgd->program_trap_handler_settings)
535 for_each_inst(xcc_id, xcc_mask)
536 dqm->dev->kfd2kgd->program_trap_handler_settings(
537 dqm->dev->adev, qpd->vmid, qpd->tba_addr,
538 qpd->tma_addr, xcc_id);
539}
540
541static int allocate_vmid(struct device_queue_manager *dqm,
542 struct qcm_process_device *qpd,
543 struct queue *q)
544{
545 struct device *dev = dqm->dev->adev->dev;
546 int allocated_vmid = -1, i;
547
548 for (i = dqm->dev->vm_info.first_vmid_kfd;
549 i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
550 if (!dqm->vmid_pasid[i]) {
551 allocated_vmid = i;
552 break;
553 }
554 }
555
556 if (allocated_vmid < 0) {
557 dev_err(dev, "no more vmid to allocate\n");
558 return -ENOSPC;
559 }
560
561 pr_debug("vmid allocated: %d\n", allocated_vmid);
562
563 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
564
565 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
566
567 qpd->vmid = allocated_vmid;
568 q->properties.vmid = allocated_vmid;
569
570 program_sh_mem_settings(dqm, qpd);
571
572 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled)
573 program_trap_handler_settings(dqm, qpd);
574
575 /* qpd->page_table_base is set earlier when register_process()
576 * is called, i.e. when the first queue is created.
577 */
578 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev,
579 qpd->vmid,
580 qpd->page_table_base);
581 /* invalidate the VM context after pasid and vmid mapping is set up */
582 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
583
584 if (dqm->dev->kfd2kgd->set_scratch_backing_va)
585 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev,
586 qpd->sh_hidden_private_base, qpd->vmid);
587
588 return 0;
589}
590
591static int flush_texture_cache_nocpsch(struct kfd_node *kdev,
592 struct qcm_process_device *qpd)
593{
594 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf;
595 int ret;
596
597 if (!qpd->ib_kaddr)
598 return -ENOMEM;
599
600 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
601 if (ret)
602 return ret;
603
604 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid,
605 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
606 pmf->release_mem_size / sizeof(uint32_t));
607}
608
609static void deallocate_vmid(struct device_queue_manager *dqm,
610 struct qcm_process_device *qpd,
611 struct queue *q)
612{
613 struct device *dev = dqm->dev->adev->dev;
614
615 /* On GFX v7, CP doesn't flush TC at dequeue */
616 if (q->device->adev->asic_type == CHIP_HAWAII)
617 if (flush_texture_cache_nocpsch(q->device, qpd))
618 dev_err(dev, "Failed to flush TC\n");
619
620 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
621
622 /* Release the vmid mapping */
623 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
624 dqm->vmid_pasid[qpd->vmid] = 0;
625
626 qpd->vmid = 0;
627 q->properties.vmid = 0;
628}
629
630static int create_queue_nocpsch(struct device_queue_manager *dqm,
631 struct queue *q,
632 struct qcm_process_device *qpd,
633 const struct kfd_criu_queue_priv_data *qd,
634 const void *restore_mqd, const void *restore_ctl_stack)
635{
636 struct mqd_manager *mqd_mgr;
637 int retval;
638
639 dqm_lock(dqm);
640
641 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
642 pr_warn("Can't create new usermode queue because %d queues were already created\n",
643 dqm->total_queue_count);
644 retval = -EPERM;
645 goto out_unlock;
646 }
647
648 if (list_empty(&qpd->queues_list)) {
649 retval = allocate_vmid(dqm, qpd, q);
650 if (retval)
651 goto out_unlock;
652 }
653 q->properties.vmid = qpd->vmid;
654 /*
655 * Eviction state logic: mark all queues as evicted, even ones
656 * not currently active. Restoring inactive queues later only
657 * updates the is_evicted flag but is a no-op otherwise.
658 */
659 q->properties.is_evicted = !!qpd->evicted;
660
661 q->properties.tba_addr = qpd->tba_addr;
662 q->properties.tma_addr = qpd->tma_addr;
663
664 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
665 q->properties.type)];
666 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
667 retval = allocate_hqd(dqm, q);
668 if (retval)
669 goto deallocate_vmid;
670 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
671 q->pipe, q->queue);
672 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
673 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
674 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
675 if (retval)
676 goto deallocate_vmid;
677 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
678 }
679
680 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
681 if (retval)
682 goto out_deallocate_hqd;
683
684 /* Temporarily release dqm lock to avoid a circular lock dependency */
685 dqm_unlock(dqm);
686 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
687 dqm_lock(dqm);
688
689 if (!q->mqd_mem_obj) {
690 retval = -ENOMEM;
691 goto out_deallocate_doorbell;
692 }
693
694 if (qd)
695 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
696 &q->properties, restore_mqd, restore_ctl_stack,
697 qd->ctl_stack_size);
698 else
699 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
700 &q->gart_mqd_addr, &q->properties);
701
702 if (q->properties.is_active) {
703 if (!dqm->sched_running) {
704 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
705 goto add_queue_to_list;
706 }
707
708 if (WARN(q->process->mm != current->mm,
709 "should only run in user thread"))
710 retval = -EFAULT;
711 else
712 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
713 q->queue, &q->properties, current->mm);
714 if (retval)
715 goto out_free_mqd;
716 }
717
718add_queue_to_list:
719 list_add(&q->list, &qpd->queues_list);
720 qpd->queue_count++;
721 if (q->properties.is_active)
722 increment_queue_count(dqm, qpd, q);
723
724 /*
725 * Unconditionally increment this counter, regardless of the queue's
726 * type or whether the queue is active.
727 */
728 dqm->total_queue_count++;
729 pr_debug("Total of %d queues are accountable so far\n",
730 dqm->total_queue_count);
731 goto out_unlock;
732
733out_free_mqd:
734 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
735out_deallocate_doorbell:
736 deallocate_doorbell(qpd, q);
737out_deallocate_hqd:
738 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
739 deallocate_hqd(dqm, q);
740 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
741 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
742 deallocate_sdma_queue(dqm, q);
743deallocate_vmid:
744 if (list_empty(&qpd->queues_list))
745 deallocate_vmid(dqm, qpd, q);
746out_unlock:
747 dqm_unlock(dqm);
748 return retval;
749}
750
751static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
752{
753 bool set;
754 int pipe, bit, i;
755
756 set = false;
757
758 for (pipe = dqm->next_pipe_to_allocate, i = 0;
759 i < get_pipes_per_mec(dqm);
760 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
761
762 if (!is_pipe_enabled(dqm, 0, pipe))
763 continue;
764
765 if (dqm->allocated_queues[pipe] != 0) {
766 bit = ffs(dqm->allocated_queues[pipe]) - 1;
767 dqm->allocated_queues[pipe] &= ~(1 << bit);
768 q->pipe = pipe;
769 q->queue = bit;
770 set = true;
771 break;
772 }
773 }
774
775 if (!set)
776 return -EBUSY;
777
778 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
779 /* horizontal hqd allocation */
780 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
781
782 return 0;
783}
784
785static inline void deallocate_hqd(struct device_queue_manager *dqm,
786 struct queue *q)
787{
788 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
789}
790
791#define SQ_IND_CMD_CMD_KILL 0x00000003
792#define SQ_IND_CMD_MODE_BROADCAST 0x00000001
793
794static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p)
795{
796 int status = 0;
797 unsigned int vmid;
798 uint16_t queried_pasid;
799 union SQ_CMD_BITS reg_sq_cmd;
800 union GRBM_GFX_INDEX_BITS reg_gfx_index;
801 struct kfd_process_device *pdd;
802 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
803 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
804 uint32_t xcc_mask = dev->xcc_mask;
805 int xcc_id;
806
807 reg_sq_cmd.u32All = 0;
808 reg_gfx_index.u32All = 0;
809
810 pr_debug("Killing all process wavefronts\n");
811
812 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) {
813 dev_err(dev->adev->dev, "no vmid pasid mapping supported\n");
814 return -EOPNOTSUPP;
815 }
816
817 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
818 * ATC_VMID15_PASID_MAPPING
819 * to check which VMID the current process is mapped to.
820 */
821
822 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
823 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
824 (dev->adev, vmid, &queried_pasid);
825
826 if (status && queried_pasid == p->pasid) {
827 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
828 vmid, p->pasid);
829 break;
830 }
831 }
832
833 if (vmid > last_vmid_to_scan) {
834 dev_err(dev->adev->dev, "Didn't find vmid for pasid 0x%x\n", p->pasid);
835 return -EFAULT;
836 }
837
838 /* taking the VMID for that process on the safe way using PDD */
839 pdd = kfd_get_process_device_data(dev, p);
840 if (!pdd)
841 return -EFAULT;
842
843 reg_gfx_index.bits.sh_broadcast_writes = 1;
844 reg_gfx_index.bits.se_broadcast_writes = 1;
845 reg_gfx_index.bits.instance_broadcast_writes = 1;
846 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
847 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
848 reg_sq_cmd.bits.vm_id = vmid;
849
850 for_each_inst(xcc_id, xcc_mask)
851 dev->kfd2kgd->wave_control_execute(
852 dev->adev, reg_gfx_index.u32All,
853 reg_sq_cmd.u32All, xcc_id);
854
855 return 0;
856}
857
858/* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
859 * to avoid asynchronized access
860 */
861static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
862 struct qcm_process_device *qpd,
863 struct queue *q)
864{
865 int retval;
866 struct mqd_manager *mqd_mgr;
867
868 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
869 q->properties.type)];
870
871 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
872 deallocate_hqd(dqm, q);
873 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
874 deallocate_sdma_queue(dqm, q);
875 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
876 deallocate_sdma_queue(dqm, q);
877 else {
878 pr_debug("q->properties.type %d is invalid\n",
879 q->properties.type);
880 return -EINVAL;
881 }
882 dqm->total_queue_count--;
883
884 deallocate_doorbell(qpd, q);
885
886 if (!dqm->sched_running) {
887 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
888 return 0;
889 }
890
891 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
892 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
893 KFD_UNMAP_LATENCY_MS,
894 q->pipe, q->queue);
895 if (retval == -ETIME)
896 qpd->reset_wavefronts = true;
897
898 list_del(&q->list);
899 if (list_empty(&qpd->queues_list)) {
900 if (qpd->reset_wavefronts) {
901 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
902 dqm->dev);
903 /* dbgdev_wave_reset_wavefronts has to be called before
904 * deallocate_vmid(), i.e. when vmid is still in use.
905 */
906 dbgdev_wave_reset_wavefronts(dqm->dev,
907 qpd->pqm->process);
908 qpd->reset_wavefronts = false;
909 }
910
911 deallocate_vmid(dqm, qpd, q);
912 }
913 qpd->queue_count--;
914 if (q->properties.is_active)
915 decrement_queue_count(dqm, qpd, q);
916
917 return retval;
918}
919
920static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
921 struct qcm_process_device *qpd,
922 struct queue *q)
923{
924 int retval;
925 uint64_t sdma_val = 0;
926 struct device *dev = dqm->dev->adev->dev;
927 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
928 struct mqd_manager *mqd_mgr =
929 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
930
931 /* Get the SDMA queue stats */
932 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
933 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
934 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
935 &sdma_val);
936 if (retval)
937 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n",
938 q->properties.queue_id);
939 }
940
941 dqm_lock(dqm);
942 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
943 if (!retval)
944 pdd->sdma_past_activity_counter += sdma_val;
945 dqm_unlock(dqm);
946
947 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
948
949 return retval;
950}
951
952static int update_queue(struct device_queue_manager *dqm, struct queue *q,
953 struct mqd_update_info *minfo)
954{
955 int retval = 0;
956 struct device *dev = dqm->dev->adev->dev;
957 struct mqd_manager *mqd_mgr;
958 struct kfd_process_device *pdd;
959 bool prev_active = false;
960
961 dqm_lock(dqm);
962 pdd = kfd_get_process_device_data(q->device, q->process);
963 if (!pdd) {
964 retval = -ENODEV;
965 goto out_unlock;
966 }
967 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
968 q->properties.type)];
969
970 /* Save previous activity state for counters */
971 prev_active = q->properties.is_active;
972
973 /* Make sure the queue is unmapped before updating the MQD */
974 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
975 if (!dqm->dev->kfd->shared_resources.enable_mes)
976 retval = unmap_queues_cpsch(dqm,
977 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
978 else if (prev_active)
979 retval = remove_queue_mes(dqm, q, &pdd->qpd);
980
981 /* queue is reset so inaccessable */
982 if (pdd->has_reset_queue) {
983 retval = -EACCES;
984 goto out_unlock;
985 }
986
987 if (retval) {
988 dev_err(dev, "unmap queue failed\n");
989 goto out_unlock;
990 }
991 } else if (prev_active &&
992 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
993 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
994 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
995
996 if (!dqm->sched_running) {
997 WARN_ONCE(1, "Update non-HWS queue while stopped\n");
998 goto out_unlock;
999 }
1000
1001 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
1002 (dqm->dev->kfd->cwsr_enabled ?
1003 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
1004 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
1005 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
1006 if (retval) {
1007 dev_err(dev, "destroy mqd failed\n");
1008 goto out_unlock;
1009 }
1010 }
1011
1012 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo);
1013
1014 /*
1015 * check active state vs. the previous state and modify
1016 * counter accordingly. map_queues_cpsch uses the
1017 * dqm->active_queue_count to determine whether a new runlist must be
1018 * uploaded.
1019 */
1020 if (q->properties.is_active && !prev_active) {
1021 increment_queue_count(dqm, &pdd->qpd, q);
1022 } else if (!q->properties.is_active && prev_active) {
1023 decrement_queue_count(dqm, &pdd->qpd, q);
1024 } else if (q->gws && !q->properties.is_gws) {
1025 if (q->properties.is_active) {
1026 dqm->gws_queue_count++;
1027 pdd->qpd.mapped_gws_queue = true;
1028 }
1029 q->properties.is_gws = true;
1030 } else if (!q->gws && q->properties.is_gws) {
1031 if (q->properties.is_active) {
1032 dqm->gws_queue_count--;
1033 pdd->qpd.mapped_gws_queue = false;
1034 }
1035 q->properties.is_gws = false;
1036 }
1037
1038 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
1039 if (!dqm->dev->kfd->shared_resources.enable_mes)
1040 retval = map_queues_cpsch(dqm);
1041 else if (q->properties.is_active)
1042 retval = add_queue_mes(dqm, q, &pdd->qpd);
1043 } else if (q->properties.is_active &&
1044 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
1045 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1046 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
1047 if (WARN(q->process->mm != current->mm,
1048 "should only run in user thread"))
1049 retval = -EFAULT;
1050 else
1051 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
1052 q->pipe, q->queue,
1053 &q->properties, current->mm);
1054 }
1055
1056out_unlock:
1057 dqm_unlock(dqm);
1058 return retval;
1059}
1060
1061/* suspend_single_queue does not lock the dqm like the
1062 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should
1063 * lock the dqm before calling, and unlock after calling.
1064 *
1065 * The reason we don't lock the dqm is because this function may be
1066 * called on multiple queues in a loop, so rather than locking/unlocking
1067 * multiple times, we will just keep the dqm locked for all of the calls.
1068 */
1069static int suspend_single_queue(struct device_queue_manager *dqm,
1070 struct kfd_process_device *pdd,
1071 struct queue *q)
1072{
1073 bool is_new;
1074
1075 if (q->properties.is_suspended)
1076 return 0;
1077
1078 pr_debug("Suspending PASID %u queue [%i]\n",
1079 pdd->process->pasid,
1080 q->properties.queue_id);
1081
1082 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW);
1083
1084 if (is_new || q->properties.is_being_destroyed) {
1085 pr_debug("Suspend: skip %s queue id %i\n",
1086 is_new ? "new" : "destroyed",
1087 q->properties.queue_id);
1088 return -EBUSY;
1089 }
1090
1091 q->properties.is_suspended = true;
1092 if (q->properties.is_active) {
1093 if (dqm->dev->kfd->shared_resources.enable_mes) {
1094 int r = remove_queue_mes(dqm, q, &pdd->qpd);
1095
1096 if (r)
1097 return r;
1098 }
1099
1100 decrement_queue_count(dqm, &pdd->qpd, q);
1101 q->properties.is_active = false;
1102 }
1103
1104 return 0;
1105}
1106
1107/* resume_single_queue does not lock the dqm like the functions
1108 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should
1109 * lock the dqm before calling, and unlock after calling.
1110 *
1111 * The reason we don't lock the dqm is because this function may be
1112 * called on multiple queues in a loop, so rather than locking/unlocking
1113 * multiple times, we will just keep the dqm locked for all of the calls.
1114 */
1115static int resume_single_queue(struct device_queue_manager *dqm,
1116 struct qcm_process_device *qpd,
1117 struct queue *q)
1118{
1119 struct kfd_process_device *pdd;
1120
1121 if (!q->properties.is_suspended)
1122 return 0;
1123
1124 pdd = qpd_to_pdd(qpd);
1125
1126 pr_debug("Restoring from suspend PASID %u queue [%i]\n",
1127 pdd->process->pasid,
1128 q->properties.queue_id);
1129
1130 q->properties.is_suspended = false;
1131
1132 if (QUEUE_IS_ACTIVE(q->properties)) {
1133 if (dqm->dev->kfd->shared_resources.enable_mes) {
1134 int r = add_queue_mes(dqm, q, &pdd->qpd);
1135
1136 if (r)
1137 return r;
1138 }
1139
1140 q->properties.is_active = true;
1141 increment_queue_count(dqm, qpd, q);
1142 }
1143
1144 return 0;
1145}
1146
1147static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
1148 struct qcm_process_device *qpd)
1149{
1150 struct queue *q;
1151 struct mqd_manager *mqd_mgr;
1152 struct kfd_process_device *pdd;
1153 int retval, ret = 0;
1154
1155 dqm_lock(dqm);
1156 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1157 goto out;
1158
1159 pdd = qpd_to_pdd(qpd);
1160 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1161 pdd->process->pasid);
1162
1163 pdd->last_evict_timestamp = get_jiffies_64();
1164 /* Mark all queues as evicted. Deactivate all active queues on
1165 * the qpd.
1166 */
1167 list_for_each_entry(q, &qpd->queues_list, list) {
1168 q->properties.is_evicted = true;
1169 if (!q->properties.is_active)
1170 continue;
1171
1172 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1173 q->properties.type)];
1174 q->properties.is_active = false;
1175 decrement_queue_count(dqm, qpd, q);
1176
1177 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
1178 continue;
1179
1180 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
1181 (dqm->dev->kfd->cwsr_enabled ?
1182 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
1183 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
1184 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
1185 if (retval && !ret)
1186 /* Return the first error, but keep going to
1187 * maintain a consistent eviction state
1188 */
1189 ret = retval;
1190 }
1191
1192out:
1193 dqm_unlock(dqm);
1194 return ret;
1195}
1196
1197static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
1198 struct qcm_process_device *qpd)
1199{
1200 struct queue *q;
1201 struct device *dev = dqm->dev->adev->dev;
1202 struct kfd_process_device *pdd;
1203 int retval = 0;
1204
1205 dqm_lock(dqm);
1206 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1207 goto out;
1208
1209 pdd = qpd_to_pdd(qpd);
1210
1211 /* The debugger creates processes that temporarily have not acquired
1212 * all VMs for all devices and has no VMs itself.
1213 * Skip queue eviction on process eviction.
1214 */
1215 if (!pdd->drm_priv)
1216 goto out;
1217
1218 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1219 pdd->process->pasid);
1220
1221 /* Mark all queues as evicted. Deactivate all active queues on
1222 * the qpd.
1223 */
1224 list_for_each_entry(q, &qpd->queues_list, list) {
1225 q->properties.is_evicted = true;
1226 if (!q->properties.is_active)
1227 continue;
1228
1229 q->properties.is_active = false;
1230 decrement_queue_count(dqm, qpd, q);
1231
1232 if (dqm->dev->kfd->shared_resources.enable_mes) {
1233 retval = remove_queue_mes(dqm, q, qpd);
1234 if (retval) {
1235 dev_err(dev, "Failed to evict queue %d\n",
1236 q->properties.queue_id);
1237 goto out;
1238 }
1239 }
1240 }
1241 pdd->last_evict_timestamp = get_jiffies_64();
1242 if (!dqm->dev->kfd->shared_resources.enable_mes)
1243 retval = execute_queues_cpsch(dqm,
1244 qpd->is_debug ?
1245 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
1246 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1247 USE_DEFAULT_GRACE_PERIOD);
1248
1249out:
1250 dqm_unlock(dqm);
1251 return retval;
1252}
1253
1254static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
1255 struct qcm_process_device *qpd)
1256{
1257 struct mm_struct *mm = NULL;
1258 struct queue *q;
1259 struct mqd_manager *mqd_mgr;
1260 struct kfd_process_device *pdd;
1261 uint64_t pd_base;
1262 uint64_t eviction_duration;
1263 int retval, ret = 0;
1264
1265 pdd = qpd_to_pdd(qpd);
1266 /* Retrieve PD base */
1267 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1268
1269 dqm_lock(dqm);
1270 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1271 goto out;
1272 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1273 qpd->evicted--;
1274 goto out;
1275 }
1276
1277 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1278 pdd->process->pasid);
1279
1280 /* Update PD Base in QPD */
1281 qpd->page_table_base = pd_base;
1282 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1283
1284 if (!list_empty(&qpd->queues_list)) {
1285 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
1286 dqm->dev->adev,
1287 qpd->vmid,
1288 qpd->page_table_base);
1289 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
1290 }
1291
1292 /* Take a safe reference to the mm_struct, which may otherwise
1293 * disappear even while the kfd_process is still referenced.
1294 */
1295 mm = get_task_mm(pdd->process->lead_thread);
1296 if (!mm) {
1297 ret = -EFAULT;
1298 goto out;
1299 }
1300
1301 /* Remove the eviction flags. Activate queues that are not
1302 * inactive for other reasons.
1303 */
1304 list_for_each_entry(q, &qpd->queues_list, list) {
1305 q->properties.is_evicted = false;
1306 if (!QUEUE_IS_ACTIVE(q->properties))
1307 continue;
1308
1309 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1310 q->properties.type)];
1311 q->properties.is_active = true;
1312 increment_queue_count(dqm, qpd, q);
1313
1314 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
1315 continue;
1316
1317 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
1318 q->queue, &q->properties, mm);
1319 if (retval && !ret)
1320 /* Return the first error, but keep going to
1321 * maintain a consistent eviction state
1322 */
1323 ret = retval;
1324 }
1325 qpd->evicted = 0;
1326 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1327 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1328out:
1329 if (mm)
1330 mmput(mm);
1331 dqm_unlock(dqm);
1332 return ret;
1333}
1334
1335static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
1336 struct qcm_process_device *qpd)
1337{
1338 struct queue *q;
1339 struct device *dev = dqm->dev->adev->dev;
1340 struct kfd_process_device *pdd;
1341 uint64_t eviction_duration;
1342 int retval = 0;
1343
1344 pdd = qpd_to_pdd(qpd);
1345
1346 dqm_lock(dqm);
1347 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1348 goto out;
1349 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1350 qpd->evicted--;
1351 goto out;
1352 }
1353
1354 /* The debugger creates processes that temporarily have not acquired
1355 * all VMs for all devices and has no VMs itself.
1356 * Skip queue restore on process restore.
1357 */
1358 if (!pdd->drm_priv)
1359 goto vm_not_acquired;
1360
1361 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1362 pdd->process->pasid);
1363
1364 /* Update PD Base in QPD */
1365 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1366 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base);
1367
1368 /* activate all active queues on the qpd */
1369 list_for_each_entry(q, &qpd->queues_list, list) {
1370 q->properties.is_evicted = false;
1371 if (!QUEUE_IS_ACTIVE(q->properties))
1372 continue;
1373
1374 q->properties.is_active = true;
1375 increment_queue_count(dqm, &pdd->qpd, q);
1376
1377 if (dqm->dev->kfd->shared_resources.enable_mes) {
1378 retval = add_queue_mes(dqm, q, qpd);
1379 if (retval) {
1380 dev_err(dev, "Failed to restore queue %d\n",
1381 q->properties.queue_id);
1382 goto out;
1383 }
1384 }
1385 }
1386 if (!dqm->dev->kfd->shared_resources.enable_mes)
1387 retval = execute_queues_cpsch(dqm,
1388 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1389 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1390 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1391vm_not_acquired:
1392 qpd->evicted = 0;
1393out:
1394 dqm_unlock(dqm);
1395 return retval;
1396}
1397
1398static int register_process(struct device_queue_manager *dqm,
1399 struct qcm_process_device *qpd)
1400{
1401 struct device_process_node *n;
1402 struct kfd_process_device *pdd;
1403 uint64_t pd_base;
1404 int retval;
1405
1406 n = kzalloc(sizeof(*n), GFP_KERNEL);
1407 if (!n)
1408 return -ENOMEM;
1409
1410 n->qpd = qpd;
1411
1412 pdd = qpd_to_pdd(qpd);
1413 /* Retrieve PD base */
1414 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1415
1416 dqm_lock(dqm);
1417 list_add(&n->list, &dqm->queues);
1418
1419 /* Update PD Base in QPD */
1420 qpd->page_table_base = pd_base;
1421 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1422
1423 retval = dqm->asic_ops.update_qpd(dqm, qpd);
1424
1425 dqm->processes_count++;
1426
1427 dqm_unlock(dqm);
1428
1429 /* Outside the DQM lock because under the DQM lock we can't do
1430 * reclaim or take other locks that others hold while reclaiming.
1431 */
1432 kfd_inc_compute_active(dqm->dev);
1433
1434 return retval;
1435}
1436
1437static int unregister_process(struct device_queue_manager *dqm,
1438 struct qcm_process_device *qpd)
1439{
1440 int retval;
1441 struct device_process_node *cur, *next;
1442
1443 pr_debug("qpd->queues_list is %s\n",
1444 list_empty(&qpd->queues_list) ? "empty" : "not empty");
1445
1446 retval = 0;
1447 dqm_lock(dqm);
1448
1449 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
1450 if (qpd == cur->qpd) {
1451 list_del(&cur->list);
1452 kfree(cur);
1453 dqm->processes_count--;
1454 goto out;
1455 }
1456 }
1457 /* qpd not found in dqm list */
1458 retval = 1;
1459out:
1460 dqm_unlock(dqm);
1461
1462 /* Outside the DQM lock because under the DQM lock we can't do
1463 * reclaim or take other locks that others hold while reclaiming.
1464 */
1465 if (!retval)
1466 kfd_dec_compute_active(dqm->dev);
1467
1468 return retval;
1469}
1470
1471static int
1472set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid,
1473 unsigned int vmid)
1474{
1475 uint32_t xcc_mask = dqm->dev->xcc_mask;
1476 int xcc_id, ret;
1477
1478 for_each_inst(xcc_id, xcc_mask) {
1479 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
1480 dqm->dev->adev, pasid, vmid, xcc_id);
1481 if (ret)
1482 break;
1483 }
1484
1485 return ret;
1486}
1487
1488static void init_interrupts(struct device_queue_manager *dqm)
1489{
1490 uint32_t xcc_mask = dqm->dev->xcc_mask;
1491 unsigned int i, xcc_id;
1492
1493 for_each_inst(xcc_id, xcc_mask) {
1494 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) {
1495 if (is_pipe_enabled(dqm, 0, i)) {
1496 dqm->dev->kfd2kgd->init_interrupts(
1497 dqm->dev->adev, i, xcc_id);
1498 }
1499 }
1500 }
1501}
1502
1503static int initialize_nocpsch(struct device_queue_manager *dqm)
1504{
1505 int pipe, queue;
1506
1507 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1508
1509 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
1510 sizeof(unsigned int), GFP_KERNEL);
1511 if (!dqm->allocated_queues)
1512 return -ENOMEM;
1513
1514 mutex_init(&dqm->lock_hidden);
1515 INIT_LIST_HEAD(&dqm->queues);
1516 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0;
1517 dqm->active_cp_queue_count = 0;
1518 dqm->gws_queue_count = 0;
1519
1520 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1521 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1522
1523 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
1524 if (test_bit(pipe_offset + queue,
1525 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1526 dqm->allocated_queues[pipe] |= 1 << queue;
1527 }
1528
1529 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
1530
1531 init_sdma_bitmaps(dqm);
1532
1533 return 0;
1534}
1535
1536static void uninitialize(struct device_queue_manager *dqm)
1537{
1538 int i;
1539
1540 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0);
1541
1542 kfree(dqm->allocated_queues);
1543 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
1544 kfree(dqm->mqd_mgrs[i]);
1545 mutex_destroy(&dqm->lock_hidden);
1546}
1547
1548static int start_nocpsch(struct device_queue_manager *dqm)
1549{
1550 int r = 0;
1551
1552 pr_info("SW scheduler is used");
1553 init_interrupts(dqm);
1554
1555 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1556 r = pm_init(&dqm->packet_mgr, dqm);
1557 if (!r)
1558 dqm->sched_running = true;
1559
1560 return r;
1561}
1562
1563static int stop_nocpsch(struct device_queue_manager *dqm)
1564{
1565 dqm_lock(dqm);
1566 if (!dqm->sched_running) {
1567 dqm_unlock(dqm);
1568 return 0;
1569 }
1570
1571 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1572 pm_uninit(&dqm->packet_mgr);
1573 dqm->sched_running = false;
1574 dqm_unlock(dqm);
1575
1576 return 0;
1577}
1578
1579static int allocate_sdma_queue(struct device_queue_manager *dqm,
1580 struct queue *q, const uint32_t *restore_sdma_id)
1581{
1582 struct device *dev = dqm->dev->adev->dev;
1583 int bit;
1584
1585 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1586 if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1587 dev_err(dev, "No more SDMA queue to allocate\n");
1588 return -ENOMEM;
1589 }
1590
1591 if (restore_sdma_id) {
1592 /* Re-use existing sdma_id */
1593 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) {
1594 dev_err(dev, "SDMA queue already in use\n");
1595 return -EBUSY;
1596 }
1597 clear_bit(*restore_sdma_id, dqm->sdma_bitmap);
1598 q->sdma_id = *restore_sdma_id;
1599 } else {
1600 /* Find first available sdma_id */
1601 bit = find_first_bit(dqm->sdma_bitmap,
1602 get_num_sdma_queues(dqm));
1603 clear_bit(bit, dqm->sdma_bitmap);
1604 q->sdma_id = bit;
1605 }
1606
1607 q->properties.sdma_engine_id =
1608 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev);
1609 q->properties.sdma_queue_id = q->sdma_id /
1610 kfd_get_num_sdma_engines(dqm->dev);
1611 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1612 if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1613 dev_err(dev, "No more XGMI SDMA queue to allocate\n");
1614 return -ENOMEM;
1615 }
1616 if (restore_sdma_id) {
1617 /* Re-use existing sdma_id */
1618 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) {
1619 dev_err(dev, "SDMA queue already in use\n");
1620 return -EBUSY;
1621 }
1622 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap);
1623 q->sdma_id = *restore_sdma_id;
1624 } else {
1625 bit = find_first_bit(dqm->xgmi_sdma_bitmap,
1626 get_num_xgmi_sdma_queues(dqm));
1627 clear_bit(bit, dqm->xgmi_sdma_bitmap);
1628 q->sdma_id = bit;
1629 }
1630 /* sdma_engine_id is sdma id including
1631 * both PCIe-optimized SDMAs and XGMI-
1632 * optimized SDMAs. The calculation below
1633 * assumes the first N engines are always
1634 * PCIe-optimized ones
1635 */
1636 q->properties.sdma_engine_id =
1637 kfd_get_num_sdma_engines(dqm->dev) +
1638 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev);
1639 q->properties.sdma_queue_id = q->sdma_id /
1640 kfd_get_num_xgmi_sdma_engines(dqm->dev);
1641 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) {
1642 int i, num_queues, num_engines, eng_offset = 0, start_engine;
1643 bool free_bit_found = false, is_xgmi = false;
1644
1645 if (q->properties.sdma_engine_id < kfd_get_num_sdma_engines(dqm->dev)) {
1646 num_queues = get_num_sdma_queues(dqm);
1647 num_engines = kfd_get_num_sdma_engines(dqm->dev);
1648 q->properties.type = KFD_QUEUE_TYPE_SDMA;
1649 } else {
1650 num_queues = get_num_xgmi_sdma_queues(dqm);
1651 num_engines = kfd_get_num_xgmi_sdma_engines(dqm->dev);
1652 eng_offset = kfd_get_num_sdma_engines(dqm->dev);
1653 q->properties.type = KFD_QUEUE_TYPE_SDMA_XGMI;
1654 is_xgmi = true;
1655 }
1656
1657 /* Scan available bit based on target engine ID. */
1658 start_engine = q->properties.sdma_engine_id - eng_offset;
1659 for (i = start_engine; i < num_queues; i += num_engines) {
1660
1661 if (!test_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap))
1662 continue;
1663
1664 clear_bit(i, is_xgmi ? dqm->xgmi_sdma_bitmap : dqm->sdma_bitmap);
1665 q->sdma_id = i;
1666 q->properties.sdma_queue_id = q->sdma_id / num_engines;
1667 free_bit_found = true;
1668 break;
1669 }
1670
1671 if (!free_bit_found) {
1672 dev_err(dev, "No more SDMA queue to allocate for target ID %i\n",
1673 q->properties.sdma_engine_id);
1674 return -ENOMEM;
1675 }
1676 }
1677
1678 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
1679 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
1680
1681 return 0;
1682}
1683
1684static void deallocate_sdma_queue(struct device_queue_manager *dqm,
1685 struct queue *q)
1686{
1687 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1688 if (q->sdma_id >= get_num_sdma_queues(dqm))
1689 return;
1690 set_bit(q->sdma_id, dqm->sdma_bitmap);
1691 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1692 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1693 return;
1694 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap);
1695 }
1696}
1697
1698/*
1699 * Device Queue Manager implementation for cp scheduler
1700 */
1701
1702static int set_sched_resources(struct device_queue_manager *dqm)
1703{
1704 int i, mec;
1705 struct scheduling_resources res;
1706 struct device *dev = dqm->dev->adev->dev;
1707
1708 res.vmid_mask = dqm->dev->compute_vmid_bitmap;
1709
1710 res.queue_mask = 0;
1711 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) {
1712 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe)
1713 / dqm->dev->kfd->shared_resources.num_pipe_per_mec;
1714
1715 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1716 continue;
1717
1718 /* only acquire queues from the first MEC */
1719 if (mec > 0)
1720 continue;
1721
1722 /* This situation may be hit in the future if a new HW
1723 * generation exposes more than 64 queues. If so, the
1724 * definition of res.queue_mask needs updating
1725 */
1726 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1727 dev_err(dev, "Invalid queue enabled by amdgpu: %d\n", i);
1728 break;
1729 }
1730
1731 res.queue_mask |= 1ull
1732 << amdgpu_queue_mask_bit_to_set_resource_bit(
1733 dqm->dev->adev, i);
1734 }
1735 res.gws_mask = ~0ull;
1736 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1737
1738 pr_debug("Scheduling resources:\n"
1739 "vmid mask: 0x%8X\n"
1740 "queue mask: 0x%8llX\n",
1741 res.vmid_mask, res.queue_mask);
1742
1743 return pm_send_set_resources(&dqm->packet_mgr, &res);
1744}
1745
1746static int initialize_cpsch(struct device_queue_manager *dqm)
1747{
1748 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1749
1750 mutex_init(&dqm->lock_hidden);
1751 INIT_LIST_HEAD(&dqm->queues);
1752 dqm->active_queue_count = dqm->processes_count = 0;
1753 dqm->active_cp_queue_count = 0;
1754 dqm->gws_queue_count = 0;
1755 dqm->active_runlist = false;
1756 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1757 dqm->trap_debug_vmid = 0;
1758
1759 init_sdma_bitmaps(dqm);
1760
1761 if (dqm->dev->kfd2kgd->get_iq_wait_times)
1762 dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev,
1763 &dqm->wait_times,
1764 ffs(dqm->dev->xcc_mask) - 1);
1765 return 0;
1766}
1767
1768/* halt_cpsch:
1769 * Unmap queues so the schedule doesn't continue remaining jobs in the queue.
1770 * Then set dqm->sched_halt so queues don't map to runlist until unhalt_cpsch
1771 * is called.
1772 */
1773static int halt_cpsch(struct device_queue_manager *dqm)
1774{
1775 int ret = 0;
1776
1777 dqm_lock(dqm);
1778 if (!dqm->sched_running) {
1779 dqm_unlock(dqm);
1780 return 0;
1781 }
1782
1783 WARN_ONCE(dqm->sched_halt, "Scheduling is already on halt\n");
1784
1785 if (!dqm->is_hws_hang) {
1786 if (!dqm->dev->kfd->shared_resources.enable_mes)
1787 ret = unmap_queues_cpsch(dqm,
1788 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
1789 USE_DEFAULT_GRACE_PERIOD, false);
1790 else
1791 ret = remove_all_kfd_queues_mes(dqm);
1792 }
1793 dqm->sched_halt = true;
1794 dqm_unlock(dqm);
1795
1796 return ret;
1797}
1798
1799/* unhalt_cpsch
1800 * Unset dqm->sched_halt and map queues back to runlist
1801 */
1802static int unhalt_cpsch(struct device_queue_manager *dqm)
1803{
1804 int ret = 0;
1805
1806 dqm_lock(dqm);
1807 if (!dqm->sched_running || !dqm->sched_halt) {
1808 WARN_ONCE(!dqm->sched_halt, "Scheduling is not on halt.\n");
1809 dqm_unlock(dqm);
1810 return 0;
1811 }
1812 dqm->sched_halt = false;
1813 if (!dqm->dev->kfd->shared_resources.enable_mes)
1814 ret = execute_queues_cpsch(dqm,
1815 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
1816 0, USE_DEFAULT_GRACE_PERIOD);
1817 else
1818 ret = add_all_kfd_queues_mes(dqm);
1819
1820 dqm_unlock(dqm);
1821
1822 return ret;
1823}
1824
1825static int start_cpsch(struct device_queue_manager *dqm)
1826{
1827 struct device *dev = dqm->dev->adev->dev;
1828 int retval, num_hw_queue_slots;
1829
1830 retval = 0;
1831
1832 dqm_lock(dqm);
1833
1834 if (!dqm->dev->kfd->shared_resources.enable_mes) {
1835 retval = pm_init(&dqm->packet_mgr, dqm);
1836 if (retval)
1837 goto fail_packet_manager_init;
1838
1839 retval = set_sched_resources(dqm);
1840 if (retval)
1841 goto fail_set_sched_resources;
1842 }
1843 pr_debug("Allocating fence memory\n");
1844
1845 /* allocate fence memory on the gart */
1846 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1847 &dqm->fence_mem);
1848
1849 if (retval)
1850 goto fail_allocate_vidmem;
1851
1852 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr;
1853 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1854
1855 init_interrupts(dqm);
1856
1857 /* clear hang status when driver try to start the hw scheduler */
1858 dqm->sched_running = true;
1859
1860 if (!dqm->dev->kfd->shared_resources.enable_mes)
1861 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1862
1863 /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */
1864 if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu &&
1865 (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) {
1866 uint32_t reg_offset = 0;
1867 uint32_t grace_period = 1;
1868
1869 retval = pm_update_grace_period(&dqm->packet_mgr,
1870 grace_period);
1871 if (retval)
1872 dev_err(dev, "Setting grace timeout failed\n");
1873 else if (dqm->dev->kfd2kgd->build_grace_period_packet_info)
1874 /* Update dqm->wait_times maintained in software */
1875 dqm->dev->kfd2kgd->build_grace_period_packet_info(
1876 dqm->dev->adev, dqm->wait_times,
1877 grace_period, ®_offset,
1878 &dqm->wait_times);
1879 }
1880
1881 /* setup per-queue reset detection buffer */
1882 num_hw_queue_slots = dqm->dev->kfd->shared_resources.num_queue_per_pipe *
1883 dqm->dev->kfd->shared_resources.num_pipe_per_mec *
1884 NUM_XCC(dqm->dev->xcc_mask);
1885
1886 dqm->detect_hang_info_size = num_hw_queue_slots * sizeof(struct dqm_detect_hang_info);
1887 dqm->detect_hang_info = kzalloc(dqm->detect_hang_info_size, GFP_KERNEL);
1888
1889 if (!dqm->detect_hang_info) {
1890 retval = -ENOMEM;
1891 goto fail_detect_hang_buffer;
1892 }
1893
1894 dqm_unlock(dqm);
1895
1896 return 0;
1897fail_detect_hang_buffer:
1898 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1899fail_allocate_vidmem:
1900fail_set_sched_resources:
1901 if (!dqm->dev->kfd->shared_resources.enable_mes)
1902 pm_uninit(&dqm->packet_mgr);
1903fail_packet_manager_init:
1904 dqm_unlock(dqm);
1905 return retval;
1906}
1907
1908static int stop_cpsch(struct device_queue_manager *dqm)
1909{
1910 dqm_lock(dqm);
1911 if (!dqm->sched_running) {
1912 dqm_unlock(dqm);
1913 return 0;
1914 }
1915
1916 if (!dqm->dev->kfd->shared_resources.enable_mes)
1917 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
1918 else
1919 remove_all_kfd_queues_mes(dqm);
1920
1921 dqm->sched_running = false;
1922
1923 if (!dqm->dev->kfd->shared_resources.enable_mes)
1924 pm_release_ib(&dqm->packet_mgr);
1925
1926 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1927 if (!dqm->dev->kfd->shared_resources.enable_mes)
1928 pm_uninit(&dqm->packet_mgr);
1929 kfree(dqm->detect_hang_info);
1930 dqm->detect_hang_info = NULL;
1931 dqm_unlock(dqm);
1932
1933 return 0;
1934}
1935
1936static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1937 struct kernel_queue *kq,
1938 struct qcm_process_device *qpd)
1939{
1940 dqm_lock(dqm);
1941 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1942 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1943 dqm->total_queue_count);
1944 dqm_unlock(dqm);
1945 return -EPERM;
1946 }
1947
1948 /*
1949 * Unconditionally increment this counter, regardless of the queue's
1950 * type or whether the queue is active.
1951 */
1952 dqm->total_queue_count++;
1953 pr_debug("Total of %d queues are accountable so far\n",
1954 dqm->total_queue_count);
1955
1956 list_add(&kq->list, &qpd->priv_queue_list);
1957 increment_queue_count(dqm, qpd, kq->queue);
1958 qpd->is_debug = true;
1959 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1960 USE_DEFAULT_GRACE_PERIOD);
1961 dqm_unlock(dqm);
1962
1963 return 0;
1964}
1965
1966static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1967 struct kernel_queue *kq,
1968 struct qcm_process_device *qpd)
1969{
1970 dqm_lock(dqm);
1971 list_del(&kq->list);
1972 decrement_queue_count(dqm, qpd, kq->queue);
1973 qpd->is_debug = false;
1974 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
1975 USE_DEFAULT_GRACE_PERIOD);
1976 /*
1977 * Unconditionally decrement this counter, regardless of the queue's
1978 * type.
1979 */
1980 dqm->total_queue_count--;
1981 pr_debug("Total of %d queues are accountable so far\n",
1982 dqm->total_queue_count);
1983 dqm_unlock(dqm);
1984}
1985
1986static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1987 struct qcm_process_device *qpd,
1988 const struct kfd_criu_queue_priv_data *qd,
1989 const void *restore_mqd, const void *restore_ctl_stack)
1990{
1991 int retval;
1992 struct mqd_manager *mqd_mgr;
1993
1994 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1995 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1996 dqm->total_queue_count);
1997 retval = -EPERM;
1998 goto out;
1999 }
2000
2001 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
2002 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI ||
2003 q->properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) {
2004 dqm_lock(dqm);
2005 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
2006 dqm_unlock(dqm);
2007 if (retval)
2008 goto out;
2009 }
2010
2011 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
2012 if (retval)
2013 goto out_deallocate_sdma_queue;
2014
2015 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2016 q->properties.type)];
2017
2018 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
2019 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
2020 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
2021 q->properties.tba_addr = qpd->tba_addr;
2022 q->properties.tma_addr = qpd->tma_addr;
2023 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
2024 if (!q->mqd_mem_obj) {
2025 retval = -ENOMEM;
2026 goto out_deallocate_doorbell;
2027 }
2028
2029 dqm_lock(dqm);
2030 /*
2031 * Eviction state logic: mark all queues as evicted, even ones
2032 * not currently active. Restoring inactive queues later only
2033 * updates the is_evicted flag but is a no-op otherwise.
2034 */
2035 q->properties.is_evicted = !!qpd->evicted;
2036 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled &&
2037 kfd_dbg_has_cwsr_workaround(q->device);
2038
2039 if (qd)
2040 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
2041 &q->properties, restore_mqd, restore_ctl_stack,
2042 qd->ctl_stack_size);
2043 else
2044 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
2045 &q->gart_mqd_addr, &q->properties);
2046
2047 list_add(&q->list, &qpd->queues_list);
2048 qpd->queue_count++;
2049
2050 if (q->properties.is_active) {
2051 increment_queue_count(dqm, qpd, q);
2052
2053 if (!dqm->dev->kfd->shared_resources.enable_mes)
2054 retval = execute_queues_cpsch(dqm,
2055 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
2056 else
2057 retval = add_queue_mes(dqm, q, qpd);
2058 if (retval)
2059 goto cleanup_queue;
2060 }
2061
2062 /*
2063 * Unconditionally increment this counter, regardless of the queue's
2064 * type or whether the queue is active.
2065 */
2066 dqm->total_queue_count++;
2067
2068 pr_debug("Total of %d queues are accountable so far\n",
2069 dqm->total_queue_count);
2070
2071 dqm_unlock(dqm);
2072 return retval;
2073
2074cleanup_queue:
2075 qpd->queue_count--;
2076 list_del(&q->list);
2077 if (q->properties.is_active)
2078 decrement_queue_count(dqm, qpd, q);
2079 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2080 dqm_unlock(dqm);
2081out_deallocate_doorbell:
2082 deallocate_doorbell(qpd, q);
2083out_deallocate_sdma_queue:
2084 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
2085 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
2086 dqm_lock(dqm);
2087 deallocate_sdma_queue(dqm, q);
2088 dqm_unlock(dqm);
2089 }
2090out:
2091 return retval;
2092}
2093
2094int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm,
2095 uint64_t fence_value,
2096 unsigned int timeout_ms)
2097{
2098 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
2099 struct device *dev = dqm->dev->adev->dev;
2100 uint64_t *fence_addr = dqm->fence_addr;
2101
2102 while (*fence_addr != fence_value) {
2103 /* Fatal err detected, this response won't come */
2104 if (amdgpu_amdkfd_is_fed(dqm->dev->adev))
2105 return -EIO;
2106
2107 if (time_after(jiffies, end_jiffies)) {
2108 dev_err(dev, "qcm fence wait loop timeout expired\n");
2109 /* In HWS case, this is used to halt the driver thread
2110 * in order not to mess up CP states before doing
2111 * scandumps for FW debugging.
2112 */
2113 while (halt_if_hws_hang)
2114 schedule();
2115
2116 return -ETIME;
2117 }
2118 schedule();
2119 }
2120
2121 return 0;
2122}
2123
2124/* dqm->lock mutex has to be locked before calling this function */
2125static int map_queues_cpsch(struct device_queue_manager *dqm)
2126{
2127 struct device *dev = dqm->dev->adev->dev;
2128 int retval;
2129
2130 if (!dqm->sched_running || dqm->sched_halt)
2131 return 0;
2132 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0)
2133 return 0;
2134 if (dqm->active_runlist)
2135 return 0;
2136
2137 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues);
2138 pr_debug("%s sent runlist\n", __func__);
2139 if (retval) {
2140 dev_err(dev, "failed to execute runlist\n");
2141 return retval;
2142 }
2143 dqm->active_runlist = true;
2144
2145 return retval;
2146}
2147
2148static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q,
2149 struct qcm_process_device *qpd)
2150{
2151 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
2152
2153 dev_err(dqm->dev->adev->dev, "queue id 0x%0x at pasid 0x%0x is reset\n",
2154 q->properties.queue_id, q->process->pasid);
2155
2156 pdd->has_reset_queue = true;
2157 if (q->properties.is_active) {
2158 q->properties.is_active = false;
2159 decrement_queue_count(dqm, qpd, q);
2160 }
2161}
2162
2163static int detect_queue_hang(struct device_queue_manager *dqm)
2164{
2165 int i;
2166
2167 /* detect should be used only in dqm locked queue reset */
2168 if (WARN_ON(dqm->detect_hang_count > 0))
2169 return 0;
2170
2171 memset(dqm->detect_hang_info, 0, dqm->detect_hang_info_size);
2172
2173 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) {
2174 uint32_t mec, pipe, queue;
2175 int xcc_id;
2176
2177 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe)
2178 / dqm->dev->kfd->shared_resources.num_pipe_per_mec;
2179
2180 if (mec || !test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap))
2181 continue;
2182
2183 amdgpu_queue_mask_bit_to_mec_queue(dqm->dev->adev, i, &mec, &pipe, &queue);
2184
2185 for_each_inst(xcc_id, dqm->dev->xcc_mask) {
2186 uint64_t queue_addr = dqm->dev->kfd2kgd->hqd_get_pq_addr(
2187 dqm->dev->adev, pipe, queue, xcc_id);
2188 struct dqm_detect_hang_info hang_info;
2189
2190 if (!queue_addr)
2191 continue;
2192
2193 hang_info.pipe_id = pipe;
2194 hang_info.queue_id = queue;
2195 hang_info.xcc_id = xcc_id;
2196 hang_info.queue_address = queue_addr;
2197
2198 dqm->detect_hang_info[dqm->detect_hang_count] = hang_info;
2199 dqm->detect_hang_count++;
2200 }
2201 }
2202
2203 return dqm->detect_hang_count;
2204}
2205
2206static struct queue *find_queue_by_address(struct device_queue_manager *dqm, uint64_t queue_address)
2207{
2208 struct device_process_node *cur;
2209 struct qcm_process_device *qpd;
2210 struct queue *q;
2211
2212 list_for_each_entry(cur, &dqm->queues, list) {
2213 qpd = cur->qpd;
2214 list_for_each_entry(q, &qpd->queues_list, list) {
2215 if (queue_address == q->properties.queue_address)
2216 return q;
2217 }
2218 }
2219
2220 return NULL;
2221}
2222
2223/* only for compute queue */
2224static int reset_queues_on_hws_hang(struct device_queue_manager *dqm)
2225{
2226 int r = 0, reset_count = 0, i;
2227
2228 if (!dqm->detect_hang_info || dqm->is_hws_hang)
2229 return -EIO;
2230
2231 /* assume dqm locked. */
2232 if (!detect_queue_hang(dqm))
2233 return -ENOTRECOVERABLE;
2234
2235 for (i = 0; i < dqm->detect_hang_count; i++) {
2236 struct dqm_detect_hang_info hang_info = dqm->detect_hang_info[i];
2237 struct queue *q = find_queue_by_address(dqm, hang_info.queue_address);
2238 struct kfd_process_device *pdd;
2239 uint64_t queue_addr = 0;
2240
2241 if (!q) {
2242 r = -ENOTRECOVERABLE;
2243 goto reset_fail;
2244 }
2245
2246 pdd = kfd_get_process_device_data(dqm->dev, q->process);
2247 if (!pdd) {
2248 r = -ENOTRECOVERABLE;
2249 goto reset_fail;
2250 }
2251
2252 queue_addr = dqm->dev->kfd2kgd->hqd_reset(dqm->dev->adev,
2253 hang_info.pipe_id, hang_info.queue_id, hang_info.xcc_id,
2254 KFD_UNMAP_LATENCY_MS);
2255
2256 /* either reset failed or we reset an unexpected queue. */
2257 if (queue_addr != q->properties.queue_address) {
2258 r = -ENOTRECOVERABLE;
2259 goto reset_fail;
2260 }
2261
2262 set_queue_as_reset(dqm, q, &pdd->qpd);
2263 reset_count++;
2264 }
2265
2266 if (reset_count == dqm->detect_hang_count)
2267 kfd_signal_reset_event(dqm->dev);
2268 else
2269 r = -ENOTRECOVERABLE;
2270
2271reset_fail:
2272 dqm->detect_hang_count = 0;
2273
2274 return r;
2275}
2276
2277/* dqm->lock mutex has to be locked before calling this function */
2278static int unmap_queues_cpsch(struct device_queue_manager *dqm,
2279 enum kfd_unmap_queues_filter filter,
2280 uint32_t filter_param,
2281 uint32_t grace_period,
2282 bool reset)
2283{
2284 struct device *dev = dqm->dev->adev->dev;
2285 struct mqd_manager *mqd_mgr;
2286 int retval;
2287
2288 if (!dqm->sched_running)
2289 return 0;
2290 if (!dqm->active_runlist)
2291 return 0;
2292 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem))
2293 return -EIO;
2294
2295 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
2296 retval = pm_update_grace_period(&dqm->packet_mgr, grace_period);
2297 if (retval)
2298 goto out;
2299 }
2300
2301 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset);
2302 if (retval)
2303 goto out;
2304
2305 *dqm->fence_addr = KFD_FENCE_INIT;
2306 mb();
2307 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr,
2308 KFD_FENCE_COMPLETED);
2309 /* should be timed out */
2310 retval = amdkfd_fence_wait_timeout(dqm, KFD_FENCE_COMPLETED,
2311 queue_preemption_timeout_ms);
2312 if (retval) {
2313 dev_err(dev, "The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
2314 kfd_hws_hang(dqm);
2315 goto out;
2316 }
2317
2318 /* In the current MEC firmware implementation, if compute queue
2319 * doesn't response to the preemption request in time, HIQ will
2320 * abandon the unmap request without returning any timeout error
2321 * to driver. Instead, MEC firmware will log the doorbell of the
2322 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields.
2323 * To make sure the queue unmap was successful, driver need to
2324 * check those fields
2325 */
2326 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];
2327 if (mqd_mgr->check_preemption_failed(mqd_mgr, dqm->packet_mgr.priv_queue->queue->mqd)) {
2328 while (halt_if_hws_hang)
2329 schedule();
2330 if (reset_queues_on_hws_hang(dqm)) {
2331 dqm->is_hws_hang = true;
2332 kfd_hws_hang(dqm);
2333 retval = -ETIME;
2334 goto out;
2335 }
2336 }
2337
2338 /* We need to reset the grace period value for this device */
2339 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
2340 if (pm_update_grace_period(&dqm->packet_mgr,
2341 USE_DEFAULT_GRACE_PERIOD))
2342 dev_err(dev, "Failed to reset grace period\n");
2343 }
2344
2345 pm_release_ib(&dqm->packet_mgr);
2346 dqm->active_runlist = false;
2347
2348out:
2349 up_read(&dqm->dev->adev->reset_domain->sem);
2350 return retval;
2351}
2352
2353/* only for compute queue */
2354static int reset_queues_cpsch(struct device_queue_manager *dqm, uint16_t pasid)
2355{
2356 int retval;
2357
2358 dqm_lock(dqm);
2359
2360 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID,
2361 pasid, USE_DEFAULT_GRACE_PERIOD, true);
2362
2363 dqm_unlock(dqm);
2364 return retval;
2365}
2366
2367/* dqm->lock mutex has to be locked before calling this function */
2368static int execute_queues_cpsch(struct device_queue_manager *dqm,
2369 enum kfd_unmap_queues_filter filter,
2370 uint32_t filter_param,
2371 uint32_t grace_period)
2372{
2373 int retval;
2374
2375 if (!down_read_trylock(&dqm->dev->adev->reset_domain->sem))
2376 return -EIO;
2377 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false);
2378 if (!retval)
2379 retval = map_queues_cpsch(dqm);
2380 up_read(&dqm->dev->adev->reset_domain->sem);
2381 return retval;
2382}
2383
2384static int wait_on_destroy_queue(struct device_queue_manager *dqm,
2385 struct queue *q)
2386{
2387 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device,
2388 q->process);
2389 int ret = 0;
2390
2391 if (pdd->qpd.is_debug)
2392 return ret;
2393
2394 q->properties.is_being_destroyed = true;
2395
2396 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) {
2397 dqm_unlock(dqm);
2398 mutex_unlock(&q->process->mutex);
2399 ret = wait_event_interruptible(dqm->destroy_wait,
2400 !q->properties.is_suspended);
2401
2402 mutex_lock(&q->process->mutex);
2403 dqm_lock(dqm);
2404 }
2405
2406 return ret;
2407}
2408
2409static int destroy_queue_cpsch(struct device_queue_manager *dqm,
2410 struct qcm_process_device *qpd,
2411 struct queue *q)
2412{
2413 int retval;
2414 struct mqd_manager *mqd_mgr;
2415 uint64_t sdma_val = 0;
2416 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
2417 struct device *dev = dqm->dev->adev->dev;
2418
2419 /* Get the SDMA queue stats */
2420 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2421 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2422 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
2423 &sdma_val);
2424 if (retval)
2425 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n",
2426 q->properties.queue_id);
2427 }
2428
2429 /* remove queue from list to prevent rescheduling after preemption */
2430 dqm_lock(dqm);
2431
2432 retval = wait_on_destroy_queue(dqm, q);
2433
2434 if (retval) {
2435 dqm_unlock(dqm);
2436 return retval;
2437 }
2438
2439 if (qpd->is_debug) {
2440 /*
2441 * error, currently we do not allow to destroy a queue
2442 * of a currently debugged process
2443 */
2444 retval = -EBUSY;
2445 goto failed_try_destroy_debugged_queue;
2446
2447 }
2448
2449 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2450 q->properties.type)];
2451
2452 deallocate_doorbell(qpd, q);
2453
2454 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2455 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2456 deallocate_sdma_queue(dqm, q);
2457 pdd->sdma_past_activity_counter += sdma_val;
2458 }
2459
2460 if (q->properties.is_active) {
2461 decrement_queue_count(dqm, qpd, q);
2462 q->properties.is_active = false;
2463 if (!dqm->dev->kfd->shared_resources.enable_mes) {
2464 retval = execute_queues_cpsch(dqm,
2465 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
2466 USE_DEFAULT_GRACE_PERIOD);
2467 if (retval == -ETIME)
2468 qpd->reset_wavefronts = true;
2469 } else {
2470 retval = remove_queue_mes(dqm, q, qpd);
2471 }
2472 }
2473 list_del(&q->list);
2474 qpd->queue_count--;
2475
2476 /*
2477 * Unconditionally decrement this counter, regardless of the queue's
2478 * type
2479 */
2480 dqm->total_queue_count--;
2481 pr_debug("Total of %d queues are accountable so far\n",
2482 dqm->total_queue_count);
2483
2484 dqm_unlock(dqm);
2485
2486 /*
2487 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid
2488 * circular locking
2489 */
2490 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE),
2491 qpd->pqm->process, q->device,
2492 -1, false, NULL, 0);
2493
2494 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2495
2496 return retval;
2497
2498failed_try_destroy_debugged_queue:
2499
2500 dqm_unlock(dqm);
2501 return retval;
2502}
2503
2504/*
2505 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
2506 * stay in user mode.
2507 */
2508#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
2509/* APE1 limit is inclusive and 64K aligned. */
2510#define APE1_LIMIT_ALIGNMENT 0xFFFF
2511
2512static bool set_cache_memory_policy(struct device_queue_manager *dqm,
2513 struct qcm_process_device *qpd,
2514 enum cache_policy default_policy,
2515 enum cache_policy alternate_policy,
2516 void __user *alternate_aperture_base,
2517 uint64_t alternate_aperture_size)
2518{
2519 bool retval = true;
2520
2521 if (!dqm->asic_ops.set_cache_memory_policy)
2522 return retval;
2523
2524 dqm_lock(dqm);
2525
2526 if (alternate_aperture_size == 0) {
2527 /* base > limit disables APE1 */
2528 qpd->sh_mem_ape1_base = 1;
2529 qpd->sh_mem_ape1_limit = 0;
2530 } else {
2531 /*
2532 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
2533 * SH_MEM_APE1_BASE[31:0], 0x0000 }
2534 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
2535 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
2536 * Verify that the base and size parameters can be
2537 * represented in this format and convert them.
2538 * Additionally restrict APE1 to user-mode addresses.
2539 */
2540
2541 uint64_t base = (uintptr_t)alternate_aperture_base;
2542 uint64_t limit = base + alternate_aperture_size - 1;
2543
2544 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
2545 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
2546 retval = false;
2547 goto out;
2548 }
2549
2550 qpd->sh_mem_ape1_base = base >> 16;
2551 qpd->sh_mem_ape1_limit = limit >> 16;
2552 }
2553
2554 retval = dqm->asic_ops.set_cache_memory_policy(
2555 dqm,
2556 qpd,
2557 default_policy,
2558 alternate_policy,
2559 alternate_aperture_base,
2560 alternate_aperture_size);
2561
2562 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
2563 program_sh_mem_settings(dqm, qpd);
2564
2565 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
2566 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
2567 qpd->sh_mem_ape1_limit);
2568
2569out:
2570 dqm_unlock(dqm);
2571 return retval;
2572}
2573
2574static int process_termination_nocpsch(struct device_queue_manager *dqm,
2575 struct qcm_process_device *qpd)
2576{
2577 struct queue *q;
2578 struct device_process_node *cur, *next_dpn;
2579 int retval = 0;
2580 bool found = false;
2581
2582 dqm_lock(dqm);
2583
2584 /* Clear all user mode queues */
2585 while (!list_empty(&qpd->queues_list)) {
2586 struct mqd_manager *mqd_mgr;
2587 int ret;
2588
2589 q = list_first_entry(&qpd->queues_list, struct queue, list);
2590 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2591 q->properties.type)];
2592 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
2593 if (ret)
2594 retval = ret;
2595 dqm_unlock(dqm);
2596 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2597 dqm_lock(dqm);
2598 }
2599
2600 /* Unregister process */
2601 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2602 if (qpd == cur->qpd) {
2603 list_del(&cur->list);
2604 kfree(cur);
2605 dqm->processes_count--;
2606 found = true;
2607 break;
2608 }
2609 }
2610
2611 dqm_unlock(dqm);
2612
2613 /* Outside the DQM lock because under the DQM lock we can't do
2614 * reclaim or take other locks that others hold while reclaiming.
2615 */
2616 if (found)
2617 kfd_dec_compute_active(dqm->dev);
2618
2619 return retval;
2620}
2621
2622static int get_wave_state(struct device_queue_manager *dqm,
2623 struct queue *q,
2624 void __user *ctl_stack,
2625 u32 *ctl_stack_used_size,
2626 u32 *save_area_used_size)
2627{
2628 struct mqd_manager *mqd_mgr;
2629
2630 dqm_lock(dqm);
2631
2632 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2633
2634 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
2635 q->properties.is_active || !q->device->kfd->cwsr_enabled ||
2636 !mqd_mgr->get_wave_state) {
2637 dqm_unlock(dqm);
2638 return -EINVAL;
2639 }
2640
2641 dqm_unlock(dqm);
2642
2643 /*
2644 * get_wave_state is outside the dqm lock to prevent circular locking
2645 * and the queue should be protected against destruction by the process
2646 * lock.
2647 */
2648 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties,
2649 ctl_stack, ctl_stack_used_size, save_area_used_size);
2650}
2651
2652static void get_queue_checkpoint_info(struct device_queue_manager *dqm,
2653 const struct queue *q,
2654 u32 *mqd_size,
2655 u32 *ctl_stack_size)
2656{
2657 struct mqd_manager *mqd_mgr;
2658 enum KFD_MQD_TYPE mqd_type =
2659 get_mqd_type_from_queue_type(q->properties.type);
2660
2661 dqm_lock(dqm);
2662 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2663 *mqd_size = mqd_mgr->mqd_size;
2664 *ctl_stack_size = 0;
2665
2666 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info)
2667 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size);
2668
2669 dqm_unlock(dqm);
2670}
2671
2672static int checkpoint_mqd(struct device_queue_manager *dqm,
2673 const struct queue *q,
2674 void *mqd,
2675 void *ctl_stack)
2676{
2677 struct mqd_manager *mqd_mgr;
2678 int r = 0;
2679 enum KFD_MQD_TYPE mqd_type =
2680 get_mqd_type_from_queue_type(q->properties.type);
2681
2682 dqm_lock(dqm);
2683
2684 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) {
2685 r = -EINVAL;
2686 goto dqm_unlock;
2687 }
2688
2689 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2690 if (!mqd_mgr->checkpoint_mqd) {
2691 r = -EOPNOTSUPP;
2692 goto dqm_unlock;
2693 }
2694
2695 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack);
2696
2697dqm_unlock:
2698 dqm_unlock(dqm);
2699 return r;
2700}
2701
2702static int process_termination_cpsch(struct device_queue_manager *dqm,
2703 struct qcm_process_device *qpd)
2704{
2705 int retval;
2706 struct queue *q;
2707 struct device *dev = dqm->dev->adev->dev;
2708 struct kernel_queue *kq, *kq_next;
2709 struct mqd_manager *mqd_mgr;
2710 struct device_process_node *cur, *next_dpn;
2711 enum kfd_unmap_queues_filter filter =
2712 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
2713 bool found = false;
2714
2715 retval = 0;
2716
2717 dqm_lock(dqm);
2718
2719 /* Clean all kernel queues */
2720 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
2721 list_del(&kq->list);
2722 decrement_queue_count(dqm, qpd, kq->queue);
2723 qpd->is_debug = false;
2724 dqm->total_queue_count--;
2725 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
2726 }
2727
2728 /* Clear all user mode queues */
2729 list_for_each_entry(q, &qpd->queues_list, list) {
2730 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
2731 deallocate_sdma_queue(dqm, q);
2732 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
2733 deallocate_sdma_queue(dqm, q);
2734
2735 if (q->properties.is_active) {
2736 decrement_queue_count(dqm, qpd, q);
2737
2738 if (dqm->dev->kfd->shared_resources.enable_mes) {
2739 retval = remove_queue_mes(dqm, q, qpd);
2740 if (retval)
2741 dev_err(dev, "Failed to remove queue %d\n",
2742 q->properties.queue_id);
2743 }
2744 }
2745
2746 dqm->total_queue_count--;
2747 }
2748
2749 /* Unregister process */
2750 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2751 if (qpd == cur->qpd) {
2752 list_del(&cur->list);
2753 kfree(cur);
2754 dqm->processes_count--;
2755 found = true;
2756 break;
2757 }
2758 }
2759
2760 if (!dqm->dev->kfd->shared_resources.enable_mes)
2761 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD);
2762
2763 if ((retval || qpd->reset_wavefronts) &&
2764 down_read_trylock(&dqm->dev->adev->reset_domain->sem)) {
2765 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
2766 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
2767 qpd->reset_wavefronts = false;
2768 up_read(&dqm->dev->adev->reset_domain->sem);
2769 }
2770
2771 /* Lastly, free mqd resources.
2772 * Do free_mqd() after dqm_unlock to avoid circular locking.
2773 */
2774 while (!list_empty(&qpd->queues_list)) {
2775 q = list_first_entry(&qpd->queues_list, struct queue, list);
2776 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2777 q->properties.type)];
2778 list_del(&q->list);
2779 qpd->queue_count--;
2780 dqm_unlock(dqm);
2781 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2782 dqm_lock(dqm);
2783 }
2784 dqm_unlock(dqm);
2785
2786 /* Outside the DQM lock because under the DQM lock we can't do
2787 * reclaim or take other locks that others hold while reclaiming.
2788 */
2789 if (found)
2790 kfd_dec_compute_active(dqm->dev);
2791
2792 return retval;
2793}
2794
2795static int init_mqd_managers(struct device_queue_manager *dqm)
2796{
2797 int i, j;
2798 struct device *dev = dqm->dev->adev->dev;
2799 struct mqd_manager *mqd_mgr;
2800
2801 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
2802 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
2803 if (!mqd_mgr) {
2804 dev_err(dev, "mqd manager [%d] initialization failed\n", i);
2805 goto out_free;
2806 }
2807 dqm->mqd_mgrs[i] = mqd_mgr;
2808 }
2809
2810 return 0;
2811
2812out_free:
2813 for (j = 0; j < i; j++) {
2814 kfree(dqm->mqd_mgrs[j]);
2815 dqm->mqd_mgrs[j] = NULL;
2816 }
2817
2818 return -ENOMEM;
2819}
2820
2821/* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
2822static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
2823{
2824 int retval;
2825 struct kfd_node *dev = dqm->dev;
2826 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
2827 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
2828 get_num_all_sdma_engines(dqm) *
2829 dev->kfd->device_info.num_sdma_queues_per_engine +
2830 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size *
2831 NUM_XCC(dqm->dev->xcc_mask));
2832
2833 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
2834 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
2835 (void *)&(mem_obj->cpu_ptr), false);
2836
2837 return retval;
2838}
2839
2840struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)
2841{
2842 struct device_queue_manager *dqm;
2843
2844 pr_debug("Loading device queue manager\n");
2845
2846 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
2847 if (!dqm)
2848 return NULL;
2849
2850 switch (dev->adev->asic_type) {
2851 /* HWS is not available on Hawaii. */
2852 case CHIP_HAWAII:
2853 /* HWS depends on CWSR for timely dequeue. CWSR is not
2854 * available on Tonga.
2855 *
2856 * FIXME: This argument also applies to Kaveri.
2857 */
2858 case CHIP_TONGA:
2859 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
2860 break;
2861 default:
2862 dqm->sched_policy = sched_policy;
2863 break;
2864 }
2865
2866 dqm->dev = dev;
2867 switch (dqm->sched_policy) {
2868 case KFD_SCHED_POLICY_HWS:
2869 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
2870 /* initialize dqm for cp scheduling */
2871 dqm->ops.create_queue = create_queue_cpsch;
2872 dqm->ops.initialize = initialize_cpsch;
2873 dqm->ops.start = start_cpsch;
2874 dqm->ops.stop = stop_cpsch;
2875 dqm->ops.halt = halt_cpsch;
2876 dqm->ops.unhalt = unhalt_cpsch;
2877 dqm->ops.destroy_queue = destroy_queue_cpsch;
2878 dqm->ops.update_queue = update_queue;
2879 dqm->ops.register_process = register_process;
2880 dqm->ops.unregister_process = unregister_process;
2881 dqm->ops.uninitialize = uninitialize;
2882 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
2883 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
2884 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2885 dqm->ops.process_termination = process_termination_cpsch;
2886 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
2887 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
2888 dqm->ops.get_wave_state = get_wave_state;
2889 dqm->ops.reset_queues = reset_queues_cpsch;
2890 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2891 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2892 break;
2893 case KFD_SCHED_POLICY_NO_HWS:
2894 /* initialize dqm for no cp scheduling */
2895 dqm->ops.start = start_nocpsch;
2896 dqm->ops.stop = stop_nocpsch;
2897 dqm->ops.create_queue = create_queue_nocpsch;
2898 dqm->ops.destroy_queue = destroy_queue_nocpsch;
2899 dqm->ops.update_queue = update_queue;
2900 dqm->ops.register_process = register_process;
2901 dqm->ops.unregister_process = unregister_process;
2902 dqm->ops.initialize = initialize_nocpsch;
2903 dqm->ops.uninitialize = uninitialize;
2904 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2905 dqm->ops.process_termination = process_termination_nocpsch;
2906 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
2907 dqm->ops.restore_process_queues =
2908 restore_process_queues_nocpsch;
2909 dqm->ops.get_wave_state = get_wave_state;
2910 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2911 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2912 break;
2913 default:
2914 dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy);
2915 goto out_free;
2916 }
2917
2918 switch (dev->adev->asic_type) {
2919 case CHIP_KAVERI:
2920 case CHIP_HAWAII:
2921 device_queue_manager_init_cik(&dqm->asic_ops);
2922 break;
2923
2924 case CHIP_CARRIZO:
2925 case CHIP_TONGA:
2926 case CHIP_FIJI:
2927 case CHIP_POLARIS10:
2928 case CHIP_POLARIS11:
2929 case CHIP_POLARIS12:
2930 case CHIP_VEGAM:
2931 device_queue_manager_init_vi(&dqm->asic_ops);
2932 break;
2933
2934 default:
2935 if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 0, 0))
2936 device_queue_manager_init_v12(&dqm->asic_ops);
2937 else if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0))
2938 device_queue_manager_init_v11(&dqm->asic_ops);
2939 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1))
2940 device_queue_manager_init_v10(&dqm->asic_ops);
2941 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1))
2942 device_queue_manager_init_v9(&dqm->asic_ops);
2943 else {
2944 WARN(1, "Unexpected ASIC family %u",
2945 dev->adev->asic_type);
2946 goto out_free;
2947 }
2948 }
2949
2950 if (init_mqd_managers(dqm))
2951 goto out_free;
2952
2953 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) {
2954 dev_err(dev->adev->dev, "Failed to allocate hiq sdma mqd trunk buffer\n");
2955 goto out_free;
2956 }
2957
2958 if (!dqm->ops.initialize(dqm)) {
2959 init_waitqueue_head(&dqm->destroy_wait);
2960 return dqm;
2961 }
2962
2963out_free:
2964 kfree(dqm);
2965 return NULL;
2966}
2967
2968static void deallocate_hiq_sdma_mqd(struct kfd_node *dev,
2969 struct kfd_mem_obj *mqd)
2970{
2971 WARN(!mqd, "No hiq sdma mqd trunk to free");
2972
2973 amdgpu_amdkfd_free_gtt_mem(dev->adev, &mqd->gtt_mem);
2974}
2975
2976void device_queue_manager_uninit(struct device_queue_manager *dqm)
2977{
2978 dqm->ops.stop(dqm);
2979 dqm->ops.uninitialize(dqm);
2980 if (!dqm->dev->kfd->shared_resources.enable_mes)
2981 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
2982 kfree(dqm);
2983}
2984
2985int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id)
2986{
2987 struct kfd_process_device *pdd;
2988 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
2989 struct device_queue_manager *dqm = knode->dqm;
2990 struct device *dev = dqm->dev->adev->dev;
2991 struct qcm_process_device *qpd;
2992 struct queue *q = NULL;
2993 int ret = 0;
2994
2995 if (!p)
2996 return -EINVAL;
2997
2998 dqm_lock(dqm);
2999
3000 pdd = kfd_get_process_device_data(dqm->dev, p);
3001 if (pdd) {
3002 qpd = &pdd->qpd;
3003
3004 list_for_each_entry(q, &qpd->queues_list, list) {
3005 if (q->doorbell_id == doorbell_id && q->properties.is_active) {
3006 ret = suspend_all_queues_mes(dqm);
3007 if (ret) {
3008 dev_err(dev, "Suspending all queues failed");
3009 goto out;
3010 }
3011
3012 q->properties.is_evicted = true;
3013 q->properties.is_active = false;
3014 decrement_queue_count(dqm, qpd, q);
3015
3016 ret = remove_queue_mes(dqm, q, qpd);
3017 if (ret) {
3018 dev_err(dev, "Removing bad queue failed");
3019 goto out;
3020 }
3021
3022 ret = resume_all_queues_mes(dqm);
3023 if (ret)
3024 dev_err(dev, "Resuming all queues failed");
3025
3026 break;
3027 }
3028 }
3029 }
3030
3031out:
3032 dqm_unlock(dqm);
3033 return ret;
3034}
3035
3036static int kfd_dqm_evict_pasid_mes(struct device_queue_manager *dqm,
3037 struct qcm_process_device *qpd)
3038{
3039 struct device *dev = dqm->dev->adev->dev;
3040 int ret = 0;
3041
3042 /* Check if process is already evicted */
3043 dqm_lock(dqm);
3044 if (qpd->evicted) {
3045 /* Increment the evicted count to make sure the
3046 * process stays evicted before its terminated.
3047 */
3048 qpd->evicted++;
3049 dqm_unlock(dqm);
3050 goto out;
3051 }
3052 dqm_unlock(dqm);
3053
3054 ret = suspend_all_queues_mes(dqm);
3055 if (ret) {
3056 dev_err(dev, "Suspending all queues failed");
3057 goto out;
3058 }
3059
3060 ret = dqm->ops.evict_process_queues(dqm, qpd);
3061 if (ret) {
3062 dev_err(dev, "Evicting process queues failed");
3063 goto out;
3064 }
3065
3066 ret = resume_all_queues_mes(dqm);
3067 if (ret)
3068 dev_err(dev, "Resuming all queues failed");
3069
3070out:
3071 return ret;
3072}
3073
3074int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid)
3075{
3076 struct kfd_process_device *pdd;
3077 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
3078 int ret = 0;
3079
3080 if (!p)
3081 return -EINVAL;
3082 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
3083 pdd = kfd_get_process_device_data(dqm->dev, p);
3084 if (pdd) {
3085 if (dqm->dev->kfd->shared_resources.enable_mes)
3086 ret = kfd_dqm_evict_pasid_mes(dqm, &pdd->qpd);
3087 else
3088 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
3089 }
3090
3091 kfd_unref_process(p);
3092
3093 return ret;
3094}
3095
3096static void kfd_process_hw_exception(struct work_struct *work)
3097{
3098 struct device_queue_manager *dqm = container_of(work,
3099 struct device_queue_manager, hw_exception_work);
3100 amdgpu_amdkfd_gpu_reset(dqm->dev->adev);
3101}
3102
3103int reserve_debug_trap_vmid(struct device_queue_manager *dqm,
3104 struct qcm_process_device *qpd)
3105{
3106 int r;
3107 struct device *dev = dqm->dev->adev->dev;
3108 int updated_vmid_mask;
3109
3110 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3111 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
3112 return -EINVAL;
3113 }
3114
3115 dqm_lock(dqm);
3116
3117 if (dqm->trap_debug_vmid != 0) {
3118 dev_err(dev, "Trap debug id already reserved\n");
3119 r = -EBUSY;
3120 goto out_unlock;
3121 }
3122
3123 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
3124 USE_DEFAULT_GRACE_PERIOD, false);
3125 if (r)
3126 goto out_unlock;
3127
3128 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
3129 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd);
3130
3131 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
3132 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd;
3133 r = set_sched_resources(dqm);
3134 if (r)
3135 goto out_unlock;
3136
3137 r = map_queues_cpsch(dqm);
3138 if (r)
3139 goto out_unlock;
3140
3141 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid);
3142
3143out_unlock:
3144 dqm_unlock(dqm);
3145 return r;
3146}
3147
3148/*
3149 * Releases vmid for the trap debugger
3150 */
3151int release_debug_trap_vmid(struct device_queue_manager *dqm,
3152 struct qcm_process_device *qpd)
3153{
3154 struct device *dev = dqm->dev->adev->dev;
3155 int r;
3156 int updated_vmid_mask;
3157 uint32_t trap_debug_vmid;
3158
3159 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3160 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
3161 return -EINVAL;
3162 }
3163
3164 dqm_lock(dqm);
3165 trap_debug_vmid = dqm->trap_debug_vmid;
3166 if (dqm->trap_debug_vmid == 0) {
3167 dev_err(dev, "Trap debug id is not reserved\n");
3168 r = -EINVAL;
3169 goto out_unlock;
3170 }
3171
3172 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
3173 USE_DEFAULT_GRACE_PERIOD, false);
3174 if (r)
3175 goto out_unlock;
3176
3177 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
3178 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd);
3179
3180 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
3181 dqm->trap_debug_vmid = 0;
3182 r = set_sched_resources(dqm);
3183 if (r)
3184 goto out_unlock;
3185
3186 r = map_queues_cpsch(dqm);
3187 if (r)
3188 goto out_unlock;
3189
3190 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid);
3191
3192out_unlock:
3193 dqm_unlock(dqm);
3194 return r;
3195}
3196
3197#define QUEUE_NOT_FOUND -1
3198/* invalidate queue operation in array */
3199static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids)
3200{
3201 int i;
3202
3203 for (i = 0; i < num_queues; i++)
3204 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK;
3205}
3206
3207/* find queue index in array */
3208static int q_array_get_index(unsigned int queue_id,
3209 uint32_t num_queues,
3210 uint32_t *queue_ids)
3211{
3212 int i;
3213
3214 for (i = 0; i < num_queues; i++)
3215 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK))
3216 return i;
3217
3218 return QUEUE_NOT_FOUND;
3219}
3220
3221struct copy_context_work_handler_workarea {
3222 struct work_struct copy_context_work;
3223 struct kfd_process *p;
3224};
3225
3226static void copy_context_work_handler(struct work_struct *work)
3227{
3228 struct copy_context_work_handler_workarea *workarea;
3229 struct mqd_manager *mqd_mgr;
3230 struct queue *q;
3231 struct mm_struct *mm;
3232 struct kfd_process *p;
3233 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size;
3234 int i;
3235
3236 workarea = container_of(work,
3237 struct copy_context_work_handler_workarea,
3238 copy_context_work);
3239
3240 p = workarea->p;
3241 mm = get_task_mm(p->lead_thread);
3242
3243 if (!mm)
3244 return;
3245
3246 kthread_use_mm(mm);
3247 for (i = 0; i < p->n_pdds; i++) {
3248 struct kfd_process_device *pdd = p->pdds[i];
3249 struct device_queue_manager *dqm = pdd->dev->dqm;
3250 struct qcm_process_device *qpd = &pdd->qpd;
3251
3252 list_for_each_entry(q, &qpd->queues_list, list) {
3253 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE)
3254 continue;
3255
3256 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
3257
3258 /* We ignore the return value from get_wave_state
3259 * because
3260 * i) right now, it always returns 0, and
3261 * ii) if we hit an error, we would continue to the
3262 * next queue anyway.
3263 */
3264 mqd_mgr->get_wave_state(mqd_mgr,
3265 q->mqd,
3266 &q->properties,
3267 (void __user *) q->properties.ctx_save_restore_area_address,
3268 &tmp_ctl_stack_used_size,
3269 &tmp_save_area_used_size);
3270 }
3271 }
3272 kthread_unuse_mm(mm);
3273 mmput(mm);
3274}
3275
3276static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array)
3277{
3278 size_t array_size = num_queues * sizeof(uint32_t);
3279
3280 if (!usr_queue_id_array)
3281 return NULL;
3282
3283 return memdup_user(usr_queue_id_array, array_size);
3284}
3285
3286int resume_queues(struct kfd_process *p,
3287 uint32_t num_queues,
3288 uint32_t *usr_queue_id_array)
3289{
3290 uint32_t *queue_ids = NULL;
3291 int total_resumed = 0;
3292 int i;
3293
3294 if (usr_queue_id_array) {
3295 queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
3296
3297 if (IS_ERR(queue_ids))
3298 return PTR_ERR(queue_ids);
3299
3300 /* mask all queues as invalid. unmask per successful request */
3301 q_array_invalidate(num_queues, queue_ids);
3302 }
3303
3304 for (i = 0; i < p->n_pdds; i++) {
3305 struct kfd_process_device *pdd = p->pdds[i];
3306 struct device_queue_manager *dqm = pdd->dev->dqm;
3307 struct device *dev = dqm->dev->adev->dev;
3308 struct qcm_process_device *qpd = &pdd->qpd;
3309 struct queue *q;
3310 int r, per_device_resumed = 0;
3311
3312 dqm_lock(dqm);
3313
3314 /* unmask queues that resume or already resumed as valid */
3315 list_for_each_entry(q, &qpd->queues_list, list) {
3316 int q_idx = QUEUE_NOT_FOUND;
3317
3318 if (queue_ids)
3319 q_idx = q_array_get_index(
3320 q->properties.queue_id,
3321 num_queues,
3322 queue_ids);
3323
3324 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) {
3325 int err = resume_single_queue(dqm, &pdd->qpd, q);
3326
3327 if (queue_ids) {
3328 if (!err) {
3329 queue_ids[q_idx] &=
3330 ~KFD_DBG_QUEUE_INVALID_MASK;
3331 } else {
3332 queue_ids[q_idx] |=
3333 KFD_DBG_QUEUE_ERROR_MASK;
3334 break;
3335 }
3336 }
3337
3338 if (dqm->dev->kfd->shared_resources.enable_mes) {
3339 wake_up_all(&dqm->destroy_wait);
3340 if (!err)
3341 total_resumed++;
3342 } else {
3343 per_device_resumed++;
3344 }
3345 }
3346 }
3347
3348 if (!per_device_resumed) {
3349 dqm_unlock(dqm);
3350 continue;
3351 }
3352
3353 r = execute_queues_cpsch(dqm,
3354 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
3355 0,
3356 USE_DEFAULT_GRACE_PERIOD);
3357 if (r) {
3358 dev_err(dev, "Failed to resume process queues\n");
3359 if (queue_ids) {
3360 list_for_each_entry(q, &qpd->queues_list, list) {
3361 int q_idx = q_array_get_index(
3362 q->properties.queue_id,
3363 num_queues,
3364 queue_ids);
3365
3366 /* mask queue as error on resume fail */
3367 if (q_idx != QUEUE_NOT_FOUND)
3368 queue_ids[q_idx] |=
3369 KFD_DBG_QUEUE_ERROR_MASK;
3370 }
3371 }
3372 } else {
3373 wake_up_all(&dqm->destroy_wait);
3374 total_resumed += per_device_resumed;
3375 }
3376
3377 dqm_unlock(dqm);
3378 }
3379
3380 if (queue_ids) {
3381 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
3382 num_queues * sizeof(uint32_t)))
3383 pr_err("copy_to_user failed on queue resume\n");
3384
3385 kfree(queue_ids);
3386 }
3387
3388 return total_resumed;
3389}
3390
3391int suspend_queues(struct kfd_process *p,
3392 uint32_t num_queues,
3393 uint32_t grace_period,
3394 uint64_t exception_clear_mask,
3395 uint32_t *usr_queue_id_array)
3396{
3397 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
3398 int total_suspended = 0;
3399 int i;
3400
3401 if (IS_ERR(queue_ids))
3402 return PTR_ERR(queue_ids);
3403
3404 /* mask all queues as invalid. umask on successful request */
3405 q_array_invalidate(num_queues, queue_ids);
3406
3407 for (i = 0; i < p->n_pdds; i++) {
3408 struct kfd_process_device *pdd = p->pdds[i];
3409 struct device_queue_manager *dqm = pdd->dev->dqm;
3410 struct device *dev = dqm->dev->adev->dev;
3411 struct qcm_process_device *qpd = &pdd->qpd;
3412 struct queue *q;
3413 int r, per_device_suspended = 0;
3414
3415 mutex_lock(&p->event_mutex);
3416 dqm_lock(dqm);
3417
3418 /* unmask queues that suspend or already suspended */
3419 list_for_each_entry(q, &qpd->queues_list, list) {
3420 int q_idx = q_array_get_index(q->properties.queue_id,
3421 num_queues,
3422 queue_ids);
3423
3424 if (q_idx != QUEUE_NOT_FOUND) {
3425 int err = suspend_single_queue(dqm, pdd, q);
3426 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes;
3427
3428 if (!err) {
3429 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK;
3430 if (exception_clear_mask && is_mes)
3431 q->properties.exception_status &=
3432 ~exception_clear_mask;
3433
3434 if (is_mes)
3435 total_suspended++;
3436 else
3437 per_device_suspended++;
3438 } else if (err != -EBUSY) {
3439 r = err;
3440 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
3441 break;
3442 }
3443 }
3444 }
3445
3446 if (!per_device_suspended) {
3447 dqm_unlock(dqm);
3448 mutex_unlock(&p->event_mutex);
3449 if (total_suspended)
3450 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev);
3451 continue;
3452 }
3453
3454 r = execute_queues_cpsch(dqm,
3455 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
3456 grace_period);
3457
3458 if (r)
3459 dev_err(dev, "Failed to suspend process queues.\n");
3460 else
3461 total_suspended += per_device_suspended;
3462
3463 list_for_each_entry(q, &qpd->queues_list, list) {
3464 int q_idx = q_array_get_index(q->properties.queue_id,
3465 num_queues, queue_ids);
3466
3467 if (q_idx == QUEUE_NOT_FOUND)
3468 continue;
3469
3470 /* mask queue as error on suspend fail */
3471 if (r)
3472 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
3473 else if (exception_clear_mask)
3474 q->properties.exception_status &=
3475 ~exception_clear_mask;
3476 }
3477
3478 dqm_unlock(dqm);
3479 mutex_unlock(&p->event_mutex);
3480 amdgpu_device_flush_hdp(dqm->dev->adev, NULL);
3481 }
3482
3483 if (total_suspended) {
3484 struct copy_context_work_handler_workarea copy_context_worker;
3485
3486 INIT_WORK_ONSTACK(
3487 ©_context_worker.copy_context_work,
3488 copy_context_work_handler);
3489
3490 copy_context_worker.p = p;
3491
3492 schedule_work(©_context_worker.copy_context_work);
3493
3494
3495 flush_work(©_context_worker.copy_context_work);
3496 destroy_work_on_stack(©_context_worker.copy_context_work);
3497 }
3498
3499 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
3500 num_queues * sizeof(uint32_t)))
3501 pr_err("copy_to_user failed on queue suspend\n");
3502
3503 kfree(queue_ids);
3504
3505 return total_suspended;
3506}
3507
3508static uint32_t set_queue_type_for_user(struct queue_properties *q_props)
3509{
3510 switch (q_props->type) {
3511 case KFD_QUEUE_TYPE_COMPUTE:
3512 return q_props->format == KFD_QUEUE_FORMAT_PM4
3513 ? KFD_IOC_QUEUE_TYPE_COMPUTE
3514 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL;
3515 case KFD_QUEUE_TYPE_SDMA:
3516 return KFD_IOC_QUEUE_TYPE_SDMA;
3517 case KFD_QUEUE_TYPE_SDMA_XGMI:
3518 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI;
3519 default:
3520 WARN_ONCE(true, "queue type not recognized!");
3521 return 0xffffffff;
3522 };
3523}
3524
3525void set_queue_snapshot_entry(struct queue *q,
3526 uint64_t exception_clear_mask,
3527 struct kfd_queue_snapshot_entry *qss_entry)
3528{
3529 qss_entry->ring_base_address = q->properties.queue_address;
3530 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr;
3531 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr;
3532 qss_entry->ctx_save_restore_address =
3533 q->properties.ctx_save_restore_area_address;
3534 qss_entry->ctx_save_restore_area_size =
3535 q->properties.ctx_save_restore_area_size;
3536 qss_entry->exception_status = q->properties.exception_status;
3537 qss_entry->queue_id = q->properties.queue_id;
3538 qss_entry->gpu_id = q->device->id;
3539 qss_entry->ring_size = (uint32_t)q->properties.queue_size;
3540 qss_entry->queue_type = set_queue_type_for_user(&q->properties);
3541 q->properties.exception_status &= ~exception_clear_mask;
3542}
3543
3544int debug_lock_and_unmap(struct device_queue_manager *dqm)
3545{
3546 struct device *dev = dqm->dev->adev->dev;
3547 int r;
3548
3549 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3550 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
3551 return -EINVAL;
3552 }
3553
3554 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3555 return 0;
3556
3557 dqm_lock(dqm);
3558
3559 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false);
3560 if (r)
3561 dqm_unlock(dqm);
3562
3563 return r;
3564}
3565
3566int debug_map_and_unlock(struct device_queue_manager *dqm)
3567{
3568 struct device *dev = dqm->dev->adev->dev;
3569 int r;
3570
3571 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3572 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
3573 return -EINVAL;
3574 }
3575
3576 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3577 return 0;
3578
3579 r = map_queues_cpsch(dqm);
3580
3581 dqm_unlock(dqm);
3582
3583 return r;
3584}
3585
3586int debug_refresh_runlist(struct device_queue_manager *dqm)
3587{
3588 int r = debug_lock_and_unmap(dqm);
3589
3590 if (r)
3591 return r;
3592
3593 return debug_map_and_unlock(dqm);
3594}
3595
3596bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm,
3597 struct qcm_process_device *qpd,
3598 int doorbell_off, u32 *queue_format)
3599{
3600 struct queue *q;
3601 bool r = false;
3602
3603 if (!queue_format)
3604 return r;
3605
3606 dqm_lock(dqm);
3607
3608 list_for_each_entry(q, &qpd->queues_list, list) {
3609 if (q->properties.doorbell_off == doorbell_off) {
3610 *queue_format = q->properties.format;
3611 r = true;
3612 goto out;
3613 }
3614 }
3615
3616out:
3617 dqm_unlock(dqm);
3618 return r;
3619}
3620#if defined(CONFIG_DEBUG_FS)
3621
3622static void seq_reg_dump(struct seq_file *m,
3623 uint32_t (*dump)[2], uint32_t n_regs)
3624{
3625 uint32_t i, count;
3626
3627 for (i = 0, count = 0; i < n_regs; i++) {
3628 if (count == 0 ||
3629 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
3630 seq_printf(m, "%s %08x: %08x",
3631 i ? "\n" : "",
3632 dump[i][0], dump[i][1]);
3633 count = 7;
3634 } else {
3635 seq_printf(m, " %08x", dump[i][1]);
3636 count--;
3637 }
3638 }
3639
3640 seq_puts(m, "\n");
3641}
3642
3643int dqm_debugfs_hqds(struct seq_file *m, void *data)
3644{
3645 struct device_queue_manager *dqm = data;
3646 uint32_t xcc_mask = dqm->dev->xcc_mask;
3647 uint32_t (*dump)[2], n_regs;
3648 int pipe, queue;
3649 int r = 0, xcc_id;
3650 uint32_t sdma_engine_start;
3651
3652 if (!dqm->sched_running) {
3653 seq_puts(m, " Device is stopped\n");
3654 return 0;
3655 }
3656
3657 for_each_inst(xcc_id, xcc_mask) {
3658 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3659 KFD_CIK_HIQ_PIPE,
3660 KFD_CIK_HIQ_QUEUE, &dump,
3661 &n_regs, xcc_id);
3662 if (!r) {
3663 seq_printf(
3664 m,
3665 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n",
3666 xcc_id,
3667 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1,
3668 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm),
3669 KFD_CIK_HIQ_QUEUE);
3670 seq_reg_dump(m, dump, n_regs);
3671
3672 kfree(dump);
3673 }
3674
3675 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
3676 int pipe_offset = pipe * get_queues_per_pipe(dqm);
3677
3678 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
3679 if (!test_bit(pipe_offset + queue,
3680 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
3681 continue;
3682
3683 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3684 pipe, queue,
3685 &dump, &n_regs,
3686 xcc_id);
3687 if (r)
3688 break;
3689
3690 seq_printf(m,
3691 " Inst %d, CP Pipe %d, Queue %d\n",
3692 xcc_id, pipe, queue);
3693 seq_reg_dump(m, dump, n_regs);
3694
3695 kfree(dump);
3696 }
3697 }
3698 }
3699
3700 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm);
3701 for (pipe = sdma_engine_start;
3702 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm));
3703 pipe++) {
3704 for (queue = 0;
3705 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
3706 queue++) {
3707 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
3708 dqm->dev->adev, pipe, queue, &dump, &n_regs);
3709 if (r)
3710 break;
3711
3712 seq_printf(m, " SDMA Engine %d, RLC %d\n",
3713 pipe, queue);
3714 seq_reg_dump(m, dump, n_regs);
3715
3716 kfree(dump);
3717 }
3718 }
3719
3720 return r;
3721}
3722
3723int dqm_debugfs_hang_hws(struct device_queue_manager *dqm)
3724{
3725 int r = 0;
3726
3727 dqm_lock(dqm);
3728 r = pm_debugfs_hang_hws(&dqm->packet_mgr);
3729 if (r) {
3730 dqm_unlock(dqm);
3731 return r;
3732 }
3733 dqm->active_runlist = true;
3734 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
3735 0, USE_DEFAULT_GRACE_PERIOD);
3736 dqm_unlock(dqm);
3737
3738 return r;
3739}
3740
3741#endif
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/ratelimit.h>
25#include <linux/printk.h>
26#include <linux/slab.h>
27#include <linux/list.h>
28#include <linux/types.h>
29#include <linux/bitops.h>
30#include <linux/sched.h>
31#include "kfd_priv.h"
32#include "kfd_device_queue_manager.h"
33#include "kfd_mqd_manager.h"
34#include "cik_regs.h"
35#include "kfd_kernel_queue.h"
36#include "amdgpu_amdkfd.h"
37
38/* Size of the per-pipe EOP queue */
39#define CIK_HPD_EOP_BYTES_LOG2 11
40#define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
41
42static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
43 unsigned int pasid, unsigned int vmid);
44
45static int execute_queues_cpsch(struct device_queue_manager *dqm,
46 enum kfd_unmap_queues_filter filter,
47 uint32_t filter_param);
48static int unmap_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param);
51
52static int map_queues_cpsch(struct device_queue_manager *dqm);
53
54static void deallocate_sdma_queue(struct device_queue_manager *dqm,
55 struct queue *q);
56
57static inline void deallocate_hqd(struct device_queue_manager *dqm,
58 struct queue *q);
59static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
60static int allocate_sdma_queue(struct device_queue_manager *dqm,
61 struct queue *q);
62static void kfd_process_hw_exception(struct work_struct *work);
63
64static inline
65enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
66{
67 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
68 return KFD_MQD_TYPE_SDMA;
69 return KFD_MQD_TYPE_CP;
70}
71
72static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
73{
74 int i;
75 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
76 + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
77
78 /* queue is available for KFD usage if bit is 1 */
79 for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
80 if (test_bit(pipe_offset + i,
81 dqm->dev->shared_resources.queue_bitmap))
82 return true;
83 return false;
84}
85
86unsigned int get_queues_num(struct device_queue_manager *dqm)
87{
88 return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
89 KGD_MAX_QUEUES);
90}
91
92unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
93{
94 return dqm->dev->shared_resources.num_queue_per_pipe;
95}
96
97unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
98{
99 return dqm->dev->shared_resources.num_pipe_per_mec;
100}
101
102static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
103{
104 return dqm->dev->device_info->num_sdma_engines;
105}
106
107static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm)
108{
109 return dqm->dev->device_info->num_xgmi_sdma_engines;
110}
111
112unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
113{
114 return dqm->dev->device_info->num_sdma_engines
115 * dqm->dev->device_info->num_sdma_queues_per_engine;
116}
117
118unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
119{
120 return dqm->dev->device_info->num_xgmi_sdma_engines
121 * dqm->dev->device_info->num_sdma_queues_per_engine;
122}
123
124void program_sh_mem_settings(struct device_queue_manager *dqm,
125 struct qcm_process_device *qpd)
126{
127 return dqm->dev->kfd2kgd->program_sh_mem_settings(
128 dqm->dev->kgd, qpd->vmid,
129 qpd->sh_mem_config,
130 qpd->sh_mem_ape1_base,
131 qpd->sh_mem_ape1_limit,
132 qpd->sh_mem_bases);
133}
134
135static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
136{
137 struct kfd_dev *dev = qpd->dqm->dev;
138
139 if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
140 /* On pre-SOC15 chips we need to use the queue ID to
141 * preserve the user mode ABI.
142 */
143 q->doorbell_id = q->properties.queue_id;
144 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
145 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
146 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
147 * doorbell assignments based on the engine and queue id.
148 * The doobell index distance between RLC (2*i) and (2*i+1)
149 * for a SDMA engine is 512.
150 */
151 uint32_t *idx_offset =
152 dev->shared_resources.sdma_doorbell_idx;
153
154 q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
155 + (q->properties.sdma_queue_id & 1)
156 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
157 + (q->properties.sdma_queue_id >> 1);
158 } else {
159 /* For CP queues on SOC15 reserve a free doorbell ID */
160 unsigned int found;
161
162 found = find_first_zero_bit(qpd->doorbell_bitmap,
163 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
164 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
165 pr_debug("No doorbells available");
166 return -EBUSY;
167 }
168 set_bit(found, qpd->doorbell_bitmap);
169 q->doorbell_id = found;
170 }
171
172 q->properties.doorbell_off =
173 kfd_doorbell_id_to_offset(dev, q->process,
174 q->doorbell_id);
175
176 return 0;
177}
178
179static void deallocate_doorbell(struct qcm_process_device *qpd,
180 struct queue *q)
181{
182 unsigned int old;
183 struct kfd_dev *dev = qpd->dqm->dev;
184
185 if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
186 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
187 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
188 return;
189
190 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
191 WARN_ON(!old);
192}
193
194static int allocate_vmid(struct device_queue_manager *dqm,
195 struct qcm_process_device *qpd,
196 struct queue *q)
197{
198 int bit, allocated_vmid;
199
200 if (dqm->vmid_bitmap == 0)
201 return -ENOMEM;
202
203 bit = ffs(dqm->vmid_bitmap) - 1;
204 dqm->vmid_bitmap &= ~(1 << bit);
205
206 allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
207 pr_debug("vmid allocation %d\n", allocated_vmid);
208 qpd->vmid = allocated_vmid;
209 q->properties.vmid = allocated_vmid;
210
211 set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
212 program_sh_mem_settings(dqm, qpd);
213
214 /* qpd->page_table_base is set earlier when register_process()
215 * is called, i.e. when the first queue is created.
216 */
217 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
218 qpd->vmid,
219 qpd->page_table_base);
220 /* invalidate the VM context after pasid and vmid mapping is set up */
221 kfd_flush_tlb(qpd_to_pdd(qpd));
222
223 dqm->dev->kfd2kgd->set_scratch_backing_va(
224 dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
225
226 return 0;
227}
228
229static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
230 struct qcm_process_device *qpd)
231{
232 const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
233 int ret;
234
235 if (!qpd->ib_kaddr)
236 return -ENOMEM;
237
238 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
239 if (ret)
240 return ret;
241
242 return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
243 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
244 pmf->release_mem_size / sizeof(uint32_t));
245}
246
247static void deallocate_vmid(struct device_queue_manager *dqm,
248 struct qcm_process_device *qpd,
249 struct queue *q)
250{
251 int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
252
253 /* On GFX v7, CP doesn't flush TC at dequeue */
254 if (q->device->device_info->asic_family == CHIP_HAWAII)
255 if (flush_texture_cache_nocpsch(q->device, qpd))
256 pr_err("Failed to flush TC\n");
257
258 kfd_flush_tlb(qpd_to_pdd(qpd));
259
260 /* Release the vmid mapping */
261 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
262
263 dqm->vmid_bitmap |= (1 << bit);
264 qpd->vmid = 0;
265 q->properties.vmid = 0;
266}
267
268static int create_queue_nocpsch(struct device_queue_manager *dqm,
269 struct queue *q,
270 struct qcm_process_device *qpd)
271{
272 struct mqd_manager *mqd_mgr;
273 int retval;
274
275 print_queue(q);
276
277 dqm_lock(dqm);
278
279 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
280 pr_warn("Can't create new usermode queue because %d queues were already created\n",
281 dqm->total_queue_count);
282 retval = -EPERM;
283 goto out_unlock;
284 }
285
286 if (list_empty(&qpd->queues_list)) {
287 retval = allocate_vmid(dqm, qpd, q);
288 if (retval)
289 goto out_unlock;
290 }
291 q->properties.vmid = qpd->vmid;
292 /*
293 * Eviction state logic: mark all queues as evicted, even ones
294 * not currently active. Restoring inactive queues later only
295 * updates the is_evicted flag but is a no-op otherwise.
296 */
297 q->properties.is_evicted = !!qpd->evicted;
298
299 q->properties.tba_addr = qpd->tba_addr;
300 q->properties.tma_addr = qpd->tma_addr;
301
302 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
303 q->properties.type)];
304 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
305 retval = allocate_hqd(dqm, q);
306 if (retval)
307 goto deallocate_vmid;
308 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
309 q->pipe, q->queue);
310 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
311 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
312 retval = allocate_sdma_queue(dqm, q);
313 if (retval)
314 goto deallocate_vmid;
315 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
316 }
317
318 retval = allocate_doorbell(qpd, q);
319 if (retval)
320 goto out_deallocate_hqd;
321
322 /* Temporarily release dqm lock to avoid a circular lock dependency */
323 dqm_unlock(dqm);
324 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
325 dqm_lock(dqm);
326
327 if (!q->mqd_mem_obj) {
328 retval = -ENOMEM;
329 goto out_deallocate_doorbell;
330 }
331 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
332 &q->gart_mqd_addr, &q->properties);
333 if (q->properties.is_active) {
334
335 if (WARN(q->process->mm != current->mm,
336 "should only run in user thread"))
337 retval = -EFAULT;
338 else
339 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
340 q->queue, &q->properties, current->mm);
341 if (retval)
342 goto out_free_mqd;
343 }
344
345 list_add(&q->list, &qpd->queues_list);
346 qpd->queue_count++;
347 if (q->properties.is_active)
348 dqm->queue_count++;
349
350 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
351 dqm->sdma_queue_count++;
352 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
353 dqm->xgmi_sdma_queue_count++;
354
355 /*
356 * Unconditionally increment this counter, regardless of the queue's
357 * type or whether the queue is active.
358 */
359 dqm->total_queue_count++;
360 pr_debug("Total of %d queues are accountable so far\n",
361 dqm->total_queue_count);
362 goto out_unlock;
363
364out_free_mqd:
365 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
366out_deallocate_doorbell:
367 deallocate_doorbell(qpd, q);
368out_deallocate_hqd:
369 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
370 deallocate_hqd(dqm, q);
371 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
372 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
373 deallocate_sdma_queue(dqm, q);
374deallocate_vmid:
375 if (list_empty(&qpd->queues_list))
376 deallocate_vmid(dqm, qpd, q);
377out_unlock:
378 dqm_unlock(dqm);
379 return retval;
380}
381
382static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
383{
384 bool set;
385 int pipe, bit, i;
386
387 set = false;
388
389 for (pipe = dqm->next_pipe_to_allocate, i = 0;
390 i < get_pipes_per_mec(dqm);
391 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
392
393 if (!is_pipe_enabled(dqm, 0, pipe))
394 continue;
395
396 if (dqm->allocated_queues[pipe] != 0) {
397 bit = ffs(dqm->allocated_queues[pipe]) - 1;
398 dqm->allocated_queues[pipe] &= ~(1 << bit);
399 q->pipe = pipe;
400 q->queue = bit;
401 set = true;
402 break;
403 }
404 }
405
406 if (!set)
407 return -EBUSY;
408
409 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
410 /* horizontal hqd allocation */
411 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
412
413 return 0;
414}
415
416static inline void deallocate_hqd(struct device_queue_manager *dqm,
417 struct queue *q)
418{
419 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
420}
421
422/* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
423 * to avoid asynchronized access
424 */
425static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
426 struct qcm_process_device *qpd,
427 struct queue *q)
428{
429 int retval;
430 struct mqd_manager *mqd_mgr;
431
432 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
433 q->properties.type)];
434
435 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
436 deallocate_hqd(dqm, q);
437 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
438 dqm->sdma_queue_count--;
439 deallocate_sdma_queue(dqm, q);
440 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
441 dqm->xgmi_sdma_queue_count--;
442 deallocate_sdma_queue(dqm, q);
443 } else {
444 pr_debug("q->properties.type %d is invalid\n",
445 q->properties.type);
446 return -EINVAL;
447 }
448 dqm->total_queue_count--;
449
450 deallocate_doorbell(qpd, q);
451
452 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
453 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
454 KFD_UNMAP_LATENCY_MS,
455 q->pipe, q->queue);
456 if (retval == -ETIME)
457 qpd->reset_wavefronts = true;
458
459 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
460
461 list_del(&q->list);
462 if (list_empty(&qpd->queues_list)) {
463 if (qpd->reset_wavefronts) {
464 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
465 dqm->dev);
466 /* dbgdev_wave_reset_wavefronts has to be called before
467 * deallocate_vmid(), i.e. when vmid is still in use.
468 */
469 dbgdev_wave_reset_wavefronts(dqm->dev,
470 qpd->pqm->process);
471 qpd->reset_wavefronts = false;
472 }
473
474 deallocate_vmid(dqm, qpd, q);
475 }
476 qpd->queue_count--;
477 if (q->properties.is_active)
478 dqm->queue_count--;
479
480 return retval;
481}
482
483static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
484 struct qcm_process_device *qpd,
485 struct queue *q)
486{
487 int retval;
488
489 dqm_lock(dqm);
490 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
491 dqm_unlock(dqm);
492
493 return retval;
494}
495
496static int update_queue(struct device_queue_manager *dqm, struct queue *q)
497{
498 int retval = 0;
499 struct mqd_manager *mqd_mgr;
500 struct kfd_process_device *pdd;
501 bool prev_active = false;
502
503 dqm_lock(dqm);
504 pdd = kfd_get_process_device_data(q->device, q->process);
505 if (!pdd) {
506 retval = -ENODEV;
507 goto out_unlock;
508 }
509 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
510 q->properties.type)];
511
512 /* Save previous activity state for counters */
513 prev_active = q->properties.is_active;
514
515 /* Make sure the queue is unmapped before updating the MQD */
516 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
517 retval = unmap_queues_cpsch(dqm,
518 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
519 if (retval) {
520 pr_err("unmap queue failed\n");
521 goto out_unlock;
522 }
523 } else if (prev_active &&
524 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
525 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
526 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
527 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
528 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
529 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
530 if (retval) {
531 pr_err("destroy mqd failed\n");
532 goto out_unlock;
533 }
534 }
535
536 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties);
537
538 /*
539 * check active state vs. the previous state and modify
540 * counter accordingly. map_queues_cpsch uses the
541 * dqm->queue_count to determine whether a new runlist must be
542 * uploaded.
543 */
544 if (q->properties.is_active && !prev_active)
545 dqm->queue_count++;
546 else if (!q->properties.is_active && prev_active)
547 dqm->queue_count--;
548
549 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
550 retval = map_queues_cpsch(dqm);
551 else if (q->properties.is_active &&
552 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
553 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
554 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
555 if (WARN(q->process->mm != current->mm,
556 "should only run in user thread"))
557 retval = -EFAULT;
558 else
559 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
560 q->pipe, q->queue,
561 &q->properties, current->mm);
562 }
563
564out_unlock:
565 dqm_unlock(dqm);
566 return retval;
567}
568
569static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
570 struct qcm_process_device *qpd)
571{
572 struct queue *q;
573 struct mqd_manager *mqd_mgr;
574 struct kfd_process_device *pdd;
575 int retval, ret = 0;
576
577 dqm_lock(dqm);
578 if (qpd->evicted++ > 0) /* already evicted, do nothing */
579 goto out;
580
581 pdd = qpd_to_pdd(qpd);
582 pr_info_ratelimited("Evicting PASID %u queues\n",
583 pdd->process->pasid);
584
585 /* Mark all queues as evicted. Deactivate all active queues on
586 * the qpd.
587 */
588 list_for_each_entry(q, &qpd->queues_list, list) {
589 q->properties.is_evicted = true;
590 if (!q->properties.is_active)
591 continue;
592
593 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
594 q->properties.type)];
595 q->properties.is_active = false;
596 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
597 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
598 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
599 if (retval && !ret)
600 /* Return the first error, but keep going to
601 * maintain a consistent eviction state
602 */
603 ret = retval;
604 dqm->queue_count--;
605 }
606
607out:
608 dqm_unlock(dqm);
609 return ret;
610}
611
612static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
613 struct qcm_process_device *qpd)
614{
615 struct queue *q;
616 struct kfd_process_device *pdd;
617 int retval = 0;
618
619 dqm_lock(dqm);
620 if (qpd->evicted++ > 0) /* already evicted, do nothing */
621 goto out;
622
623 pdd = qpd_to_pdd(qpd);
624 pr_info_ratelimited("Evicting PASID %u queues\n",
625 pdd->process->pasid);
626
627 /* Mark all queues as evicted. Deactivate all active queues on
628 * the qpd.
629 */
630 list_for_each_entry(q, &qpd->queues_list, list) {
631 q->properties.is_evicted = true;
632 if (!q->properties.is_active)
633 continue;
634
635 q->properties.is_active = false;
636 dqm->queue_count--;
637 }
638 retval = execute_queues_cpsch(dqm,
639 qpd->is_debug ?
640 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
641 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
642
643out:
644 dqm_unlock(dqm);
645 return retval;
646}
647
648static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
649 struct qcm_process_device *qpd)
650{
651 struct mm_struct *mm = NULL;
652 struct queue *q;
653 struct mqd_manager *mqd_mgr;
654 struct kfd_process_device *pdd;
655 uint64_t pd_base;
656 int retval, ret = 0;
657
658 pdd = qpd_to_pdd(qpd);
659 /* Retrieve PD base */
660 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
661
662 dqm_lock(dqm);
663 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
664 goto out;
665 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
666 qpd->evicted--;
667 goto out;
668 }
669
670 pr_info_ratelimited("Restoring PASID %u queues\n",
671 pdd->process->pasid);
672
673 /* Update PD Base in QPD */
674 qpd->page_table_base = pd_base;
675 pr_debug("Updated PD address to 0x%llx\n", pd_base);
676
677 if (!list_empty(&qpd->queues_list)) {
678 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
679 dqm->dev->kgd,
680 qpd->vmid,
681 qpd->page_table_base);
682 kfd_flush_tlb(pdd);
683 }
684
685 /* Take a safe reference to the mm_struct, which may otherwise
686 * disappear even while the kfd_process is still referenced.
687 */
688 mm = get_task_mm(pdd->process->lead_thread);
689 if (!mm) {
690 ret = -EFAULT;
691 goto out;
692 }
693
694 /* Remove the eviction flags. Activate queues that are not
695 * inactive for other reasons.
696 */
697 list_for_each_entry(q, &qpd->queues_list, list) {
698 q->properties.is_evicted = false;
699 if (!QUEUE_IS_ACTIVE(q->properties))
700 continue;
701
702 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
703 q->properties.type)];
704 q->properties.is_active = true;
705 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
706 q->queue, &q->properties, mm);
707 if (retval && !ret)
708 /* Return the first error, but keep going to
709 * maintain a consistent eviction state
710 */
711 ret = retval;
712 dqm->queue_count++;
713 }
714 qpd->evicted = 0;
715out:
716 if (mm)
717 mmput(mm);
718 dqm_unlock(dqm);
719 return ret;
720}
721
722static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
723 struct qcm_process_device *qpd)
724{
725 struct queue *q;
726 struct kfd_process_device *pdd;
727 uint64_t pd_base;
728 int retval = 0;
729
730 pdd = qpd_to_pdd(qpd);
731 /* Retrieve PD base */
732 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
733
734 dqm_lock(dqm);
735 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
736 goto out;
737 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
738 qpd->evicted--;
739 goto out;
740 }
741
742 pr_info_ratelimited("Restoring PASID %u queues\n",
743 pdd->process->pasid);
744
745 /* Update PD Base in QPD */
746 qpd->page_table_base = pd_base;
747 pr_debug("Updated PD address to 0x%llx\n", pd_base);
748
749 /* activate all active queues on the qpd */
750 list_for_each_entry(q, &qpd->queues_list, list) {
751 q->properties.is_evicted = false;
752 if (!QUEUE_IS_ACTIVE(q->properties))
753 continue;
754
755 q->properties.is_active = true;
756 dqm->queue_count++;
757 }
758 retval = execute_queues_cpsch(dqm,
759 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
760 qpd->evicted = 0;
761out:
762 dqm_unlock(dqm);
763 return retval;
764}
765
766static int register_process(struct device_queue_manager *dqm,
767 struct qcm_process_device *qpd)
768{
769 struct device_process_node *n;
770 struct kfd_process_device *pdd;
771 uint64_t pd_base;
772 int retval;
773
774 n = kzalloc(sizeof(*n), GFP_KERNEL);
775 if (!n)
776 return -ENOMEM;
777
778 n->qpd = qpd;
779
780 pdd = qpd_to_pdd(qpd);
781 /* Retrieve PD base */
782 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
783
784 dqm_lock(dqm);
785 list_add(&n->list, &dqm->queues);
786
787 /* Update PD Base in QPD */
788 qpd->page_table_base = pd_base;
789 pr_debug("Updated PD address to 0x%llx\n", pd_base);
790
791 retval = dqm->asic_ops.update_qpd(dqm, qpd);
792
793 dqm->processes_count++;
794
795 dqm_unlock(dqm);
796
797 /* Outside the DQM lock because under the DQM lock we can't do
798 * reclaim or take other locks that others hold while reclaiming.
799 */
800 kfd_inc_compute_active(dqm->dev);
801
802 return retval;
803}
804
805static int unregister_process(struct device_queue_manager *dqm,
806 struct qcm_process_device *qpd)
807{
808 int retval;
809 struct device_process_node *cur, *next;
810
811 pr_debug("qpd->queues_list is %s\n",
812 list_empty(&qpd->queues_list) ? "empty" : "not empty");
813
814 retval = 0;
815 dqm_lock(dqm);
816
817 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
818 if (qpd == cur->qpd) {
819 list_del(&cur->list);
820 kfree(cur);
821 dqm->processes_count--;
822 goto out;
823 }
824 }
825 /* qpd not found in dqm list */
826 retval = 1;
827out:
828 dqm_unlock(dqm);
829
830 /* Outside the DQM lock because under the DQM lock we can't do
831 * reclaim or take other locks that others hold while reclaiming.
832 */
833 if (!retval)
834 kfd_dec_compute_active(dqm->dev);
835
836 return retval;
837}
838
839static int
840set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
841 unsigned int vmid)
842{
843 return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
844 dqm->dev->kgd, pasid, vmid);
845}
846
847static void init_interrupts(struct device_queue_manager *dqm)
848{
849 unsigned int i;
850
851 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
852 if (is_pipe_enabled(dqm, 0, i))
853 dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
854}
855
856static int initialize_nocpsch(struct device_queue_manager *dqm)
857{
858 int pipe, queue;
859
860 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
861
862 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
863 sizeof(unsigned int), GFP_KERNEL);
864 if (!dqm->allocated_queues)
865 return -ENOMEM;
866
867 mutex_init(&dqm->lock_hidden);
868 INIT_LIST_HEAD(&dqm->queues);
869 dqm->queue_count = dqm->next_pipe_to_allocate = 0;
870 dqm->sdma_queue_count = 0;
871 dqm->xgmi_sdma_queue_count = 0;
872
873 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
874 int pipe_offset = pipe * get_queues_per_pipe(dqm);
875
876 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
877 if (test_bit(pipe_offset + queue,
878 dqm->dev->shared_resources.queue_bitmap))
879 dqm->allocated_queues[pipe] |= 1 << queue;
880 }
881
882 dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
883 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
884 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
885
886 return 0;
887}
888
889static void uninitialize(struct device_queue_manager *dqm)
890{
891 int i;
892
893 WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
894
895 kfree(dqm->allocated_queues);
896 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
897 kfree(dqm->mqd_mgrs[i]);
898 mutex_destroy(&dqm->lock_hidden);
899 kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
900}
901
902static int start_nocpsch(struct device_queue_manager *dqm)
903{
904 init_interrupts(dqm);
905 return pm_init(&dqm->packets, dqm);
906}
907
908static int stop_nocpsch(struct device_queue_manager *dqm)
909{
910 pm_uninit(&dqm->packets);
911 return 0;
912}
913
914static int allocate_sdma_queue(struct device_queue_manager *dqm,
915 struct queue *q)
916{
917 int bit;
918
919 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
920 if (dqm->sdma_bitmap == 0)
921 return -ENOMEM;
922 bit = __ffs64(dqm->sdma_bitmap);
923 dqm->sdma_bitmap &= ~(1ULL << bit);
924 q->sdma_id = bit;
925 q->properties.sdma_engine_id = q->sdma_id %
926 get_num_sdma_engines(dqm);
927 q->properties.sdma_queue_id = q->sdma_id /
928 get_num_sdma_engines(dqm);
929 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
930 if (dqm->xgmi_sdma_bitmap == 0)
931 return -ENOMEM;
932 bit = __ffs64(dqm->xgmi_sdma_bitmap);
933 dqm->xgmi_sdma_bitmap &= ~(1ULL << bit);
934 q->sdma_id = bit;
935 /* sdma_engine_id is sdma id including
936 * both PCIe-optimized SDMAs and XGMI-
937 * optimized SDMAs. The calculation below
938 * assumes the first N engines are always
939 * PCIe-optimized ones
940 */
941 q->properties.sdma_engine_id = get_num_sdma_engines(dqm) +
942 q->sdma_id % get_num_xgmi_sdma_engines(dqm);
943 q->properties.sdma_queue_id = q->sdma_id /
944 get_num_xgmi_sdma_engines(dqm);
945 }
946
947 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
948 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
949
950 return 0;
951}
952
953static void deallocate_sdma_queue(struct device_queue_manager *dqm,
954 struct queue *q)
955{
956 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
957 if (q->sdma_id >= get_num_sdma_queues(dqm))
958 return;
959 dqm->sdma_bitmap |= (1ULL << q->sdma_id);
960 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
961 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
962 return;
963 dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id);
964 }
965}
966
967/*
968 * Device Queue Manager implementation for cp scheduler
969 */
970
971static int set_sched_resources(struct device_queue_manager *dqm)
972{
973 int i, mec;
974 struct scheduling_resources res;
975
976 res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
977
978 res.queue_mask = 0;
979 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
980 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
981 / dqm->dev->shared_resources.num_pipe_per_mec;
982
983 if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
984 continue;
985
986 /* only acquire queues from the first MEC */
987 if (mec > 0)
988 continue;
989
990 /* This situation may be hit in the future if a new HW
991 * generation exposes more than 64 queues. If so, the
992 * definition of res.queue_mask needs updating
993 */
994 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
995 pr_err("Invalid queue enabled by amdgpu: %d\n", i);
996 break;
997 }
998
999 res.queue_mask |= (1ull << i);
1000 }
1001 res.gws_mask = ~0ull;
1002 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1003
1004 pr_debug("Scheduling resources:\n"
1005 "vmid mask: 0x%8X\n"
1006 "queue mask: 0x%8llX\n",
1007 res.vmid_mask, res.queue_mask);
1008
1009 return pm_send_set_resources(&dqm->packets, &res);
1010}
1011
1012static int initialize_cpsch(struct device_queue_manager *dqm)
1013{
1014 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1015
1016 mutex_init(&dqm->lock_hidden);
1017 INIT_LIST_HEAD(&dqm->queues);
1018 dqm->queue_count = dqm->processes_count = 0;
1019 dqm->sdma_queue_count = 0;
1020 dqm->xgmi_sdma_queue_count = 0;
1021 dqm->active_runlist = false;
1022 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
1023 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
1024
1025 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1026
1027 return 0;
1028}
1029
1030static int start_cpsch(struct device_queue_manager *dqm)
1031{
1032 int retval;
1033
1034 retval = 0;
1035
1036 retval = pm_init(&dqm->packets, dqm);
1037 if (retval)
1038 goto fail_packet_manager_init;
1039
1040 retval = set_sched_resources(dqm);
1041 if (retval)
1042 goto fail_set_sched_resources;
1043
1044 pr_debug("Allocating fence memory\n");
1045
1046 /* allocate fence memory on the gart */
1047 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1048 &dqm->fence_mem);
1049
1050 if (retval)
1051 goto fail_allocate_vidmem;
1052
1053 dqm->fence_addr = dqm->fence_mem->cpu_ptr;
1054 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1055
1056 init_interrupts(dqm);
1057
1058 dqm_lock(dqm);
1059 /* clear hang status when driver try to start the hw scheduler */
1060 dqm->is_hws_hang = false;
1061 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1062 dqm_unlock(dqm);
1063
1064 return 0;
1065fail_allocate_vidmem:
1066fail_set_sched_resources:
1067 pm_uninit(&dqm->packets);
1068fail_packet_manager_init:
1069 return retval;
1070}
1071
1072static int stop_cpsch(struct device_queue_manager *dqm)
1073{
1074 dqm_lock(dqm);
1075 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1076 dqm_unlock(dqm);
1077
1078 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1079 pm_uninit(&dqm->packets);
1080
1081 return 0;
1082}
1083
1084static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1085 struct kernel_queue *kq,
1086 struct qcm_process_device *qpd)
1087{
1088 dqm_lock(dqm);
1089 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1090 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1091 dqm->total_queue_count);
1092 dqm_unlock(dqm);
1093 return -EPERM;
1094 }
1095
1096 /*
1097 * Unconditionally increment this counter, regardless of the queue's
1098 * type or whether the queue is active.
1099 */
1100 dqm->total_queue_count++;
1101 pr_debug("Total of %d queues are accountable so far\n",
1102 dqm->total_queue_count);
1103
1104 list_add(&kq->list, &qpd->priv_queue_list);
1105 dqm->queue_count++;
1106 qpd->is_debug = true;
1107 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1108 dqm_unlock(dqm);
1109
1110 return 0;
1111}
1112
1113static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1114 struct kernel_queue *kq,
1115 struct qcm_process_device *qpd)
1116{
1117 dqm_lock(dqm);
1118 list_del(&kq->list);
1119 dqm->queue_count--;
1120 qpd->is_debug = false;
1121 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1122 /*
1123 * Unconditionally decrement this counter, regardless of the queue's
1124 * type.
1125 */
1126 dqm->total_queue_count--;
1127 pr_debug("Total of %d queues are accountable so far\n",
1128 dqm->total_queue_count);
1129 dqm_unlock(dqm);
1130}
1131
1132static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1133 struct qcm_process_device *qpd)
1134{
1135 int retval;
1136 struct mqd_manager *mqd_mgr;
1137
1138 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1139 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1140 dqm->total_queue_count);
1141 retval = -EPERM;
1142 goto out;
1143 }
1144
1145 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1146 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1147 dqm_lock(dqm);
1148 retval = allocate_sdma_queue(dqm, q);
1149 dqm_unlock(dqm);
1150 if (retval)
1151 goto out;
1152 }
1153
1154 retval = allocate_doorbell(qpd, q);
1155 if (retval)
1156 goto out_deallocate_sdma_queue;
1157
1158 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1159 q->properties.type)];
1160
1161 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1162 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1163 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1164 q->properties.tba_addr = qpd->tba_addr;
1165 q->properties.tma_addr = qpd->tma_addr;
1166 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1167 if (!q->mqd_mem_obj) {
1168 retval = -ENOMEM;
1169 goto out_deallocate_doorbell;
1170 }
1171
1172 dqm_lock(dqm);
1173 /*
1174 * Eviction state logic: mark all queues as evicted, even ones
1175 * not currently active. Restoring inactive queues later only
1176 * updates the is_evicted flag but is a no-op otherwise.
1177 */
1178 q->properties.is_evicted = !!qpd->evicted;
1179 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1180 &q->gart_mqd_addr, &q->properties);
1181
1182 list_add(&q->list, &qpd->queues_list);
1183 qpd->queue_count++;
1184 if (q->properties.is_active) {
1185 dqm->queue_count++;
1186 retval = execute_queues_cpsch(dqm,
1187 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1188 }
1189
1190 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
1191 dqm->sdma_queue_count++;
1192 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1193 dqm->xgmi_sdma_queue_count++;
1194 /*
1195 * Unconditionally increment this counter, regardless of the queue's
1196 * type or whether the queue is active.
1197 */
1198 dqm->total_queue_count++;
1199
1200 pr_debug("Total of %d queues are accountable so far\n",
1201 dqm->total_queue_count);
1202
1203 dqm_unlock(dqm);
1204 return retval;
1205
1206out_deallocate_doorbell:
1207 deallocate_doorbell(qpd, q);
1208out_deallocate_sdma_queue:
1209 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1210 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1211 dqm_lock(dqm);
1212 deallocate_sdma_queue(dqm, q);
1213 dqm_unlock(dqm);
1214 }
1215out:
1216 return retval;
1217}
1218
1219int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
1220 unsigned int fence_value,
1221 unsigned int timeout_ms)
1222{
1223 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1224
1225 while (*fence_addr != fence_value) {
1226 if (time_after(jiffies, end_jiffies)) {
1227 pr_err("qcm fence wait loop timeout expired\n");
1228 /* In HWS case, this is used to halt the driver thread
1229 * in order not to mess up CP states before doing
1230 * scandumps for FW debugging.
1231 */
1232 while (halt_if_hws_hang)
1233 schedule();
1234
1235 return -ETIME;
1236 }
1237 schedule();
1238 }
1239
1240 return 0;
1241}
1242
1243static int unmap_sdma_queues(struct device_queue_manager *dqm)
1244{
1245 int i, retval = 0;
1246
1247 for (i = 0; i < dqm->dev->device_info->num_sdma_engines +
1248 dqm->dev->device_info->num_xgmi_sdma_engines; i++) {
1249 retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
1250 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false, i);
1251 if (retval)
1252 return retval;
1253 }
1254 return retval;
1255}
1256
1257/* dqm->lock mutex has to be locked before calling this function */
1258static int map_queues_cpsch(struct device_queue_manager *dqm)
1259{
1260 int retval;
1261
1262 if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
1263 return 0;
1264
1265 if (dqm->active_runlist)
1266 return 0;
1267
1268 retval = pm_send_runlist(&dqm->packets, &dqm->queues);
1269 pr_debug("%s sent runlist\n", __func__);
1270 if (retval) {
1271 pr_err("failed to execute runlist\n");
1272 return retval;
1273 }
1274 dqm->active_runlist = true;
1275
1276 return retval;
1277}
1278
1279/* dqm->lock mutex has to be locked before calling this function */
1280static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1281 enum kfd_unmap_queues_filter filter,
1282 uint32_t filter_param)
1283{
1284 int retval = 0;
1285
1286 if (dqm->is_hws_hang)
1287 return -EIO;
1288 if (!dqm->active_runlist)
1289 return retval;
1290
1291 pr_debug("Before destroying queues, sdma queue count is : %u, xgmi sdma queue count is : %u\n",
1292 dqm->sdma_queue_count, dqm->xgmi_sdma_queue_count);
1293
1294 if (dqm->sdma_queue_count > 0 || dqm->xgmi_sdma_queue_count)
1295 unmap_sdma_queues(dqm);
1296
1297 retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
1298 filter, filter_param, false, 0);
1299 if (retval)
1300 return retval;
1301
1302 *dqm->fence_addr = KFD_FENCE_INIT;
1303 pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
1304 KFD_FENCE_COMPLETED);
1305 /* should be timed out */
1306 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1307 queue_preemption_timeout_ms);
1308 if (retval)
1309 return retval;
1310
1311 pm_release_ib(&dqm->packets);
1312 dqm->active_runlist = false;
1313
1314 return retval;
1315}
1316
1317/* dqm->lock mutex has to be locked before calling this function */
1318static int execute_queues_cpsch(struct device_queue_manager *dqm,
1319 enum kfd_unmap_queues_filter filter,
1320 uint32_t filter_param)
1321{
1322 int retval;
1323
1324 if (dqm->is_hws_hang)
1325 return -EIO;
1326 retval = unmap_queues_cpsch(dqm, filter, filter_param);
1327 if (retval) {
1328 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1329 dqm->is_hws_hang = true;
1330 schedule_work(&dqm->hw_exception_work);
1331 return retval;
1332 }
1333
1334 return map_queues_cpsch(dqm);
1335}
1336
1337static int destroy_queue_cpsch(struct device_queue_manager *dqm,
1338 struct qcm_process_device *qpd,
1339 struct queue *q)
1340{
1341 int retval;
1342 struct mqd_manager *mqd_mgr;
1343
1344 retval = 0;
1345
1346 /* remove queue from list to prevent rescheduling after preemption */
1347 dqm_lock(dqm);
1348
1349 if (qpd->is_debug) {
1350 /*
1351 * error, currently we do not allow to destroy a queue
1352 * of a currently debugged process
1353 */
1354 retval = -EBUSY;
1355 goto failed_try_destroy_debugged_queue;
1356
1357 }
1358
1359 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1360 q->properties.type)];
1361
1362 deallocate_doorbell(qpd, q);
1363
1364 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1365 dqm->sdma_queue_count--;
1366 deallocate_sdma_queue(dqm, q);
1367 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1368 dqm->xgmi_sdma_queue_count--;
1369 deallocate_sdma_queue(dqm, q);
1370 }
1371
1372 list_del(&q->list);
1373 qpd->queue_count--;
1374 if (q->properties.is_active) {
1375 dqm->queue_count--;
1376 retval = execute_queues_cpsch(dqm,
1377 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1378 if (retval == -ETIME)
1379 qpd->reset_wavefronts = true;
1380 }
1381
1382 /*
1383 * Unconditionally decrement this counter, regardless of the queue's
1384 * type
1385 */
1386 dqm->total_queue_count--;
1387 pr_debug("Total of %d queues are accountable so far\n",
1388 dqm->total_queue_count);
1389
1390 dqm_unlock(dqm);
1391
1392 /* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */
1393 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1394
1395 return retval;
1396
1397failed_try_destroy_debugged_queue:
1398
1399 dqm_unlock(dqm);
1400 return retval;
1401}
1402
1403/*
1404 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
1405 * stay in user mode.
1406 */
1407#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
1408/* APE1 limit is inclusive and 64K aligned. */
1409#define APE1_LIMIT_ALIGNMENT 0xFFFF
1410
1411static bool set_cache_memory_policy(struct device_queue_manager *dqm,
1412 struct qcm_process_device *qpd,
1413 enum cache_policy default_policy,
1414 enum cache_policy alternate_policy,
1415 void __user *alternate_aperture_base,
1416 uint64_t alternate_aperture_size)
1417{
1418 bool retval = true;
1419
1420 if (!dqm->asic_ops.set_cache_memory_policy)
1421 return retval;
1422
1423 dqm_lock(dqm);
1424
1425 if (alternate_aperture_size == 0) {
1426 /* base > limit disables APE1 */
1427 qpd->sh_mem_ape1_base = 1;
1428 qpd->sh_mem_ape1_limit = 0;
1429 } else {
1430 /*
1431 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
1432 * SH_MEM_APE1_BASE[31:0], 0x0000 }
1433 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
1434 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
1435 * Verify that the base and size parameters can be
1436 * represented in this format and convert them.
1437 * Additionally restrict APE1 to user-mode addresses.
1438 */
1439
1440 uint64_t base = (uintptr_t)alternate_aperture_base;
1441 uint64_t limit = base + alternate_aperture_size - 1;
1442
1443 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
1444 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
1445 retval = false;
1446 goto out;
1447 }
1448
1449 qpd->sh_mem_ape1_base = base >> 16;
1450 qpd->sh_mem_ape1_limit = limit >> 16;
1451 }
1452
1453 retval = dqm->asic_ops.set_cache_memory_policy(
1454 dqm,
1455 qpd,
1456 default_policy,
1457 alternate_policy,
1458 alternate_aperture_base,
1459 alternate_aperture_size);
1460
1461 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
1462 program_sh_mem_settings(dqm, qpd);
1463
1464 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
1465 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
1466 qpd->sh_mem_ape1_limit);
1467
1468out:
1469 dqm_unlock(dqm);
1470 return retval;
1471}
1472
1473static int set_trap_handler(struct device_queue_manager *dqm,
1474 struct qcm_process_device *qpd,
1475 uint64_t tba_addr,
1476 uint64_t tma_addr)
1477{
1478 uint64_t *tma;
1479
1480 if (dqm->dev->cwsr_enabled) {
1481 /* Jump from CWSR trap handler to user trap */
1482 tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
1483 tma[0] = tba_addr;
1484 tma[1] = tma_addr;
1485 } else {
1486 qpd->tba_addr = tba_addr;
1487 qpd->tma_addr = tma_addr;
1488 }
1489
1490 return 0;
1491}
1492
1493static int process_termination_nocpsch(struct device_queue_manager *dqm,
1494 struct qcm_process_device *qpd)
1495{
1496 struct queue *q, *next;
1497 struct device_process_node *cur, *next_dpn;
1498 int retval = 0;
1499 bool found = false;
1500
1501 dqm_lock(dqm);
1502
1503 /* Clear all user mode queues */
1504 list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1505 int ret;
1506
1507 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
1508 if (ret)
1509 retval = ret;
1510 }
1511
1512 /* Unregister process */
1513 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1514 if (qpd == cur->qpd) {
1515 list_del(&cur->list);
1516 kfree(cur);
1517 dqm->processes_count--;
1518 found = true;
1519 break;
1520 }
1521 }
1522
1523 dqm_unlock(dqm);
1524
1525 /* Outside the DQM lock because under the DQM lock we can't do
1526 * reclaim or take other locks that others hold while reclaiming.
1527 */
1528 if (found)
1529 kfd_dec_compute_active(dqm->dev);
1530
1531 return retval;
1532}
1533
1534static int get_wave_state(struct device_queue_manager *dqm,
1535 struct queue *q,
1536 void __user *ctl_stack,
1537 u32 *ctl_stack_used_size,
1538 u32 *save_area_used_size)
1539{
1540 struct mqd_manager *mqd_mgr;
1541 int r;
1542
1543 dqm_lock(dqm);
1544
1545 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
1546 q->properties.is_active || !q->device->cwsr_enabled) {
1547 r = -EINVAL;
1548 goto dqm_unlock;
1549 }
1550
1551 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
1552
1553 if (!mqd_mgr->get_wave_state) {
1554 r = -EINVAL;
1555 goto dqm_unlock;
1556 }
1557
1558 r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
1559 ctl_stack_used_size, save_area_used_size);
1560
1561dqm_unlock:
1562 dqm_unlock(dqm);
1563 return r;
1564}
1565
1566static int process_termination_cpsch(struct device_queue_manager *dqm,
1567 struct qcm_process_device *qpd)
1568{
1569 int retval;
1570 struct queue *q, *next;
1571 struct kernel_queue *kq, *kq_next;
1572 struct mqd_manager *mqd_mgr;
1573 struct device_process_node *cur, *next_dpn;
1574 enum kfd_unmap_queues_filter filter =
1575 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
1576 bool found = false;
1577
1578 retval = 0;
1579
1580 dqm_lock(dqm);
1581
1582 /* Clean all kernel queues */
1583 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
1584 list_del(&kq->list);
1585 dqm->queue_count--;
1586 qpd->is_debug = false;
1587 dqm->total_queue_count--;
1588 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
1589 }
1590
1591 /* Clear all user mode queues */
1592 list_for_each_entry(q, &qpd->queues_list, list) {
1593 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1594 dqm->sdma_queue_count--;
1595 deallocate_sdma_queue(dqm, q);
1596 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1597 dqm->xgmi_sdma_queue_count--;
1598 deallocate_sdma_queue(dqm, q);
1599 }
1600
1601 if (q->properties.is_active)
1602 dqm->queue_count--;
1603
1604 dqm->total_queue_count--;
1605 }
1606
1607 /* Unregister process */
1608 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1609 if (qpd == cur->qpd) {
1610 list_del(&cur->list);
1611 kfree(cur);
1612 dqm->processes_count--;
1613 found = true;
1614 break;
1615 }
1616 }
1617
1618 retval = execute_queues_cpsch(dqm, filter, 0);
1619 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
1620 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
1621 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
1622 qpd->reset_wavefronts = false;
1623 }
1624
1625 dqm_unlock(dqm);
1626
1627 /* Outside the DQM lock because under the DQM lock we can't do
1628 * reclaim or take other locks that others hold while reclaiming.
1629 */
1630 if (found)
1631 kfd_dec_compute_active(dqm->dev);
1632
1633 /* Lastly, free mqd resources.
1634 * Do free_mqd() after dqm_unlock to avoid circular locking.
1635 */
1636 list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1637 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1638 q->properties.type)];
1639 list_del(&q->list);
1640 qpd->queue_count--;
1641 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1642 }
1643
1644 return retval;
1645}
1646
1647static int init_mqd_managers(struct device_queue_manager *dqm)
1648{
1649 int i, j;
1650 struct mqd_manager *mqd_mgr;
1651
1652 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
1653 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
1654 if (!mqd_mgr) {
1655 pr_err("mqd manager [%d] initialization failed\n", i);
1656 goto out_free;
1657 }
1658 dqm->mqd_mgrs[i] = mqd_mgr;
1659 }
1660
1661 return 0;
1662
1663out_free:
1664 for (j = 0; j < i; j++) {
1665 kfree(dqm->mqd_mgrs[j]);
1666 dqm->mqd_mgrs[j] = NULL;
1667 }
1668
1669 return -ENOMEM;
1670}
1671
1672/* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
1673static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
1674{
1675 int retval;
1676 struct kfd_dev *dev = dqm->dev;
1677 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
1678 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
1679 dev->device_info->num_sdma_engines *
1680 dev->device_info->num_sdma_queues_per_engine +
1681 dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
1682
1683 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->kgd, size,
1684 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
1685 (void *)&(mem_obj->cpu_ptr), true);
1686
1687 return retval;
1688}
1689
1690struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
1691{
1692 struct device_queue_manager *dqm;
1693
1694 pr_debug("Loading device queue manager\n");
1695
1696 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
1697 if (!dqm)
1698 return NULL;
1699
1700 switch (dev->device_info->asic_family) {
1701 /* HWS is not available on Hawaii. */
1702 case CHIP_HAWAII:
1703 /* HWS depends on CWSR for timely dequeue. CWSR is not
1704 * available on Tonga.
1705 *
1706 * FIXME: This argument also applies to Kaveri.
1707 */
1708 case CHIP_TONGA:
1709 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
1710 break;
1711 default:
1712 dqm->sched_policy = sched_policy;
1713 break;
1714 }
1715
1716 dqm->dev = dev;
1717 switch (dqm->sched_policy) {
1718 case KFD_SCHED_POLICY_HWS:
1719 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
1720 /* initialize dqm for cp scheduling */
1721 dqm->ops.create_queue = create_queue_cpsch;
1722 dqm->ops.initialize = initialize_cpsch;
1723 dqm->ops.start = start_cpsch;
1724 dqm->ops.stop = stop_cpsch;
1725 dqm->ops.destroy_queue = destroy_queue_cpsch;
1726 dqm->ops.update_queue = update_queue;
1727 dqm->ops.register_process = register_process;
1728 dqm->ops.unregister_process = unregister_process;
1729 dqm->ops.uninitialize = uninitialize;
1730 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
1731 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
1732 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1733 dqm->ops.set_trap_handler = set_trap_handler;
1734 dqm->ops.process_termination = process_termination_cpsch;
1735 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
1736 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
1737 dqm->ops.get_wave_state = get_wave_state;
1738 break;
1739 case KFD_SCHED_POLICY_NO_HWS:
1740 /* initialize dqm for no cp scheduling */
1741 dqm->ops.start = start_nocpsch;
1742 dqm->ops.stop = stop_nocpsch;
1743 dqm->ops.create_queue = create_queue_nocpsch;
1744 dqm->ops.destroy_queue = destroy_queue_nocpsch;
1745 dqm->ops.update_queue = update_queue;
1746 dqm->ops.register_process = register_process;
1747 dqm->ops.unregister_process = unregister_process;
1748 dqm->ops.initialize = initialize_nocpsch;
1749 dqm->ops.uninitialize = uninitialize;
1750 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1751 dqm->ops.set_trap_handler = set_trap_handler;
1752 dqm->ops.process_termination = process_termination_nocpsch;
1753 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
1754 dqm->ops.restore_process_queues =
1755 restore_process_queues_nocpsch;
1756 dqm->ops.get_wave_state = get_wave_state;
1757 break;
1758 default:
1759 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
1760 goto out_free;
1761 }
1762
1763 switch (dev->device_info->asic_family) {
1764 case CHIP_CARRIZO:
1765 device_queue_manager_init_vi(&dqm->asic_ops);
1766 break;
1767
1768 case CHIP_KAVERI:
1769 device_queue_manager_init_cik(&dqm->asic_ops);
1770 break;
1771
1772 case CHIP_HAWAII:
1773 device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
1774 break;
1775
1776 case CHIP_TONGA:
1777 case CHIP_FIJI:
1778 case CHIP_POLARIS10:
1779 case CHIP_POLARIS11:
1780 case CHIP_POLARIS12:
1781 case CHIP_VEGAM:
1782 device_queue_manager_init_vi_tonga(&dqm->asic_ops);
1783 break;
1784
1785 case CHIP_VEGA10:
1786 case CHIP_VEGA12:
1787 case CHIP_VEGA20:
1788 case CHIP_RAVEN:
1789 case CHIP_ARCTURUS:
1790 device_queue_manager_init_v9(&dqm->asic_ops);
1791 break;
1792 case CHIP_NAVI10:
1793 device_queue_manager_init_v10_navi10(&dqm->asic_ops);
1794 break;
1795 default:
1796 WARN(1, "Unexpected ASIC family %u",
1797 dev->device_info->asic_family);
1798 goto out_free;
1799 }
1800
1801 if (init_mqd_managers(dqm))
1802 goto out_free;
1803
1804 if (allocate_hiq_sdma_mqd(dqm)) {
1805 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
1806 goto out_free;
1807 }
1808
1809 if (!dqm->ops.initialize(dqm))
1810 return dqm;
1811
1812out_free:
1813 kfree(dqm);
1814 return NULL;
1815}
1816
1817static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev,
1818 struct kfd_mem_obj *mqd)
1819{
1820 WARN(!mqd, "No hiq sdma mqd trunk to free");
1821
1822 amdgpu_amdkfd_free_gtt_mem(dev->kgd, mqd->gtt_mem);
1823}
1824
1825void device_queue_manager_uninit(struct device_queue_manager *dqm)
1826{
1827 dqm->ops.uninitialize(dqm);
1828 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
1829 kfree(dqm);
1830}
1831
1832int kfd_process_vm_fault(struct device_queue_manager *dqm,
1833 unsigned int pasid)
1834{
1835 struct kfd_process_device *pdd;
1836 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
1837 int ret = 0;
1838
1839 if (!p)
1840 return -EINVAL;
1841 pdd = kfd_get_process_device_data(dqm->dev, p);
1842 if (pdd)
1843 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
1844 kfd_unref_process(p);
1845
1846 return ret;
1847}
1848
1849static void kfd_process_hw_exception(struct work_struct *work)
1850{
1851 struct device_queue_manager *dqm = container_of(work,
1852 struct device_queue_manager, hw_exception_work);
1853 amdgpu_amdkfd_gpu_reset(dqm->dev->kgd);
1854}
1855
1856#if defined(CONFIG_DEBUG_FS)
1857
1858static void seq_reg_dump(struct seq_file *m,
1859 uint32_t (*dump)[2], uint32_t n_regs)
1860{
1861 uint32_t i, count;
1862
1863 for (i = 0, count = 0; i < n_regs; i++) {
1864 if (count == 0 ||
1865 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
1866 seq_printf(m, "%s %08x: %08x",
1867 i ? "\n" : "",
1868 dump[i][0], dump[i][1]);
1869 count = 7;
1870 } else {
1871 seq_printf(m, " %08x", dump[i][1]);
1872 count--;
1873 }
1874 }
1875
1876 seq_puts(m, "\n");
1877}
1878
1879int dqm_debugfs_hqds(struct seq_file *m, void *data)
1880{
1881 struct device_queue_manager *dqm = data;
1882 uint32_t (*dump)[2], n_regs;
1883 int pipe, queue;
1884 int r = 0;
1885
1886 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
1887 KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE,
1888 &dump, &n_regs);
1889 if (!r) {
1890 seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n",
1891 KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1,
1892 KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm),
1893 KFD_CIK_HIQ_QUEUE);
1894 seq_reg_dump(m, dump, n_regs);
1895
1896 kfree(dump);
1897 }
1898
1899 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1900 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1901
1902 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
1903 if (!test_bit(pipe_offset + queue,
1904 dqm->dev->shared_resources.queue_bitmap))
1905 continue;
1906
1907 r = dqm->dev->kfd2kgd->hqd_dump(
1908 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
1909 if (r)
1910 break;
1911
1912 seq_printf(m, " CP Pipe %d, Queue %d\n",
1913 pipe, queue);
1914 seq_reg_dump(m, dump, n_regs);
1915
1916 kfree(dump);
1917 }
1918 }
1919
1920 for (pipe = 0; pipe < get_num_sdma_engines(dqm); pipe++) {
1921 for (queue = 0;
1922 queue < dqm->dev->device_info->num_sdma_queues_per_engine;
1923 queue++) {
1924 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
1925 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
1926 if (r)
1927 break;
1928
1929 seq_printf(m, " SDMA Engine %d, RLC %d\n",
1930 pipe, queue);
1931 seq_reg_dump(m, dump, n_regs);
1932
1933 kfree(dump);
1934 }
1935 }
1936
1937 return r;
1938}
1939
1940int dqm_debugfs_execute_queues(struct device_queue_manager *dqm)
1941{
1942 int r = 0;
1943
1944 dqm_lock(dqm);
1945 dqm->active_runlist = true;
1946 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1947 dqm_unlock(dqm);
1948
1949 return r;
1950}
1951
1952#endif