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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <linux/dma-buf.h>
24#include <linux/list.h>
25#include <linux/pagemap.h>
26#include <linux/sched/mm.h>
27#include <linux/sched/task.h>
28#include <drm/ttm/ttm_tt.h>
29
30#include <drm/drm_exec.h>
31
32#include "amdgpu_object.h"
33#include "amdgpu_gem.h"
34#include "amdgpu_vm.h"
35#include "amdgpu_hmm.h"
36#include "amdgpu_amdkfd.h"
37#include "amdgpu_dma_buf.h"
38#include <uapi/linux/kfd_ioctl.h>
39#include "amdgpu_xgmi.h"
40#include "kfd_priv.h"
41#include "kfd_smi_events.h"
42
43/* Userptr restore delay, just long enough to allow consecutive VM
44 * changes to accumulate
45 */
46#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
47#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
48
49/*
50 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
51 * BO chunk
52 */
53#define VRAM_AVAILABLITY_ALIGN (1 << 21)
54
55/* Impose limit on how much memory KFD can use */
56static struct {
57 uint64_t max_system_mem_limit;
58 uint64_t max_ttm_mem_limit;
59 int64_t system_mem_used;
60 int64_t ttm_mem_used;
61 spinlock_t mem_limit_lock;
62} kfd_mem_limit;
63
64static const char * const domain_bit_to_string[] = {
65 "CPU",
66 "GTT",
67 "VRAM",
68 "GDS",
69 "GWS",
70 "OA"
71};
72
73#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
74
75static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
76
77static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
78 struct kgd_mem *mem)
79{
80 struct kfd_mem_attachment *entry;
81
82 list_for_each_entry(entry, &mem->attachments, list)
83 if (entry->bo_va->base.vm == avm)
84 return true;
85
86 return false;
87}
88
89/**
90 * reuse_dmamap() - Check whether adev can share the original
91 * userptr BO
92 *
93 * If both adev and bo_adev are in direct mapping or
94 * in the same iommu group, they can share the original BO.
95 *
96 * @adev: Device to which can or cannot share the original BO
97 * @bo_adev: Device to which allocated BO belongs to
98 *
99 * Return: returns true if adev can share original userptr BO,
100 * false otherwise.
101 */
102static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
103{
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
106}
107
108/* Set memory usage limits. Current, limits are
109 * System (TTM + userptr) memory - 15/16th System RAM
110 * TTM memory - 3/8th System RAM
111 */
112void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
113{
114 struct sysinfo si;
115 uint64_t mem;
116
117 if (kfd_mem_limit.max_system_mem_limit)
118 return;
119
120 si_meminfo(&si);
121 mem = si.totalram - si.totalhigh;
122 mem *= si.mem_unit;
123
124 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
125 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
126 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
127 kfd_mem_limit.max_system_mem_limit >>= 1;
128 else
129 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
130
131 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
132 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
133 (kfd_mem_limit.max_system_mem_limit >> 20),
134 (kfd_mem_limit.max_ttm_mem_limit >> 20));
135}
136
137void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
138{
139 kfd_mem_limit.system_mem_used += size;
140}
141
142/* Estimate page table size needed to represent a given memory size
143 *
144 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
145 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
146 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
147 * for 2MB pages for TLB efficiency. However, small allocations and
148 * fragmented system memory still need some 4KB pages. We choose a
149 * compromise that should work in most cases without reserving too
150 * much memory for page tables unnecessarily (factor 16K, >> 14).
151 */
152
153#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
154
155/**
156 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
157 * of buffer.
158 *
159 * @adev: Device to which allocated BO belongs to
160 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
161 * equivalent to amdgpu_bo_size(BO)
162 * @alloc_flag: Flag used in allocating a BO as noted above
163 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
164 * managed as one compute node in driver for app
165 *
166 * Return:
167 * returns -ENOMEM in case of error, ZERO otherwise
168 */
169int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
170 uint64_t size, u32 alloc_flag, int8_t xcp_id)
171{
172 uint64_t reserved_for_pt =
173 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
174 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
175 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0);
176 size_t system_mem_needed, ttm_mem_needed, vram_needed;
177 int ret = 0;
178 uint64_t vram_size = 0;
179
180 system_mem_needed = 0;
181 ttm_mem_needed = 0;
182 vram_needed = 0;
183 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
184 system_mem_needed = size;
185 ttm_mem_needed = size;
186 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
187 /*
188 * Conservatively round up the allocation requirement to 2 MB
189 * to avoid fragmentation caused by 4K allocations in the tail
190 * 2M BO chunk.
191 */
192 vram_needed = size;
193 /*
194 * For GFX 9.4.3, get the VRAM size from XCP structs
195 */
196 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
197 return -EINVAL;
198
199 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
200 if (adev->flags & AMD_IS_APU) {
201 system_mem_needed = size;
202 ttm_mem_needed = size;
203 }
204 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
205 system_mem_needed = size;
206 } else if (!(alloc_flag &
207 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
208 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
209 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
210 return -ENOMEM;
211 }
212
213 spin_lock(&kfd_mem_limit.mem_limit_lock);
214
215 if (kfd_mem_limit.system_mem_used + system_mem_needed >
216 kfd_mem_limit.max_system_mem_limit)
217 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
218
219 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
220 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
221 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
222 kfd_mem_limit.max_ttm_mem_limit) ||
223 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
224 vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size))) {
225 ret = -ENOMEM;
226 goto release;
227 }
228
229 /* Update memory accounting by decreasing available system
230 * memory, TTM memory and GPU memory as computed above
231 */
232 WARN_ONCE(vram_needed && !adev,
233 "adev reference can't be null when vram is used");
234 if (adev && xcp_id >= 0) {
235 adev->kfd.vram_used[xcp_id] += vram_needed;
236 adev->kfd.vram_used_aligned[xcp_id] +=
237 (adev->flags & AMD_IS_APU) ?
238 vram_needed :
239 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
240 }
241 kfd_mem_limit.system_mem_used += system_mem_needed;
242 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
243
244release:
245 spin_unlock(&kfd_mem_limit.mem_limit_lock);
246 return ret;
247}
248
249void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
250 uint64_t size, u32 alloc_flag, int8_t xcp_id)
251{
252 spin_lock(&kfd_mem_limit.mem_limit_lock);
253
254 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
255 kfd_mem_limit.system_mem_used -= size;
256 kfd_mem_limit.ttm_mem_used -= size;
257 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
258 WARN_ONCE(!adev,
259 "adev reference can't be null when alloc mem flags vram is set");
260 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
261 goto release;
262
263 if (adev) {
264 adev->kfd.vram_used[xcp_id] -= size;
265 if (adev->flags & AMD_IS_APU) {
266 adev->kfd.vram_used_aligned[xcp_id] -= size;
267 kfd_mem_limit.system_mem_used -= size;
268 kfd_mem_limit.ttm_mem_used -= size;
269 } else {
270 adev->kfd.vram_used_aligned[xcp_id] -=
271 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
272 }
273 }
274 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
275 kfd_mem_limit.system_mem_used -= size;
276 } else if (!(alloc_flag &
277 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
278 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
279 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
280 goto release;
281 }
282 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
283 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
284 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
285 "KFD TTM memory accounting unbalanced");
286 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
287 "KFD system memory accounting unbalanced");
288
289release:
290 spin_unlock(&kfd_mem_limit.mem_limit_lock);
291}
292
293void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
294{
295 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
296 u32 alloc_flags = bo->kfd_bo->alloc_flags;
297 u64 size = amdgpu_bo_size(bo);
298
299 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
300 bo->xcp_id);
301
302 kfree(bo->kfd_bo);
303}
304
305/**
306 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
307 * about USERPTR or DOOREBELL or MMIO BO.
308 *
309 * @adev: Device for which dmamap BO is being created
310 * @mem: BO of peer device that is being DMA mapped. Provides parameters
311 * in building the dmamap BO
312 * @bo_out: Output parameter updated with handle of dmamap BO
313 */
314static int
315create_dmamap_sg_bo(struct amdgpu_device *adev,
316 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
317{
318 struct drm_gem_object *gem_obj;
319 int ret;
320 uint64_t flags = 0;
321
322 ret = amdgpu_bo_reserve(mem->bo, false);
323 if (ret)
324 return ret;
325
326 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
327 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
328 AMDGPU_GEM_CREATE_UNCACHED);
329
330 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
331 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
332 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
333
334 amdgpu_bo_unreserve(mem->bo);
335
336 if (ret) {
337 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
338 return -EINVAL;
339 }
340
341 *bo_out = gem_to_amdgpu_bo(gem_obj);
342 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
343 return ret;
344}
345
346/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
347 * reservation object.
348 *
349 * @bo: [IN] Remove eviction fence(s) from this BO
350 * @ef: [IN] This eviction fence is removed if it
351 * is present in the shared list.
352 *
353 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
354 */
355static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
356 struct amdgpu_amdkfd_fence *ef)
357{
358 struct dma_fence *replacement;
359
360 if (!ef)
361 return -EINVAL;
362
363 /* TODO: Instead of block before we should use the fence of the page
364 * table update and TLB flush here directly.
365 */
366 replacement = dma_fence_get_stub();
367 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
368 replacement, DMA_RESV_USAGE_BOOKKEEP);
369 dma_fence_put(replacement);
370 return 0;
371}
372
373int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
374{
375 struct amdgpu_bo *root = bo;
376 struct amdgpu_vm_bo_base *vm_bo;
377 struct amdgpu_vm *vm;
378 struct amdkfd_process_info *info;
379 struct amdgpu_amdkfd_fence *ef;
380 int ret;
381
382 /* we can always get vm_bo from root PD bo.*/
383 while (root->parent)
384 root = root->parent;
385
386 vm_bo = root->vm_bo;
387 if (!vm_bo)
388 return 0;
389
390 vm = vm_bo->vm;
391 if (!vm)
392 return 0;
393
394 info = vm->process_info;
395 if (!info || !info->eviction_fence)
396 return 0;
397
398 ef = container_of(dma_fence_get(&info->eviction_fence->base),
399 struct amdgpu_amdkfd_fence, base);
400
401 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
402 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
403 dma_resv_unlock(bo->tbo.base.resv);
404
405 dma_fence_put(&ef->base);
406 return ret;
407}
408
409static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
410 bool wait)
411{
412 struct ttm_operation_ctx ctx = { false, false };
413 int ret;
414
415 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
416 "Called with userptr BO"))
417 return -EINVAL;
418
419 /* bo has been pinned, not need validate it */
420 if (bo->tbo.pin_count)
421 return 0;
422
423 amdgpu_bo_placement_from_domain(bo, domain);
424
425 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
426 if (ret)
427 goto validate_fail;
428 if (wait)
429 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
430
431validate_fail:
432 return ret;
433}
434
435int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
436 uint32_t domain,
437 struct dma_fence *fence)
438{
439 int ret = amdgpu_bo_reserve(bo, false);
440
441 if (ret)
442 return ret;
443
444 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
445 if (ret)
446 goto unreserve_out;
447
448 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
449 if (ret)
450 goto unreserve_out;
451
452 dma_resv_add_fence(bo->tbo.base.resv, fence,
453 DMA_RESV_USAGE_BOOKKEEP);
454
455unreserve_out:
456 amdgpu_bo_unreserve(bo);
457
458 return ret;
459}
460
461static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
462{
463 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
464}
465
466/* vm_validate_pt_pd_bos - Validate page table and directory BOs
467 *
468 * Page directories are not updated here because huge page handling
469 * during page table updates can invalidate page directory entries
470 * again. Page directories are only updated after updating page
471 * tables.
472 */
473static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm,
474 struct ww_acquire_ctx *ticket)
475{
476 struct amdgpu_bo *pd = vm->root.bo;
477 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
478 int ret;
479
480 ret = amdgpu_vm_validate(adev, vm, ticket,
481 amdgpu_amdkfd_validate_vm_bo, NULL);
482 if (ret) {
483 pr_err("failed to validate PT BOs\n");
484 return ret;
485 }
486
487 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
488
489 return 0;
490}
491
492static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
493{
494 struct amdgpu_bo *pd = vm->root.bo;
495 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
496 int ret;
497
498 ret = amdgpu_vm_update_pdes(adev, vm, false);
499 if (ret)
500 return ret;
501
502 return amdgpu_sync_fence(sync, vm->last_update);
503}
504
505static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
506{
507 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
508 AMDGPU_VM_MTYPE_DEFAULT;
509
510 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
511 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
512 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
513 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
514
515 return amdgpu_gem_va_map_flags(adev, mapping_flags);
516}
517
518/**
519 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
520 * @addr: The starting address to point to
521 * @size: Size of memory area in bytes being pointed to
522 *
523 * Allocates an instance of sg_table and initializes it to point to memory
524 * area specified by input parameters. The address used to build is assumed
525 * to be DMA mapped, if needed.
526 *
527 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
528 * because they are physically contiguous.
529 *
530 * Return: Initialized instance of SG Table or NULL
531 */
532static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
533{
534 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
535
536 if (!sg)
537 return NULL;
538 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
539 kfree(sg);
540 return NULL;
541 }
542 sg_dma_address(sg->sgl) = addr;
543 sg->sgl->length = size;
544#ifdef CONFIG_NEED_SG_DMA_LENGTH
545 sg->sgl->dma_length = size;
546#endif
547 return sg;
548}
549
550static int
551kfd_mem_dmamap_userptr(struct kgd_mem *mem,
552 struct kfd_mem_attachment *attachment)
553{
554 enum dma_data_direction direction =
555 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
556 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
557 struct ttm_operation_ctx ctx = {.interruptible = true};
558 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
559 struct amdgpu_device *adev = attachment->adev;
560 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
561 struct ttm_tt *ttm = bo->tbo.ttm;
562 int ret;
563
564 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
565 return -EINVAL;
566
567 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
568 if (unlikely(!ttm->sg))
569 return -ENOMEM;
570
571 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
572 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
573 ttm->num_pages, 0,
574 (u64)ttm->num_pages << PAGE_SHIFT,
575 GFP_KERNEL);
576 if (unlikely(ret))
577 goto free_sg;
578
579 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
580 if (unlikely(ret))
581 goto release_sg;
582
583 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
584 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
585 if (ret)
586 goto unmap_sg;
587
588 return 0;
589
590unmap_sg:
591 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
592release_sg:
593 pr_err("DMA map userptr failed: %d\n", ret);
594 sg_free_table(ttm->sg);
595free_sg:
596 kfree(ttm->sg);
597 ttm->sg = NULL;
598 return ret;
599}
600
601static int
602kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
603{
604 struct ttm_operation_ctx ctx = {.interruptible = true};
605 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
606 int ret;
607
608 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
609 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
610 if (ret)
611 return ret;
612
613 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
614 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
615}
616
617/**
618 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
619 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
620 * @attachment: Virtual address attachment of the BO on accessing device
621 *
622 * An access request from the device that owns DOORBELL does not require DMA mapping.
623 * This is because the request doesn't go through PCIe root complex i.e. it instead
624 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
625 *
626 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
627 * device ownership. This is because access requests for MMIO go through PCIe root
628 * complex.
629 *
630 * This is accomplished in two steps:
631 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
632 * in updating requesting device's page table
633 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
634 * accessible. This allows an update of requesting device's page table
635 * with entries associated with DOOREBELL or MMIO memory
636 *
637 * This method is invoked in the following contexts:
638 * - Mapping of DOORBELL or MMIO BO of same or peer device
639 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
640 *
641 * Return: ZERO if successful, NON-ZERO otherwise
642 */
643static int
644kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
645 struct kfd_mem_attachment *attachment)
646{
647 struct ttm_operation_ctx ctx = {.interruptible = true};
648 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
649 struct amdgpu_device *adev = attachment->adev;
650 struct ttm_tt *ttm = bo->tbo.ttm;
651 enum dma_data_direction dir;
652 dma_addr_t dma_addr;
653 bool mmio;
654 int ret;
655
656 /* Expect SG Table of dmapmap BO to be NULL */
657 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
658 if (unlikely(ttm->sg)) {
659 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
660 return -EINVAL;
661 }
662
663 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
664 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
665 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
666 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
667 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
668 dma_addr = dma_map_resource(adev->dev, dma_addr,
669 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
670 ret = dma_mapping_error(adev->dev, dma_addr);
671 if (unlikely(ret))
672 return ret;
673 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
674
675 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
676 if (unlikely(!ttm->sg)) {
677 ret = -ENOMEM;
678 goto unmap_sg;
679 }
680
681 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
682 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
683 if (unlikely(ret))
684 goto free_sg;
685
686 return ret;
687
688free_sg:
689 sg_free_table(ttm->sg);
690 kfree(ttm->sg);
691 ttm->sg = NULL;
692unmap_sg:
693 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
694 dir, DMA_ATTR_SKIP_CPU_SYNC);
695 return ret;
696}
697
698static int
699kfd_mem_dmamap_attachment(struct kgd_mem *mem,
700 struct kfd_mem_attachment *attachment)
701{
702 switch (attachment->type) {
703 case KFD_MEM_ATT_SHARED:
704 return 0;
705 case KFD_MEM_ATT_USERPTR:
706 return kfd_mem_dmamap_userptr(mem, attachment);
707 case KFD_MEM_ATT_DMABUF:
708 return kfd_mem_dmamap_dmabuf(attachment);
709 case KFD_MEM_ATT_SG:
710 return kfd_mem_dmamap_sg_bo(mem, attachment);
711 default:
712 WARN_ON_ONCE(1);
713 }
714 return -EINVAL;
715}
716
717static void
718kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
719 struct kfd_mem_attachment *attachment)
720{
721 enum dma_data_direction direction =
722 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
723 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
724 struct ttm_operation_ctx ctx = {.interruptible = false};
725 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
726 struct amdgpu_device *adev = attachment->adev;
727 struct ttm_tt *ttm = bo->tbo.ttm;
728
729 if (unlikely(!ttm->sg))
730 return;
731
732 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
733 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
734
735 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
736 sg_free_table(ttm->sg);
737 kfree(ttm->sg);
738 ttm->sg = NULL;
739}
740
741static void
742kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
743{
744 /* This is a no-op. We don't want to trigger eviction fences when
745 * unmapping DMABufs. Therefore the invalidation (moving to system
746 * domain) is done in kfd_mem_dmamap_dmabuf.
747 */
748}
749
750/**
751 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
752 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
753 * @attachment: Virtual address attachment of the BO on accessing device
754 *
755 * The method performs following steps:
756 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
757 * - Free SG Table that is used to encapsulate DMA mapped memory of
758 * peer device's DOORBELL or MMIO memory
759 *
760 * This method is invoked in the following contexts:
761 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
762 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
763 *
764 * Return: void
765 */
766static void
767kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
768 struct kfd_mem_attachment *attachment)
769{
770 struct ttm_operation_ctx ctx = {.interruptible = true};
771 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
772 struct amdgpu_device *adev = attachment->adev;
773 struct ttm_tt *ttm = bo->tbo.ttm;
774 enum dma_data_direction dir;
775
776 if (unlikely(!ttm->sg)) {
777 pr_debug("SG Table of BO is NULL");
778 return;
779 }
780
781 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
782 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
783
784 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
785 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
786 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
787 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
788 sg_free_table(ttm->sg);
789 kfree(ttm->sg);
790 ttm->sg = NULL;
791 bo->tbo.sg = NULL;
792}
793
794static void
795kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
796 struct kfd_mem_attachment *attachment)
797{
798 switch (attachment->type) {
799 case KFD_MEM_ATT_SHARED:
800 break;
801 case KFD_MEM_ATT_USERPTR:
802 kfd_mem_dmaunmap_userptr(mem, attachment);
803 break;
804 case KFD_MEM_ATT_DMABUF:
805 kfd_mem_dmaunmap_dmabuf(attachment);
806 break;
807 case KFD_MEM_ATT_SG:
808 kfd_mem_dmaunmap_sg_bo(mem, attachment);
809 break;
810 default:
811 WARN_ON_ONCE(1);
812 }
813}
814
815static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
816{
817 if (!mem->dmabuf) {
818 struct amdgpu_device *bo_adev;
819 struct dma_buf *dmabuf;
820
821 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
822 dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file,
823 mem->gem_handle,
824 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
825 DRM_RDWR : 0);
826 if (IS_ERR(dmabuf))
827 return PTR_ERR(dmabuf);
828 mem->dmabuf = dmabuf;
829 }
830
831 return 0;
832}
833
834static int
835kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
836 struct amdgpu_bo **bo)
837{
838 struct drm_gem_object *gobj;
839 int ret;
840
841 ret = kfd_mem_export_dmabuf(mem);
842 if (ret)
843 return ret;
844
845 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
846 if (IS_ERR(gobj))
847 return PTR_ERR(gobj);
848
849 *bo = gem_to_amdgpu_bo(gobj);
850 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
851
852 return 0;
853}
854
855/* kfd_mem_attach - Add a BO to a VM
856 *
857 * Everything that needs to bo done only once when a BO is first added
858 * to a VM. It can later be mapped and unmapped many times without
859 * repeating these steps.
860 *
861 * 0. Create BO for DMA mapping, if needed
862 * 1. Allocate and initialize BO VA entry data structure
863 * 2. Add BO to the VM
864 * 3. Determine ASIC-specific PTE flags
865 * 4. Alloc page tables and directories if needed
866 * 4a. Validate new page tables and directories
867 */
868static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
869 struct amdgpu_vm *vm, bool is_aql)
870{
871 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
872 unsigned long bo_size = mem->bo->tbo.base.size;
873 uint64_t va = mem->va;
874 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
875 struct amdgpu_bo *bo[2] = {NULL, NULL};
876 struct amdgpu_bo_va *bo_va;
877 bool same_hive = false;
878 int i, ret;
879
880 if (!va) {
881 pr_err("Invalid VA when adding BO to VM\n");
882 return -EINVAL;
883 }
884
885 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
886 *
887 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
888 * In contrast the access path of VRAM BOs depens upon the type of
889 * link that connects the peer device. Access over PCIe is allowed
890 * if peer device has large BAR. In contrast, access over xGMI is
891 * allowed for both small and large BAR configurations of peer device
892 */
893 if ((adev != bo_adev && !(adev->flags & AMD_IS_APU)) &&
894 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
895 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
896 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
897 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
898 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
899 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
900 return -EINVAL;
901 }
902
903 for (i = 0; i <= is_aql; i++) {
904 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
905 if (unlikely(!attachment[i])) {
906 ret = -ENOMEM;
907 goto unwind;
908 }
909
910 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
911 va + bo_size, vm);
912
913 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
914 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
915 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
916 same_hive) {
917 /* Mappings on the local GPU, or VRAM mappings in the
918 * local hive, or userptr, or GTT mapping can reuse dma map
919 * address space share the original BO
920 */
921 attachment[i]->type = KFD_MEM_ATT_SHARED;
922 bo[i] = mem->bo;
923 drm_gem_object_get(&bo[i]->tbo.base);
924 } else if (i > 0) {
925 /* Multiple mappings on the same GPU share the BO */
926 attachment[i]->type = KFD_MEM_ATT_SHARED;
927 bo[i] = bo[0];
928 drm_gem_object_get(&bo[i]->tbo.base);
929 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
930 /* Create an SG BO to DMA-map userptrs on other GPUs */
931 attachment[i]->type = KFD_MEM_ATT_USERPTR;
932 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
933 if (ret)
934 goto unwind;
935 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
936 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
937 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
938 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
939 "Handing invalid SG BO in ATTACH request");
940 attachment[i]->type = KFD_MEM_ATT_SG;
941 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
942 if (ret)
943 goto unwind;
944 /* Enable acces to GTT and VRAM BOs of peer devices */
945 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
946 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
947 attachment[i]->type = KFD_MEM_ATT_DMABUF;
948 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
949 if (ret)
950 goto unwind;
951 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
952 } else {
953 WARN_ONCE(true, "Handling invalid ATTACH request");
954 ret = -EINVAL;
955 goto unwind;
956 }
957
958 /* Add BO to VM internal data structures */
959 ret = amdgpu_bo_reserve(bo[i], false);
960 if (ret) {
961 pr_debug("Unable to reserve BO during memory attach");
962 goto unwind;
963 }
964 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
965 if (!bo_va)
966 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
967 else
968 ++bo_va->ref_count;
969 attachment[i]->bo_va = bo_va;
970 amdgpu_bo_unreserve(bo[i]);
971 if (unlikely(!attachment[i]->bo_va)) {
972 ret = -ENOMEM;
973 pr_err("Failed to add BO object to VM. ret == %d\n",
974 ret);
975 goto unwind;
976 }
977 attachment[i]->va = va;
978 attachment[i]->pte_flags = get_pte_flags(adev, mem);
979 attachment[i]->adev = adev;
980 list_add(&attachment[i]->list, &mem->attachments);
981
982 va += bo_size;
983 }
984
985 return 0;
986
987unwind:
988 for (; i >= 0; i--) {
989 if (!attachment[i])
990 continue;
991 if (attachment[i]->bo_va) {
992 amdgpu_bo_reserve(bo[i], true);
993 if (--attachment[i]->bo_va->ref_count == 0)
994 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
995 amdgpu_bo_unreserve(bo[i]);
996 list_del(&attachment[i]->list);
997 }
998 if (bo[i])
999 drm_gem_object_put(&bo[i]->tbo.base);
1000 kfree(attachment[i]);
1001 }
1002 return ret;
1003}
1004
1005static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1006{
1007 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1008
1009 pr_debug("\t remove VA 0x%llx in entry %p\n",
1010 attachment->va, attachment);
1011 if (--attachment->bo_va->ref_count == 0)
1012 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1013 drm_gem_object_put(&bo->tbo.base);
1014 list_del(&attachment->list);
1015 kfree(attachment);
1016}
1017
1018static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1019 struct amdkfd_process_info *process_info,
1020 bool userptr)
1021{
1022 mutex_lock(&process_info->lock);
1023 if (userptr)
1024 list_add_tail(&mem->validate_list,
1025 &process_info->userptr_valid_list);
1026 else
1027 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1028 mutex_unlock(&process_info->lock);
1029}
1030
1031static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1032 struct amdkfd_process_info *process_info)
1033{
1034 mutex_lock(&process_info->lock);
1035 list_del(&mem->validate_list);
1036 mutex_unlock(&process_info->lock);
1037}
1038
1039/* Initializes user pages. It registers the MMU notifier and validates
1040 * the userptr BO in the GTT domain.
1041 *
1042 * The BO must already be on the userptr_valid_list. Otherwise an
1043 * eviction and restore may happen that leaves the new BO unmapped
1044 * with the user mode queues running.
1045 *
1046 * Takes the process_info->lock to protect against concurrent restore
1047 * workers.
1048 *
1049 * Returns 0 for success, negative errno for errors.
1050 */
1051static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1052 bool criu_resume)
1053{
1054 struct amdkfd_process_info *process_info = mem->process_info;
1055 struct amdgpu_bo *bo = mem->bo;
1056 struct ttm_operation_ctx ctx = { true, false };
1057 struct hmm_range *range;
1058 int ret = 0;
1059
1060 mutex_lock(&process_info->lock);
1061
1062 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1063 if (ret) {
1064 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1065 goto out;
1066 }
1067
1068 ret = amdgpu_hmm_register(bo, user_addr);
1069 if (ret) {
1070 pr_err("%s: Failed to register MMU notifier: %d\n",
1071 __func__, ret);
1072 goto out;
1073 }
1074
1075 if (criu_resume) {
1076 /*
1077 * During a CRIU restore operation, the userptr buffer objects
1078 * will be validated in the restore_userptr_work worker at a
1079 * later stage when it is scheduled by another ioctl called by
1080 * CRIU master process for the target pid for restore.
1081 */
1082 mutex_lock(&process_info->notifier_lock);
1083 mem->invalid++;
1084 mutex_unlock(&process_info->notifier_lock);
1085 mutex_unlock(&process_info->lock);
1086 return 0;
1087 }
1088
1089 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1090 if (ret) {
1091 if (ret == -EAGAIN)
1092 pr_debug("Failed to get user pages, try again\n");
1093 else
1094 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1095 goto unregister_out;
1096 }
1097
1098 ret = amdgpu_bo_reserve(bo, true);
1099 if (ret) {
1100 pr_err("%s: Failed to reserve BO\n", __func__);
1101 goto release_out;
1102 }
1103 amdgpu_bo_placement_from_domain(bo, mem->domain);
1104 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1105 if (ret)
1106 pr_err("%s: failed to validate BO\n", __func__);
1107 amdgpu_bo_unreserve(bo);
1108
1109release_out:
1110 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1111unregister_out:
1112 if (ret)
1113 amdgpu_hmm_unregister(bo);
1114out:
1115 mutex_unlock(&process_info->lock);
1116 return ret;
1117}
1118
1119/* Reserving a BO and its page table BOs must happen atomically to
1120 * avoid deadlocks. Some operations update multiple VMs at once. Track
1121 * all the reservation info in a context structure. Optionally a sync
1122 * object can track VM updates.
1123 */
1124struct bo_vm_reservation_context {
1125 /* DRM execution context for the reservation */
1126 struct drm_exec exec;
1127 /* Number of VMs reserved */
1128 unsigned int n_vms;
1129 /* Pointer to sync object */
1130 struct amdgpu_sync *sync;
1131};
1132
1133enum bo_vm_match {
1134 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1135 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1136 BO_VM_ALL, /* Match all VMs a BO was added to */
1137};
1138
1139/**
1140 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1141 * @mem: KFD BO structure.
1142 * @vm: the VM to reserve.
1143 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1144 */
1145static int reserve_bo_and_vm(struct kgd_mem *mem,
1146 struct amdgpu_vm *vm,
1147 struct bo_vm_reservation_context *ctx)
1148{
1149 struct amdgpu_bo *bo = mem->bo;
1150 int ret;
1151
1152 WARN_ON(!vm);
1153
1154 ctx->n_vms = 1;
1155 ctx->sync = &mem->sync;
1156 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1157 drm_exec_until_all_locked(&ctx->exec) {
1158 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1159 drm_exec_retry_on_contention(&ctx->exec);
1160 if (unlikely(ret))
1161 goto error;
1162
1163 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1164 drm_exec_retry_on_contention(&ctx->exec);
1165 if (unlikely(ret))
1166 goto error;
1167 }
1168 return 0;
1169
1170error:
1171 pr_err("Failed to reserve buffers in ttm.\n");
1172 drm_exec_fini(&ctx->exec);
1173 return ret;
1174}
1175
1176/**
1177 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1178 * @mem: KFD BO structure.
1179 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1180 * is used. Otherwise, a single VM associated with the BO.
1181 * @map_type: the mapping status that will be used to filter the VMs.
1182 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1183 *
1184 * Returns 0 for success, negative for failure.
1185 */
1186static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1187 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1188 struct bo_vm_reservation_context *ctx)
1189{
1190 struct kfd_mem_attachment *entry;
1191 struct amdgpu_bo *bo = mem->bo;
1192 int ret;
1193
1194 ctx->sync = &mem->sync;
1195 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
1196 DRM_EXEC_IGNORE_DUPLICATES, 0);
1197 drm_exec_until_all_locked(&ctx->exec) {
1198 ctx->n_vms = 0;
1199 list_for_each_entry(entry, &mem->attachments, list) {
1200 if ((vm && vm != entry->bo_va->base.vm) ||
1201 (entry->is_mapped != map_type
1202 && map_type != BO_VM_ALL))
1203 continue;
1204
1205 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1206 &ctx->exec, 2);
1207 drm_exec_retry_on_contention(&ctx->exec);
1208 if (unlikely(ret))
1209 goto error;
1210 ++ctx->n_vms;
1211 }
1212
1213 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1214 drm_exec_retry_on_contention(&ctx->exec);
1215 if (unlikely(ret))
1216 goto error;
1217 }
1218 return 0;
1219
1220error:
1221 pr_err("Failed to reserve buffers in ttm.\n");
1222 drm_exec_fini(&ctx->exec);
1223 return ret;
1224}
1225
1226/**
1227 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1228 * @ctx: Reservation context to unreserve
1229 * @wait: Optionally wait for a sync object representing pending VM updates
1230 * @intr: Whether the wait is interruptible
1231 *
1232 * Also frees any resources allocated in
1233 * reserve_bo_and_(cond_)vm(s). Returns the status from
1234 * amdgpu_sync_wait.
1235 */
1236static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1237 bool wait, bool intr)
1238{
1239 int ret = 0;
1240
1241 if (wait)
1242 ret = amdgpu_sync_wait(ctx->sync, intr);
1243
1244 drm_exec_fini(&ctx->exec);
1245 ctx->sync = NULL;
1246 return ret;
1247}
1248
1249static int unmap_bo_from_gpuvm(struct kgd_mem *mem,
1250 struct kfd_mem_attachment *entry,
1251 struct amdgpu_sync *sync)
1252{
1253 struct amdgpu_bo_va *bo_va = entry->bo_va;
1254 struct amdgpu_device *adev = entry->adev;
1255 struct amdgpu_vm *vm = bo_va->base.vm;
1256
1257 if (bo_va->queue_refcount) {
1258 pr_debug("bo_va->queue_refcount %d\n", bo_va->queue_refcount);
1259 return -EBUSY;
1260 }
1261
1262 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1263
1264 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1265
1266 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1267
1268 return 0;
1269}
1270
1271static int update_gpuvm_pte(struct kgd_mem *mem,
1272 struct kfd_mem_attachment *entry,
1273 struct amdgpu_sync *sync)
1274{
1275 struct amdgpu_bo_va *bo_va = entry->bo_va;
1276 struct amdgpu_device *adev = entry->adev;
1277 int ret;
1278
1279 ret = kfd_mem_dmamap_attachment(mem, entry);
1280 if (ret)
1281 return ret;
1282
1283 /* Update the page tables */
1284 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1285 if (ret) {
1286 pr_err("amdgpu_vm_bo_update failed\n");
1287 return ret;
1288 }
1289
1290 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1291}
1292
1293static int map_bo_to_gpuvm(struct kgd_mem *mem,
1294 struct kfd_mem_attachment *entry,
1295 struct amdgpu_sync *sync,
1296 bool no_update_pte)
1297{
1298 int ret;
1299
1300 /* Set virtual address for the allocation */
1301 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1302 amdgpu_bo_size(entry->bo_va->base.bo),
1303 entry->pte_flags);
1304 if (ret) {
1305 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1306 entry->va, ret);
1307 return ret;
1308 }
1309
1310 if (no_update_pte)
1311 return 0;
1312
1313 ret = update_gpuvm_pte(mem, entry, sync);
1314 if (ret) {
1315 pr_err("update_gpuvm_pte() failed\n");
1316 goto update_gpuvm_pte_failed;
1317 }
1318
1319 return 0;
1320
1321update_gpuvm_pte_failed:
1322 unmap_bo_from_gpuvm(mem, entry, sync);
1323 kfd_mem_dmaunmap_attachment(mem, entry);
1324 return ret;
1325}
1326
1327static int process_validate_vms(struct amdkfd_process_info *process_info,
1328 struct ww_acquire_ctx *ticket)
1329{
1330 struct amdgpu_vm *peer_vm;
1331 int ret;
1332
1333 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1334 vm_list_node) {
1335 ret = vm_validate_pt_pd_bos(peer_vm, ticket);
1336 if (ret)
1337 return ret;
1338 }
1339
1340 return 0;
1341}
1342
1343static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1344 struct amdgpu_sync *sync)
1345{
1346 struct amdgpu_vm *peer_vm;
1347 int ret;
1348
1349 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1350 vm_list_node) {
1351 struct amdgpu_bo *pd = peer_vm->root.bo;
1352
1353 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1354 AMDGPU_SYNC_NE_OWNER,
1355 AMDGPU_FENCE_OWNER_KFD);
1356 if (ret)
1357 return ret;
1358 }
1359
1360 return 0;
1361}
1362
1363static int process_update_pds(struct amdkfd_process_info *process_info,
1364 struct amdgpu_sync *sync)
1365{
1366 struct amdgpu_vm *peer_vm;
1367 int ret;
1368
1369 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1370 vm_list_node) {
1371 ret = vm_update_pds(peer_vm, sync);
1372 if (ret)
1373 return ret;
1374 }
1375
1376 return 0;
1377}
1378
1379static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1380 struct dma_fence **ef)
1381{
1382 struct amdkfd_process_info *info = NULL;
1383 int ret;
1384
1385 if (!*process_info) {
1386 info = kzalloc(sizeof(*info), GFP_KERNEL);
1387 if (!info)
1388 return -ENOMEM;
1389
1390 mutex_init(&info->lock);
1391 mutex_init(&info->notifier_lock);
1392 INIT_LIST_HEAD(&info->vm_list_head);
1393 INIT_LIST_HEAD(&info->kfd_bo_list);
1394 INIT_LIST_HEAD(&info->userptr_valid_list);
1395 INIT_LIST_HEAD(&info->userptr_inval_list);
1396
1397 info->eviction_fence =
1398 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1399 current->mm,
1400 NULL);
1401 if (!info->eviction_fence) {
1402 pr_err("Failed to create eviction fence\n");
1403 ret = -ENOMEM;
1404 goto create_evict_fence_fail;
1405 }
1406
1407 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1408 INIT_DELAYED_WORK(&info->restore_userptr_work,
1409 amdgpu_amdkfd_restore_userptr_worker);
1410
1411 *process_info = info;
1412 }
1413
1414 vm->process_info = *process_info;
1415
1416 /* Validate page directory and attach eviction fence */
1417 ret = amdgpu_bo_reserve(vm->root.bo, true);
1418 if (ret)
1419 goto reserve_pd_fail;
1420 ret = vm_validate_pt_pd_bos(vm, NULL);
1421 if (ret) {
1422 pr_err("validate_pt_pd_bos() failed\n");
1423 goto validate_pd_fail;
1424 }
1425 ret = amdgpu_bo_sync_wait(vm->root.bo,
1426 AMDGPU_FENCE_OWNER_KFD, false);
1427 if (ret)
1428 goto wait_pd_fail;
1429 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1430 if (ret)
1431 goto reserve_shared_fail;
1432 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1433 &vm->process_info->eviction_fence->base,
1434 DMA_RESV_USAGE_BOOKKEEP);
1435 amdgpu_bo_unreserve(vm->root.bo);
1436
1437 /* Update process info */
1438 mutex_lock(&vm->process_info->lock);
1439 list_add_tail(&vm->vm_list_node,
1440 &(vm->process_info->vm_list_head));
1441 vm->process_info->n_vms++;
1442 if (ef)
1443 *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1444 mutex_unlock(&vm->process_info->lock);
1445
1446 return 0;
1447
1448reserve_shared_fail:
1449wait_pd_fail:
1450validate_pd_fail:
1451 amdgpu_bo_unreserve(vm->root.bo);
1452reserve_pd_fail:
1453 vm->process_info = NULL;
1454 if (info) {
1455 dma_fence_put(&info->eviction_fence->base);
1456 *process_info = NULL;
1457 put_pid(info->pid);
1458create_evict_fence_fail:
1459 mutex_destroy(&info->lock);
1460 mutex_destroy(&info->notifier_lock);
1461 kfree(info);
1462 }
1463 return ret;
1464}
1465
1466/**
1467 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1468 * @bo: Handle of buffer object being pinned
1469 * @domain: Domain into which BO should be pinned
1470 *
1471 * - USERPTR BOs are UNPINNABLE and will return error
1472 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1473 * PIN count incremented. It is valid to PIN a BO multiple times
1474 *
1475 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1476 */
1477static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1478{
1479 int ret = 0;
1480
1481 ret = amdgpu_bo_reserve(bo, false);
1482 if (unlikely(ret))
1483 return ret;
1484
1485 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) {
1486 /*
1487 * If bo is not contiguous on VRAM, move to system memory first to ensure
1488 * we can get contiguous VRAM space after evicting other BOs.
1489 */
1490 if (!(bo->tbo.resource->placement & TTM_PL_FLAG_CONTIGUOUS)) {
1491 struct ttm_operation_ctx ctx = { true, false };
1492
1493 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
1494 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1495 if (unlikely(ret)) {
1496 pr_debug("validate bo 0x%p to GTT failed %d\n", &bo->tbo, ret);
1497 goto out;
1498 }
1499 }
1500 }
1501
1502 ret = amdgpu_bo_pin(bo, domain);
1503 if (ret)
1504 pr_err("Error in Pinning BO to domain: %d\n", domain);
1505
1506 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1507out:
1508 amdgpu_bo_unreserve(bo);
1509 return ret;
1510}
1511
1512/**
1513 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1514 * @bo: Handle of buffer object being unpinned
1515 *
1516 * - Is a illegal request for USERPTR BOs and is ignored
1517 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1518 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1519 */
1520static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1521{
1522 int ret = 0;
1523
1524 ret = amdgpu_bo_reserve(bo, false);
1525 if (unlikely(ret))
1526 return;
1527
1528 amdgpu_bo_unpin(bo);
1529 amdgpu_bo_unreserve(bo);
1530}
1531
1532int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1533 struct amdgpu_vm *avm, u32 pasid)
1534
1535{
1536 int ret;
1537
1538 /* Free the original amdgpu allocated pasid,
1539 * will be replaced with kfd allocated pasid.
1540 */
1541 if (avm->pasid) {
1542 amdgpu_pasid_free(avm->pasid);
1543 amdgpu_vm_set_pasid(adev, avm, 0);
1544 }
1545
1546 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1547 if (ret)
1548 return ret;
1549
1550 return 0;
1551}
1552
1553int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1554 struct amdgpu_vm *avm,
1555 void **process_info,
1556 struct dma_fence **ef)
1557{
1558 int ret;
1559
1560 /* Already a compute VM? */
1561 if (avm->process_info)
1562 return -EINVAL;
1563
1564 /* Convert VM into a compute VM */
1565 ret = amdgpu_vm_make_compute(adev, avm);
1566 if (ret)
1567 return ret;
1568
1569 /* Initialize KFD part of the VM and process info */
1570 ret = init_kfd_vm(avm, process_info, ef);
1571 if (ret)
1572 return ret;
1573
1574 amdgpu_vm_set_task_info(avm);
1575
1576 return 0;
1577}
1578
1579void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1580 struct amdgpu_vm *vm)
1581{
1582 struct amdkfd_process_info *process_info = vm->process_info;
1583
1584 if (!process_info)
1585 return;
1586
1587 /* Update process info */
1588 mutex_lock(&process_info->lock);
1589 process_info->n_vms--;
1590 list_del(&vm->vm_list_node);
1591 mutex_unlock(&process_info->lock);
1592
1593 vm->process_info = NULL;
1594
1595 /* Release per-process resources when last compute VM is destroyed */
1596 if (!process_info->n_vms) {
1597 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1598 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1599 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1600
1601 dma_fence_put(&process_info->eviction_fence->base);
1602 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1603 put_pid(process_info->pid);
1604 mutex_destroy(&process_info->lock);
1605 mutex_destroy(&process_info->notifier_lock);
1606 kfree(process_info);
1607 }
1608}
1609
1610void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1611 void *drm_priv)
1612{
1613 struct amdgpu_vm *avm;
1614
1615 if (WARN_ON(!adev || !drm_priv))
1616 return;
1617
1618 avm = drm_priv_to_vm(drm_priv);
1619
1620 pr_debug("Releasing process vm %p\n", avm);
1621
1622 /* The original pasid of amdgpu vm has already been
1623 * released during making a amdgpu vm to a compute vm
1624 * The current pasid is managed by kfd and will be
1625 * released on kfd process destroy. Set amdgpu pasid
1626 * to 0 to avoid duplicate release.
1627 */
1628 amdgpu_vm_release_compute(adev, avm);
1629}
1630
1631uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1632{
1633 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1634 struct amdgpu_bo *pd = avm->root.bo;
1635 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1636
1637 if (adev->asic_type < CHIP_VEGA10)
1638 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1639 return avm->pd_phys_addr;
1640}
1641
1642void amdgpu_amdkfd_block_mmu_notifications(void *p)
1643{
1644 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1645
1646 mutex_lock(&pinfo->lock);
1647 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1648 mutex_unlock(&pinfo->lock);
1649}
1650
1651int amdgpu_amdkfd_criu_resume(void *p)
1652{
1653 int ret = 0;
1654 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1655
1656 mutex_lock(&pinfo->lock);
1657 pr_debug("scheduling work\n");
1658 mutex_lock(&pinfo->notifier_lock);
1659 pinfo->evicted_bos++;
1660 mutex_unlock(&pinfo->notifier_lock);
1661 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1662 ret = -EINVAL;
1663 goto out_unlock;
1664 }
1665 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1666 queue_delayed_work(system_freezable_wq,
1667 &pinfo->restore_userptr_work, 0);
1668
1669out_unlock:
1670 mutex_unlock(&pinfo->lock);
1671 return ret;
1672}
1673
1674size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1675 uint8_t xcp_id)
1676{
1677 uint64_t reserved_for_pt =
1678 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1679 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1680 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0);
1681 ssize_t available;
1682 uint64_t vram_available, system_mem_available, ttm_mem_available;
1683
1684 spin_lock(&kfd_mem_limit.mem_limit_lock);
1685 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1686 - adev->kfd.vram_used_aligned[xcp_id]
1687 - atomic64_read(&adev->vram_pin_size)
1688 - reserved_for_pt
1689 - reserved_for_ras;
1690
1691 if (adev->flags & AMD_IS_APU) {
1692 system_mem_available = no_system_mem_limit ?
1693 kfd_mem_limit.max_system_mem_limit :
1694 kfd_mem_limit.max_system_mem_limit -
1695 kfd_mem_limit.system_mem_used;
1696
1697 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1698 kfd_mem_limit.ttm_mem_used;
1699
1700 available = min3(system_mem_available, ttm_mem_available,
1701 vram_available);
1702 available = ALIGN_DOWN(available, PAGE_SIZE);
1703 } else {
1704 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1705 }
1706
1707 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1708
1709 if (available < 0)
1710 available = 0;
1711
1712 return available;
1713}
1714
1715int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1716 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1717 void *drm_priv, struct kgd_mem **mem,
1718 uint64_t *offset, uint32_t flags, bool criu_resume)
1719{
1720 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1721 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1722 enum ttm_bo_type bo_type = ttm_bo_type_device;
1723 struct sg_table *sg = NULL;
1724 uint64_t user_addr = 0;
1725 struct amdgpu_bo *bo;
1726 struct drm_gem_object *gobj = NULL;
1727 u32 domain, alloc_domain;
1728 uint64_t aligned_size;
1729 int8_t xcp_id = -1;
1730 u64 alloc_flags;
1731 int ret;
1732
1733 /*
1734 * Check on which domain to allocate BO
1735 */
1736 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1737 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1738
1739 if (adev->flags & AMD_IS_APU) {
1740 domain = AMDGPU_GEM_DOMAIN_GTT;
1741 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1742 alloc_flags = 0;
1743 } else {
1744 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1745 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1746 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1747
1748 /* For contiguous VRAM allocation */
1749 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_CONTIGUOUS)
1750 alloc_flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1751 }
1752 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1753 0 : fpriv->xcp_id;
1754 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1755 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1756 alloc_flags = 0;
1757 } else {
1758 domain = AMDGPU_GEM_DOMAIN_GTT;
1759 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1760 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1761
1762 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1763 if (!offset || !*offset)
1764 return -EINVAL;
1765 user_addr = untagged_addr(*offset);
1766 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1767 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1768 bo_type = ttm_bo_type_sg;
1769 if (size > UINT_MAX)
1770 return -EINVAL;
1771 sg = create_sg_table(*offset, size);
1772 if (!sg)
1773 return -ENOMEM;
1774 } else {
1775 return -EINVAL;
1776 }
1777 }
1778
1779 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1780 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1781 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1782 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1783 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1784 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1785
1786 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1787 if (!*mem) {
1788 ret = -ENOMEM;
1789 goto err;
1790 }
1791 INIT_LIST_HEAD(&(*mem)->attachments);
1792 mutex_init(&(*mem)->lock);
1793 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1794
1795 /* Workaround for AQL queue wraparound bug. Map the same
1796 * memory twice. That means we only actually allocate half
1797 * the memory.
1798 */
1799 if ((*mem)->aql_queue)
1800 size >>= 1;
1801 aligned_size = PAGE_ALIGN(size);
1802
1803 (*mem)->alloc_flags = flags;
1804
1805 amdgpu_sync_create(&(*mem)->sync);
1806
1807 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1808 xcp_id);
1809 if (ret) {
1810 pr_debug("Insufficient memory\n");
1811 goto err_reserve_limit;
1812 }
1813
1814 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1815 va, (*mem)->aql_queue ? size << 1 : size,
1816 domain_string(alloc_domain), xcp_id);
1817
1818 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1819 bo_type, NULL, &gobj, xcp_id + 1);
1820 if (ret) {
1821 pr_debug("Failed to create BO on domain %s. ret %d\n",
1822 domain_string(alloc_domain), ret);
1823 goto err_bo_create;
1824 }
1825 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1826 if (ret) {
1827 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1828 goto err_node_allow;
1829 }
1830 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1831 if (ret)
1832 goto err_gem_handle_create;
1833 bo = gem_to_amdgpu_bo(gobj);
1834 if (bo_type == ttm_bo_type_sg) {
1835 bo->tbo.sg = sg;
1836 bo->tbo.ttm->sg = sg;
1837 }
1838 bo->kfd_bo = *mem;
1839 (*mem)->bo = bo;
1840 if (user_addr)
1841 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1842
1843 (*mem)->va = va;
1844 (*mem)->domain = domain;
1845 (*mem)->mapped_to_gpu_memory = 0;
1846 (*mem)->process_info = avm->process_info;
1847
1848 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1849
1850 if (user_addr) {
1851 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1852 ret = init_user_pages(*mem, user_addr, criu_resume);
1853 if (ret)
1854 goto allocate_init_user_pages_failed;
1855 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1856 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1857 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1858 if (ret) {
1859 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1860 goto err_pin_bo;
1861 }
1862 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1863 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1864 } else {
1865 mutex_lock(&avm->process_info->lock);
1866 if (avm->process_info->eviction_fence &&
1867 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1868 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1869 &avm->process_info->eviction_fence->base);
1870 mutex_unlock(&avm->process_info->lock);
1871 if (ret)
1872 goto err_validate_bo;
1873 }
1874
1875 if (offset)
1876 *offset = amdgpu_bo_mmap_offset(bo);
1877
1878 return 0;
1879
1880allocate_init_user_pages_failed:
1881err_pin_bo:
1882err_validate_bo:
1883 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1884 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1885err_gem_handle_create:
1886 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1887err_node_allow:
1888 /* Don't unreserve system mem limit twice */
1889 goto err_reserve_limit;
1890err_bo_create:
1891 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1892err_reserve_limit:
1893 amdgpu_sync_free(&(*mem)->sync);
1894 mutex_destroy(&(*mem)->lock);
1895 if (gobj)
1896 drm_gem_object_put(gobj);
1897 else
1898 kfree(*mem);
1899err:
1900 if (sg) {
1901 sg_free_table(sg);
1902 kfree(sg);
1903 }
1904 return ret;
1905}
1906
1907int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1908 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1909 uint64_t *size)
1910{
1911 struct amdkfd_process_info *process_info = mem->process_info;
1912 unsigned long bo_size = mem->bo->tbo.base.size;
1913 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1914 struct kfd_mem_attachment *entry, *tmp;
1915 struct bo_vm_reservation_context ctx;
1916 unsigned int mapped_to_gpu_memory;
1917 int ret;
1918 bool is_imported = false;
1919
1920 mutex_lock(&mem->lock);
1921
1922 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1923 if (mem->alloc_flags &
1924 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1925 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1926 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1927 }
1928
1929 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1930 is_imported = mem->is_imported;
1931 mutex_unlock(&mem->lock);
1932 /* lock is not needed after this, since mem is unused and will
1933 * be freed anyway
1934 */
1935
1936 if (mapped_to_gpu_memory > 0) {
1937 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1938 mem->va, bo_size);
1939 return -EBUSY;
1940 }
1941
1942 /* Make sure restore workers don't access the BO any more */
1943 mutex_lock(&process_info->lock);
1944 list_del(&mem->validate_list);
1945 mutex_unlock(&process_info->lock);
1946
1947 /* Cleanup user pages and MMU notifiers */
1948 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1949 amdgpu_hmm_unregister(mem->bo);
1950 mutex_lock(&process_info->notifier_lock);
1951 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1952 mutex_unlock(&process_info->notifier_lock);
1953 }
1954
1955 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1956 if (unlikely(ret))
1957 return ret;
1958
1959 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1960 process_info->eviction_fence);
1961 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1962 mem->va + bo_size * (1 + mem->aql_queue));
1963
1964 /* Remove from VM internal data structures */
1965 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1966 kfd_mem_dmaunmap_attachment(mem, entry);
1967 kfd_mem_detach(entry);
1968 }
1969
1970 ret = unreserve_bo_and_vms(&ctx, false, false);
1971
1972 /* Free the sync object */
1973 amdgpu_sync_free(&mem->sync);
1974
1975 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1976 * remap BO. We need to free it.
1977 */
1978 if (mem->bo->tbo.sg) {
1979 sg_free_table(mem->bo->tbo.sg);
1980 kfree(mem->bo->tbo.sg);
1981 }
1982
1983 /* Update the size of the BO being freed if it was allocated from
1984 * VRAM and is not imported. For APP APU VRAM allocations are done
1985 * in GTT domain
1986 */
1987 if (size) {
1988 if (!is_imported &&
1989 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1990 ((adev->flags & AMD_IS_APU) &&
1991 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1992 *size = bo_size;
1993 else
1994 *size = 0;
1995 }
1996
1997 /* Free the BO*/
1998 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1999 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
2000 if (mem->dmabuf) {
2001 dma_buf_put(mem->dmabuf);
2002 mem->dmabuf = NULL;
2003 }
2004 mutex_destroy(&mem->lock);
2005
2006 /* If this releases the last reference, it will end up calling
2007 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
2008 * this needs to be the last call here.
2009 */
2010 drm_gem_object_put(&mem->bo->tbo.base);
2011
2012 /*
2013 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
2014 * explicitly free it here.
2015 */
2016 if (!use_release_notifier)
2017 kfree(mem);
2018
2019 return ret;
2020}
2021
2022int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
2023 struct amdgpu_device *adev, struct kgd_mem *mem,
2024 void *drm_priv)
2025{
2026 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2027 int ret;
2028 struct amdgpu_bo *bo;
2029 uint32_t domain;
2030 struct kfd_mem_attachment *entry;
2031 struct bo_vm_reservation_context ctx;
2032 unsigned long bo_size;
2033 bool is_invalid_userptr = false;
2034
2035 bo = mem->bo;
2036 if (!bo) {
2037 pr_err("Invalid BO when mapping memory to GPU\n");
2038 return -EINVAL;
2039 }
2040
2041 /* Make sure restore is not running concurrently. Since we
2042 * don't map invalid userptr BOs, we rely on the next restore
2043 * worker to do the mapping
2044 */
2045 mutex_lock(&mem->process_info->lock);
2046
2047 /* Lock notifier lock. If we find an invalid userptr BO, we can be
2048 * sure that the MMU notifier is no longer running
2049 * concurrently and the queues are actually stopped
2050 */
2051 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2052 mutex_lock(&mem->process_info->notifier_lock);
2053 is_invalid_userptr = !!mem->invalid;
2054 mutex_unlock(&mem->process_info->notifier_lock);
2055 }
2056
2057 mutex_lock(&mem->lock);
2058
2059 domain = mem->domain;
2060 bo_size = bo->tbo.base.size;
2061
2062 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2063 mem->va,
2064 mem->va + bo_size * (1 + mem->aql_queue),
2065 avm, domain_string(domain));
2066
2067 if (!kfd_mem_is_attached(avm, mem)) {
2068 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2069 if (ret)
2070 goto out;
2071 }
2072
2073 ret = reserve_bo_and_vm(mem, avm, &ctx);
2074 if (unlikely(ret))
2075 goto out;
2076
2077 /* Userptr can be marked as "not invalid", but not actually be
2078 * validated yet (still in the system domain). In that case
2079 * the queues are still stopped and we can leave mapping for
2080 * the next restore worker
2081 */
2082 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2083 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2084 is_invalid_userptr = true;
2085
2086 ret = vm_validate_pt_pd_bos(avm, NULL);
2087 if (unlikely(ret))
2088 goto out_unreserve;
2089
2090 list_for_each_entry(entry, &mem->attachments, list) {
2091 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2092 continue;
2093
2094 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2095 entry->va, entry->va + bo_size, entry);
2096
2097 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2098 is_invalid_userptr);
2099 if (ret) {
2100 pr_err("Failed to map bo to gpuvm\n");
2101 goto out_unreserve;
2102 }
2103
2104 ret = vm_update_pds(avm, ctx.sync);
2105 if (ret) {
2106 pr_err("Failed to update page directories\n");
2107 goto out_unreserve;
2108 }
2109
2110 entry->is_mapped = true;
2111 mem->mapped_to_gpu_memory++;
2112 pr_debug("\t INC mapping count %d\n",
2113 mem->mapped_to_gpu_memory);
2114 }
2115
2116 ret = unreserve_bo_and_vms(&ctx, false, false);
2117
2118 goto out;
2119
2120out_unreserve:
2121 unreserve_bo_and_vms(&ctx, false, false);
2122out:
2123 mutex_unlock(&mem->process_info->lock);
2124 mutex_unlock(&mem->lock);
2125 return ret;
2126}
2127
2128int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2129{
2130 struct kfd_mem_attachment *entry;
2131 struct amdgpu_vm *vm;
2132 int ret;
2133
2134 vm = drm_priv_to_vm(drm_priv);
2135
2136 mutex_lock(&mem->lock);
2137
2138 ret = amdgpu_bo_reserve(mem->bo, true);
2139 if (ret)
2140 goto out;
2141
2142 list_for_each_entry(entry, &mem->attachments, list) {
2143 if (entry->bo_va->base.vm != vm)
2144 continue;
2145 if (entry->bo_va->base.bo->tbo.ttm &&
2146 !entry->bo_va->base.bo->tbo.ttm->sg)
2147 continue;
2148
2149 kfd_mem_dmaunmap_attachment(mem, entry);
2150 }
2151
2152 amdgpu_bo_unreserve(mem->bo);
2153out:
2154 mutex_unlock(&mem->lock);
2155
2156 return ret;
2157}
2158
2159int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2160 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2161{
2162 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2163 unsigned long bo_size = mem->bo->tbo.base.size;
2164 struct kfd_mem_attachment *entry;
2165 struct bo_vm_reservation_context ctx;
2166 int ret;
2167
2168 mutex_lock(&mem->lock);
2169
2170 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2171 if (unlikely(ret))
2172 goto out;
2173 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2174 if (ctx.n_vms == 0) {
2175 ret = -EINVAL;
2176 goto unreserve_out;
2177 }
2178
2179 ret = vm_validate_pt_pd_bos(avm, NULL);
2180 if (unlikely(ret))
2181 goto unreserve_out;
2182
2183 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2184 mem->va,
2185 mem->va + bo_size * (1 + mem->aql_queue),
2186 avm);
2187
2188 list_for_each_entry(entry, &mem->attachments, list) {
2189 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2190 continue;
2191
2192 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2193 entry->va, entry->va + bo_size, entry);
2194
2195 ret = unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2196 if (ret)
2197 goto unreserve_out;
2198
2199 entry->is_mapped = false;
2200
2201 mem->mapped_to_gpu_memory--;
2202 pr_debug("\t DEC mapping count %d\n",
2203 mem->mapped_to_gpu_memory);
2204 }
2205
2206unreserve_out:
2207 unreserve_bo_and_vms(&ctx, false, false);
2208out:
2209 mutex_unlock(&mem->lock);
2210 return ret;
2211}
2212
2213int amdgpu_amdkfd_gpuvm_sync_memory(
2214 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2215{
2216 struct amdgpu_sync sync;
2217 int ret;
2218
2219 amdgpu_sync_create(&sync);
2220
2221 mutex_lock(&mem->lock);
2222 amdgpu_sync_clone(&mem->sync, &sync);
2223 mutex_unlock(&mem->lock);
2224
2225 ret = amdgpu_sync_wait(&sync, intr);
2226 amdgpu_sync_free(&sync);
2227 return ret;
2228}
2229
2230/**
2231 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2232 * @bo: Buffer object to be mapped
2233 * @bo_gart: Return bo reference
2234 *
2235 * Before return, bo reference count is incremented. To release the reference and unpin/
2236 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2237 */
2238int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart)
2239{
2240 int ret;
2241
2242 ret = amdgpu_bo_reserve(bo, true);
2243 if (ret) {
2244 pr_err("Failed to reserve bo. ret %d\n", ret);
2245 goto err_reserve_bo_failed;
2246 }
2247
2248 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2249 if (ret) {
2250 pr_err("Failed to pin bo. ret %d\n", ret);
2251 goto err_pin_bo_failed;
2252 }
2253
2254 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2255 if (ret) {
2256 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2257 goto err_map_bo_gart_failed;
2258 }
2259
2260 amdgpu_amdkfd_remove_eviction_fence(
2261 bo, bo->vm_bo->vm->process_info->eviction_fence);
2262
2263 amdgpu_bo_unreserve(bo);
2264
2265 *bo_gart = amdgpu_bo_ref(bo);
2266
2267 return 0;
2268
2269err_map_bo_gart_failed:
2270 amdgpu_bo_unpin(bo);
2271err_pin_bo_failed:
2272 amdgpu_bo_unreserve(bo);
2273err_reserve_bo_failed:
2274
2275 return ret;
2276}
2277
2278/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2279 *
2280 * @mem: Buffer object to be mapped for CPU access
2281 * @kptr[out]: pointer in kernel CPU address space
2282 * @size[out]: size of the buffer
2283 *
2284 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2285 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2286 * validate_list, so the GPU mapping can be restored after a page table was
2287 * evicted.
2288 *
2289 * Return: 0 on success, error code on failure
2290 */
2291int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2292 void **kptr, uint64_t *size)
2293{
2294 int ret;
2295 struct amdgpu_bo *bo = mem->bo;
2296
2297 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2298 pr_err("userptr can't be mapped to kernel\n");
2299 return -EINVAL;
2300 }
2301
2302 mutex_lock(&mem->process_info->lock);
2303
2304 ret = amdgpu_bo_reserve(bo, true);
2305 if (ret) {
2306 pr_err("Failed to reserve bo. ret %d\n", ret);
2307 goto bo_reserve_failed;
2308 }
2309
2310 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2311 if (ret) {
2312 pr_err("Failed to pin bo. ret %d\n", ret);
2313 goto pin_failed;
2314 }
2315
2316 ret = amdgpu_bo_kmap(bo, kptr);
2317 if (ret) {
2318 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2319 goto kmap_failed;
2320 }
2321
2322 amdgpu_amdkfd_remove_eviction_fence(
2323 bo, mem->process_info->eviction_fence);
2324
2325 if (size)
2326 *size = amdgpu_bo_size(bo);
2327
2328 amdgpu_bo_unreserve(bo);
2329
2330 mutex_unlock(&mem->process_info->lock);
2331 return 0;
2332
2333kmap_failed:
2334 amdgpu_bo_unpin(bo);
2335pin_failed:
2336 amdgpu_bo_unreserve(bo);
2337bo_reserve_failed:
2338 mutex_unlock(&mem->process_info->lock);
2339
2340 return ret;
2341}
2342
2343/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2344 *
2345 * @mem: Buffer object to be unmapped for CPU access
2346 *
2347 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2348 * eviction fence, so this function should only be used for cleanup before the
2349 * BO is destroyed.
2350 */
2351void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2352{
2353 struct amdgpu_bo *bo = mem->bo;
2354
2355 amdgpu_bo_reserve(bo, true);
2356 amdgpu_bo_kunmap(bo);
2357 amdgpu_bo_unpin(bo);
2358 amdgpu_bo_unreserve(bo);
2359}
2360
2361int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2362 struct kfd_vm_fault_info *mem)
2363{
2364 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2365 *mem = *adev->gmc.vm_fault_info;
2366 mb(); /* make sure read happened */
2367 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2368 }
2369 return 0;
2370}
2371
2372static int import_obj_create(struct amdgpu_device *adev,
2373 struct dma_buf *dma_buf,
2374 struct drm_gem_object *obj,
2375 uint64_t va, void *drm_priv,
2376 struct kgd_mem **mem, uint64_t *size,
2377 uint64_t *mmap_offset)
2378{
2379 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2380 struct amdgpu_bo *bo;
2381 int ret;
2382
2383 bo = gem_to_amdgpu_bo(obj);
2384 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2385 AMDGPU_GEM_DOMAIN_GTT)))
2386 /* Only VRAM and GTT BOs are supported */
2387 return -EINVAL;
2388
2389 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2390 if (!*mem)
2391 return -ENOMEM;
2392
2393 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2394 if (ret)
2395 goto err_free_mem;
2396
2397 if (size)
2398 *size = amdgpu_bo_size(bo);
2399
2400 if (mmap_offset)
2401 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2402
2403 INIT_LIST_HEAD(&(*mem)->attachments);
2404 mutex_init(&(*mem)->lock);
2405
2406 (*mem)->alloc_flags =
2407 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2408 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2409 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2410 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2411
2412 get_dma_buf(dma_buf);
2413 (*mem)->dmabuf = dma_buf;
2414 (*mem)->bo = bo;
2415 (*mem)->va = va;
2416 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) &&
2417 !(adev->flags & AMD_IS_APU) ?
2418 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2419
2420 (*mem)->mapped_to_gpu_memory = 0;
2421 (*mem)->process_info = avm->process_info;
2422 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2423 amdgpu_sync_create(&(*mem)->sync);
2424 (*mem)->is_imported = true;
2425
2426 mutex_lock(&avm->process_info->lock);
2427 if (avm->process_info->eviction_fence &&
2428 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2429 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2430 &avm->process_info->eviction_fence->base);
2431 mutex_unlock(&avm->process_info->lock);
2432 if (ret)
2433 goto err_remove_mem;
2434
2435 return 0;
2436
2437err_remove_mem:
2438 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2439 drm_vma_node_revoke(&obj->vma_node, drm_priv);
2440err_free_mem:
2441 kfree(*mem);
2442 return ret;
2443}
2444
2445int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2446 uint64_t va, void *drm_priv,
2447 struct kgd_mem **mem, uint64_t *size,
2448 uint64_t *mmap_offset)
2449{
2450 struct drm_gem_object *obj;
2451 uint32_t handle;
2452 int ret;
2453
2454 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2455 &handle);
2456 if (ret)
2457 return ret;
2458 obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2459 if (!obj) {
2460 ret = -EINVAL;
2461 goto err_release_handle;
2462 }
2463
2464 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2465 mmap_offset);
2466 if (ret)
2467 goto err_put_obj;
2468
2469 (*mem)->gem_handle = handle;
2470
2471 return 0;
2472
2473err_put_obj:
2474 drm_gem_object_put(obj);
2475err_release_handle:
2476 drm_gem_handle_delete(adev->kfd.client.file, handle);
2477 return ret;
2478}
2479
2480int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2481 struct dma_buf **dma_buf)
2482{
2483 int ret;
2484
2485 mutex_lock(&mem->lock);
2486 ret = kfd_mem_export_dmabuf(mem);
2487 if (ret)
2488 goto out;
2489
2490 get_dma_buf(mem->dmabuf);
2491 *dma_buf = mem->dmabuf;
2492out:
2493 mutex_unlock(&mem->lock);
2494 return ret;
2495}
2496
2497/* Evict a userptr BO by stopping the queues if necessary
2498 *
2499 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2500 * cannot do any memory allocations, and cannot take any locks that
2501 * are held elsewhere while allocating memory.
2502 *
2503 * It doesn't do anything to the BO itself. The real work happens in
2504 * restore, where we get updated page addresses. This function only
2505 * ensures that GPU access to the BO is stopped.
2506 */
2507int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2508 unsigned long cur_seq, struct kgd_mem *mem)
2509{
2510 struct amdkfd_process_info *process_info = mem->process_info;
2511 int r = 0;
2512
2513 /* Do not process MMU notifications during CRIU restore until
2514 * KFD_CRIU_OP_RESUME IOCTL is received
2515 */
2516 if (READ_ONCE(process_info->block_mmu_notifications))
2517 return 0;
2518
2519 mutex_lock(&process_info->notifier_lock);
2520 mmu_interval_set_seq(mni, cur_seq);
2521
2522 mem->invalid++;
2523 if (++process_info->evicted_bos == 1) {
2524 /* First eviction, stop the queues */
2525 r = kgd2kfd_quiesce_mm(mni->mm,
2526 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2527
2528 if (r && r != -ESRCH)
2529 pr_err("Failed to quiesce KFD\n");
2530
2531 if (r != -ESRCH)
2532 queue_delayed_work(system_freezable_wq,
2533 &process_info->restore_userptr_work,
2534 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2535 }
2536 mutex_unlock(&process_info->notifier_lock);
2537
2538 return r;
2539}
2540
2541/* Update invalid userptr BOs
2542 *
2543 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2544 * userptr_inval_list and updates user pages for all BOs that have
2545 * been invalidated since their last update.
2546 */
2547static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2548 struct mm_struct *mm)
2549{
2550 struct kgd_mem *mem, *tmp_mem;
2551 struct amdgpu_bo *bo;
2552 struct ttm_operation_ctx ctx = { false, false };
2553 uint32_t invalid;
2554 int ret = 0;
2555
2556 mutex_lock(&process_info->notifier_lock);
2557
2558 /* Move all invalidated BOs to the userptr_inval_list */
2559 list_for_each_entry_safe(mem, tmp_mem,
2560 &process_info->userptr_valid_list,
2561 validate_list)
2562 if (mem->invalid)
2563 list_move_tail(&mem->validate_list,
2564 &process_info->userptr_inval_list);
2565
2566 /* Go through userptr_inval_list and update any invalid user_pages */
2567 list_for_each_entry(mem, &process_info->userptr_inval_list,
2568 validate_list) {
2569 invalid = mem->invalid;
2570 if (!invalid)
2571 /* BO hasn't been invalidated since the last
2572 * revalidation attempt. Keep its page list.
2573 */
2574 continue;
2575
2576 bo = mem->bo;
2577
2578 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2579 mem->range = NULL;
2580
2581 /* BO reservations and getting user pages (hmm_range_fault)
2582 * must happen outside the notifier lock
2583 */
2584 mutex_unlock(&process_info->notifier_lock);
2585
2586 /* Move the BO to system (CPU) domain if necessary to unmap
2587 * and free the SG table
2588 */
2589 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2590 if (amdgpu_bo_reserve(bo, true))
2591 return -EAGAIN;
2592 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2593 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2594 amdgpu_bo_unreserve(bo);
2595 if (ret) {
2596 pr_err("%s: Failed to invalidate userptr BO\n",
2597 __func__);
2598 return -EAGAIN;
2599 }
2600 }
2601
2602 /* Get updated user pages */
2603 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2604 &mem->range);
2605 if (ret) {
2606 pr_debug("Failed %d to get user pages\n", ret);
2607
2608 /* Return -EFAULT bad address error as success. It will
2609 * fail later with a VM fault if the GPU tries to access
2610 * it. Better than hanging indefinitely with stalled
2611 * user mode queues.
2612 *
2613 * Return other error -EBUSY or -ENOMEM to retry restore
2614 */
2615 if (ret != -EFAULT)
2616 return ret;
2617
2618 ret = 0;
2619 }
2620
2621 mutex_lock(&process_info->notifier_lock);
2622
2623 /* Mark the BO as valid unless it was invalidated
2624 * again concurrently.
2625 */
2626 if (mem->invalid != invalid) {
2627 ret = -EAGAIN;
2628 goto unlock_out;
2629 }
2630 /* set mem valid if mem has hmm range associated */
2631 if (mem->range)
2632 mem->invalid = 0;
2633 }
2634
2635unlock_out:
2636 mutex_unlock(&process_info->notifier_lock);
2637
2638 return ret;
2639}
2640
2641/* Validate invalid userptr BOs
2642 *
2643 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2644 * with new page addresses and waits for the page table updates to complete.
2645 */
2646static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2647{
2648 struct ttm_operation_ctx ctx = { false, false };
2649 struct amdgpu_sync sync;
2650 struct drm_exec exec;
2651
2652 struct amdgpu_vm *peer_vm;
2653 struct kgd_mem *mem, *tmp_mem;
2654 struct amdgpu_bo *bo;
2655 int ret;
2656
2657 amdgpu_sync_create(&sync);
2658
2659 drm_exec_init(&exec, 0, 0);
2660 /* Reserve all BOs and page tables for validation */
2661 drm_exec_until_all_locked(&exec) {
2662 /* Reserve all the page directories */
2663 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2664 vm_list_node) {
2665 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2666 drm_exec_retry_on_contention(&exec);
2667 if (unlikely(ret))
2668 goto unreserve_out;
2669 }
2670
2671 /* Reserve the userptr_inval_list entries to resv_list */
2672 list_for_each_entry(mem, &process_info->userptr_inval_list,
2673 validate_list) {
2674 struct drm_gem_object *gobj;
2675
2676 gobj = &mem->bo->tbo.base;
2677 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2678 drm_exec_retry_on_contention(&exec);
2679 if (unlikely(ret))
2680 goto unreserve_out;
2681 }
2682 }
2683
2684 ret = process_validate_vms(process_info, NULL);
2685 if (ret)
2686 goto unreserve_out;
2687
2688 /* Validate BOs and update GPUVM page tables */
2689 list_for_each_entry_safe(mem, tmp_mem,
2690 &process_info->userptr_inval_list,
2691 validate_list) {
2692 struct kfd_mem_attachment *attachment;
2693
2694 bo = mem->bo;
2695
2696 /* Validate the BO if we got user pages */
2697 if (bo->tbo.ttm->pages[0]) {
2698 amdgpu_bo_placement_from_domain(bo, mem->domain);
2699 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2700 if (ret) {
2701 pr_err("%s: failed to validate BO\n", __func__);
2702 goto unreserve_out;
2703 }
2704 }
2705
2706 /* Update mapping. If the BO was not validated
2707 * (because we couldn't get user pages), this will
2708 * clear the page table entries, which will result in
2709 * VM faults if the GPU tries to access the invalid
2710 * memory.
2711 */
2712 list_for_each_entry(attachment, &mem->attachments, list) {
2713 if (!attachment->is_mapped)
2714 continue;
2715
2716 kfd_mem_dmaunmap_attachment(mem, attachment);
2717 ret = update_gpuvm_pte(mem, attachment, &sync);
2718 if (ret) {
2719 pr_err("%s: update PTE failed\n", __func__);
2720 /* make sure this gets validated again */
2721 mutex_lock(&process_info->notifier_lock);
2722 mem->invalid++;
2723 mutex_unlock(&process_info->notifier_lock);
2724 goto unreserve_out;
2725 }
2726 }
2727 }
2728
2729 /* Update page directories */
2730 ret = process_update_pds(process_info, &sync);
2731
2732unreserve_out:
2733 drm_exec_fini(&exec);
2734 amdgpu_sync_wait(&sync, false);
2735 amdgpu_sync_free(&sync);
2736
2737 return ret;
2738}
2739
2740/* Confirm that all user pages are valid while holding the notifier lock
2741 *
2742 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2743 */
2744static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2745{
2746 struct kgd_mem *mem, *tmp_mem;
2747 int ret = 0;
2748
2749 list_for_each_entry_safe(mem, tmp_mem,
2750 &process_info->userptr_inval_list,
2751 validate_list) {
2752 bool valid;
2753
2754 /* keep mem without hmm range at userptr_inval_list */
2755 if (!mem->range)
2756 continue;
2757
2758 /* Only check mem with hmm range associated */
2759 valid = amdgpu_ttm_tt_get_user_pages_done(
2760 mem->bo->tbo.ttm, mem->range);
2761
2762 mem->range = NULL;
2763 if (!valid) {
2764 WARN(!mem->invalid, "Invalid BO not marked invalid");
2765 ret = -EAGAIN;
2766 continue;
2767 }
2768
2769 if (mem->invalid) {
2770 WARN(1, "Valid BO is marked invalid");
2771 ret = -EAGAIN;
2772 continue;
2773 }
2774
2775 list_move_tail(&mem->validate_list,
2776 &process_info->userptr_valid_list);
2777 }
2778
2779 return ret;
2780}
2781
2782/* Worker callback to restore evicted userptr BOs
2783 *
2784 * Tries to update and validate all userptr BOs. If successful and no
2785 * concurrent evictions happened, the queues are restarted. Otherwise,
2786 * reschedule for another attempt later.
2787 */
2788static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2789{
2790 struct delayed_work *dwork = to_delayed_work(work);
2791 struct amdkfd_process_info *process_info =
2792 container_of(dwork, struct amdkfd_process_info,
2793 restore_userptr_work);
2794 struct task_struct *usertask;
2795 struct mm_struct *mm;
2796 uint32_t evicted_bos;
2797
2798 mutex_lock(&process_info->notifier_lock);
2799 evicted_bos = process_info->evicted_bos;
2800 mutex_unlock(&process_info->notifier_lock);
2801 if (!evicted_bos)
2802 return;
2803
2804 /* Reference task and mm in case of concurrent process termination */
2805 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2806 if (!usertask)
2807 return;
2808 mm = get_task_mm(usertask);
2809 if (!mm) {
2810 put_task_struct(usertask);
2811 return;
2812 }
2813
2814 mutex_lock(&process_info->lock);
2815
2816 if (update_invalid_user_pages(process_info, mm))
2817 goto unlock_out;
2818 /* userptr_inval_list can be empty if all evicted userptr BOs
2819 * have been freed. In that case there is nothing to validate
2820 * and we can just restart the queues.
2821 */
2822 if (!list_empty(&process_info->userptr_inval_list)) {
2823 if (validate_invalid_user_pages(process_info))
2824 goto unlock_out;
2825 }
2826 /* Final check for concurrent evicton and atomic update. If
2827 * another eviction happens after successful update, it will
2828 * be a first eviction that calls quiesce_mm. The eviction
2829 * reference counting inside KFD will handle this case.
2830 */
2831 mutex_lock(&process_info->notifier_lock);
2832 if (process_info->evicted_bos != evicted_bos)
2833 goto unlock_notifier_out;
2834
2835 if (confirm_valid_user_pages_locked(process_info)) {
2836 WARN(1, "User pages unexpectedly invalid");
2837 goto unlock_notifier_out;
2838 }
2839
2840 process_info->evicted_bos = evicted_bos = 0;
2841
2842 if (kgd2kfd_resume_mm(mm)) {
2843 pr_err("%s: Failed to resume KFD\n", __func__);
2844 /* No recovery from this failure. Probably the CP is
2845 * hanging. No point trying again.
2846 */
2847 }
2848
2849unlock_notifier_out:
2850 mutex_unlock(&process_info->notifier_lock);
2851unlock_out:
2852 mutex_unlock(&process_info->lock);
2853
2854 /* If validation failed, reschedule another attempt */
2855 if (evicted_bos) {
2856 queue_delayed_work(system_freezable_wq,
2857 &process_info->restore_userptr_work,
2858 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2859
2860 kfd_smi_event_queue_restore_rescheduled(mm);
2861 }
2862 mmput(mm);
2863 put_task_struct(usertask);
2864}
2865
2866static void replace_eviction_fence(struct dma_fence __rcu **ef,
2867 struct dma_fence *new_ef)
2868{
2869 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2870 /* protected by process_info->lock */);
2871
2872 /* If we're replacing an unsignaled eviction fence, that fence will
2873 * never be signaled, and if anyone is still waiting on that fence,
2874 * they will hang forever. This should never happen. We should only
2875 * replace the fence in restore_work that only gets scheduled after
2876 * eviction work signaled the fence.
2877 */
2878 WARN_ONCE(!dma_fence_is_signaled(old_ef),
2879 "Replacing unsignaled eviction fence");
2880 dma_fence_put(old_ef);
2881}
2882
2883/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2884 * KFD process identified by process_info
2885 *
2886 * @process_info: amdkfd_process_info of the KFD process
2887 *
2888 * After memory eviction, restore thread calls this function. The function
2889 * should be called when the Process is still valid. BO restore involves -
2890 *
2891 * 1. Release old eviction fence and create new one
2892 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2893 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2894 * BOs that need to be reserved.
2895 * 4. Reserve all the BOs
2896 * 5. Validate of PD and PT BOs.
2897 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2898 * 7. Add fence to all PD and PT BOs.
2899 * 8. Unreserve all BOs
2900 */
2901int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)
2902{
2903 struct amdkfd_process_info *process_info = info;
2904 struct amdgpu_vm *peer_vm;
2905 struct kgd_mem *mem;
2906 struct list_head duplicate_save;
2907 struct amdgpu_sync sync_obj;
2908 unsigned long failed_size = 0;
2909 unsigned long total_size = 0;
2910 struct drm_exec exec;
2911 int ret;
2912
2913 INIT_LIST_HEAD(&duplicate_save);
2914
2915 mutex_lock(&process_info->lock);
2916
2917 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
2918 drm_exec_until_all_locked(&exec) {
2919 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2920 vm_list_node) {
2921 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2922 drm_exec_retry_on_contention(&exec);
2923 if (unlikely(ret)) {
2924 pr_err("Locking VM PD failed, ret: %d\n", ret);
2925 goto ttm_reserve_fail;
2926 }
2927 }
2928
2929 /* Reserve all BOs and page tables/directory. Add all BOs from
2930 * kfd_bo_list to ctx.list
2931 */
2932 list_for_each_entry(mem, &process_info->kfd_bo_list,
2933 validate_list) {
2934 struct drm_gem_object *gobj;
2935
2936 gobj = &mem->bo->tbo.base;
2937 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2938 drm_exec_retry_on_contention(&exec);
2939 if (unlikely(ret)) {
2940 pr_err("drm_exec_prepare_obj failed, ret: %d\n", ret);
2941 goto ttm_reserve_fail;
2942 }
2943 }
2944 }
2945
2946 amdgpu_sync_create(&sync_obj);
2947
2948 /* Validate BOs managed by KFD */
2949 list_for_each_entry(mem, &process_info->kfd_bo_list,
2950 validate_list) {
2951
2952 struct amdgpu_bo *bo = mem->bo;
2953 uint32_t domain = mem->domain;
2954 struct dma_resv_iter cursor;
2955 struct dma_fence *fence;
2956
2957 total_size += amdgpu_bo_size(bo);
2958
2959 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2960 if (ret) {
2961 pr_debug("Memory eviction: Validate BOs failed\n");
2962 failed_size += amdgpu_bo_size(bo);
2963 ret = amdgpu_amdkfd_bo_validate(bo,
2964 AMDGPU_GEM_DOMAIN_GTT, false);
2965 if (ret) {
2966 pr_debug("Memory eviction: Try again\n");
2967 goto validate_map_fail;
2968 }
2969 }
2970 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2971 DMA_RESV_USAGE_KERNEL, fence) {
2972 ret = amdgpu_sync_fence(&sync_obj, fence);
2973 if (ret) {
2974 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2975 goto validate_map_fail;
2976 }
2977 }
2978 }
2979
2980 if (failed_size)
2981 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2982
2983 /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
2984 * validations above would invalidate DMABuf imports again.
2985 */
2986 ret = process_validate_vms(process_info, &exec.ticket);
2987 if (ret) {
2988 pr_debug("Validating VMs failed, ret: %d\n", ret);
2989 goto validate_map_fail;
2990 }
2991
2992 /* Update mappings managed by KFD. */
2993 list_for_each_entry(mem, &process_info->kfd_bo_list,
2994 validate_list) {
2995 struct kfd_mem_attachment *attachment;
2996
2997 list_for_each_entry(attachment, &mem->attachments, list) {
2998 if (!attachment->is_mapped)
2999 continue;
3000
3001 kfd_mem_dmaunmap_attachment(mem, attachment);
3002 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
3003 if (ret) {
3004 pr_debug("Memory eviction: update PTE failed. Try again\n");
3005 goto validate_map_fail;
3006 }
3007 }
3008 }
3009
3010 /* Update mappings not managed by KFD */
3011 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3012 vm_list_node) {
3013 struct amdgpu_device *adev = amdgpu_ttm_adev(
3014 peer_vm->root.bo->tbo.bdev);
3015
3016 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket);
3017 if (ret) {
3018 pr_debug("Memory eviction: handle moved failed. Try again\n");
3019 goto validate_map_fail;
3020 }
3021 }
3022
3023 /* Update page directories */
3024 ret = process_update_pds(process_info, &sync_obj);
3025 if (ret) {
3026 pr_debug("Memory eviction: update PDs failed. Try again\n");
3027 goto validate_map_fail;
3028 }
3029
3030 /* Sync with fences on all the page tables. They implicitly depend on any
3031 * move fences from amdgpu_vm_handle_moved above.
3032 */
3033 ret = process_sync_pds_resv(process_info, &sync_obj);
3034 if (ret) {
3035 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
3036 goto validate_map_fail;
3037 }
3038
3039 /* Wait for validate and PT updates to finish */
3040 amdgpu_sync_wait(&sync_obj, false);
3041
3042 /* The old eviction fence may be unsignaled if restore happens
3043 * after a GPU reset or suspend/resume. Keep the old fence in that
3044 * case. Otherwise release the old eviction fence and create new
3045 * one, because fence only goes from unsignaled to signaled once
3046 * and cannot be reused. Use context and mm from the old fence.
3047 *
3048 * If an old eviction fence signals after this check, that's OK.
3049 * Anyone signaling an eviction fence must stop the queues first
3050 * and schedule another restore worker.
3051 */
3052 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
3053 struct amdgpu_amdkfd_fence *new_fence =
3054 amdgpu_amdkfd_fence_create(
3055 process_info->eviction_fence->base.context,
3056 process_info->eviction_fence->mm,
3057 NULL);
3058
3059 if (!new_fence) {
3060 pr_err("Failed to create eviction fence\n");
3061 ret = -ENOMEM;
3062 goto validate_map_fail;
3063 }
3064 dma_fence_put(&process_info->eviction_fence->base);
3065 process_info->eviction_fence = new_fence;
3066 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
3067 } else {
3068 WARN_ONCE(*ef != &process_info->eviction_fence->base,
3069 "KFD eviction fence doesn't match KGD process_info");
3070 }
3071
3072 /* Attach new eviction fence to all BOs except pinned ones */
3073 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3074 if (mem->bo->tbo.pin_count)
3075 continue;
3076
3077 dma_resv_add_fence(mem->bo->tbo.base.resv,
3078 &process_info->eviction_fence->base,
3079 DMA_RESV_USAGE_BOOKKEEP);
3080 }
3081 /* Attach eviction fence to PD / PT BOs and DMABuf imports */
3082 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3083 vm_list_node) {
3084 struct amdgpu_bo *bo = peer_vm->root.bo;
3085
3086 dma_resv_add_fence(bo->tbo.base.resv,
3087 &process_info->eviction_fence->base,
3088 DMA_RESV_USAGE_BOOKKEEP);
3089 }
3090
3091validate_map_fail:
3092 amdgpu_sync_free(&sync_obj);
3093ttm_reserve_fail:
3094 drm_exec_fini(&exec);
3095 mutex_unlock(&process_info->lock);
3096 return ret;
3097}
3098
3099int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3100{
3101 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3102 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3103 int ret;
3104
3105 if (!info || !gws)
3106 return -EINVAL;
3107
3108 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
3109 if (!*mem)
3110 return -ENOMEM;
3111
3112 mutex_init(&(*mem)->lock);
3113 INIT_LIST_HEAD(&(*mem)->attachments);
3114 (*mem)->bo = amdgpu_bo_ref(gws_bo);
3115 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3116 (*mem)->process_info = process_info;
3117 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3118 amdgpu_sync_create(&(*mem)->sync);
3119
3120
3121 /* Validate gws bo the first time it is added to process */
3122 mutex_lock(&(*mem)->process_info->lock);
3123 ret = amdgpu_bo_reserve(gws_bo, false);
3124 if (unlikely(ret)) {
3125 pr_err("Reserve gws bo failed %d\n", ret);
3126 goto bo_reservation_failure;
3127 }
3128
3129 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3130 if (ret) {
3131 pr_err("GWS BO validate failed %d\n", ret);
3132 goto bo_validation_failure;
3133 }
3134 /* GWS resource is shared b/t amdgpu and amdkfd
3135 * Add process eviction fence to bo so they can
3136 * evict each other.
3137 */
3138 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3139 if (ret)
3140 goto reserve_shared_fail;
3141 dma_resv_add_fence(gws_bo->tbo.base.resv,
3142 &process_info->eviction_fence->base,
3143 DMA_RESV_USAGE_BOOKKEEP);
3144 amdgpu_bo_unreserve(gws_bo);
3145 mutex_unlock(&(*mem)->process_info->lock);
3146
3147 return ret;
3148
3149reserve_shared_fail:
3150bo_validation_failure:
3151 amdgpu_bo_unreserve(gws_bo);
3152bo_reservation_failure:
3153 mutex_unlock(&(*mem)->process_info->lock);
3154 amdgpu_sync_free(&(*mem)->sync);
3155 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3156 amdgpu_bo_unref(&gws_bo);
3157 mutex_destroy(&(*mem)->lock);
3158 kfree(*mem);
3159 *mem = NULL;
3160 return ret;
3161}
3162
3163int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3164{
3165 int ret;
3166 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3167 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3168 struct amdgpu_bo *gws_bo = kgd_mem->bo;
3169
3170 /* Remove BO from process's validate list so restore worker won't touch
3171 * it anymore
3172 */
3173 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3174
3175 ret = amdgpu_bo_reserve(gws_bo, false);
3176 if (unlikely(ret)) {
3177 pr_err("Reserve gws bo failed %d\n", ret);
3178 //TODO add BO back to validate_list?
3179 return ret;
3180 }
3181 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3182 process_info->eviction_fence);
3183 amdgpu_bo_unreserve(gws_bo);
3184 amdgpu_sync_free(&kgd_mem->sync);
3185 amdgpu_bo_unref(&gws_bo);
3186 mutex_destroy(&kgd_mem->lock);
3187 kfree(mem);
3188 return 0;
3189}
3190
3191/* Returns GPU-specific tiling mode information */
3192int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3193 struct tile_config *config)
3194{
3195 config->gb_addr_config = adev->gfx.config.gb_addr_config;
3196 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3197 config->num_tile_configs =
3198 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3199 config->macro_tile_config_ptr =
3200 adev->gfx.config.macrotile_mode_array;
3201 config->num_macro_tile_configs =
3202 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3203
3204 /* Those values are not set from GFX9 onwards */
3205 config->num_banks = adev->gfx.config.num_banks;
3206 config->num_ranks = adev->gfx.config.num_ranks;
3207
3208 return 0;
3209}
3210
3211bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem)
3212{
3213 struct amdgpu_vm *vm = drm_priv_to_vm(drm_priv);
3214 struct kfd_mem_attachment *entry;
3215
3216 list_for_each_entry(entry, &mem->attachments, list) {
3217 if (entry->is_mapped && entry->bo_va->base.vm == vm)
3218 return true;
3219 }
3220 return false;
3221}
3222
3223#if defined(CONFIG_DEBUG_FS)
3224
3225int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3226{
3227
3228 spin_lock(&kfd_mem_limit.mem_limit_lock);
3229 seq_printf(m, "System mem used %lldM out of %lluM\n",
3230 (kfd_mem_limit.system_mem_used >> 20),
3231 (kfd_mem_limit.max_system_mem_limit >> 20));
3232 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3233 (kfd_mem_limit.ttm_mem_used >> 20),
3234 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3235 spin_unlock(&kfd_mem_limit.mem_limit_lock);
3236
3237 return 0;
3238}
3239
3240#endif
1/*
2 * Copyright 2014-2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#define pr_fmt(fmt) "kfd2kgd: " fmt
24
25#include <linux/dma-buf.h>
26#include <linux/list.h>
27#include <linux/pagemap.h>
28#include <linux/sched/mm.h>
29#include <linux/sched/task.h>
30
31#include "amdgpu_object.h"
32#include "amdgpu_vm.h"
33#include "amdgpu_amdkfd.h"
34#include "amdgpu_dma_buf.h"
35
36/* Special VM and GART address alignment needed for VI pre-Fiji due to
37 * a HW bug.
38 */
39#define VI_BO_SIZE_ALIGN (0x8000)
40
41/* BO flag to indicate a KFD userptr BO */
42#define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
43
44/* Userptr restore delay, just long enough to allow consecutive VM
45 * changes to accumulate
46 */
47#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
48
49/* Impose limit on how much memory KFD can use */
50static struct {
51 uint64_t max_system_mem_limit;
52 uint64_t max_ttm_mem_limit;
53 int64_t system_mem_used;
54 int64_t ttm_mem_used;
55 spinlock_t mem_limit_lock;
56} kfd_mem_limit;
57
58/* Struct used for amdgpu_amdkfd_bo_validate */
59struct amdgpu_vm_parser {
60 uint32_t domain;
61 bool wait;
62};
63
64static const char * const domain_bit_to_string[] = {
65 "CPU",
66 "GTT",
67 "VRAM",
68 "GDS",
69 "GWS",
70 "OA"
71};
72
73#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
74
75static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
76
77
78static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
79{
80 return (struct amdgpu_device *)kgd;
81}
82
83static bool check_if_add_bo_to_vm(struct amdgpu_vm *avm,
84 struct kgd_mem *mem)
85{
86 struct kfd_bo_va_list *entry;
87
88 list_for_each_entry(entry, &mem->bo_va_list, bo_list)
89 if (entry->bo_va->base.vm == avm)
90 return false;
91
92 return true;
93}
94
95/* Set memory usage limits. Current, limits are
96 * System (TTM + userptr) memory - 3/4th System RAM
97 * TTM memory - 3/8th System RAM
98 */
99void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
100{
101 struct sysinfo si;
102 uint64_t mem;
103
104 si_meminfo(&si);
105 mem = si.totalram - si.totalhigh;
106 mem *= si.mem_unit;
107
108 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
109 kfd_mem_limit.max_system_mem_limit = (mem >> 1) + (mem >> 2);
110 kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
111 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
112 (kfd_mem_limit.max_system_mem_limit >> 20),
113 (kfd_mem_limit.max_ttm_mem_limit >> 20));
114}
115
116static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
117 uint64_t size, u32 domain, bool sg)
118{
119 size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
120 uint64_t reserved_for_pt = amdgpu_amdkfd_total_mem_size >> 9;
121 int ret = 0;
122
123 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
124 sizeof(struct amdgpu_bo));
125
126 vram_needed = 0;
127 if (domain == AMDGPU_GEM_DOMAIN_GTT) {
128 /* TTM GTT memory */
129 system_mem_needed = acc_size + size;
130 ttm_mem_needed = acc_size + size;
131 } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
132 /* Userptr */
133 system_mem_needed = acc_size + size;
134 ttm_mem_needed = acc_size;
135 } else {
136 /* VRAM and SG */
137 system_mem_needed = acc_size;
138 ttm_mem_needed = acc_size;
139 if (domain == AMDGPU_GEM_DOMAIN_VRAM)
140 vram_needed = size;
141 }
142
143 spin_lock(&kfd_mem_limit.mem_limit_lock);
144
145 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
146 kfd_mem_limit.max_system_mem_limit) ||
147 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
148 kfd_mem_limit.max_ttm_mem_limit) ||
149 (adev->kfd.vram_used + vram_needed >
150 adev->gmc.real_vram_size - reserved_for_pt)) {
151 ret = -ENOMEM;
152 } else {
153 kfd_mem_limit.system_mem_used += system_mem_needed;
154 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
155 adev->kfd.vram_used += vram_needed;
156 }
157
158 spin_unlock(&kfd_mem_limit.mem_limit_lock);
159 return ret;
160}
161
162static void unreserve_mem_limit(struct amdgpu_device *adev,
163 uint64_t size, u32 domain, bool sg)
164{
165 size_t acc_size;
166
167 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
168 sizeof(struct amdgpu_bo));
169
170 spin_lock(&kfd_mem_limit.mem_limit_lock);
171 if (domain == AMDGPU_GEM_DOMAIN_GTT) {
172 kfd_mem_limit.system_mem_used -= (acc_size + size);
173 kfd_mem_limit.ttm_mem_used -= (acc_size + size);
174 } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
175 kfd_mem_limit.system_mem_used -= (acc_size + size);
176 kfd_mem_limit.ttm_mem_used -= acc_size;
177 } else {
178 kfd_mem_limit.system_mem_used -= acc_size;
179 kfd_mem_limit.ttm_mem_used -= acc_size;
180 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
181 adev->kfd.vram_used -= size;
182 WARN_ONCE(adev->kfd.vram_used < 0,
183 "kfd VRAM memory accounting unbalanced");
184 }
185 }
186 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
187 "kfd system memory accounting unbalanced");
188 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
189 "kfd TTM memory accounting unbalanced");
190
191 spin_unlock(&kfd_mem_limit.mem_limit_lock);
192}
193
194void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
195{
196 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
197 u32 domain = bo->preferred_domains;
198 bool sg = (bo->preferred_domains == AMDGPU_GEM_DOMAIN_CPU);
199
200 if (bo->flags & AMDGPU_AMDKFD_USERPTR_BO) {
201 domain = AMDGPU_GEM_DOMAIN_CPU;
202 sg = false;
203 }
204
205 unreserve_mem_limit(adev, amdgpu_bo_size(bo), domain, sg);
206}
207
208
209/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
210 * reservation object.
211 *
212 * @bo: [IN] Remove eviction fence(s) from this BO
213 * @ef: [IN] This eviction fence is removed if it
214 * is present in the shared list.
215 *
216 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
217 */
218static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
219 struct amdgpu_amdkfd_fence *ef)
220{
221 struct dma_resv *resv = bo->tbo.base.resv;
222 struct dma_resv_list *old, *new;
223 unsigned int i, j, k;
224
225 if (!ef)
226 return -EINVAL;
227
228 old = dma_resv_get_list(resv);
229 if (!old)
230 return 0;
231
232 new = kmalloc(offsetof(typeof(*new), shared[old->shared_max]),
233 GFP_KERNEL);
234 if (!new)
235 return -ENOMEM;
236
237 /* Go through all the shared fences in the resevation object and sort
238 * the interesting ones to the end of the list.
239 */
240 for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {
241 struct dma_fence *f;
242
243 f = rcu_dereference_protected(old->shared[i],
244 dma_resv_held(resv));
245
246 if (f->context == ef->base.context)
247 RCU_INIT_POINTER(new->shared[--j], f);
248 else
249 RCU_INIT_POINTER(new->shared[k++], f);
250 }
251 new->shared_max = old->shared_max;
252 new->shared_count = k;
253
254 /* Install the new fence list, seqcount provides the barriers */
255 preempt_disable();
256 write_seqcount_begin(&resv->seq);
257 RCU_INIT_POINTER(resv->fence, new);
258 write_seqcount_end(&resv->seq);
259 preempt_enable();
260
261 /* Drop the references to the removed fences or move them to ef_list */
262 for (i = j, k = 0; i < old->shared_count; ++i) {
263 struct dma_fence *f;
264
265 f = rcu_dereference_protected(new->shared[i],
266 dma_resv_held(resv));
267 dma_fence_put(f);
268 }
269 kfree_rcu(old, rcu);
270
271 return 0;
272}
273
274static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
275 bool wait)
276{
277 struct ttm_operation_ctx ctx = { false, false };
278 int ret;
279
280 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
281 "Called with userptr BO"))
282 return -EINVAL;
283
284 amdgpu_bo_placement_from_domain(bo, domain);
285
286 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
287 if (ret)
288 goto validate_fail;
289 if (wait)
290 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
291
292validate_fail:
293 return ret;
294}
295
296static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo)
297{
298 struct amdgpu_vm_parser *p = param;
299
300 return amdgpu_amdkfd_bo_validate(bo, p->domain, p->wait);
301}
302
303/* vm_validate_pt_pd_bos - Validate page table and directory BOs
304 *
305 * Page directories are not updated here because huge page handling
306 * during page table updates can invalidate page directory entries
307 * again. Page directories are only updated after updating page
308 * tables.
309 */
310static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
311{
312 struct amdgpu_bo *pd = vm->root.base.bo;
313 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
314 struct amdgpu_vm_parser param;
315 int ret;
316
317 param.domain = AMDGPU_GEM_DOMAIN_VRAM;
318 param.wait = false;
319
320 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,
321 ¶m);
322 if (ret) {
323 pr_err("amdgpu: failed to validate PT BOs\n");
324 return ret;
325 }
326
327 ret = amdgpu_amdkfd_validate(¶m, pd);
328 if (ret) {
329 pr_err("amdgpu: failed to validate PD\n");
330 return ret;
331 }
332
333 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
334
335 if (vm->use_cpu_for_update) {
336 ret = amdgpu_bo_kmap(pd, NULL);
337 if (ret) {
338 pr_err("amdgpu: failed to kmap PD, ret=%d\n", ret);
339 return ret;
340 }
341 }
342
343 return 0;
344}
345
346static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
347{
348 struct amdgpu_bo *pd = vm->root.base.bo;
349 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
350 int ret;
351
352 ret = amdgpu_vm_update_directories(adev, vm);
353 if (ret)
354 return ret;
355
356 return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
357}
358
359/* add_bo_to_vm - Add a BO to a VM
360 *
361 * Everything that needs to bo done only once when a BO is first added
362 * to a VM. It can later be mapped and unmapped many times without
363 * repeating these steps.
364 *
365 * 1. Allocate and initialize BO VA entry data structure
366 * 2. Add BO to the VM
367 * 3. Determine ASIC-specific PTE flags
368 * 4. Alloc page tables and directories if needed
369 * 4a. Validate new page tables and directories
370 */
371static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem,
372 struct amdgpu_vm *vm, bool is_aql,
373 struct kfd_bo_va_list **p_bo_va_entry)
374{
375 int ret;
376 struct kfd_bo_va_list *bo_va_entry;
377 struct amdgpu_bo *bo = mem->bo;
378 uint64_t va = mem->va;
379 struct list_head *list_bo_va = &mem->bo_va_list;
380 unsigned long bo_size = bo->tbo.mem.size;
381
382 if (!va) {
383 pr_err("Invalid VA when adding BO to VM\n");
384 return -EINVAL;
385 }
386
387 if (is_aql)
388 va += bo_size;
389
390 bo_va_entry = kzalloc(sizeof(*bo_va_entry), GFP_KERNEL);
391 if (!bo_va_entry)
392 return -ENOMEM;
393
394 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
395 va + bo_size, vm);
396
397 /* Add BO to VM internal data structures*/
398 bo_va_entry->bo_va = amdgpu_vm_bo_add(adev, vm, bo);
399 if (!bo_va_entry->bo_va) {
400 ret = -EINVAL;
401 pr_err("Failed to add BO object to VM. ret == %d\n",
402 ret);
403 goto err_vmadd;
404 }
405
406 bo_va_entry->va = va;
407 bo_va_entry->pte_flags = amdgpu_gmc_get_pte_flags(adev,
408 mem->mapping_flags);
409 bo_va_entry->kgd_dev = (void *)adev;
410 list_add(&bo_va_entry->bo_list, list_bo_va);
411
412 if (p_bo_va_entry)
413 *p_bo_va_entry = bo_va_entry;
414
415 /* Allocate validate page tables if needed */
416 ret = vm_validate_pt_pd_bos(vm);
417 if (ret) {
418 pr_err("validate_pt_pd_bos() failed\n");
419 goto err_alloc_pts;
420 }
421
422 return 0;
423
424err_alloc_pts:
425 amdgpu_vm_bo_rmv(adev, bo_va_entry->bo_va);
426 list_del(&bo_va_entry->bo_list);
427err_vmadd:
428 kfree(bo_va_entry);
429 return ret;
430}
431
432static void remove_bo_from_vm(struct amdgpu_device *adev,
433 struct kfd_bo_va_list *entry, unsigned long size)
434{
435 pr_debug("\t remove VA 0x%llx - 0x%llx in entry %p\n",
436 entry->va,
437 entry->va + size, entry);
438 amdgpu_vm_bo_rmv(adev, entry->bo_va);
439 list_del(&entry->bo_list);
440 kfree(entry);
441}
442
443static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
444 struct amdkfd_process_info *process_info,
445 bool userptr)
446{
447 struct ttm_validate_buffer *entry = &mem->validate_list;
448 struct amdgpu_bo *bo = mem->bo;
449
450 INIT_LIST_HEAD(&entry->head);
451 entry->num_shared = 1;
452 entry->bo = &bo->tbo;
453 mutex_lock(&process_info->lock);
454 if (userptr)
455 list_add_tail(&entry->head, &process_info->userptr_valid_list);
456 else
457 list_add_tail(&entry->head, &process_info->kfd_bo_list);
458 mutex_unlock(&process_info->lock);
459}
460
461static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
462 struct amdkfd_process_info *process_info)
463{
464 struct ttm_validate_buffer *bo_list_entry;
465
466 bo_list_entry = &mem->validate_list;
467 mutex_lock(&process_info->lock);
468 list_del(&bo_list_entry->head);
469 mutex_unlock(&process_info->lock);
470}
471
472/* Initializes user pages. It registers the MMU notifier and validates
473 * the userptr BO in the GTT domain.
474 *
475 * The BO must already be on the userptr_valid_list. Otherwise an
476 * eviction and restore may happen that leaves the new BO unmapped
477 * with the user mode queues running.
478 *
479 * Takes the process_info->lock to protect against concurrent restore
480 * workers.
481 *
482 * Returns 0 for success, negative errno for errors.
483 */
484static int init_user_pages(struct kgd_mem *mem, struct mm_struct *mm,
485 uint64_t user_addr)
486{
487 struct amdkfd_process_info *process_info = mem->process_info;
488 struct amdgpu_bo *bo = mem->bo;
489 struct ttm_operation_ctx ctx = { true, false };
490 int ret = 0;
491
492 mutex_lock(&process_info->lock);
493
494 ret = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, user_addr, 0);
495 if (ret) {
496 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
497 goto out;
498 }
499
500 ret = amdgpu_mn_register(bo, user_addr);
501 if (ret) {
502 pr_err("%s: Failed to register MMU notifier: %d\n",
503 __func__, ret);
504 goto out;
505 }
506
507 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
508 if (ret) {
509 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
510 goto unregister_out;
511 }
512
513 ret = amdgpu_bo_reserve(bo, true);
514 if (ret) {
515 pr_err("%s: Failed to reserve BO\n", __func__);
516 goto release_out;
517 }
518 amdgpu_bo_placement_from_domain(bo, mem->domain);
519 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
520 if (ret)
521 pr_err("%s: failed to validate BO\n", __func__);
522 amdgpu_bo_unreserve(bo);
523
524release_out:
525 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
526unregister_out:
527 if (ret)
528 amdgpu_mn_unregister(bo);
529out:
530 mutex_unlock(&process_info->lock);
531 return ret;
532}
533
534/* Reserving a BO and its page table BOs must happen atomically to
535 * avoid deadlocks. Some operations update multiple VMs at once. Track
536 * all the reservation info in a context structure. Optionally a sync
537 * object can track VM updates.
538 */
539struct bo_vm_reservation_context {
540 struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */
541 unsigned int n_vms; /* Number of VMs reserved */
542 struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries */
543 struct ww_acquire_ctx ticket; /* Reservation ticket */
544 struct list_head list, duplicates; /* BO lists */
545 struct amdgpu_sync *sync; /* Pointer to sync object */
546 bool reserved; /* Whether BOs are reserved */
547};
548
549enum bo_vm_match {
550 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
551 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
552 BO_VM_ALL, /* Match all VMs a BO was added to */
553};
554
555/**
556 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
557 * @mem: KFD BO structure.
558 * @vm: the VM to reserve.
559 * @ctx: the struct that will be used in unreserve_bo_and_vms().
560 */
561static int reserve_bo_and_vm(struct kgd_mem *mem,
562 struct amdgpu_vm *vm,
563 struct bo_vm_reservation_context *ctx)
564{
565 struct amdgpu_bo *bo = mem->bo;
566 int ret;
567
568 WARN_ON(!vm);
569
570 ctx->reserved = false;
571 ctx->n_vms = 1;
572 ctx->sync = &mem->sync;
573
574 INIT_LIST_HEAD(&ctx->list);
575 INIT_LIST_HEAD(&ctx->duplicates);
576
577 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL);
578 if (!ctx->vm_pd)
579 return -ENOMEM;
580
581 ctx->kfd_bo.priority = 0;
582 ctx->kfd_bo.tv.bo = &bo->tbo;
583 ctx->kfd_bo.tv.num_shared = 1;
584 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
585
586 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]);
587
588 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
589 false, &ctx->duplicates, true);
590 if (!ret)
591 ctx->reserved = true;
592 else {
593 pr_err("Failed to reserve buffers in ttm\n");
594 kfree(ctx->vm_pd);
595 ctx->vm_pd = NULL;
596 }
597
598 return ret;
599}
600
601/**
602 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
603 * @mem: KFD BO structure.
604 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
605 * is used. Otherwise, a single VM associated with the BO.
606 * @map_type: the mapping status that will be used to filter the VMs.
607 * @ctx: the struct that will be used in unreserve_bo_and_vms().
608 *
609 * Returns 0 for success, negative for failure.
610 */
611static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
612 struct amdgpu_vm *vm, enum bo_vm_match map_type,
613 struct bo_vm_reservation_context *ctx)
614{
615 struct amdgpu_bo *bo = mem->bo;
616 struct kfd_bo_va_list *entry;
617 unsigned int i;
618 int ret;
619
620 ctx->reserved = false;
621 ctx->n_vms = 0;
622 ctx->vm_pd = NULL;
623 ctx->sync = &mem->sync;
624
625 INIT_LIST_HEAD(&ctx->list);
626 INIT_LIST_HEAD(&ctx->duplicates);
627
628 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
629 if ((vm && vm != entry->bo_va->base.vm) ||
630 (entry->is_mapped != map_type
631 && map_type != BO_VM_ALL))
632 continue;
633
634 ctx->n_vms++;
635 }
636
637 if (ctx->n_vms != 0) {
638 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd),
639 GFP_KERNEL);
640 if (!ctx->vm_pd)
641 return -ENOMEM;
642 }
643
644 ctx->kfd_bo.priority = 0;
645 ctx->kfd_bo.tv.bo = &bo->tbo;
646 ctx->kfd_bo.tv.num_shared = 1;
647 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
648
649 i = 0;
650 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
651 if ((vm && vm != entry->bo_va->base.vm) ||
652 (entry->is_mapped != map_type
653 && map_type != BO_VM_ALL))
654 continue;
655
656 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list,
657 &ctx->vm_pd[i]);
658 i++;
659 }
660
661 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
662 false, &ctx->duplicates, true);
663 if (!ret)
664 ctx->reserved = true;
665 else
666 pr_err("Failed to reserve buffers in ttm.\n");
667
668 if (ret) {
669 kfree(ctx->vm_pd);
670 ctx->vm_pd = NULL;
671 }
672
673 return ret;
674}
675
676/**
677 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
678 * @ctx: Reservation context to unreserve
679 * @wait: Optionally wait for a sync object representing pending VM updates
680 * @intr: Whether the wait is interruptible
681 *
682 * Also frees any resources allocated in
683 * reserve_bo_and_(cond_)vm(s). Returns the status from
684 * amdgpu_sync_wait.
685 */
686static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
687 bool wait, bool intr)
688{
689 int ret = 0;
690
691 if (wait)
692 ret = amdgpu_sync_wait(ctx->sync, intr);
693
694 if (ctx->reserved)
695 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list);
696 kfree(ctx->vm_pd);
697
698 ctx->sync = NULL;
699
700 ctx->reserved = false;
701 ctx->vm_pd = NULL;
702
703 return ret;
704}
705
706static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
707 struct kfd_bo_va_list *entry,
708 struct amdgpu_sync *sync)
709{
710 struct amdgpu_bo_va *bo_va = entry->bo_va;
711 struct amdgpu_vm *vm = bo_va->base.vm;
712
713 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
714
715 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
716
717 amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
718
719 return 0;
720}
721
722static int update_gpuvm_pte(struct amdgpu_device *adev,
723 struct kfd_bo_va_list *entry,
724 struct amdgpu_sync *sync)
725{
726 int ret;
727 struct amdgpu_bo_va *bo_va = entry->bo_va;
728
729 /* Update the page tables */
730 ret = amdgpu_vm_bo_update(adev, bo_va, false);
731 if (ret) {
732 pr_err("amdgpu_vm_bo_update failed\n");
733 return ret;
734 }
735
736 return amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
737}
738
739static int map_bo_to_gpuvm(struct amdgpu_device *adev,
740 struct kfd_bo_va_list *entry, struct amdgpu_sync *sync,
741 bool no_update_pte)
742{
743 int ret;
744
745 /* Set virtual address for the allocation */
746 ret = amdgpu_vm_bo_map(adev, entry->bo_va, entry->va, 0,
747 amdgpu_bo_size(entry->bo_va->base.bo),
748 entry->pte_flags);
749 if (ret) {
750 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
751 entry->va, ret);
752 return ret;
753 }
754
755 if (no_update_pte)
756 return 0;
757
758 ret = update_gpuvm_pte(adev, entry, sync);
759 if (ret) {
760 pr_err("update_gpuvm_pte() failed\n");
761 goto update_gpuvm_pte_failed;
762 }
763
764 return 0;
765
766update_gpuvm_pte_failed:
767 unmap_bo_from_gpuvm(adev, entry, sync);
768 return ret;
769}
770
771static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
772{
773 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
774
775 if (!sg)
776 return NULL;
777 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
778 kfree(sg);
779 return NULL;
780 }
781 sg->sgl->dma_address = addr;
782 sg->sgl->length = size;
783#ifdef CONFIG_NEED_SG_DMA_LENGTH
784 sg->sgl->dma_length = size;
785#endif
786 return sg;
787}
788
789static int process_validate_vms(struct amdkfd_process_info *process_info)
790{
791 struct amdgpu_vm *peer_vm;
792 int ret;
793
794 list_for_each_entry(peer_vm, &process_info->vm_list_head,
795 vm_list_node) {
796 ret = vm_validate_pt_pd_bos(peer_vm);
797 if (ret)
798 return ret;
799 }
800
801 return 0;
802}
803
804static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
805 struct amdgpu_sync *sync)
806{
807 struct amdgpu_vm *peer_vm;
808 int ret;
809
810 list_for_each_entry(peer_vm, &process_info->vm_list_head,
811 vm_list_node) {
812 struct amdgpu_bo *pd = peer_vm->root.base.bo;
813
814 ret = amdgpu_sync_resv(NULL,
815 sync, pd->tbo.base.resv,
816 AMDGPU_FENCE_OWNER_KFD, false);
817 if (ret)
818 return ret;
819 }
820
821 return 0;
822}
823
824static int process_update_pds(struct amdkfd_process_info *process_info,
825 struct amdgpu_sync *sync)
826{
827 struct amdgpu_vm *peer_vm;
828 int ret;
829
830 list_for_each_entry(peer_vm, &process_info->vm_list_head,
831 vm_list_node) {
832 ret = vm_update_pds(peer_vm, sync);
833 if (ret)
834 return ret;
835 }
836
837 return 0;
838}
839
840static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
841 struct dma_fence **ef)
842{
843 struct amdkfd_process_info *info = NULL;
844 int ret;
845
846 if (!*process_info) {
847 info = kzalloc(sizeof(*info), GFP_KERNEL);
848 if (!info)
849 return -ENOMEM;
850
851 mutex_init(&info->lock);
852 INIT_LIST_HEAD(&info->vm_list_head);
853 INIT_LIST_HEAD(&info->kfd_bo_list);
854 INIT_LIST_HEAD(&info->userptr_valid_list);
855 INIT_LIST_HEAD(&info->userptr_inval_list);
856
857 info->eviction_fence =
858 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
859 current->mm);
860 if (!info->eviction_fence) {
861 pr_err("Failed to create eviction fence\n");
862 ret = -ENOMEM;
863 goto create_evict_fence_fail;
864 }
865
866 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
867 atomic_set(&info->evicted_bos, 0);
868 INIT_DELAYED_WORK(&info->restore_userptr_work,
869 amdgpu_amdkfd_restore_userptr_worker);
870
871 *process_info = info;
872 *ef = dma_fence_get(&info->eviction_fence->base);
873 }
874
875 vm->process_info = *process_info;
876
877 /* Validate page directory and attach eviction fence */
878 ret = amdgpu_bo_reserve(vm->root.base.bo, true);
879 if (ret)
880 goto reserve_pd_fail;
881 ret = vm_validate_pt_pd_bos(vm);
882 if (ret) {
883 pr_err("validate_pt_pd_bos() failed\n");
884 goto validate_pd_fail;
885 }
886 ret = amdgpu_bo_sync_wait(vm->root.base.bo,
887 AMDGPU_FENCE_OWNER_KFD, false);
888 if (ret)
889 goto wait_pd_fail;
890 ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);
891 if (ret)
892 goto reserve_shared_fail;
893 amdgpu_bo_fence(vm->root.base.bo,
894 &vm->process_info->eviction_fence->base, true);
895 amdgpu_bo_unreserve(vm->root.base.bo);
896
897 /* Update process info */
898 mutex_lock(&vm->process_info->lock);
899 list_add_tail(&vm->vm_list_node,
900 &(vm->process_info->vm_list_head));
901 vm->process_info->n_vms++;
902 mutex_unlock(&vm->process_info->lock);
903
904 return 0;
905
906reserve_shared_fail:
907wait_pd_fail:
908validate_pd_fail:
909 amdgpu_bo_unreserve(vm->root.base.bo);
910reserve_pd_fail:
911 vm->process_info = NULL;
912 if (info) {
913 /* Two fence references: one in info and one in *ef */
914 dma_fence_put(&info->eviction_fence->base);
915 dma_fence_put(*ef);
916 *ef = NULL;
917 *process_info = NULL;
918 put_pid(info->pid);
919create_evict_fence_fail:
920 mutex_destroy(&info->lock);
921 kfree(info);
922 }
923 return ret;
924}
925
926int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, unsigned int pasid,
927 void **vm, void **process_info,
928 struct dma_fence **ef)
929{
930 struct amdgpu_device *adev = get_amdgpu_device(kgd);
931 struct amdgpu_vm *new_vm;
932 int ret;
933
934 new_vm = kzalloc(sizeof(*new_vm), GFP_KERNEL);
935 if (!new_vm)
936 return -ENOMEM;
937
938 /* Initialize AMDGPU part of the VM */
939 ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, pasid);
940 if (ret) {
941 pr_err("Failed init vm ret %d\n", ret);
942 goto amdgpu_vm_init_fail;
943 }
944
945 /* Initialize KFD part of the VM and process info */
946 ret = init_kfd_vm(new_vm, process_info, ef);
947 if (ret)
948 goto init_kfd_vm_fail;
949
950 *vm = (void *) new_vm;
951
952 return 0;
953
954init_kfd_vm_fail:
955 amdgpu_vm_fini(adev, new_vm);
956amdgpu_vm_init_fail:
957 kfree(new_vm);
958 return ret;
959}
960
961int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
962 struct file *filp, unsigned int pasid,
963 void **vm, void **process_info,
964 struct dma_fence **ef)
965{
966 struct amdgpu_device *adev = get_amdgpu_device(kgd);
967 struct drm_file *drm_priv = filp->private_data;
968 struct amdgpu_fpriv *drv_priv = drm_priv->driver_priv;
969 struct amdgpu_vm *avm = &drv_priv->vm;
970 int ret;
971
972 /* Already a compute VM? */
973 if (avm->process_info)
974 return -EINVAL;
975
976 /* Convert VM into a compute VM */
977 ret = amdgpu_vm_make_compute(adev, avm, pasid);
978 if (ret)
979 return ret;
980
981 /* Initialize KFD part of the VM and process info */
982 ret = init_kfd_vm(avm, process_info, ef);
983 if (ret)
984 return ret;
985
986 *vm = (void *)avm;
987
988 return 0;
989}
990
991void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
992 struct amdgpu_vm *vm)
993{
994 struct amdkfd_process_info *process_info = vm->process_info;
995 struct amdgpu_bo *pd = vm->root.base.bo;
996
997 if (!process_info)
998 return;
999
1000 /* Release eviction fence from PD */
1001 amdgpu_bo_reserve(pd, false);
1002 amdgpu_bo_fence(pd, NULL, false);
1003 amdgpu_bo_unreserve(pd);
1004
1005 /* Update process info */
1006 mutex_lock(&process_info->lock);
1007 process_info->n_vms--;
1008 list_del(&vm->vm_list_node);
1009 mutex_unlock(&process_info->lock);
1010
1011 /* Release per-process resources when last compute VM is destroyed */
1012 if (!process_info->n_vms) {
1013 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1014 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1015 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1016
1017 dma_fence_put(&process_info->eviction_fence->base);
1018 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1019 put_pid(process_info->pid);
1020 mutex_destroy(&process_info->lock);
1021 kfree(process_info);
1022 }
1023}
1024
1025void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm)
1026{
1027 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1028 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1029
1030 if (WARN_ON(!kgd || !vm))
1031 return;
1032
1033 pr_debug("Destroying process vm %p\n", vm);
1034
1035 /* Release the VM context */
1036 amdgpu_vm_fini(adev, avm);
1037 kfree(vm);
1038}
1039
1040void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
1041{
1042 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1043 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1044
1045 if (WARN_ON(!kgd || !vm))
1046 return;
1047
1048 pr_debug("Releasing process vm %p\n", vm);
1049
1050 /* The original pasid of amdgpu vm has already been
1051 * released during making a amdgpu vm to a compute vm
1052 * The current pasid is managed by kfd and will be
1053 * released on kfd process destroy. Set amdgpu pasid
1054 * to 0 to avoid duplicate release.
1055 */
1056 amdgpu_vm_release_compute(adev, avm);
1057}
1058
1059uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm)
1060{
1061 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1062 struct amdgpu_bo *pd = avm->root.base.bo;
1063 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1064
1065 if (adev->asic_type < CHIP_VEGA10)
1066 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1067 return avm->pd_phys_addr;
1068}
1069
1070int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1071 struct kgd_dev *kgd, uint64_t va, uint64_t size,
1072 void *vm, struct kgd_mem **mem,
1073 uint64_t *offset, uint32_t flags)
1074{
1075 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1076 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1077 enum ttm_bo_type bo_type = ttm_bo_type_device;
1078 struct sg_table *sg = NULL;
1079 uint64_t user_addr = 0;
1080 struct amdgpu_bo *bo;
1081 struct amdgpu_bo_param bp;
1082 int byte_align;
1083 u32 domain, alloc_domain;
1084 u64 alloc_flags;
1085 uint32_t mapping_flags;
1086 int ret;
1087
1088 /*
1089 * Check on which domain to allocate BO
1090 */
1091 if (flags & ALLOC_MEM_FLAGS_VRAM) {
1092 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1093 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1094 alloc_flags |= (flags & ALLOC_MEM_FLAGS_PUBLIC) ?
1095 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
1096 AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1097 } else if (flags & ALLOC_MEM_FLAGS_GTT) {
1098 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1099 alloc_flags = 0;
1100 } else if (flags & ALLOC_MEM_FLAGS_USERPTR) {
1101 domain = AMDGPU_GEM_DOMAIN_GTT;
1102 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1103 alloc_flags = 0;
1104 if (!offset || !*offset)
1105 return -EINVAL;
1106 user_addr = untagged_addr(*offset);
1107 } else if (flags & (ALLOC_MEM_FLAGS_DOORBELL |
1108 ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1109 domain = AMDGPU_GEM_DOMAIN_GTT;
1110 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1111 bo_type = ttm_bo_type_sg;
1112 alloc_flags = 0;
1113 if (size > UINT_MAX)
1114 return -EINVAL;
1115 sg = create_doorbell_sg(*offset, size);
1116 if (!sg)
1117 return -ENOMEM;
1118 } else {
1119 return -EINVAL;
1120 }
1121
1122 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1123 if (!*mem) {
1124 ret = -ENOMEM;
1125 goto err;
1126 }
1127 INIT_LIST_HEAD(&(*mem)->bo_va_list);
1128 mutex_init(&(*mem)->lock);
1129 (*mem)->aql_queue = !!(flags & ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1130
1131 /* Workaround for AQL queue wraparound bug. Map the same
1132 * memory twice. That means we only actually allocate half
1133 * the memory.
1134 */
1135 if ((*mem)->aql_queue)
1136 size = size >> 1;
1137
1138 /* Workaround for TLB bug on older VI chips */
1139 byte_align = (adev->family == AMDGPU_FAMILY_VI &&
1140 adev->asic_type != CHIP_FIJI &&
1141 adev->asic_type != CHIP_POLARIS10 &&
1142 adev->asic_type != CHIP_POLARIS11 &&
1143 adev->asic_type != CHIP_POLARIS12 &&
1144 adev->asic_type != CHIP_VEGAM) ?
1145 VI_BO_SIZE_ALIGN : 1;
1146
1147 mapping_flags = AMDGPU_VM_PAGE_READABLE;
1148 if (flags & ALLOC_MEM_FLAGS_WRITABLE)
1149 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
1150 if (flags & ALLOC_MEM_FLAGS_EXECUTABLE)
1151 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
1152 if (flags & ALLOC_MEM_FLAGS_COHERENT)
1153 mapping_flags |= AMDGPU_VM_MTYPE_UC;
1154 else
1155 mapping_flags |= AMDGPU_VM_MTYPE_NC;
1156 (*mem)->mapping_flags = mapping_flags;
1157
1158 amdgpu_sync_create(&(*mem)->sync);
1159
1160 ret = amdgpu_amdkfd_reserve_mem_limit(adev, size, alloc_domain, !!sg);
1161 if (ret) {
1162 pr_debug("Insufficient system memory\n");
1163 goto err_reserve_limit;
1164 }
1165
1166 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
1167 va, size, domain_string(alloc_domain));
1168
1169 memset(&bp, 0, sizeof(bp));
1170 bp.size = size;
1171 bp.byte_align = byte_align;
1172 bp.domain = alloc_domain;
1173 bp.flags = alloc_flags;
1174 bp.type = bo_type;
1175 bp.resv = NULL;
1176 ret = amdgpu_bo_create(adev, &bp, &bo);
1177 if (ret) {
1178 pr_debug("Failed to create BO on domain %s. ret %d\n",
1179 domain_string(alloc_domain), ret);
1180 goto err_bo_create;
1181 }
1182 if (bo_type == ttm_bo_type_sg) {
1183 bo->tbo.sg = sg;
1184 bo->tbo.ttm->sg = sg;
1185 }
1186 bo->kfd_bo = *mem;
1187 (*mem)->bo = bo;
1188 if (user_addr)
1189 bo->flags |= AMDGPU_AMDKFD_USERPTR_BO;
1190
1191 (*mem)->va = va;
1192 (*mem)->domain = domain;
1193 (*mem)->mapped_to_gpu_memory = 0;
1194 (*mem)->process_info = avm->process_info;
1195 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1196
1197 if (user_addr) {
1198 ret = init_user_pages(*mem, current->mm, user_addr);
1199 if (ret)
1200 goto allocate_init_user_pages_failed;
1201 }
1202
1203 if (offset)
1204 *offset = amdgpu_bo_mmap_offset(bo);
1205
1206 return 0;
1207
1208allocate_init_user_pages_failed:
1209 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1210 amdgpu_bo_unref(&bo);
1211 /* Don't unreserve system mem limit twice */
1212 goto err_reserve_limit;
1213err_bo_create:
1214 unreserve_mem_limit(adev, size, alloc_domain, !!sg);
1215err_reserve_limit:
1216 mutex_destroy(&(*mem)->lock);
1217 kfree(*mem);
1218err:
1219 if (sg) {
1220 sg_free_table(sg);
1221 kfree(sg);
1222 }
1223 return ret;
1224}
1225
1226int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1227 struct kgd_dev *kgd, struct kgd_mem *mem)
1228{
1229 struct amdkfd_process_info *process_info = mem->process_info;
1230 unsigned long bo_size = mem->bo->tbo.mem.size;
1231 struct kfd_bo_va_list *entry, *tmp;
1232 struct bo_vm_reservation_context ctx;
1233 struct ttm_validate_buffer *bo_list_entry;
1234 int ret;
1235
1236 mutex_lock(&mem->lock);
1237
1238 if (mem->mapped_to_gpu_memory > 0) {
1239 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1240 mem->va, bo_size);
1241 mutex_unlock(&mem->lock);
1242 return -EBUSY;
1243 }
1244
1245 mutex_unlock(&mem->lock);
1246 /* lock is not needed after this, since mem is unused and will
1247 * be freed anyway
1248 */
1249
1250 /* No more MMU notifiers */
1251 amdgpu_mn_unregister(mem->bo);
1252
1253 /* Make sure restore workers don't access the BO any more */
1254 bo_list_entry = &mem->validate_list;
1255 mutex_lock(&process_info->lock);
1256 list_del(&bo_list_entry->head);
1257 mutex_unlock(&process_info->lock);
1258
1259 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1260 if (unlikely(ret))
1261 return ret;
1262
1263 /* The eviction fence should be removed by the last unmap.
1264 * TODO: Log an error condition if the bo still has the eviction fence
1265 * attached
1266 */
1267 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1268 process_info->eviction_fence);
1269 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1270 mem->va + bo_size * (1 + mem->aql_queue));
1271
1272 /* Remove from VM internal data structures */
1273 list_for_each_entry_safe(entry, tmp, &mem->bo_va_list, bo_list)
1274 remove_bo_from_vm((struct amdgpu_device *)entry->kgd_dev,
1275 entry, bo_size);
1276
1277 ret = unreserve_bo_and_vms(&ctx, false, false);
1278
1279 /* Free the sync object */
1280 amdgpu_sync_free(&mem->sync);
1281
1282 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1283 * remap BO. We need to free it.
1284 */
1285 if (mem->bo->tbo.sg) {
1286 sg_free_table(mem->bo->tbo.sg);
1287 kfree(mem->bo->tbo.sg);
1288 }
1289
1290 /* Free the BO*/
1291 amdgpu_bo_unref(&mem->bo);
1292 mutex_destroy(&mem->lock);
1293 kfree(mem);
1294
1295 return ret;
1296}
1297
1298int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1299 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm)
1300{
1301 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1302 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1303 int ret;
1304 struct amdgpu_bo *bo;
1305 uint32_t domain;
1306 struct kfd_bo_va_list *entry;
1307 struct bo_vm_reservation_context ctx;
1308 struct kfd_bo_va_list *bo_va_entry = NULL;
1309 struct kfd_bo_va_list *bo_va_entry_aql = NULL;
1310 unsigned long bo_size;
1311 bool is_invalid_userptr = false;
1312
1313 bo = mem->bo;
1314 if (!bo) {
1315 pr_err("Invalid BO when mapping memory to GPU\n");
1316 return -EINVAL;
1317 }
1318
1319 /* Make sure restore is not running concurrently. Since we
1320 * don't map invalid userptr BOs, we rely on the next restore
1321 * worker to do the mapping
1322 */
1323 mutex_lock(&mem->process_info->lock);
1324
1325 /* Lock mmap-sem. If we find an invalid userptr BO, we can be
1326 * sure that the MMU notifier is no longer running
1327 * concurrently and the queues are actually stopped
1328 */
1329 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1330 down_write(¤t->mm->mmap_sem);
1331 is_invalid_userptr = atomic_read(&mem->invalid);
1332 up_write(¤t->mm->mmap_sem);
1333 }
1334
1335 mutex_lock(&mem->lock);
1336
1337 domain = mem->domain;
1338 bo_size = bo->tbo.mem.size;
1339
1340 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1341 mem->va,
1342 mem->va + bo_size * (1 + mem->aql_queue),
1343 vm, domain_string(domain));
1344
1345 ret = reserve_bo_and_vm(mem, vm, &ctx);
1346 if (unlikely(ret))
1347 goto out;
1348
1349 /* Userptr can be marked as "not invalid", but not actually be
1350 * validated yet (still in the system domain). In that case
1351 * the queues are still stopped and we can leave mapping for
1352 * the next restore worker
1353 */
1354 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1355 bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
1356 is_invalid_userptr = true;
1357
1358 if (check_if_add_bo_to_vm(avm, mem)) {
1359 ret = add_bo_to_vm(adev, mem, avm, false,
1360 &bo_va_entry);
1361 if (ret)
1362 goto add_bo_to_vm_failed;
1363 if (mem->aql_queue) {
1364 ret = add_bo_to_vm(adev, mem, avm,
1365 true, &bo_va_entry_aql);
1366 if (ret)
1367 goto add_bo_to_vm_failed_aql;
1368 }
1369 } else {
1370 ret = vm_validate_pt_pd_bos(avm);
1371 if (unlikely(ret))
1372 goto add_bo_to_vm_failed;
1373 }
1374
1375 if (mem->mapped_to_gpu_memory == 0 &&
1376 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1377 /* Validate BO only once. The eviction fence gets added to BO
1378 * the first time it is mapped. Validate will wait for all
1379 * background evictions to complete.
1380 */
1381 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1382 if (ret) {
1383 pr_debug("Validate failed\n");
1384 goto map_bo_to_gpuvm_failed;
1385 }
1386 }
1387
1388 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
1389 if (entry->bo_va->base.vm == vm && !entry->is_mapped) {
1390 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
1391 entry->va, entry->va + bo_size,
1392 entry);
1393
1394 ret = map_bo_to_gpuvm(adev, entry, ctx.sync,
1395 is_invalid_userptr);
1396 if (ret) {
1397 pr_err("Failed to map bo to gpuvm\n");
1398 goto map_bo_to_gpuvm_failed;
1399 }
1400
1401 ret = vm_update_pds(vm, ctx.sync);
1402 if (ret) {
1403 pr_err("Failed to update page directories\n");
1404 goto map_bo_to_gpuvm_failed;
1405 }
1406
1407 entry->is_mapped = true;
1408 mem->mapped_to_gpu_memory++;
1409 pr_debug("\t INC mapping count %d\n",
1410 mem->mapped_to_gpu_memory);
1411 }
1412 }
1413
1414 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->pin_count)
1415 amdgpu_bo_fence(bo,
1416 &avm->process_info->eviction_fence->base,
1417 true);
1418 ret = unreserve_bo_and_vms(&ctx, false, false);
1419
1420 goto out;
1421
1422map_bo_to_gpuvm_failed:
1423 if (bo_va_entry_aql)
1424 remove_bo_from_vm(adev, bo_va_entry_aql, bo_size);
1425add_bo_to_vm_failed_aql:
1426 if (bo_va_entry)
1427 remove_bo_from_vm(adev, bo_va_entry, bo_size);
1428add_bo_to_vm_failed:
1429 unreserve_bo_and_vms(&ctx, false, false);
1430out:
1431 mutex_unlock(&mem->process_info->lock);
1432 mutex_unlock(&mem->lock);
1433 return ret;
1434}
1435
1436int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1437 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm)
1438{
1439 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1440 struct amdkfd_process_info *process_info =
1441 ((struct amdgpu_vm *)vm)->process_info;
1442 unsigned long bo_size = mem->bo->tbo.mem.size;
1443 struct kfd_bo_va_list *entry;
1444 struct bo_vm_reservation_context ctx;
1445 int ret;
1446
1447 mutex_lock(&mem->lock);
1448
1449 ret = reserve_bo_and_cond_vms(mem, vm, BO_VM_MAPPED, &ctx);
1450 if (unlikely(ret))
1451 goto out;
1452 /* If no VMs were reserved, it means the BO wasn't actually mapped */
1453 if (ctx.n_vms == 0) {
1454 ret = -EINVAL;
1455 goto unreserve_out;
1456 }
1457
1458 ret = vm_validate_pt_pd_bos((struct amdgpu_vm *)vm);
1459 if (unlikely(ret))
1460 goto unreserve_out;
1461
1462 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
1463 mem->va,
1464 mem->va + bo_size * (1 + mem->aql_queue),
1465 vm);
1466
1467 list_for_each_entry(entry, &mem->bo_va_list, bo_list) {
1468 if (entry->bo_va->base.vm == vm && entry->is_mapped) {
1469 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
1470 entry->va,
1471 entry->va + bo_size,
1472 entry);
1473
1474 ret = unmap_bo_from_gpuvm(adev, entry, ctx.sync);
1475 if (ret == 0) {
1476 entry->is_mapped = false;
1477 } else {
1478 pr_err("failed to unmap VA 0x%llx\n",
1479 mem->va);
1480 goto unreserve_out;
1481 }
1482
1483 mem->mapped_to_gpu_memory--;
1484 pr_debug("\t DEC mapping count %d\n",
1485 mem->mapped_to_gpu_memory);
1486 }
1487 }
1488
1489 /* If BO is unmapped from all VMs, unfence it. It can be evicted if
1490 * required.
1491 */
1492 if (mem->mapped_to_gpu_memory == 0 &&
1493 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && !mem->bo->pin_count)
1494 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1495 process_info->eviction_fence);
1496
1497unreserve_out:
1498 unreserve_bo_and_vms(&ctx, false, false);
1499out:
1500 mutex_unlock(&mem->lock);
1501 return ret;
1502}
1503
1504int amdgpu_amdkfd_gpuvm_sync_memory(
1505 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr)
1506{
1507 struct amdgpu_sync sync;
1508 int ret;
1509
1510 amdgpu_sync_create(&sync);
1511
1512 mutex_lock(&mem->lock);
1513 amdgpu_sync_clone(&mem->sync, &sync);
1514 mutex_unlock(&mem->lock);
1515
1516 ret = amdgpu_sync_wait(&sync, intr);
1517 amdgpu_sync_free(&sync);
1518 return ret;
1519}
1520
1521int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
1522 struct kgd_mem *mem, void **kptr, uint64_t *size)
1523{
1524 int ret;
1525 struct amdgpu_bo *bo = mem->bo;
1526
1527 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1528 pr_err("userptr can't be mapped to kernel\n");
1529 return -EINVAL;
1530 }
1531
1532 /* delete kgd_mem from kfd_bo_list to avoid re-validating
1533 * this BO in BO's restoring after eviction.
1534 */
1535 mutex_lock(&mem->process_info->lock);
1536
1537 ret = amdgpu_bo_reserve(bo, true);
1538 if (ret) {
1539 pr_err("Failed to reserve bo. ret %d\n", ret);
1540 goto bo_reserve_failed;
1541 }
1542
1543 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
1544 if (ret) {
1545 pr_err("Failed to pin bo. ret %d\n", ret);
1546 goto pin_failed;
1547 }
1548
1549 ret = amdgpu_bo_kmap(bo, kptr);
1550 if (ret) {
1551 pr_err("Failed to map bo to kernel. ret %d\n", ret);
1552 goto kmap_failed;
1553 }
1554
1555 amdgpu_amdkfd_remove_eviction_fence(
1556 bo, mem->process_info->eviction_fence);
1557 list_del_init(&mem->validate_list.head);
1558
1559 if (size)
1560 *size = amdgpu_bo_size(bo);
1561
1562 amdgpu_bo_unreserve(bo);
1563
1564 mutex_unlock(&mem->process_info->lock);
1565 return 0;
1566
1567kmap_failed:
1568 amdgpu_bo_unpin(bo);
1569pin_failed:
1570 amdgpu_bo_unreserve(bo);
1571bo_reserve_failed:
1572 mutex_unlock(&mem->process_info->lock);
1573
1574 return ret;
1575}
1576
1577int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
1578 struct kfd_vm_fault_info *mem)
1579{
1580 struct amdgpu_device *adev;
1581
1582 adev = (struct amdgpu_device *)kgd;
1583 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
1584 *mem = *adev->gmc.vm_fault_info;
1585 mb();
1586 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1587 }
1588 return 0;
1589}
1590
1591int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
1592 struct dma_buf *dma_buf,
1593 uint64_t va, void *vm,
1594 struct kgd_mem **mem, uint64_t *size,
1595 uint64_t *mmap_offset)
1596{
1597 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
1598 struct drm_gem_object *obj;
1599 struct amdgpu_bo *bo;
1600 struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
1601
1602 if (dma_buf->ops != &amdgpu_dmabuf_ops)
1603 /* Can't handle non-graphics buffers */
1604 return -EINVAL;
1605
1606 obj = dma_buf->priv;
1607 if (obj->dev->dev_private != adev)
1608 /* Can't handle buffers from other devices */
1609 return -EINVAL;
1610
1611 bo = gem_to_amdgpu_bo(obj);
1612 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
1613 AMDGPU_GEM_DOMAIN_GTT)))
1614 /* Only VRAM and GTT BOs are supported */
1615 return -EINVAL;
1616
1617 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1618 if (!*mem)
1619 return -ENOMEM;
1620
1621 if (size)
1622 *size = amdgpu_bo_size(bo);
1623
1624 if (mmap_offset)
1625 *mmap_offset = amdgpu_bo_mmap_offset(bo);
1626
1627 INIT_LIST_HEAD(&(*mem)->bo_va_list);
1628 mutex_init(&(*mem)->lock);
1629 (*mem)->mapping_flags =
1630 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
1631 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_NC;
1632
1633 (*mem)->bo = amdgpu_bo_ref(bo);
1634 (*mem)->va = va;
1635 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1636 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
1637 (*mem)->mapped_to_gpu_memory = 0;
1638 (*mem)->process_info = avm->process_info;
1639 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
1640 amdgpu_sync_create(&(*mem)->sync);
1641
1642 return 0;
1643}
1644
1645/* Evict a userptr BO by stopping the queues if necessary
1646 *
1647 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
1648 * cannot do any memory allocations, and cannot take any locks that
1649 * are held elsewhere while allocating memory. Therefore this is as
1650 * simple as possible, using atomic counters.
1651 *
1652 * It doesn't do anything to the BO itself. The real work happens in
1653 * restore, where we get updated page addresses. This function only
1654 * ensures that GPU access to the BO is stopped.
1655 */
1656int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
1657 struct mm_struct *mm)
1658{
1659 struct amdkfd_process_info *process_info = mem->process_info;
1660 int invalid, evicted_bos;
1661 int r = 0;
1662
1663 invalid = atomic_inc_return(&mem->invalid);
1664 evicted_bos = atomic_inc_return(&process_info->evicted_bos);
1665 if (evicted_bos == 1) {
1666 /* First eviction, stop the queues */
1667 r = kgd2kfd_quiesce_mm(mm);
1668 if (r)
1669 pr_err("Failed to quiesce KFD\n");
1670 schedule_delayed_work(&process_info->restore_userptr_work,
1671 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
1672 }
1673
1674 return r;
1675}
1676
1677/* Update invalid userptr BOs
1678 *
1679 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
1680 * userptr_inval_list and updates user pages for all BOs that have
1681 * been invalidated since their last update.
1682 */
1683static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
1684 struct mm_struct *mm)
1685{
1686 struct kgd_mem *mem, *tmp_mem;
1687 struct amdgpu_bo *bo;
1688 struct ttm_operation_ctx ctx = { false, false };
1689 int invalid, ret;
1690
1691 /* Move all invalidated BOs to the userptr_inval_list and
1692 * release their user pages by migration to the CPU domain
1693 */
1694 list_for_each_entry_safe(mem, tmp_mem,
1695 &process_info->userptr_valid_list,
1696 validate_list.head) {
1697 if (!atomic_read(&mem->invalid))
1698 continue; /* BO is still valid */
1699
1700 bo = mem->bo;
1701
1702 if (amdgpu_bo_reserve(bo, true))
1703 return -EAGAIN;
1704 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
1705 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1706 amdgpu_bo_unreserve(bo);
1707 if (ret) {
1708 pr_err("%s: Failed to invalidate userptr BO\n",
1709 __func__);
1710 return -EAGAIN;
1711 }
1712
1713 list_move_tail(&mem->validate_list.head,
1714 &process_info->userptr_inval_list);
1715 }
1716
1717 if (list_empty(&process_info->userptr_inval_list))
1718 return 0; /* All evicted userptr BOs were freed */
1719
1720 /* Go through userptr_inval_list and update any invalid user_pages */
1721 list_for_each_entry(mem, &process_info->userptr_inval_list,
1722 validate_list.head) {
1723 invalid = atomic_read(&mem->invalid);
1724 if (!invalid)
1725 /* BO hasn't been invalidated since the last
1726 * revalidation attempt. Keep its BO list.
1727 */
1728 continue;
1729
1730 bo = mem->bo;
1731
1732 /* Get updated user pages */
1733 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
1734 if (ret) {
1735 pr_debug("%s: Failed to get user pages: %d\n",
1736 __func__, ret);
1737
1738 /* Return error -EBUSY or -ENOMEM, retry restore */
1739 return ret;
1740 }
1741
1742 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1743
1744 /* Mark the BO as valid unless it was invalidated
1745 * again concurrently.
1746 */
1747 if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid)
1748 return -EAGAIN;
1749 }
1750
1751 return 0;
1752}
1753
1754/* Validate invalid userptr BOs
1755 *
1756 * Validates BOs on the userptr_inval_list, and moves them back to the
1757 * userptr_valid_list. Also updates GPUVM page tables with new page
1758 * addresses and waits for the page table updates to complete.
1759 */
1760static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
1761{
1762 struct amdgpu_bo_list_entry *pd_bo_list_entries;
1763 struct list_head resv_list, duplicates;
1764 struct ww_acquire_ctx ticket;
1765 struct amdgpu_sync sync;
1766
1767 struct amdgpu_vm *peer_vm;
1768 struct kgd_mem *mem, *tmp_mem;
1769 struct amdgpu_bo *bo;
1770 struct ttm_operation_ctx ctx = { false, false };
1771 int i, ret;
1772
1773 pd_bo_list_entries = kcalloc(process_info->n_vms,
1774 sizeof(struct amdgpu_bo_list_entry),
1775 GFP_KERNEL);
1776 if (!pd_bo_list_entries) {
1777 pr_err("%s: Failed to allocate PD BO list entries\n", __func__);
1778 ret = -ENOMEM;
1779 goto out_no_mem;
1780 }
1781
1782 INIT_LIST_HEAD(&resv_list);
1783 INIT_LIST_HEAD(&duplicates);
1784
1785 /* Get all the page directory BOs that need to be reserved */
1786 i = 0;
1787 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1788 vm_list_node)
1789 amdgpu_vm_get_pd_bo(peer_vm, &resv_list,
1790 &pd_bo_list_entries[i++]);
1791 /* Add the userptr_inval_list entries to resv_list */
1792 list_for_each_entry(mem, &process_info->userptr_inval_list,
1793 validate_list.head) {
1794 list_add_tail(&mem->resv_list.head, &resv_list);
1795 mem->resv_list.bo = mem->validate_list.bo;
1796 mem->resv_list.num_shared = mem->validate_list.num_shared;
1797 }
1798
1799 /* Reserve all BOs and page tables for validation */
1800 ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates,
1801 true);
1802 WARN(!list_empty(&duplicates), "Duplicates should be empty");
1803 if (ret)
1804 goto out_free;
1805
1806 amdgpu_sync_create(&sync);
1807
1808 ret = process_validate_vms(process_info);
1809 if (ret)
1810 goto unreserve_out;
1811
1812 /* Validate BOs and update GPUVM page tables */
1813 list_for_each_entry_safe(mem, tmp_mem,
1814 &process_info->userptr_inval_list,
1815 validate_list.head) {
1816 struct kfd_bo_va_list *bo_va_entry;
1817
1818 bo = mem->bo;
1819
1820 /* Validate the BO if we got user pages */
1821 if (bo->tbo.ttm->pages[0]) {
1822 amdgpu_bo_placement_from_domain(bo, mem->domain);
1823 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1824 if (ret) {
1825 pr_err("%s: failed to validate BO\n", __func__);
1826 goto unreserve_out;
1827 }
1828 }
1829
1830 list_move_tail(&mem->validate_list.head,
1831 &process_info->userptr_valid_list);
1832
1833 /* Update mapping. If the BO was not validated
1834 * (because we couldn't get user pages), this will
1835 * clear the page table entries, which will result in
1836 * VM faults if the GPU tries to access the invalid
1837 * memory.
1838 */
1839 list_for_each_entry(bo_va_entry, &mem->bo_va_list, bo_list) {
1840 if (!bo_va_entry->is_mapped)
1841 continue;
1842
1843 ret = update_gpuvm_pte((struct amdgpu_device *)
1844 bo_va_entry->kgd_dev,
1845 bo_va_entry, &sync);
1846 if (ret) {
1847 pr_err("%s: update PTE failed\n", __func__);
1848 /* make sure this gets validated again */
1849 atomic_inc(&mem->invalid);
1850 goto unreserve_out;
1851 }
1852 }
1853 }
1854
1855 /* Update page directories */
1856 ret = process_update_pds(process_info, &sync);
1857
1858unreserve_out:
1859 ttm_eu_backoff_reservation(&ticket, &resv_list);
1860 amdgpu_sync_wait(&sync, false);
1861 amdgpu_sync_free(&sync);
1862out_free:
1863 kfree(pd_bo_list_entries);
1864out_no_mem:
1865
1866 return ret;
1867}
1868
1869/* Worker callback to restore evicted userptr BOs
1870 *
1871 * Tries to update and validate all userptr BOs. If successful and no
1872 * concurrent evictions happened, the queues are restarted. Otherwise,
1873 * reschedule for another attempt later.
1874 */
1875static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
1876{
1877 struct delayed_work *dwork = to_delayed_work(work);
1878 struct amdkfd_process_info *process_info =
1879 container_of(dwork, struct amdkfd_process_info,
1880 restore_userptr_work);
1881 struct task_struct *usertask;
1882 struct mm_struct *mm;
1883 int evicted_bos;
1884
1885 evicted_bos = atomic_read(&process_info->evicted_bos);
1886 if (!evicted_bos)
1887 return;
1888
1889 /* Reference task and mm in case of concurrent process termination */
1890 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
1891 if (!usertask)
1892 return;
1893 mm = get_task_mm(usertask);
1894 if (!mm) {
1895 put_task_struct(usertask);
1896 return;
1897 }
1898
1899 mutex_lock(&process_info->lock);
1900
1901 if (update_invalid_user_pages(process_info, mm))
1902 goto unlock_out;
1903 /* userptr_inval_list can be empty if all evicted userptr BOs
1904 * have been freed. In that case there is nothing to validate
1905 * and we can just restart the queues.
1906 */
1907 if (!list_empty(&process_info->userptr_inval_list)) {
1908 if (atomic_read(&process_info->evicted_bos) != evicted_bos)
1909 goto unlock_out; /* Concurrent eviction, try again */
1910
1911 if (validate_invalid_user_pages(process_info))
1912 goto unlock_out;
1913 }
1914 /* Final check for concurrent evicton and atomic update. If
1915 * another eviction happens after successful update, it will
1916 * be a first eviction that calls quiesce_mm. The eviction
1917 * reference counting inside KFD will handle this case.
1918 */
1919 if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) !=
1920 evicted_bos)
1921 goto unlock_out;
1922 evicted_bos = 0;
1923 if (kgd2kfd_resume_mm(mm)) {
1924 pr_err("%s: Failed to resume KFD\n", __func__);
1925 /* No recovery from this failure. Probably the CP is
1926 * hanging. No point trying again.
1927 */
1928 }
1929
1930unlock_out:
1931 mutex_unlock(&process_info->lock);
1932 mmput(mm);
1933 put_task_struct(usertask);
1934
1935 /* If validation failed, reschedule another attempt */
1936 if (evicted_bos)
1937 schedule_delayed_work(&process_info->restore_userptr_work,
1938 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
1939}
1940
1941/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
1942 * KFD process identified by process_info
1943 *
1944 * @process_info: amdkfd_process_info of the KFD process
1945 *
1946 * After memory eviction, restore thread calls this function. The function
1947 * should be called when the Process is still valid. BO restore involves -
1948 *
1949 * 1. Release old eviction fence and create new one
1950 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
1951 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
1952 * BOs that need to be reserved.
1953 * 4. Reserve all the BOs
1954 * 5. Validate of PD and PT BOs.
1955 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
1956 * 7. Add fence to all PD and PT BOs.
1957 * 8. Unreserve all BOs
1958 */
1959int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
1960{
1961 struct amdgpu_bo_list_entry *pd_bo_list;
1962 struct amdkfd_process_info *process_info = info;
1963 struct amdgpu_vm *peer_vm;
1964 struct kgd_mem *mem;
1965 struct bo_vm_reservation_context ctx;
1966 struct amdgpu_amdkfd_fence *new_fence;
1967 int ret = 0, i;
1968 struct list_head duplicate_save;
1969 struct amdgpu_sync sync_obj;
1970
1971 INIT_LIST_HEAD(&duplicate_save);
1972 INIT_LIST_HEAD(&ctx.list);
1973 INIT_LIST_HEAD(&ctx.duplicates);
1974
1975 pd_bo_list = kcalloc(process_info->n_vms,
1976 sizeof(struct amdgpu_bo_list_entry),
1977 GFP_KERNEL);
1978 if (!pd_bo_list)
1979 return -ENOMEM;
1980
1981 i = 0;
1982 mutex_lock(&process_info->lock);
1983 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1984 vm_list_node)
1985 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]);
1986
1987 /* Reserve all BOs and page tables/directory. Add all BOs from
1988 * kfd_bo_list to ctx.list
1989 */
1990 list_for_each_entry(mem, &process_info->kfd_bo_list,
1991 validate_list.head) {
1992
1993 list_add_tail(&mem->resv_list.head, &ctx.list);
1994 mem->resv_list.bo = mem->validate_list.bo;
1995 mem->resv_list.num_shared = mem->validate_list.num_shared;
1996 }
1997
1998 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list,
1999 false, &duplicate_save, true);
2000 if (ret) {
2001 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n");
2002 goto ttm_reserve_fail;
2003 }
2004
2005 amdgpu_sync_create(&sync_obj);
2006
2007 /* Validate PDs and PTs */
2008 ret = process_validate_vms(process_info);
2009 if (ret)
2010 goto validate_map_fail;
2011
2012 ret = process_sync_pds_resv(process_info, &sync_obj);
2013 if (ret) {
2014 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2015 goto validate_map_fail;
2016 }
2017
2018 /* Validate BOs and map them to GPUVM (update VM page tables). */
2019 list_for_each_entry(mem, &process_info->kfd_bo_list,
2020 validate_list.head) {
2021
2022 struct amdgpu_bo *bo = mem->bo;
2023 uint32_t domain = mem->domain;
2024 struct kfd_bo_va_list *bo_va_entry;
2025
2026 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2027 if (ret) {
2028 pr_debug("Memory eviction: Validate BOs failed. Try again\n");
2029 goto validate_map_fail;
2030 }
2031 ret = amdgpu_sync_fence(NULL, &sync_obj, bo->tbo.moving, false);
2032 if (ret) {
2033 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2034 goto validate_map_fail;
2035 }
2036 list_for_each_entry(bo_va_entry, &mem->bo_va_list,
2037 bo_list) {
2038 ret = update_gpuvm_pte((struct amdgpu_device *)
2039 bo_va_entry->kgd_dev,
2040 bo_va_entry,
2041 &sync_obj);
2042 if (ret) {
2043 pr_debug("Memory eviction: update PTE failed. Try again\n");
2044 goto validate_map_fail;
2045 }
2046 }
2047 }
2048
2049 /* Update page directories */
2050 ret = process_update_pds(process_info, &sync_obj);
2051 if (ret) {
2052 pr_debug("Memory eviction: update PDs failed. Try again\n");
2053 goto validate_map_fail;
2054 }
2055
2056 /* Wait for validate and PT updates to finish */
2057 amdgpu_sync_wait(&sync_obj, false);
2058
2059 /* Release old eviction fence and create new one, because fence only
2060 * goes from unsignaled to signaled, fence cannot be reused.
2061 * Use context and mm from the old fence.
2062 */
2063 new_fence = amdgpu_amdkfd_fence_create(
2064 process_info->eviction_fence->base.context,
2065 process_info->eviction_fence->mm);
2066 if (!new_fence) {
2067 pr_err("Failed to create eviction fence\n");
2068 ret = -ENOMEM;
2069 goto validate_map_fail;
2070 }
2071 dma_fence_put(&process_info->eviction_fence->base);
2072 process_info->eviction_fence = new_fence;
2073 *ef = dma_fence_get(&new_fence->base);
2074
2075 /* Attach new eviction fence to all BOs */
2076 list_for_each_entry(mem, &process_info->kfd_bo_list,
2077 validate_list.head)
2078 amdgpu_bo_fence(mem->bo,
2079 &process_info->eviction_fence->base, true);
2080
2081 /* Attach eviction fence to PD / PT BOs */
2082 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2083 vm_list_node) {
2084 struct amdgpu_bo *bo = peer_vm->root.base.bo;
2085
2086 amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
2087 }
2088
2089validate_map_fail:
2090 ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list);
2091 amdgpu_sync_free(&sync_obj);
2092ttm_reserve_fail:
2093 mutex_unlock(&process_info->lock);
2094 kfree(pd_bo_list);
2095 return ret;
2096}
2097
2098int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2099{
2100 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2101 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2102 int ret;
2103
2104 if (!info || !gws)
2105 return -EINVAL;
2106
2107 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2108 if (!*mem)
2109 return -ENOMEM;
2110
2111 mutex_init(&(*mem)->lock);
2112 (*mem)->bo = amdgpu_bo_ref(gws_bo);
2113 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2114 (*mem)->process_info = process_info;
2115 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2116 amdgpu_sync_create(&(*mem)->sync);
2117
2118
2119 /* Validate gws bo the first time it is added to process */
2120 mutex_lock(&(*mem)->process_info->lock);
2121 ret = amdgpu_bo_reserve(gws_bo, false);
2122 if (unlikely(ret)) {
2123 pr_err("Reserve gws bo failed %d\n", ret);
2124 goto bo_reservation_failure;
2125 }
2126
2127 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2128 if (ret) {
2129 pr_err("GWS BO validate failed %d\n", ret);
2130 goto bo_validation_failure;
2131 }
2132 /* GWS resource is shared b/t amdgpu and amdkfd
2133 * Add process eviction fence to bo so they can
2134 * evict each other.
2135 */
2136 ret = dma_resv_reserve_shared(gws_bo->tbo.base.resv, 1);
2137 if (ret)
2138 goto reserve_shared_fail;
2139 amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
2140 amdgpu_bo_unreserve(gws_bo);
2141 mutex_unlock(&(*mem)->process_info->lock);
2142
2143 return ret;
2144
2145reserve_shared_fail:
2146bo_validation_failure:
2147 amdgpu_bo_unreserve(gws_bo);
2148bo_reservation_failure:
2149 mutex_unlock(&(*mem)->process_info->lock);
2150 amdgpu_sync_free(&(*mem)->sync);
2151 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2152 amdgpu_bo_unref(&gws_bo);
2153 mutex_destroy(&(*mem)->lock);
2154 kfree(*mem);
2155 *mem = NULL;
2156 return ret;
2157}
2158
2159int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2160{
2161 int ret;
2162 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2163 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2164 struct amdgpu_bo *gws_bo = kgd_mem->bo;
2165
2166 /* Remove BO from process's validate list so restore worker won't touch
2167 * it anymore
2168 */
2169 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2170
2171 ret = amdgpu_bo_reserve(gws_bo, false);
2172 if (unlikely(ret)) {
2173 pr_err("Reserve gws bo failed %d\n", ret);
2174 //TODO add BO back to validate_list?
2175 return ret;
2176 }
2177 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2178 process_info->eviction_fence);
2179 amdgpu_bo_unreserve(gws_bo);
2180 amdgpu_sync_free(&kgd_mem->sync);
2181 amdgpu_bo_unref(&gws_bo);
2182 mutex_destroy(&kgd_mem->lock);
2183 kfree(mem);
2184 return 0;
2185}