1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Samsung's S3C2416 SoC device tree source
  4 *
  5 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  6 */
  7
  8#include <dt-bindings/clock/s3c2443.h>
  9#include "s3c24xx.dtsi"
 10#include "s3c2416-pinctrl.dtsi"
 11
 12/ {
 13	model = "Samsung S3C2416 SoC";
 14	compatible = "samsung,s3c2416";
 15
 16	aliases {
 17		serial3 = &uart_3;
 18	};
 19
 20	cpus {
 21		cpu {
 22			compatible = "arm,arm926ej-s";
 23		};
 24	};
 25
 26	interrupt-controller@4a000000 {
 27		compatible = "samsung,s3c2416-irq";
 28	};
 29
 30	clocks: clock-controller@4c000000 {
 31		compatible = "samsung,s3c2416-clock";
 32		reg = <0x4c000000 0x40>;
 33		#clock-cells = <1>;
 34	};
 35
 36	pinctrl@56000000 {
 37		compatible = "samsung,s3c2416-pinctrl";
 38	};
 39
 40	timer@51000000 {
 41		clocks = <&clocks PCLK_PWM>;
 42		clock-names = "timers";
 43	};
 44
 45	uart_0: serial@50000000 {
 46		compatible = "samsung,s3c2440-uart";
 47		clock-names = "uart", "clk_uart_baud2",
 48				"clk_uart_baud3";
 49		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
 50				<&clocks SCLK_UART>;
 51	};
 52
 53	uart_1: serial@50004000 {
 54		compatible = "samsung,s3c2440-uart";
 55		clock-names = "uart", "clk_uart_baud2",
 56				"clk_uart_baud3";
 57		clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
 58				<&clocks SCLK_UART>;
 59	};
 60
 61	uart_2: serial@50008000 {
 62		compatible = "samsung,s3c2440-uart";
 63		clock-names = "uart", "clk_uart_baud2",
 64				"clk_uart_baud3";
 65		clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
 66				<&clocks SCLK_UART>;
 67	};
 68
 69	uart_3: serial@5000c000 {
 70		compatible = "samsung,s3c2440-uart";
 71		reg = <0x5000C000 0x4000>;
 72		interrupts = <1 18 24 4>, <1 18 25 4>;
 73		clock-names = "uart", "clk_uart_baud2",
 74				"clk_uart_baud3";
 75		clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
 76				<&clocks SCLK_UART>;
 77		status = "disabled";
 78	};
 79
 80	sdhci_1: sdhci@4ac00000 {
 81		compatible = "samsung,s3c6410-sdhci";
 82		reg = <0x4AC00000 0x100>;
 83		interrupts = <0 0 21 3>;
 84		clock-names = "hsmmc", "mmc_busclk.0",
 85				"mmc_busclk.2";
 86		clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
 87				<&clocks MUX_HSMMC0>;
 88		status = "disabled";
 89	};
 90
 91	sdhci_0: sdhci@4a800000 {
 92		compatible = "samsung,s3c6410-sdhci";
 93		reg = <0x4A800000 0x100>;
 94		interrupts = <0 0 20 3>;
 95		clock-names = "hsmmc", "mmc_busclk.0",
 96				"mmc_busclk.2";
 97		clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
 98				<&clocks MUX_HSMMC1>;
 99		status = "disabled";
100	};
101
102	watchdog: watchdog@53000000 {
103		interrupts = <1 9 27 3>;
104		clocks = <&clocks PCLK_WDT>;
105		clock-names = "watchdog";
106	};
107
108	rtc: rtc@57000000 {
109		compatible = "samsung,s3c2416-rtc";
110		clocks = <&clocks PCLK_RTC>;
111		clock-names = "rtc";
112	};
113
114	i2c@54000000 {
115		compatible = "samsung,s3c2440-i2c";
116		clocks = <&clocks PCLK_I2C0>;
117		clock-names = "i2c";
118	};
119};