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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree for the ARM Integrator/CP platform
4 */
5
6/dts-v1/;
7/include/ "integrator.dtsi"
8
9/ {
10 model = "ARM Integrator/CP";
11 compatible = "arm,integrator-cp";
12
13 chosen {
14 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
15 };
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 /*
24 * Since the board has pluggable CPU modules, we
25 * cannot define a proper compatible here. Let the
26 * boot loader fill in the apropriate compatible
27 * string if necessary.
28 */
29 /* compatible = "arm,arm920t"; */
30 reg = <0>;
31 /*
32 * TBD comment.
33 */
34 /* kHz uV */
35 operating-points = <50000 0
36 48000 0>;
37 clocks = <&cmcore>;
38 clock-names = "cpu";
39 clock-latency = <1000000>; /* 1 ms */
40 };
41 };
42
43 /*
44 * The Integrator/CP overall clocking architecture can be found in
45 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
46 * appear to illustrate the layout used in most configurations.
47 */
48
49 /* The codec chrystal operates at 24.576 MHz */
50 xtal_codec: xtal24.576@24.576M {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <24576000>;
54 };
55
56 /* The chrystal is divided by 2 by the codec for the AACI bit clock */
57 aaci_bitclk: aaci_bitclk@12.288M {
58 #clock-cells = <0>;
59 compatible = "fixed-factor-clock";
60 clock-div = <2>;
61 clock-mult = <1>;
62 clocks = <&xtal_codec>;
63 };
64
65 /* This is a 25MHz chrystal on the base board */
66 xtal25mhz: xtal25mhz@25M {
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <25000000>;
70 };
71
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
73 uartclk: uartclk@14.74M {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <14745600>;
77 };
78
79 /* Actually sysclk I think */
80 pclk: pclk@0 {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <0>;
84 };
85
86 core-module@10000000 {
87 /* 24 MHz chrystal on the core module */
88 cm24mhz: cm24mhz@24M {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <24000000>;
92 };
93
94 /* Oscillator on the core module, clocks the CPU core */
95 cmcore: cmosc@24M {
96 compatible = "arm,syscon-icst525-integratorcp-cm-core";
97 #clock-cells = <0>;
98 lock-offset = <0x14>;
99 vco-offset = <0x08>;
100 clocks = <&cm24mhz>;
101 };
102
103 /* Oscillator on the core module, clocks the memory bus */
104 cmmem: cmosc@24M {
105 compatible = "arm,syscon-icst525-integratorcp-cm-mem";
106 #clock-cells = <0>;
107 lock-offset = <0x14>;
108 vco-offset = <0x08>;
109 clocks = <&cm24mhz>;
110 };
111
112 /* Auxilary oscillator on the core module, clocks the CLCD */
113 auxosc: auxosc@24M {
114 compatible = "arm,syscon-icst525";
115 #clock-cells = <0>;
116 lock-offset = <0x14>;
117 vco-offset = <0x1c>;
118 clocks = <&cm24mhz>;
119 };
120
121 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
122 kmiclk: kmiclk@1M {
123 #clock-cells = <0>;
124 compatible = "fixed-factor-clock";
125 clock-div = <3>;
126 clock-mult = <1>;
127 clocks = <&cm24mhz>;
128 };
129
130 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
131 timclk: timclk@1M {
132 #clock-cells = <0>;
133 compatible = "fixed-factor-clock";
134 clock-div = <24>;
135 clock-mult = <1>;
136 clocks = <&cm24mhz>;
137 };
138 };
139
140 syscon {
141 compatible = "arm,integrator-cp-syscon", "syscon";
142 reg = <0xcb000000 0x100>;
143 };
144
145 timer0: timer@13000000 {
146 /* TIMER0 runs directly on the 25MHz chrystal */
147 compatible = "arm,integrator-cp-timer";
148 clocks = <&xtal25mhz>;
149 };
150
151 timer1: timer@13000100 {
152 /* TIMER1 runs @ 1MHz */
153 compatible = "arm,integrator-cp-timer";
154 clocks = <&timclk>;
155 };
156
157 timer2: timer@13000200 {
158 /* TIMER2 runs @ 1MHz */
159 compatible = "arm,integrator-cp-timer";
160 clocks = <&timclk>;
161 };
162
163 pic: pic@14000000 {
164 valid-mask = <0x1fc003ff>;
165 };
166
167 cic: cic@10000040 {
168 compatible = "arm,versatile-fpga-irq";
169 #interrupt-cells = <1>;
170 interrupt-controller;
171 reg = <0x10000040 0x100>;
172 clear-mask = <0xffffffff>;
173 valid-mask = <0x00000007>;
174 };
175
176 /* The SIC is cascaded off IRQ 26 on the PIC */
177 sic: sic@ca000000 {
178 compatible = "arm,versatile-fpga-irq";
179 interrupt-parent = <&pic>;
180 interrupts = <26>;
181 #interrupt-cells = <1>;
182 interrupt-controller;
183 reg = <0xca000000 0x100>;
184 clear-mask = <0x00000fff>;
185 valid-mask = <0x00000fff>;
186 };
187
188 ethernet@c8000000 {
189 compatible = "smsc,lan91c111";
190 reg = <0xc8000000 0x10>;
191 interrupt-parent = <&pic>;
192 interrupts = <27>;
193 };
194
195 bridge {
196 compatible = "ti,ths8134a", "ti,ths8134";
197 #address-cells = <1>;
198 #size-cells = <0>;
199
200 ports {
201 #address-cells = <1>;
202 #size-cells = <0>;
203
204 port@0 {
205 reg = <0>;
206
207 vga_bridge_in: endpoint {
208 remote-endpoint = <&clcd_pads_vga_dac>;
209 };
210 };
211
212 port@1 {
213 reg = <1>;
214
215 vga_bridge_out: endpoint {
216 remote-endpoint = <&vga_con_in>;
217 };
218 };
219 };
220 };
221
222 vga {
223 compatible = "vga-connector";
224
225 port {
226 vga_con_in: endpoint {
227 remote-endpoint = <&vga_bridge_out>;
228 };
229 };
230 };
231
232 fpga {
233 /*
234 * These PrimeCells are at the same location and using
235 * the same interrupts in all Integrators, but in the CP
236 * slightly newer versions are deployed.
237 */
238 rtc@15000000 {
239 compatible = "arm,pl031", "arm,primecell";
240 clocks = <&pclk>;
241 clock-names = "apb_pclk";
242 };
243
244 uart@16000000 {
245 compatible = "arm,pl011", "arm,primecell";
246 clocks = <&uartclk>, <&pclk>;
247 clock-names = "uartclk", "apb_pclk";
248 };
249
250 uart@17000000 {
251 compatible = "arm,pl011", "arm,primecell";
252 clocks = <&uartclk>, <&pclk>;
253 clock-names = "uartclk", "apb_pclk";
254 };
255
256 kmi@18000000 {
257 compatible = "arm,pl050", "arm,primecell";
258 clocks = <&kmiclk>, <&pclk>;
259 clock-names = "KMIREFCLK", "apb_pclk";
260 };
261
262 kmi@19000000 {
263 compatible = "arm,pl050", "arm,primecell";
264 clocks = <&kmiclk>, <&pclk>;
265 clock-names = "KMIREFCLK", "apb_pclk";
266 };
267
268 /*
269 * These PrimeCells are only available on the Integrator/CP
270 */
271 mmc@1c000000 {
272 compatible = "arm,pl180", "arm,primecell";
273 reg = <0x1c000000 0x1000>;
274 interrupts = <23 24>;
275 max-frequency = <515633>;
276 clocks = <&uartclk>, <&pclk>;
277 clock-names = "mclk", "apb_pclk";
278 };
279
280 aaci@1d000000 {
281 compatible = "arm,pl041", "arm,primecell";
282 reg = <0x1d000000 0x1000>;
283 interrupts = <25>;
284 clocks = <&pclk>;
285 clock-names = "apb_pclk";
286 };
287
288 clcd@c0000000 {
289 compatible = "arm,pl110", "arm,primecell";
290 reg = <0xC0000000 0x1000>;
291 interrupts = <22>;
292 clocks = <&auxosc>, <&pclk>;
293 clock-names = "clcdclk", "apb_pclk";
294 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
295 max-memory-bandwidth = <40000000>;
296
297 /*
298 * This port is routed through a PLD (Programmable
299 * Logic Device) that routes the output from the CLCD
300 * (after transformations) to the VGA DAC and also an
301 * external panel connector. The PLD is essential for
302 * supporting RGB565/BGR565.
303 *
304 * The signals from the port thus reaches two endpoints.
305 * The PLD is managed through a few special bits in the
306 * FPGA "sysreg".
307 *
308 * This arrangement can be clearly seen in
309 * ARM DUI 0225D, page 3-41, figure 3-19.
310 */
311 port@0 {
312 clcd_pads_vga_dac: endpoint {
313 remote-endpoint = <&vga_bridge_in>;
314 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
315 };
316 };
317 };
318 };
319};