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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17
18#include <sound/asoundef.h>
19#include <sound/core.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm_params.h>
22
23#include "stm32_sai.h"
24
25#define SAI_FREE_PROTOCOL 0x0
26#define SAI_SPDIF_PROTOCOL 0x1
27
28#define SAI_SLOT_SIZE_AUTO 0x0
29#define SAI_SLOT_SIZE_16 0x1
30#define SAI_SLOT_SIZE_32 0x2
31
32#define SAI_DATASIZE_8 0x2
33#define SAI_DATASIZE_10 0x3
34#define SAI_DATASIZE_16 0x4
35#define SAI_DATASIZE_20 0x5
36#define SAI_DATASIZE_24 0x6
37#define SAI_DATASIZE_32 0x7
38
39#define STM_SAI_DAI_NAME_SIZE 15
40
41#define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42#define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
43
44#define STM_SAI_A_ID 0x0
45#define STM_SAI_B_ID 0x1
46
47#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
48
49#define SAI_SYNC_NONE 0x0
50#define SAI_SYNC_INTERNAL 0x1
51#define SAI_SYNC_EXTERNAL 0x2
52
53#define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54#define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55#define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56#define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata))
57
58#define SAI_IEC60958_BLOCK_FRAMES 192
59#define SAI_IEC60958_STATUS_BYTES 24
60
61#define SAI_MCLK_NAME_LEN 32
62#define SAI_RATE_11K 11025
63#define SAI_MAX_SAMPLE_RATE_8K 192000
64#define SAI_MAX_SAMPLE_RATE_11K 176400
65#define SAI_CK_RATE_TOLERANCE 1000 /* ppm */
66
67/**
68 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
69 * @pdev: device data pointer
70 * @regmap: SAI register map pointer
71 * @regmap_config: SAI sub block register map configuration pointer
72 * @dma_params: dma configuration data for rx or tx channel
73 * @cpu_dai_drv: DAI driver data pointer
74 * @cpu_dai: DAI runtime data pointer
75 * @substream: PCM substream data pointer
76 * @pdata: SAI block parent data pointer
77 * @np_sync_provider: synchronization provider node
78 * @sai_ck: kernel clock feeding the SAI clock generator
79 * @sai_mclk: master clock from SAI mclk provider
80 * @phys_addr: SAI registers physical base address
81 * @mclk_rate: SAI block master clock frequency (Hz). set at init
82 * @id: SAI sub block id corresponding to sub-block A or B
83 * @dir: SAI block direction (playback or capture). set at init
84 * @master: SAI block mode flag. (true=master, false=slave) set at init
85 * @spdif: SAI S/PDIF iec60958 mode flag. set at init
86 * @sai_ck_used: flag set while exclusivity on SAI kernel clock is active
87 * @fmt: SAI block format. relevant only for custom protocols. set at init
88 * @sync: SAI block synchronization mode. (none, internal or external)
89 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
90 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
91 * @fs_length: frame synchronization length. depends on protocol settings
92 * @slots: rx or tx slot number
93 * @slot_width: rx or tx slot width in bits
94 * @slot_mask: rx or tx active slots mask. set at init or at runtime
95 * @data_size: PCM data width. corresponds to PCM substream width.
96 * @spdif_frm_cnt: S/PDIF playback frame counter
97 * @iec958: iec958 data
98 * @ctrl_lock: control lock
99 * @irq_lock: prevent race condition with IRQ
100 * @set_sai_ck_rate: set SAI kernel clock rate
101 * @put_sai_ck_rate: put SAI kernel clock rate
102 */
103struct stm32_sai_sub_data {
104 struct platform_device *pdev;
105 struct regmap *regmap;
106 const struct regmap_config *regmap_config;
107 struct snd_dmaengine_dai_dma_data dma_params;
108 struct snd_soc_dai_driver cpu_dai_drv;
109 struct snd_soc_dai *cpu_dai;
110 struct snd_pcm_substream *substream;
111 struct stm32_sai_data *pdata;
112 struct device_node *np_sync_provider;
113 struct clk *sai_ck;
114 struct clk *sai_mclk;
115 dma_addr_t phys_addr;
116 unsigned int mclk_rate;
117 unsigned int id;
118 int dir;
119 bool master;
120 bool spdif;
121 bool sai_ck_used;
122 int fmt;
123 int sync;
124 int synco;
125 int synci;
126 int fs_length;
127 int slots;
128 int slot_width;
129 int slot_mask;
130 int data_size;
131 unsigned int spdif_frm_cnt;
132 struct snd_aes_iec958 iec958;
133 struct mutex ctrl_lock; /* protect resources accessed by controls */
134 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
135 int (*set_sai_ck_rate)(struct stm32_sai_sub_data *sai, unsigned int rate);
136 void (*put_sai_ck_rate)(struct stm32_sai_sub_data *sai);
137};
138
139enum stm32_sai_fifo_th {
140 STM_SAI_FIFO_TH_EMPTY,
141 STM_SAI_FIFO_TH_QUARTER,
142 STM_SAI_FIFO_TH_HALF,
143 STM_SAI_FIFO_TH_3_QUARTER,
144 STM_SAI_FIFO_TH_FULL,
145};
146
147static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
148{
149 switch (reg) {
150 case STM_SAI_CR1_REGX:
151 case STM_SAI_CR2_REGX:
152 case STM_SAI_FRCR_REGX:
153 case STM_SAI_SLOTR_REGX:
154 case STM_SAI_IMR_REGX:
155 case STM_SAI_SR_REGX:
156 case STM_SAI_CLRFR_REGX:
157 case STM_SAI_DR_REGX:
158 case STM_SAI_PDMCR_REGX:
159 case STM_SAI_PDMLY_REGX:
160 return true;
161 default:
162 return false;
163 }
164}
165
166static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
167{
168 switch (reg) {
169 case STM_SAI_DR_REGX:
170 case STM_SAI_SR_REGX:
171 return true;
172 default:
173 return false;
174 }
175}
176
177static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
178{
179 switch (reg) {
180 case STM_SAI_CR1_REGX:
181 case STM_SAI_CR2_REGX:
182 case STM_SAI_FRCR_REGX:
183 case STM_SAI_SLOTR_REGX:
184 case STM_SAI_IMR_REGX:
185 case STM_SAI_CLRFR_REGX:
186 case STM_SAI_DR_REGX:
187 case STM_SAI_PDMCR_REGX:
188 case STM_SAI_PDMLY_REGX:
189 return true;
190 default:
191 return false;
192 }
193}
194
195static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai,
196 unsigned int reg, unsigned int mask,
197 unsigned int val)
198{
199 int ret;
200
201 ret = clk_enable(sai->pdata->pclk);
202 if (ret < 0)
203 return ret;
204
205 ret = regmap_update_bits(sai->regmap, reg, mask, val);
206
207 clk_disable(sai->pdata->pclk);
208
209 return ret;
210}
211
212static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai,
213 unsigned int reg, unsigned int mask,
214 unsigned int val)
215{
216 int ret;
217
218 ret = clk_enable(sai->pdata->pclk);
219 if (ret < 0)
220 return ret;
221
222 ret = regmap_write_bits(sai->regmap, reg, mask, val);
223
224 clk_disable(sai->pdata->pclk);
225
226 return ret;
227}
228
229static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai,
230 unsigned int reg, unsigned int *val)
231{
232 int ret;
233
234 ret = clk_enable(sai->pdata->pclk);
235 if (ret < 0)
236 return ret;
237
238 ret = regmap_read(sai->regmap, reg, val);
239
240 clk_disable(sai->pdata->pclk);
241
242 return ret;
243}
244
245static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
246 .reg_bits = 32,
247 .reg_stride = 4,
248 .val_bits = 32,
249 .max_register = STM_SAI_DR_REGX,
250 .readable_reg = stm32_sai_sub_readable_reg,
251 .volatile_reg = stm32_sai_sub_volatile_reg,
252 .writeable_reg = stm32_sai_sub_writeable_reg,
253 .fast_io = true,
254 .cache_type = REGCACHE_FLAT,
255};
256
257static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
258 .reg_bits = 32,
259 .reg_stride = 4,
260 .val_bits = 32,
261 .max_register = STM_SAI_PDMLY_REGX,
262 .readable_reg = stm32_sai_sub_readable_reg,
263 .volatile_reg = stm32_sai_sub_volatile_reg,
264 .writeable_reg = stm32_sai_sub_writeable_reg,
265 .fast_io = true,
266 .cache_type = REGCACHE_FLAT,
267};
268
269static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
270 struct snd_ctl_elem_info *uinfo)
271{
272 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
273 uinfo->count = 1;
274
275 return 0;
276}
277
278static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
279 struct snd_ctl_elem_value *uctl)
280{
281 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
282
283 mutex_lock(&sai->ctrl_lock);
284 memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
285 mutex_unlock(&sai->ctrl_lock);
286
287 return 0;
288}
289
290static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *uctl)
292{
293 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
294
295 mutex_lock(&sai->ctrl_lock);
296 memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
297 mutex_unlock(&sai->ctrl_lock);
298
299 return 0;
300}
301
302static const struct snd_kcontrol_new iec958_ctls = {
303 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
304 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
305 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
306 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
307 .info = snd_pcm_iec958_info,
308 .get = snd_pcm_iec958_get,
309 .put = snd_pcm_iec958_put,
310};
311
312struct stm32_sai_mclk_data {
313 struct clk_hw hw;
314 unsigned long freq;
315 struct stm32_sai_sub_data *sai_data;
316};
317
318#define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
319#define STM32_SAI_MAX_CLKS 1
320
321static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
322 unsigned long input_rate,
323 unsigned long output_rate)
324{
325 int version = sai->pdata->conf.version;
326 int div;
327
328 div = DIV_ROUND_CLOSEST(input_rate, output_rate);
329 if (div > SAI_XCR1_MCKDIV_MAX(version) || div <= 0) {
330 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
331 return -EINVAL;
332 }
333 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
334
335 if (input_rate % div)
336 dev_dbg(&sai->pdev->dev,
337 "Rate not accurate. requested (%ld), actual (%ld)\n",
338 output_rate, input_rate / div);
339
340 return div;
341}
342
343static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
344 unsigned int div)
345{
346 int version = sai->pdata->conf.version;
347 int ret, cr1, mask;
348
349 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
350 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
351 return -EINVAL;
352 }
353
354 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
355 cr1 = SAI_XCR1_MCKDIV_SET(div);
356 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);
357 if (ret < 0)
358 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
359
360 return ret;
361}
362
363static bool stm32_sai_rate_accurate(unsigned int max_rate, unsigned int rate)
364{
365 u64 delta, dividend;
366 int ratio;
367
368 ratio = DIV_ROUND_CLOSEST(max_rate, rate);
369 if (!ratio)
370 return false;
371
372 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));
373 delta = div_u64(dividend, max_rate);
374
375 if (delta <= SAI_CK_RATE_TOLERANCE)
376 return true;
377
378 return false;
379}
380
381static int stm32_sai_set_parent_clk(struct stm32_sai_sub_data *sai,
382 unsigned int rate)
383{
384 struct platform_device *pdev = sai->pdev;
385 struct clk *parent_clk = sai->pdata->clk_x8k;
386 int ret;
387
388 if (!(rate % SAI_RATE_11K))
389 parent_clk = sai->pdata->clk_x11k;
390
391 ret = clk_set_parent(sai->sai_ck, parent_clk);
392 if (ret)
393 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
394 ret, ret == -EBUSY ?
395 "Active stream rates conflict\n" : "\n");
396
397 return ret;
398}
399
400static void stm32_sai_put_parent_rate(struct stm32_sai_sub_data *sai)
401{
402 if (sai->sai_ck_used) {
403 sai->sai_ck_used = false;
404 clk_rate_exclusive_put(sai->sai_ck);
405 }
406}
407
408static int stm32_sai_set_parent_rate(struct stm32_sai_sub_data *sai,
409 unsigned int rate)
410{
411 struct platform_device *pdev = sai->pdev;
412 unsigned int sai_ck_rate, sai_ck_max_rate, sai_curr_rate, sai_new_rate;
413 int div, ret;
414
415 /*
416 * Set maximum expected kernel clock frequency
417 * - mclk on or spdif:
418 * f_sai_ck = MCKDIV * mclk-fs * fs
419 * Here typical 256 ratio is assumed for mclk-fs
420 * - mclk off:
421 * f_sai_ck = MCKDIV * FRL * fs
422 * Where FRL=[8..256], MCKDIV=[1..n] (n depends on SAI version)
423 * Set constraint MCKDIV * FRL <= 256, to ensure MCKDIV is in available range
424 * f_sai_ck = sai_ck_max_rate * pow_of_two(FRL) / 256
425 */
426 if (!(rate % SAI_RATE_11K))
427 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_11K * 256;
428 else
429 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_8K * 256;
430
431 if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai))
432 sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length));
433
434 /*
435 * Request exclusivity, as the clock is shared by SAI sub-blocks and by
436 * some SAI instances. This allows to ensure that the rate cannot be
437 * changed while one or more SAIs are using the clock.
438 */
439 clk_rate_exclusive_get(sai->sai_ck);
440 sai->sai_ck_used = true;
441
442 /*
443 * Check current kernel clock rate. If it gives the expected accuracy
444 * return immediately.
445 */
446 sai_curr_rate = clk_get_rate(sai->sai_ck);
447 if (stm32_sai_rate_accurate(sai_ck_max_rate, sai_curr_rate))
448 return 0;
449
450 /*
451 * Otherwise try to set the maximum rate and check the new actual rate.
452 * If the new rate does not give the expected accuracy, try to set
453 * lower rates for the kernel clock.
454 */
455 sai_ck_rate = sai_ck_max_rate;
456 div = 1;
457 do {
458 /* Check new rate accuracy. Return if ok */
459 sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate);
460 if (stm32_sai_rate_accurate(sai_ck_rate, sai_new_rate)) {
461 ret = clk_set_rate(sai->sai_ck, sai_ck_rate);
462 if (ret) {
463 dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s",
464 ret, ret == -EBUSY ?
465 "Active stream rates may be in conflict\n" : "\n");
466 goto err;
467 }
468
469 return 0;
470 }
471
472 /* Try a lower frequency */
473 div++;
474 sai_ck_rate = sai_ck_max_rate / div;
475 } while (sai_ck_rate > rate);
476
477 /* No accurate rate found */
478 dev_err(&pdev->dev, "Failed to find an accurate rate");
479
480err:
481 stm32_sai_put_parent_rate(sai);
482
483 return -EINVAL;
484}
485
486static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
487 unsigned long *prate)
488{
489 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
490 struct stm32_sai_sub_data *sai = mclk->sai_data;
491 int div;
492
493 div = stm32_sai_get_clk_div(sai, *prate, rate);
494 if (div <= 0)
495 return -EINVAL;
496
497 mclk->freq = *prate / div;
498
499 return mclk->freq;
500}
501
502static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
503 unsigned long parent_rate)
504{
505 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
506
507 return mclk->freq;
508}
509
510static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
511 unsigned long parent_rate)
512{
513 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
514 struct stm32_sai_sub_data *sai = mclk->sai_data;
515 int div, ret;
516
517 div = stm32_sai_get_clk_div(sai, parent_rate, rate);
518 if (div < 0)
519 return div;
520
521 ret = stm32_sai_set_clk_div(sai, div);
522 if (ret)
523 return ret;
524
525 mclk->freq = rate;
526
527 return 0;
528}
529
530static int stm32_sai_mclk_enable(struct clk_hw *hw)
531{
532 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
533 struct stm32_sai_sub_data *sai = mclk->sai_data;
534
535 dev_dbg(&sai->pdev->dev, "Enable master clock\n");
536
537 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
538 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
539}
540
541static void stm32_sai_mclk_disable(struct clk_hw *hw)
542{
543 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
544 struct stm32_sai_sub_data *sai = mclk->sai_data;
545
546 dev_dbg(&sai->pdev->dev, "Disable master clock\n");
547
548 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
549}
550
551static const struct clk_ops mclk_ops = {
552 .enable = stm32_sai_mclk_enable,
553 .disable = stm32_sai_mclk_disable,
554 .recalc_rate = stm32_sai_mclk_recalc_rate,
555 .round_rate = stm32_sai_mclk_round_rate,
556 .set_rate = stm32_sai_mclk_set_rate,
557};
558
559static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
560{
561 struct clk_hw *hw;
562 struct stm32_sai_mclk_data *mclk;
563 struct device *dev = &sai->pdev->dev;
564 const char *pname = __clk_get_name(sai->sai_ck);
565 char *mclk_name, *p, *s = (char *)pname;
566 int ret, i = 0;
567
568 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
569 if (!mclk)
570 return -ENOMEM;
571
572 mclk_name = devm_kcalloc(dev, sizeof(char),
573 SAI_MCLK_NAME_LEN, GFP_KERNEL);
574 if (!mclk_name)
575 return -ENOMEM;
576
577 /*
578 * Forge mclk clock name from parent clock name and suffix.
579 * String after "_" char is stripped in parent name.
580 */
581 p = mclk_name;
582 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
583 *p++ = *s++;
584 i++;
585 }
586 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
587
588 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
589 mclk->sai_data = sai;
590 hw = &mclk->hw;
591
592 dev_dbg(dev, "Register master clock %s\n", mclk_name);
593 ret = devm_clk_hw_register(&sai->pdev->dev, hw);
594 if (ret) {
595 dev_err(dev, "mclk register returned %d\n", ret);
596 return ret;
597 }
598 sai->sai_mclk = hw->clk;
599
600 /* register mclk provider */
601 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
602}
603
604static irqreturn_t stm32_sai_isr(int irq, void *devid)
605{
606 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
607 struct platform_device *pdev = sai->pdev;
608 unsigned int sr, imr, flags;
609 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
610
611 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr);
612 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr);
613
614 flags = sr & imr;
615 if (!flags)
616 return IRQ_NONE;
617
618 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
619 SAI_XCLRFR_MASK);
620
621 if (!sai->substream) {
622 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
623 return IRQ_NONE;
624 }
625
626 if (flags & SAI_XIMR_OVRUDRIE) {
627 dev_err(&pdev->dev, "IRQ %s\n",
628 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
629 status = SNDRV_PCM_STATE_XRUN;
630 }
631
632 if (flags & SAI_XIMR_MUTEDETIE)
633 dev_dbg(&pdev->dev, "IRQ mute detected\n");
634
635 if (flags & SAI_XIMR_WCKCFGIE) {
636 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
637 status = SNDRV_PCM_STATE_DISCONNECTED;
638 }
639
640 if (flags & SAI_XIMR_CNRDYIE)
641 dev_err(&pdev->dev, "IRQ Codec not ready\n");
642
643 if (flags & SAI_XIMR_AFSDETIE) {
644 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
645 status = SNDRV_PCM_STATE_XRUN;
646 }
647
648 if (flags & SAI_XIMR_LFSDETIE) {
649 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
650 status = SNDRV_PCM_STATE_XRUN;
651 }
652
653 spin_lock(&sai->irq_lock);
654 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
655 snd_pcm_stop_xrun(sai->substream);
656 spin_unlock(&sai->irq_lock);
657
658 return IRQ_HANDLED;
659}
660
661static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
662 int clk_id, unsigned int freq, int dir)
663{
664 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
665 int ret;
666
667 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
668 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
669 SAI_XCR1_NODIV,
670 freq ? 0 : SAI_XCR1_NODIV);
671 if (ret < 0)
672 return ret;
673
674 /* Assume shutdown if requested frequency is 0Hz */
675 if (!freq) {
676 /* Release mclk rate only if rate was actually set */
677 if (sai->mclk_rate) {
678 clk_rate_exclusive_put(sai->sai_mclk);
679 sai->mclk_rate = 0;
680 }
681
682 if (sai->put_sai_ck_rate)
683 sai->put_sai_ck_rate(sai);
684
685 return 0;
686 }
687
688 /* If master clock is used, configure SAI kernel clock now */
689 ret = sai->set_sai_ck_rate(sai, freq);
690 if (ret)
691 return ret;
692
693 ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
694 if (ret) {
695 dev_err(cpu_dai->dev,
696 ret == -EBUSY ?
697 "Active streams have incompatible rates" :
698 "Could not set mclk rate\n");
699 return ret;
700 }
701
702 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
703 sai->mclk_rate = freq;
704 }
705
706 return 0;
707}
708
709static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
710 u32 rx_mask, int slots, int slot_width)
711{
712 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
713 int slotr, slotr_mask, slot_size;
714
715 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
716 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
717 return 0;
718 }
719
720 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
721 tx_mask, rx_mask, slots, slot_width);
722
723 switch (slot_width) {
724 case 16:
725 slot_size = SAI_SLOT_SIZE_16;
726 break;
727 case 32:
728 slot_size = SAI_SLOT_SIZE_32;
729 break;
730 default:
731 slot_size = SAI_SLOT_SIZE_AUTO;
732 break;
733 }
734
735 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
736 SAI_XSLOTR_NBSLOT_SET(slots - 1);
737 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
738
739 /* tx/rx mask set in machine init, if slot number defined in DT */
740 if (STM_SAI_IS_PLAYBACK(sai)) {
741 sai->slot_mask = tx_mask;
742 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
743 }
744
745 if (STM_SAI_IS_CAPTURE(sai)) {
746 sai->slot_mask = rx_mask;
747 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
748 }
749
750 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
751
752 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
753
754 sai->slot_width = slot_width;
755 sai->slots = slots;
756
757 return 0;
758}
759
760static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
761{
762 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
763 int cr1, frcr = 0;
764 int cr1_mask, frcr_mask = 0;
765 int ret;
766
767 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
768
769 /* Do not generate master by default */
770 cr1 = SAI_XCR1_NODIV;
771 cr1_mask = SAI_XCR1_NODIV;
772
773 cr1_mask |= SAI_XCR1_PRTCFG_MASK;
774 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
775 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
776 goto conf_update;
777 }
778
779 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
780
781 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
782 /* SCK active high for all protocols */
783 case SND_SOC_DAIFMT_I2S:
784 cr1 |= SAI_XCR1_CKSTR;
785 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
786 break;
787 /* Left justified */
788 case SND_SOC_DAIFMT_MSB:
789 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
790 break;
791 /* Right justified */
792 case SND_SOC_DAIFMT_LSB:
793 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
794 break;
795 case SND_SOC_DAIFMT_DSP_A:
796 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
797 break;
798 case SND_SOC_DAIFMT_DSP_B:
799 frcr |= SAI_XFRCR_FSPOL;
800 break;
801 default:
802 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
803 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
804 return -EINVAL;
805 }
806
807 cr1_mask |= SAI_XCR1_CKSTR;
808 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
809 SAI_XFRCR_FSDEF;
810
811 /* DAI clock strobing. Invert setting previously set */
812 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
813 case SND_SOC_DAIFMT_NB_NF:
814 break;
815 case SND_SOC_DAIFMT_IB_NF:
816 cr1 ^= SAI_XCR1_CKSTR;
817 break;
818 case SND_SOC_DAIFMT_NB_IF:
819 frcr ^= SAI_XFRCR_FSPOL;
820 break;
821 case SND_SOC_DAIFMT_IB_IF:
822 /* Invert fs & sck */
823 cr1 ^= SAI_XCR1_CKSTR;
824 frcr ^= SAI_XFRCR_FSPOL;
825 break;
826 default:
827 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
828 fmt & SND_SOC_DAIFMT_INV_MASK);
829 return -EINVAL;
830 }
831 cr1_mask |= SAI_XCR1_CKSTR;
832 frcr_mask |= SAI_XFRCR_FSPOL;
833
834 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
835
836 /* DAI clock master masks */
837 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
838 case SND_SOC_DAIFMT_BC_FC:
839 /* codec is master */
840 cr1 |= SAI_XCR1_SLAVE;
841 sai->master = false;
842 break;
843 case SND_SOC_DAIFMT_BP_FP:
844 sai->master = true;
845 break;
846 default:
847 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
848 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
849 return -EINVAL;
850 }
851
852 /* Set slave mode if sub-block is synchronized with another SAI */
853 if (sai->sync) {
854 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
855 cr1 |= SAI_XCR1_SLAVE;
856 sai->master = false;
857 }
858
859 cr1_mask |= SAI_XCR1_SLAVE;
860
861conf_update:
862 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
863 if (ret < 0) {
864 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
865 return ret;
866 }
867
868 sai->fmt = fmt;
869
870 return 0;
871}
872
873static int stm32_sai_startup(struct snd_pcm_substream *substream,
874 struct snd_soc_dai *cpu_dai)
875{
876 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
877 int imr, cr2, ret;
878 unsigned long flags;
879
880 spin_lock_irqsave(&sai->irq_lock, flags);
881 sai->substream = substream;
882 spin_unlock_irqrestore(&sai->irq_lock, flags);
883
884 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
885 snd_pcm_hw_constraint_mask64(substream->runtime,
886 SNDRV_PCM_HW_PARAM_FORMAT,
887 SNDRV_PCM_FMTBIT_S32_LE);
888 snd_pcm_hw_constraint_single(substream->runtime,
889 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
890 }
891
892 ret = clk_prepare_enable(sai->sai_ck);
893 if (ret < 0) {
894 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
895 return ret;
896 }
897
898 /* Enable ITs */
899 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX,
900 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
901
902 imr = SAI_XIMR_OVRUDRIE;
903 if (STM_SAI_IS_CAPTURE(sai)) {
904 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2);
905 if (cr2 & SAI_XCR2_MUTECNT_MASK)
906 imr |= SAI_XIMR_MUTEDETIE;
907 }
908
909 if (sai->master)
910 imr |= SAI_XIMR_WCKCFGIE;
911 else
912 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
913
914 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
915 SAI_XIMR_MASK, imr);
916
917 return 0;
918}
919
920static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
921 struct snd_pcm_substream *substream,
922 struct snd_pcm_hw_params *params)
923{
924 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
925 int cr1, cr1_mask, ret;
926
927 /*
928 * DMA bursts increment is set to 4 words.
929 * SAI fifo threshold is set to half fifo, to keep enough space
930 * for DMA incoming bursts.
931 */
932 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX,
933 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
934 SAI_XCR2_FFLUSH |
935 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
936
937 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
938 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
939 sai->spdif_frm_cnt = 0;
940 return 0;
941 }
942
943 /* Mode, data format and channel config */
944 cr1_mask = SAI_XCR1_DS_MASK;
945 switch (params_format(params)) {
946 case SNDRV_PCM_FORMAT_S8:
947 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
948 break;
949 case SNDRV_PCM_FORMAT_S16_LE:
950 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
951 break;
952 case SNDRV_PCM_FORMAT_S32_LE:
953 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
954 break;
955 default:
956 dev_err(cpu_dai->dev, "Data format not supported\n");
957 return -EINVAL;
958 }
959
960 cr1_mask |= SAI_XCR1_MONO;
961 if ((sai->slots == 2) && (params_channels(params) == 1))
962 cr1 |= SAI_XCR1_MONO;
963
964 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
965 if (ret < 0) {
966 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
967 return ret;
968 }
969
970 return 0;
971}
972
973static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
974{
975 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
976 int slotr, slot_sz;
977
978 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr);
979
980 /*
981 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
982 * By default slot width = data size, if not forced from DT
983 */
984 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
985 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
986 sai->slot_width = sai->data_size;
987
988 if (sai->slot_width < sai->data_size) {
989 dev_err(cpu_dai->dev,
990 "Data size %d larger than slot width\n",
991 sai->data_size);
992 return -EINVAL;
993 }
994
995 /* Slot number is set to 2, if not specified in DT */
996 if (!sai->slots)
997 sai->slots = 2;
998
999 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
1000 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
1001 SAI_XSLOTR_NBSLOT_MASK,
1002 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
1003
1004 /* Set default slots mask if not already set from DT */
1005 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
1006 sai->slot_mask = (1 << sai->slots) - 1;
1007 stm32_sai_sub_reg_up(sai,
1008 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
1009 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
1010 }
1011
1012 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
1013 sai->slots, sai->slot_width);
1014
1015 return 0;
1016}
1017
1018static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
1019{
1020 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1021 int fs_active, offset, format;
1022 int frcr, frcr_mask;
1023
1024 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1025 sai->fs_length = sai->slot_width * sai->slots;
1026
1027 fs_active = sai->fs_length / 2;
1028 if ((format == SND_SOC_DAIFMT_DSP_A) ||
1029 (format == SND_SOC_DAIFMT_DSP_B))
1030 fs_active = 1;
1031
1032 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
1033 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
1034 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
1035
1036 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
1037 sai->fs_length, fs_active);
1038
1039 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
1040
1041 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
1042 offset = sai->slot_width - sai->data_size;
1043
1044 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
1045 SAI_XSLOTR_FBOFF_MASK,
1046 SAI_XSLOTR_FBOFF_SET(offset));
1047 }
1048}
1049
1050static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
1051{
1052 unsigned char *cs = sai->iec958.status;
1053
1054 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
1055 cs[1] = IEC958_AES1_CON_GENERAL;
1056 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
1057 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
1058}
1059
1060static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
1061 struct snd_pcm_runtime *runtime)
1062{
1063 if (!runtime)
1064 return;
1065
1066 /* Force the sample rate according to runtime rate */
1067 mutex_lock(&sai->ctrl_lock);
1068 switch (runtime->rate) {
1069 case 22050:
1070 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
1071 break;
1072 case 44100:
1073 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
1074 break;
1075 case 88200:
1076 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
1077 break;
1078 case 176400:
1079 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
1080 break;
1081 case 24000:
1082 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
1083 break;
1084 case 48000:
1085 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
1086 break;
1087 case 96000:
1088 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
1089 break;
1090 case 192000:
1091 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
1092 break;
1093 case 32000:
1094 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
1095 break;
1096 default:
1097 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
1098 break;
1099 }
1100 mutex_unlock(&sai->ctrl_lock);
1101}
1102
1103static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
1104 struct snd_pcm_hw_params *params)
1105{
1106 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1107 int div = 0, cr1 = 0;
1108 int sai_clk_rate, mclk_ratio, den;
1109 unsigned int rate = params_rate(params);
1110 int ret;
1111
1112 if (!sai->sai_mclk) {
1113 ret = sai->set_sai_ck_rate(sai, rate);
1114 if (ret)
1115 return ret;
1116 }
1117 sai_clk_rate = clk_get_rate(sai->sai_ck);
1118
1119 if (STM_SAI_IS_F4(sai->pdata)) {
1120 /* mclk on (NODIV=0)
1121 * mclk_rate = 256 * fs
1122 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
1123 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
1124 * mclk off (NODIV=1)
1125 * MCKDIV ignored. sck = sai_ck
1126 */
1127 if (!sai->mclk_rate)
1128 return 0;
1129
1130 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
1131 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1132 2 * sai->mclk_rate);
1133 if (div < 0)
1134 return div;
1135 }
1136 } else {
1137 /*
1138 * TDM mode :
1139 * mclk on
1140 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
1141 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
1142 * mclk off
1143 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
1144 * Note: NOMCK/NODIV correspond to same bit.
1145 */
1146 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1147 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1148 rate * 128);
1149 if (div < 0)
1150 return div;
1151 } else {
1152 if (sai->mclk_rate) {
1153 mclk_ratio = sai->mclk_rate / rate;
1154 if (mclk_ratio == 512) {
1155 cr1 = SAI_XCR1_OSR;
1156 } else if (mclk_ratio != 256) {
1157 dev_err(cpu_dai->dev,
1158 "Wrong mclk ratio %d\n",
1159 mclk_ratio);
1160 return -EINVAL;
1161 }
1162
1163 stm32_sai_sub_reg_up(sai,
1164 STM_SAI_CR1_REGX,
1165 SAI_XCR1_OSR, cr1);
1166
1167 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1168 sai->mclk_rate);
1169 if (div < 0)
1170 return div;
1171 } else {
1172 /* mclk-fs not set, master clock not active */
1173 den = sai->fs_length * params_rate(params);
1174 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1175 den);
1176 if (div < 0)
1177 return div;
1178 }
1179 }
1180 }
1181
1182 return stm32_sai_set_clk_div(sai, div);
1183}
1184
1185static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
1186 struct snd_pcm_hw_params *params,
1187 struct snd_soc_dai *cpu_dai)
1188{
1189 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1190 int ret;
1191
1192 sai->data_size = params_width(params);
1193
1194 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1195 /* Rate not already set in runtime structure */
1196 substream->runtime->rate = params_rate(params);
1197 stm32_sai_set_iec958_status(sai, substream->runtime);
1198 } else {
1199 ret = stm32_sai_set_slots(cpu_dai);
1200 if (ret < 0)
1201 return ret;
1202 stm32_sai_set_frame(cpu_dai);
1203 }
1204
1205 ret = stm32_sai_set_config(cpu_dai, substream, params);
1206 if (ret)
1207 return ret;
1208
1209 if (sai->master)
1210 ret = stm32_sai_configure_clock(cpu_dai, params);
1211
1212 return ret;
1213}
1214
1215static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1216 struct snd_soc_dai *cpu_dai)
1217{
1218 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1219 int ret;
1220
1221 switch (cmd) {
1222 case SNDRV_PCM_TRIGGER_START:
1223 case SNDRV_PCM_TRIGGER_RESUME:
1224 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1225 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1226
1227 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1228 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1229
1230 /* Enable SAI */
1231 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1232 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1233 if (ret < 0)
1234 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1235 break;
1236 case SNDRV_PCM_TRIGGER_SUSPEND:
1237 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1238 case SNDRV_PCM_TRIGGER_STOP:
1239 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1240
1241 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
1242 SAI_XIMR_MASK, 0);
1243
1244 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1245 SAI_XCR1_SAIEN,
1246 (unsigned int)~SAI_XCR1_SAIEN);
1247
1248 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1249 SAI_XCR1_DMAEN,
1250 (unsigned int)~SAI_XCR1_DMAEN);
1251 if (ret < 0)
1252 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1253
1254 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1255 sai->spdif_frm_cnt = 0;
1256 break;
1257 default:
1258 return -EINVAL;
1259 }
1260
1261 return ret;
1262}
1263
1264static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1265 struct snd_soc_dai *cpu_dai)
1266{
1267 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1268 unsigned long flags;
1269
1270 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1271
1272 clk_disable_unprepare(sai->sai_ck);
1273
1274 /*
1275 * Release kernel clock if following conditions are fulfilled
1276 * - Master clock is not used. Kernel clock won't be released trough sysclk
1277 * - Put handler is defined. Involve that clock is managed exclusively
1278 */
1279 if (!sai->sai_mclk && sai->put_sai_ck_rate)
1280 sai->put_sai_ck_rate(sai);
1281
1282 spin_lock_irqsave(&sai->irq_lock, flags);
1283 sai->substream = NULL;
1284 spin_unlock_irqrestore(&sai->irq_lock, flags);
1285}
1286
1287static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1288 struct snd_soc_dai *cpu_dai)
1289{
1290 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1291 struct snd_kcontrol_new knew = iec958_ctls;
1292
1293 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1294 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
1295 knew.device = rtd->pcm->device;
1296 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
1297 }
1298
1299 return 0;
1300}
1301
1302static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1303{
1304 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1305 int cr1 = 0, cr1_mask, ret;
1306
1307 sai->cpu_dai = cpu_dai;
1308
1309 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1310 /*
1311 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1312 * as it allows bytes, half-word and words transfers. (See DMA fifos
1313 * constraints).
1314 */
1315 sai->dma_params.maxburst = 4;
1316 if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst)
1317 sai->dma_params.maxburst = 1;
1318 /* Buswidth will be set by framework at runtime */
1319 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1320
1321 if (STM_SAI_IS_PLAYBACK(sai))
1322 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1323 else
1324 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1325
1326 /* Next settings are not relevant for spdif mode */
1327 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1328 return 0;
1329
1330 cr1_mask = SAI_XCR1_RX_TX;
1331 if (STM_SAI_IS_CAPTURE(sai))
1332 cr1 |= SAI_XCR1_RX_TX;
1333
1334 /* Configure synchronization */
1335 if (sai->sync == SAI_SYNC_EXTERNAL) {
1336 /* Configure synchro client and provider */
1337 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
1338 sai->synco, sai->synci);
1339 if (ret)
1340 return ret;
1341 }
1342
1343 cr1_mask |= SAI_XCR1_SYNCEN_MASK;
1344 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
1345
1346 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
1347}
1348
1349static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1350 .probe = stm32_sai_dai_probe,
1351 .set_sysclk = stm32_sai_set_sysclk,
1352 .set_fmt = stm32_sai_set_dai_fmt,
1353 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1354 .startup = stm32_sai_startup,
1355 .hw_params = stm32_sai_hw_params,
1356 .trigger = stm32_sai_trigger,
1357 .shutdown = stm32_sai_shutdown,
1358 .pcm_new = stm32_sai_pcm_new,
1359};
1360
1361static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = {
1362 .probe = stm32_sai_dai_probe,
1363 .set_sysclk = stm32_sai_set_sysclk,
1364 .set_fmt = stm32_sai_set_dai_fmt,
1365 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1366 .startup = stm32_sai_startup,
1367 .hw_params = stm32_sai_hw_params,
1368 .trigger = stm32_sai_trigger,
1369 .shutdown = stm32_sai_shutdown,
1370};
1371
1372static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
1373 int channel, unsigned long hwoff,
1374 unsigned long bytes)
1375{
1376 struct snd_pcm_runtime *runtime = substream->runtime;
1377 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1378 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
1379 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1380 int *ptr = (int *)(runtime->dma_area + hwoff +
1381 channel * (runtime->dma_bytes / runtime->channels));
1382 ssize_t cnt = bytes_to_samples(runtime, bytes);
1383 unsigned int frm_cnt = sai->spdif_frm_cnt;
1384 unsigned int byte;
1385 unsigned int mask;
1386
1387 do {
1388 *ptr = ((*ptr >> 8) & 0x00ffffff);
1389
1390 /* Set channel status bit */
1391 byte = frm_cnt >> 3;
1392 mask = 1 << (frm_cnt - (byte << 3));
1393 if (sai->iec958.status[byte] & mask)
1394 *ptr |= 0x04000000;
1395 ptr++;
1396
1397 if (!(cnt % 2))
1398 frm_cnt++;
1399
1400 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
1401 frm_cnt = 0;
1402 } while (--cnt);
1403 sai->spdif_frm_cnt = frm_cnt;
1404
1405 return 0;
1406}
1407
1408/* No support of mmap in S/PDIF mode */
1409static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
1410 .info = SNDRV_PCM_INFO_INTERLEAVED,
1411 .buffer_bytes_max = 8 * PAGE_SIZE,
1412 .period_bytes_min = 1024,
1413 .period_bytes_max = PAGE_SIZE,
1414 .periods_min = 2,
1415 .periods_max = 8,
1416};
1417
1418static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1419 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1420 .buffer_bytes_max = 8 * PAGE_SIZE,
1421 .period_bytes_min = 1024, /* 5ms at 48kHz */
1422 .period_bytes_max = PAGE_SIZE,
1423 .periods_min = 2,
1424 .periods_max = 8,
1425};
1426
1427static struct snd_soc_dai_driver stm32_sai_playback_dai = {
1428 .id = 1, /* avoid call to fmt_single_name() */
1429 .playback = {
1430 .channels_min = 1,
1431 .channels_max = 16,
1432 .rate_min = 8000,
1433 .rate_max = 192000,
1434 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1435 /* DMA does not support 24 bits transfers */
1436 .formats =
1437 SNDRV_PCM_FMTBIT_S8 |
1438 SNDRV_PCM_FMTBIT_S16_LE |
1439 SNDRV_PCM_FMTBIT_S32_LE,
1440 },
1441 .ops = &stm32_sai_pcm_dai_ops,
1442};
1443
1444static struct snd_soc_dai_driver stm32_sai_capture_dai = {
1445 .id = 1, /* avoid call to fmt_single_name() */
1446 .capture = {
1447 .channels_min = 1,
1448 .channels_max = 16,
1449 .rate_min = 8000,
1450 .rate_max = 192000,
1451 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1452 /* DMA does not support 24 bits transfers */
1453 .formats =
1454 SNDRV_PCM_FMTBIT_S8 |
1455 SNDRV_PCM_FMTBIT_S16_LE |
1456 SNDRV_PCM_FMTBIT_S32_LE,
1457 },
1458 .ops = &stm32_sai_pcm_dai_ops2,
1459};
1460
1461static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1462 .pcm_hardware = &stm32_sai_pcm_hw,
1463 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1464};
1465
1466static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1467 .pcm_hardware = &stm32_sai_pcm_hw_spdif,
1468 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1469 .process = stm32_sai_pcm_process_spdif,
1470};
1471
1472static const struct snd_soc_component_driver stm32_component = {
1473 .name = "stm32-sai",
1474 .legacy_dai_naming = 1,
1475};
1476
1477static const struct of_device_id stm32_sai_sub_ids[] = {
1478 { .compatible = "st,stm32-sai-sub-a",
1479 .data = (void *)STM_SAI_A_ID},
1480 { .compatible = "st,stm32-sai-sub-b",
1481 .data = (void *)STM_SAI_B_ID},
1482 {}
1483};
1484MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1485
1486static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1487 struct stm32_sai_sub_data *sai)
1488{
1489 struct device_node *np = pdev->dev.of_node;
1490 struct resource *res;
1491 void __iomem *base;
1492 struct of_phandle_args args;
1493 int ret;
1494
1495 if (!np)
1496 return -ENODEV;
1497
1498 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1499 if (IS_ERR(base))
1500 return PTR_ERR(base);
1501
1502 sai->phys_addr = res->start;
1503
1504 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1505 /* Note: PDM registers not available for sub-block B */
1506 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
1507 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1508
1509 /*
1510 * Do not manage peripheral clock through regmap framework as this
1511 * can lead to circular locking issue with sai master clock provider.
1512 * Manage peripheral clock directly in driver instead.
1513 */
1514 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1515 sai->regmap_config);
1516 if (IS_ERR(sai->regmap))
1517 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
1518 "Regmap init error\n");
1519
1520 /* Get direction property */
1521 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1522 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1523 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1524 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1525 } else {
1526 dev_err(&pdev->dev, "Unsupported direction\n");
1527 return -EINVAL;
1528 }
1529
1530 /* Get spdif iec60958 property */
1531 sai->spdif = false;
1532 if (of_property_present(np, "st,iec60958")) {
1533 if (!STM_SAI_HAS_SPDIF(sai) ||
1534 sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1535 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1536 return -EINVAL;
1537 }
1538 stm32_sai_init_iec958_status(sai);
1539 sai->spdif = true;
1540 sai->master = true;
1541 }
1542
1543 /* Get synchronization property */
1544 args.np = NULL;
1545 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1546 if (ret < 0 && ret != -ENOENT) {
1547 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1548 return ret;
1549 }
1550
1551 sai->sync = SAI_SYNC_NONE;
1552 if (args.np) {
1553 if (args.np == np) {
1554 dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
1555 of_node_put(args.np);
1556 return -EINVAL;
1557 }
1558
1559 sai->np_sync_provider = of_get_parent(args.np);
1560 if (!sai->np_sync_provider) {
1561 dev_err(&pdev->dev, "%pOFn parent node not found\n",
1562 np);
1563 of_node_put(args.np);
1564 return -ENODEV;
1565 }
1566
1567 sai->sync = SAI_SYNC_INTERNAL;
1568 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1569 if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1570 dev_err(&pdev->dev,
1571 "External synchro not supported\n");
1572 of_node_put(args.np);
1573 return -EINVAL;
1574 }
1575 sai->sync = SAI_SYNC_EXTERNAL;
1576
1577 sai->synci = args.args[0];
1578 if (sai->synci < 1 ||
1579 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1580 dev_err(&pdev->dev, "Wrong SAI index\n");
1581 of_node_put(args.np);
1582 return -EINVAL;
1583 }
1584
1585 if (of_property_match_string(args.np, "compatible",
1586 "st,stm32-sai-sub-a") >= 0)
1587 sai->synco = STM_SAI_SYNC_OUT_A;
1588
1589 if (of_property_match_string(args.np, "compatible",
1590 "st,stm32-sai-sub-b") >= 0)
1591 sai->synco = STM_SAI_SYNC_OUT_B;
1592
1593 if (!sai->synco) {
1594 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1595 of_node_put(args.np);
1596 return -EINVAL;
1597 }
1598 }
1599
1600 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1601 pdev->name, args.np->full_name);
1602 }
1603
1604 of_node_put(args.np);
1605 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1606 if (IS_ERR(sai->sai_ck))
1607 return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck),
1608 "Missing kernel clock sai_ck\n");
1609
1610 ret = clk_prepare(sai->pdata->pclk);
1611 if (ret < 0)
1612 return ret;
1613
1614 if (STM_SAI_IS_F4(sai->pdata))
1615 return 0;
1616
1617 /* Register mclk provider if requested */
1618 if (of_property_present(np, "#clock-cells")) {
1619 ret = stm32_sai_add_mclk_provider(sai);
1620 if (ret < 0)
1621 return ret;
1622 } else {
1623 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK");
1624 if (IS_ERR(sai->sai_mclk))
1625 return PTR_ERR(sai->sai_mclk);
1626 }
1627
1628 return 0;
1629}
1630
1631static int stm32_sai_sub_probe(struct platform_device *pdev)
1632{
1633 struct stm32_sai_sub_data *sai;
1634 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1635 int ret;
1636
1637 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1638 if (!sai)
1639 return -ENOMEM;
1640
1641 sai->id = (uintptr_t)device_get_match_data(&pdev->dev);
1642
1643 sai->pdev = pdev;
1644 mutex_init(&sai->ctrl_lock);
1645 spin_lock_init(&sai->irq_lock);
1646 platform_set_drvdata(pdev, sai);
1647
1648 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1649 if (!sai->pdata) {
1650 dev_err(&pdev->dev, "Parent device data not available\n");
1651 return -EINVAL;
1652 }
1653
1654 if (sai->pdata->conf.get_sai_ck_parent) {
1655 sai->set_sai_ck_rate = stm32_sai_set_parent_clk;
1656 } else {
1657 sai->set_sai_ck_rate = stm32_sai_set_parent_rate;
1658 sai->put_sai_ck_rate = stm32_sai_put_parent_rate;
1659 }
1660
1661 ret = stm32_sai_sub_parse_of(pdev, sai);
1662 if (ret)
1663 return ret;
1664
1665 if (STM_SAI_IS_PLAYBACK(sai))
1666 sai->cpu_dai_drv = stm32_sai_playback_dai;
1667 else
1668 sai->cpu_dai_drv = stm32_sai_capture_dai;
1669 sai->cpu_dai_drv.name = dev_name(&pdev->dev);
1670
1671 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1672 IRQF_SHARED, dev_name(&pdev->dev), sai);
1673 if (ret) {
1674 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1675 return ret;
1676 }
1677
1678 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1679 conf = &stm32_sai_pcm_config_spdif;
1680
1681 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1682 if (ret)
1683 return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n");
1684
1685 ret = snd_soc_register_component(&pdev->dev, &stm32_component,
1686 &sai->cpu_dai_drv, 1);
1687 if (ret) {
1688 snd_dmaengine_pcm_unregister(&pdev->dev);
1689 return ret;
1690 }
1691
1692 pm_runtime_enable(&pdev->dev);
1693
1694 return 0;
1695}
1696
1697static void stm32_sai_sub_remove(struct platform_device *pdev)
1698{
1699 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
1700
1701 clk_unprepare(sai->pdata->pclk);
1702 snd_dmaengine_pcm_unregister(&pdev->dev);
1703 snd_soc_unregister_component(&pdev->dev);
1704 pm_runtime_disable(&pdev->dev);
1705}
1706
1707#ifdef CONFIG_PM_SLEEP
1708static int stm32_sai_sub_suspend(struct device *dev)
1709{
1710 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1711 int ret;
1712
1713 ret = clk_enable(sai->pdata->pclk);
1714 if (ret < 0)
1715 return ret;
1716
1717 regcache_cache_only(sai->regmap, true);
1718 regcache_mark_dirty(sai->regmap);
1719
1720 clk_disable(sai->pdata->pclk);
1721
1722 return 0;
1723}
1724
1725static int stm32_sai_sub_resume(struct device *dev)
1726{
1727 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1728 int ret;
1729
1730 ret = clk_enable(sai->pdata->pclk);
1731 if (ret < 0)
1732 return ret;
1733
1734 regcache_cache_only(sai->regmap, false);
1735 ret = regcache_sync(sai->regmap);
1736
1737 clk_disable(sai->pdata->pclk);
1738
1739 return ret;
1740}
1741#endif /* CONFIG_PM_SLEEP */
1742
1743static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
1744 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
1745};
1746
1747static struct platform_driver stm32_sai_sub_driver = {
1748 .driver = {
1749 .name = "st,stm32-sai-sub",
1750 .of_match_table = stm32_sai_sub_ids,
1751 .pm = &stm32_sai_sub_pm_ops,
1752 },
1753 .probe = stm32_sai_sub_probe,
1754 .remove = stm32_sai_sub_remove,
1755};
1756
1757module_platform_driver(stm32_sai_sub_driver);
1758
1759MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1760MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1761MODULE_ALIAS("platform:st,stm32-sai-sub");
1762MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17
18#include <sound/asoundef.h>
19#include <sound/core.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm_params.h>
22
23#include "stm32_sai.h"
24
25#define SAI_FREE_PROTOCOL 0x0
26#define SAI_SPDIF_PROTOCOL 0x1
27
28#define SAI_SLOT_SIZE_AUTO 0x0
29#define SAI_SLOT_SIZE_16 0x1
30#define SAI_SLOT_SIZE_32 0x2
31
32#define SAI_DATASIZE_8 0x2
33#define SAI_DATASIZE_10 0x3
34#define SAI_DATASIZE_16 0x4
35#define SAI_DATASIZE_20 0x5
36#define SAI_DATASIZE_24 0x6
37#define SAI_DATASIZE_32 0x7
38
39#define STM_SAI_DAI_NAME_SIZE 15
40
41#define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42#define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
43
44#define STM_SAI_A_ID 0x0
45#define STM_SAI_B_ID 0x1
46
47#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
48#define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
49#define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
50
51#define SAI_SYNC_NONE 0x0
52#define SAI_SYNC_INTERNAL 0x1
53#define SAI_SYNC_EXTERNAL 0x2
54
55#define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
56#define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
57#define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
58#define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
59
60#define SAI_IEC60958_BLOCK_FRAMES 192
61#define SAI_IEC60958_STATUS_BYTES 24
62
63#define SAI_MCLK_NAME_LEN 32
64#define SAI_RATE_11K 11025
65
66/**
67 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
68 * @pdev: device data pointer
69 * @regmap: SAI register map pointer
70 * @regmap_config: SAI sub block register map configuration pointer
71 * @dma_params: dma configuration data for rx or tx channel
72 * @cpu_dai_drv: DAI driver data pointer
73 * @cpu_dai: DAI runtime data pointer
74 * @substream: PCM substream data pointer
75 * @pdata: SAI block parent data pointer
76 * @np_sync_provider: synchronization provider node
77 * @sai_ck: kernel clock feeding the SAI clock generator
78 * @sai_mclk: master clock from SAI mclk provider
79 * @phys_addr: SAI registers physical base address
80 * @mclk_rate: SAI block master clock frequency (Hz). set at init
81 * @id: SAI sub block id corresponding to sub-block A or B
82 * @dir: SAI block direction (playback or capture). set at init
83 * @master: SAI block mode flag. (true=master, false=slave) set at init
84 * @spdif: SAI S/PDIF iec60958 mode flag. set at init
85 * @fmt: SAI block format. relevant only for custom protocols. set at init
86 * @sync: SAI block synchronization mode. (none, internal or external)
87 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
88 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
89 * @fs_length: frame synchronization length. depends on protocol settings
90 * @slots: rx or tx slot number
91 * @slot_width: rx or tx slot width in bits
92 * @slot_mask: rx or tx active slots mask. set at init or at runtime
93 * @data_size: PCM data width. corresponds to PCM substream width.
94 * @spdif_frm_cnt: S/PDIF playback frame counter
95 * @iec958: iec958 data
96 * @ctrl_lock: control lock
97 * @irq_lock: prevent race condition with IRQ
98 */
99struct stm32_sai_sub_data {
100 struct platform_device *pdev;
101 struct regmap *regmap;
102 const struct regmap_config *regmap_config;
103 struct snd_dmaengine_dai_dma_data dma_params;
104 struct snd_soc_dai_driver cpu_dai_drv;
105 struct snd_soc_dai *cpu_dai;
106 struct snd_pcm_substream *substream;
107 struct stm32_sai_data *pdata;
108 struct device_node *np_sync_provider;
109 struct clk *sai_ck;
110 struct clk *sai_mclk;
111 dma_addr_t phys_addr;
112 unsigned int mclk_rate;
113 unsigned int id;
114 int dir;
115 bool master;
116 bool spdif;
117 int fmt;
118 int sync;
119 int synco;
120 int synci;
121 int fs_length;
122 int slots;
123 int slot_width;
124 int slot_mask;
125 int data_size;
126 unsigned int spdif_frm_cnt;
127 struct snd_aes_iec958 iec958;
128 struct mutex ctrl_lock; /* protect resources accessed by controls */
129 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
130};
131
132enum stm32_sai_fifo_th {
133 STM_SAI_FIFO_TH_EMPTY,
134 STM_SAI_FIFO_TH_QUARTER,
135 STM_SAI_FIFO_TH_HALF,
136 STM_SAI_FIFO_TH_3_QUARTER,
137 STM_SAI_FIFO_TH_FULL,
138};
139
140static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
141{
142 switch (reg) {
143 case STM_SAI_CR1_REGX:
144 case STM_SAI_CR2_REGX:
145 case STM_SAI_FRCR_REGX:
146 case STM_SAI_SLOTR_REGX:
147 case STM_SAI_IMR_REGX:
148 case STM_SAI_SR_REGX:
149 case STM_SAI_CLRFR_REGX:
150 case STM_SAI_DR_REGX:
151 case STM_SAI_PDMCR_REGX:
152 case STM_SAI_PDMLY_REGX:
153 return true;
154 default:
155 return false;
156 }
157}
158
159static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
160{
161 switch (reg) {
162 case STM_SAI_DR_REGX:
163 case STM_SAI_SR_REGX:
164 return true;
165 default:
166 return false;
167 }
168}
169
170static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
171{
172 switch (reg) {
173 case STM_SAI_CR1_REGX:
174 case STM_SAI_CR2_REGX:
175 case STM_SAI_FRCR_REGX:
176 case STM_SAI_SLOTR_REGX:
177 case STM_SAI_IMR_REGX:
178 case STM_SAI_CLRFR_REGX:
179 case STM_SAI_DR_REGX:
180 case STM_SAI_PDMCR_REGX:
181 case STM_SAI_PDMLY_REGX:
182 return true;
183 default:
184 return false;
185 }
186}
187
188static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai,
189 unsigned int reg, unsigned int mask,
190 unsigned int val)
191{
192 int ret;
193
194 ret = clk_enable(sai->pdata->pclk);
195 if (ret < 0)
196 return ret;
197
198 ret = regmap_update_bits(sai->regmap, reg, mask, val);
199
200 clk_disable(sai->pdata->pclk);
201
202 return ret;
203}
204
205static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai,
206 unsigned int reg, unsigned int mask,
207 unsigned int val)
208{
209 int ret;
210
211 ret = clk_enable(sai->pdata->pclk);
212 if (ret < 0)
213 return ret;
214
215 ret = regmap_write_bits(sai->regmap, reg, mask, val);
216
217 clk_disable(sai->pdata->pclk);
218
219 return ret;
220}
221
222static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai,
223 unsigned int reg, unsigned int *val)
224{
225 int ret;
226
227 ret = clk_enable(sai->pdata->pclk);
228 if (ret < 0)
229 return ret;
230
231 ret = regmap_read(sai->regmap, reg, val);
232
233 clk_disable(sai->pdata->pclk);
234
235 return ret;
236}
237
238static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
239 .reg_bits = 32,
240 .reg_stride = 4,
241 .val_bits = 32,
242 .max_register = STM_SAI_DR_REGX,
243 .readable_reg = stm32_sai_sub_readable_reg,
244 .volatile_reg = stm32_sai_sub_volatile_reg,
245 .writeable_reg = stm32_sai_sub_writeable_reg,
246 .fast_io = true,
247 .cache_type = REGCACHE_FLAT,
248};
249
250static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
251 .reg_bits = 32,
252 .reg_stride = 4,
253 .val_bits = 32,
254 .max_register = STM_SAI_PDMLY_REGX,
255 .readable_reg = stm32_sai_sub_readable_reg,
256 .volatile_reg = stm32_sai_sub_volatile_reg,
257 .writeable_reg = stm32_sai_sub_writeable_reg,
258 .fast_io = true,
259 .cache_type = REGCACHE_FLAT,
260};
261
262static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
263 struct snd_ctl_elem_info *uinfo)
264{
265 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
266 uinfo->count = 1;
267
268 return 0;
269}
270
271static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
272 struct snd_ctl_elem_value *uctl)
273{
274 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
275
276 mutex_lock(&sai->ctrl_lock);
277 memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
278 mutex_unlock(&sai->ctrl_lock);
279
280 return 0;
281}
282
283static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
284 struct snd_ctl_elem_value *uctl)
285{
286 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
287
288 mutex_lock(&sai->ctrl_lock);
289 memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
290 mutex_unlock(&sai->ctrl_lock);
291
292 return 0;
293}
294
295static const struct snd_kcontrol_new iec958_ctls = {
296 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
297 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
298 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
299 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
300 .info = snd_pcm_iec958_info,
301 .get = snd_pcm_iec958_get,
302 .put = snd_pcm_iec958_put,
303};
304
305struct stm32_sai_mclk_data {
306 struct clk_hw hw;
307 unsigned long freq;
308 struct stm32_sai_sub_data *sai_data;
309};
310
311#define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
312#define STM32_SAI_MAX_CLKS 1
313
314static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
315 unsigned long input_rate,
316 unsigned long output_rate)
317{
318 int version = sai->pdata->conf.version;
319 int div;
320
321 div = DIV_ROUND_CLOSEST(input_rate, output_rate);
322 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
323 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
324 return -EINVAL;
325 }
326 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
327
328 if (input_rate % div)
329 dev_dbg(&sai->pdev->dev,
330 "Rate not accurate. requested (%ld), actual (%ld)\n",
331 output_rate, input_rate / div);
332
333 return div;
334}
335
336static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
337 unsigned int div)
338{
339 int version = sai->pdata->conf.version;
340 int ret, cr1, mask;
341
342 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
343 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
344 return -EINVAL;
345 }
346
347 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
348 cr1 = SAI_XCR1_MCKDIV_SET(div);
349 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);
350 if (ret < 0)
351 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
352
353 return ret;
354}
355
356static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
357 unsigned int rate)
358{
359 struct platform_device *pdev = sai->pdev;
360 struct clk *parent_clk = sai->pdata->clk_x8k;
361 int ret;
362
363 if (!(rate % SAI_RATE_11K))
364 parent_clk = sai->pdata->clk_x11k;
365
366 ret = clk_set_parent(sai->sai_ck, parent_clk);
367 if (ret)
368 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
369 ret, ret == -EBUSY ?
370 "Active stream rates conflict\n" : "\n");
371
372 return ret;
373}
374
375static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
376 unsigned long *prate)
377{
378 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
379 struct stm32_sai_sub_data *sai = mclk->sai_data;
380 int div;
381
382 div = stm32_sai_get_clk_div(sai, *prate, rate);
383 if (div < 0)
384 return div;
385
386 mclk->freq = *prate / div;
387
388 return mclk->freq;
389}
390
391static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
392 unsigned long parent_rate)
393{
394 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
395
396 return mclk->freq;
397}
398
399static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
400 unsigned long parent_rate)
401{
402 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
403 struct stm32_sai_sub_data *sai = mclk->sai_data;
404 int div, ret;
405
406 div = stm32_sai_get_clk_div(sai, parent_rate, rate);
407 if (div < 0)
408 return div;
409
410 ret = stm32_sai_set_clk_div(sai, div);
411 if (ret)
412 return ret;
413
414 mclk->freq = rate;
415
416 return 0;
417}
418
419static int stm32_sai_mclk_enable(struct clk_hw *hw)
420{
421 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
422 struct stm32_sai_sub_data *sai = mclk->sai_data;
423
424 dev_dbg(&sai->pdev->dev, "Enable master clock\n");
425
426 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
427 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
428}
429
430static void stm32_sai_mclk_disable(struct clk_hw *hw)
431{
432 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
433 struct stm32_sai_sub_data *sai = mclk->sai_data;
434
435 dev_dbg(&sai->pdev->dev, "Disable master clock\n");
436
437 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
438}
439
440static const struct clk_ops mclk_ops = {
441 .enable = stm32_sai_mclk_enable,
442 .disable = stm32_sai_mclk_disable,
443 .recalc_rate = stm32_sai_mclk_recalc_rate,
444 .round_rate = stm32_sai_mclk_round_rate,
445 .set_rate = stm32_sai_mclk_set_rate,
446};
447
448static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
449{
450 struct clk_hw *hw;
451 struct stm32_sai_mclk_data *mclk;
452 struct device *dev = &sai->pdev->dev;
453 const char *pname = __clk_get_name(sai->sai_ck);
454 char *mclk_name, *p, *s = (char *)pname;
455 int ret, i = 0;
456
457 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
458 if (!mclk)
459 return -ENOMEM;
460
461 mclk_name = devm_kcalloc(dev, sizeof(char),
462 SAI_MCLK_NAME_LEN, GFP_KERNEL);
463 if (!mclk_name)
464 return -ENOMEM;
465
466 /*
467 * Forge mclk clock name from parent clock name and suffix.
468 * String after "_" char is stripped in parent name.
469 */
470 p = mclk_name;
471 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
472 *p++ = *s++;
473 i++;
474 }
475 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
476
477 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
478 mclk->sai_data = sai;
479 hw = &mclk->hw;
480
481 dev_dbg(dev, "Register master clock %s\n", mclk_name);
482 ret = devm_clk_hw_register(&sai->pdev->dev, hw);
483 if (ret) {
484 dev_err(dev, "mclk register returned %d\n", ret);
485 return ret;
486 }
487 sai->sai_mclk = hw->clk;
488
489 /* register mclk provider */
490 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
491}
492
493static irqreturn_t stm32_sai_isr(int irq, void *devid)
494{
495 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
496 struct platform_device *pdev = sai->pdev;
497 unsigned int sr, imr, flags;
498 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
499
500 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr);
501 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr);
502
503 flags = sr & imr;
504 if (!flags)
505 return IRQ_NONE;
506
507 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
508 SAI_XCLRFR_MASK);
509
510 if (!sai->substream) {
511 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
512 return IRQ_NONE;
513 }
514
515 if (flags & SAI_XIMR_OVRUDRIE) {
516 dev_err(&pdev->dev, "IRQ %s\n",
517 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
518 status = SNDRV_PCM_STATE_XRUN;
519 }
520
521 if (flags & SAI_XIMR_MUTEDETIE)
522 dev_dbg(&pdev->dev, "IRQ mute detected\n");
523
524 if (flags & SAI_XIMR_WCKCFGIE) {
525 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
526 status = SNDRV_PCM_STATE_DISCONNECTED;
527 }
528
529 if (flags & SAI_XIMR_CNRDYIE)
530 dev_err(&pdev->dev, "IRQ Codec not ready\n");
531
532 if (flags & SAI_XIMR_AFSDETIE) {
533 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
534 status = SNDRV_PCM_STATE_XRUN;
535 }
536
537 if (flags & SAI_XIMR_LFSDETIE) {
538 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
539 status = SNDRV_PCM_STATE_XRUN;
540 }
541
542 spin_lock(&sai->irq_lock);
543 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
544 snd_pcm_stop_xrun(sai->substream);
545 spin_unlock(&sai->irq_lock);
546
547 return IRQ_HANDLED;
548}
549
550static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
551 int clk_id, unsigned int freq, int dir)
552{
553 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
554 int ret;
555
556 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
557 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
558 SAI_XCR1_NODIV,
559 freq ? 0 : SAI_XCR1_NODIV);
560 if (ret < 0)
561 return ret;
562
563 /* Assume shutdown if requested frequency is 0Hz */
564 if (!freq) {
565 /* Release mclk rate only if rate was actually set */
566 if (sai->mclk_rate) {
567 clk_rate_exclusive_put(sai->sai_mclk);
568 sai->mclk_rate = 0;
569 }
570 return 0;
571 }
572
573 /* If master clock is used, set parent clock now */
574 ret = stm32_sai_set_parent_clock(sai, freq);
575 if (ret)
576 return ret;
577
578 ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
579 if (ret) {
580 dev_err(cpu_dai->dev,
581 ret == -EBUSY ?
582 "Active streams have incompatible rates" :
583 "Could not set mclk rate\n");
584 return ret;
585 }
586
587 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
588 sai->mclk_rate = freq;
589 }
590
591 return 0;
592}
593
594static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
595 u32 rx_mask, int slots, int slot_width)
596{
597 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
598 int slotr, slotr_mask, slot_size;
599
600 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
601 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
602 return 0;
603 }
604
605 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
606 tx_mask, rx_mask, slots, slot_width);
607
608 switch (slot_width) {
609 case 16:
610 slot_size = SAI_SLOT_SIZE_16;
611 break;
612 case 32:
613 slot_size = SAI_SLOT_SIZE_32;
614 break;
615 default:
616 slot_size = SAI_SLOT_SIZE_AUTO;
617 break;
618 }
619
620 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
621 SAI_XSLOTR_NBSLOT_SET(slots - 1);
622 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
623
624 /* tx/rx mask set in machine init, if slot number defined in DT */
625 if (STM_SAI_IS_PLAYBACK(sai)) {
626 sai->slot_mask = tx_mask;
627 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
628 }
629
630 if (STM_SAI_IS_CAPTURE(sai)) {
631 sai->slot_mask = rx_mask;
632 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
633 }
634
635 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
636
637 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
638
639 sai->slot_width = slot_width;
640 sai->slots = slots;
641
642 return 0;
643}
644
645static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
646{
647 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
648 int cr1, frcr = 0;
649 int cr1_mask, frcr_mask = 0;
650 int ret;
651
652 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
653
654 /* Do not generate master by default */
655 cr1 = SAI_XCR1_NODIV;
656 cr1_mask = SAI_XCR1_NODIV;
657
658 cr1_mask |= SAI_XCR1_PRTCFG_MASK;
659 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
660 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
661 goto conf_update;
662 }
663
664 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
665
666 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
667 /* SCK active high for all protocols */
668 case SND_SOC_DAIFMT_I2S:
669 cr1 |= SAI_XCR1_CKSTR;
670 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
671 break;
672 /* Left justified */
673 case SND_SOC_DAIFMT_MSB:
674 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
675 break;
676 /* Right justified */
677 case SND_SOC_DAIFMT_LSB:
678 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
679 break;
680 case SND_SOC_DAIFMT_DSP_A:
681 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
682 break;
683 case SND_SOC_DAIFMT_DSP_B:
684 frcr |= SAI_XFRCR_FSPOL;
685 break;
686 default:
687 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
688 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
689 return -EINVAL;
690 }
691
692 cr1_mask |= SAI_XCR1_CKSTR;
693 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
694 SAI_XFRCR_FSDEF;
695
696 /* DAI clock strobing. Invert setting previously set */
697 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
698 case SND_SOC_DAIFMT_NB_NF:
699 break;
700 case SND_SOC_DAIFMT_IB_NF:
701 cr1 ^= SAI_XCR1_CKSTR;
702 break;
703 case SND_SOC_DAIFMT_NB_IF:
704 frcr ^= SAI_XFRCR_FSPOL;
705 break;
706 case SND_SOC_DAIFMT_IB_IF:
707 /* Invert fs & sck */
708 cr1 ^= SAI_XCR1_CKSTR;
709 frcr ^= SAI_XFRCR_FSPOL;
710 break;
711 default:
712 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
713 fmt & SND_SOC_DAIFMT_INV_MASK);
714 return -EINVAL;
715 }
716 cr1_mask |= SAI_XCR1_CKSTR;
717 frcr_mask |= SAI_XFRCR_FSPOL;
718
719 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
720
721 /* DAI clock master masks */
722 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
723 case SND_SOC_DAIFMT_CBM_CFM:
724 /* codec is master */
725 cr1 |= SAI_XCR1_SLAVE;
726 sai->master = false;
727 break;
728 case SND_SOC_DAIFMT_CBS_CFS:
729 sai->master = true;
730 break;
731 default:
732 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
733 fmt & SND_SOC_DAIFMT_MASTER_MASK);
734 return -EINVAL;
735 }
736
737 /* Set slave mode if sub-block is synchronized with another SAI */
738 if (sai->sync) {
739 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
740 cr1 |= SAI_XCR1_SLAVE;
741 sai->master = false;
742 }
743
744 cr1_mask |= SAI_XCR1_SLAVE;
745
746conf_update:
747 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
748 if (ret < 0) {
749 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
750 return ret;
751 }
752
753 sai->fmt = fmt;
754
755 return 0;
756}
757
758static int stm32_sai_startup(struct snd_pcm_substream *substream,
759 struct snd_soc_dai *cpu_dai)
760{
761 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
762 int imr, cr2, ret;
763 unsigned long flags;
764
765 spin_lock_irqsave(&sai->irq_lock, flags);
766 sai->substream = substream;
767 spin_unlock_irqrestore(&sai->irq_lock, flags);
768
769 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
770 snd_pcm_hw_constraint_mask64(substream->runtime,
771 SNDRV_PCM_HW_PARAM_FORMAT,
772 SNDRV_PCM_FMTBIT_S32_LE);
773 snd_pcm_hw_constraint_single(substream->runtime,
774 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
775 }
776
777 ret = clk_prepare_enable(sai->sai_ck);
778 if (ret < 0) {
779 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
780 return ret;
781 }
782
783 /* Enable ITs */
784 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX,
785 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
786
787 imr = SAI_XIMR_OVRUDRIE;
788 if (STM_SAI_IS_CAPTURE(sai)) {
789 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2);
790 if (cr2 & SAI_XCR2_MUTECNT_MASK)
791 imr |= SAI_XIMR_MUTEDETIE;
792 }
793
794 if (sai->master)
795 imr |= SAI_XIMR_WCKCFGIE;
796 else
797 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
798
799 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
800 SAI_XIMR_MASK, imr);
801
802 return 0;
803}
804
805static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
806 struct snd_pcm_substream *substream,
807 struct snd_pcm_hw_params *params)
808{
809 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
810 int cr1, cr1_mask, ret;
811
812 /*
813 * DMA bursts increment is set to 4 words.
814 * SAI fifo threshold is set to half fifo, to keep enough space
815 * for DMA incoming bursts.
816 */
817 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX,
818 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
819 SAI_XCR2_FFLUSH |
820 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
821
822 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
823 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
824 sai->spdif_frm_cnt = 0;
825 return 0;
826 }
827
828 /* Mode, data format and channel config */
829 cr1_mask = SAI_XCR1_DS_MASK;
830 switch (params_format(params)) {
831 case SNDRV_PCM_FORMAT_S8:
832 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
833 break;
834 case SNDRV_PCM_FORMAT_S16_LE:
835 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
836 break;
837 case SNDRV_PCM_FORMAT_S32_LE:
838 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
839 break;
840 default:
841 dev_err(cpu_dai->dev, "Data format not supported\n");
842 return -EINVAL;
843 }
844
845 cr1_mask |= SAI_XCR1_MONO;
846 if ((sai->slots == 2) && (params_channels(params) == 1))
847 cr1 |= SAI_XCR1_MONO;
848
849 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
850 if (ret < 0) {
851 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
852 return ret;
853 }
854
855 return 0;
856}
857
858static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
859{
860 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
861 int slotr, slot_sz;
862
863 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr);
864
865 /*
866 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
867 * By default slot width = data size, if not forced from DT
868 */
869 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
870 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
871 sai->slot_width = sai->data_size;
872
873 if (sai->slot_width < sai->data_size) {
874 dev_err(cpu_dai->dev,
875 "Data size %d larger than slot width\n",
876 sai->data_size);
877 return -EINVAL;
878 }
879
880 /* Slot number is set to 2, if not specified in DT */
881 if (!sai->slots)
882 sai->slots = 2;
883
884 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
885 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
886 SAI_XSLOTR_NBSLOT_MASK,
887 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
888
889 /* Set default slots mask if not already set from DT */
890 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
891 sai->slot_mask = (1 << sai->slots) - 1;
892 stm32_sai_sub_reg_up(sai,
893 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
894 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
895 }
896
897 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
898 sai->slots, sai->slot_width);
899
900 return 0;
901}
902
903static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
904{
905 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
906 int fs_active, offset, format;
907 int frcr, frcr_mask;
908
909 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
910 sai->fs_length = sai->slot_width * sai->slots;
911
912 fs_active = sai->fs_length / 2;
913 if ((format == SND_SOC_DAIFMT_DSP_A) ||
914 (format == SND_SOC_DAIFMT_DSP_B))
915 fs_active = 1;
916
917 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
918 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
919 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
920
921 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
922 sai->fs_length, fs_active);
923
924 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
925
926 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
927 offset = sai->slot_width - sai->data_size;
928
929 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
930 SAI_XSLOTR_FBOFF_MASK,
931 SAI_XSLOTR_FBOFF_SET(offset));
932 }
933}
934
935static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
936{
937 unsigned char *cs = sai->iec958.status;
938
939 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
940 cs[1] = IEC958_AES1_CON_GENERAL;
941 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
942 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
943}
944
945static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
946 struct snd_pcm_runtime *runtime)
947{
948 if (!runtime)
949 return;
950
951 /* Force the sample rate according to runtime rate */
952 mutex_lock(&sai->ctrl_lock);
953 switch (runtime->rate) {
954 case 22050:
955 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
956 break;
957 case 44100:
958 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
959 break;
960 case 88200:
961 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
962 break;
963 case 176400:
964 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
965 break;
966 case 24000:
967 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
968 break;
969 case 48000:
970 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
971 break;
972 case 96000:
973 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
974 break;
975 case 192000:
976 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
977 break;
978 case 32000:
979 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
980 break;
981 default:
982 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
983 break;
984 }
985 mutex_unlock(&sai->ctrl_lock);
986}
987
988static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
989 struct snd_pcm_hw_params *params)
990{
991 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
992 int div = 0, cr1 = 0;
993 int sai_clk_rate, mclk_ratio, den;
994 unsigned int rate = params_rate(params);
995 int ret;
996
997 if (!sai->sai_mclk) {
998 ret = stm32_sai_set_parent_clock(sai, rate);
999 if (ret)
1000 return ret;
1001 }
1002 sai_clk_rate = clk_get_rate(sai->sai_ck);
1003
1004 if (STM_SAI_IS_F4(sai->pdata)) {
1005 /* mclk on (NODIV=0)
1006 * mclk_rate = 256 * fs
1007 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
1008 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
1009 * mclk off (NODIV=1)
1010 * MCKDIV ignored. sck = sai_ck
1011 */
1012 if (!sai->mclk_rate)
1013 return 0;
1014
1015 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
1016 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1017 2 * sai->mclk_rate);
1018 if (div < 0)
1019 return div;
1020 }
1021 } else {
1022 /*
1023 * TDM mode :
1024 * mclk on
1025 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
1026 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
1027 * mclk off
1028 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
1029 * Note: NOMCK/NODIV correspond to same bit.
1030 */
1031 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1032 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1033 rate * 128);
1034 if (div < 0)
1035 return div;
1036 } else {
1037 if (sai->mclk_rate) {
1038 mclk_ratio = sai->mclk_rate / rate;
1039 if (mclk_ratio == 512) {
1040 cr1 = SAI_XCR1_OSR;
1041 } else if (mclk_ratio != 256) {
1042 dev_err(cpu_dai->dev,
1043 "Wrong mclk ratio %d\n",
1044 mclk_ratio);
1045 return -EINVAL;
1046 }
1047
1048 stm32_sai_sub_reg_up(sai,
1049 STM_SAI_CR1_REGX,
1050 SAI_XCR1_OSR, cr1);
1051
1052 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1053 sai->mclk_rate);
1054 if (div < 0)
1055 return div;
1056 } else {
1057 /* mclk-fs not set, master clock not active */
1058 den = sai->fs_length * params_rate(params);
1059 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1060 den);
1061 if (div < 0)
1062 return div;
1063 }
1064 }
1065 }
1066
1067 return stm32_sai_set_clk_div(sai, div);
1068}
1069
1070static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
1071 struct snd_pcm_hw_params *params,
1072 struct snd_soc_dai *cpu_dai)
1073{
1074 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1075 int ret;
1076
1077 sai->data_size = params_width(params);
1078
1079 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1080 /* Rate not already set in runtime structure */
1081 substream->runtime->rate = params_rate(params);
1082 stm32_sai_set_iec958_status(sai, substream->runtime);
1083 } else {
1084 ret = stm32_sai_set_slots(cpu_dai);
1085 if (ret < 0)
1086 return ret;
1087 stm32_sai_set_frame(cpu_dai);
1088 }
1089
1090 ret = stm32_sai_set_config(cpu_dai, substream, params);
1091 if (ret)
1092 return ret;
1093
1094 if (sai->master)
1095 ret = stm32_sai_configure_clock(cpu_dai, params);
1096
1097 return ret;
1098}
1099
1100static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1101 struct snd_soc_dai *cpu_dai)
1102{
1103 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1104 int ret;
1105
1106 switch (cmd) {
1107 case SNDRV_PCM_TRIGGER_START:
1108 case SNDRV_PCM_TRIGGER_RESUME:
1109 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1110 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1111
1112 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1113 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1114
1115 /* Enable SAI */
1116 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1117 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1118 if (ret < 0)
1119 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1120 break;
1121 case SNDRV_PCM_TRIGGER_SUSPEND:
1122 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1123 case SNDRV_PCM_TRIGGER_STOP:
1124 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1125
1126 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
1127 SAI_XIMR_MASK, 0);
1128
1129 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1130 SAI_XCR1_SAIEN,
1131 (unsigned int)~SAI_XCR1_SAIEN);
1132
1133 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
1134 SAI_XCR1_DMAEN,
1135 (unsigned int)~SAI_XCR1_DMAEN);
1136 if (ret < 0)
1137 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1138
1139 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1140 sai->spdif_frm_cnt = 0;
1141 break;
1142 default:
1143 return -EINVAL;
1144 }
1145
1146 return ret;
1147}
1148
1149static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1150 struct snd_soc_dai *cpu_dai)
1151{
1152 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1153 unsigned long flags;
1154
1155 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1156
1157 clk_disable_unprepare(sai->sai_ck);
1158
1159 spin_lock_irqsave(&sai->irq_lock, flags);
1160 sai->substream = NULL;
1161 spin_unlock_irqrestore(&sai->irq_lock, flags);
1162}
1163
1164static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1165 struct snd_soc_dai *cpu_dai)
1166{
1167 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1168 struct snd_kcontrol_new knew = iec958_ctls;
1169
1170 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1171 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
1172 knew.device = rtd->pcm->device;
1173 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
1174 }
1175
1176 return 0;
1177}
1178
1179static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1180{
1181 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1182 int cr1 = 0, cr1_mask, ret;
1183
1184 sai->cpu_dai = cpu_dai;
1185
1186 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1187 /*
1188 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1189 * as it allows bytes, half-word and words transfers. (See DMA fifos
1190 * constraints).
1191 */
1192 sai->dma_params.maxburst = 4;
1193 if (sai->pdata->conf.fifo_size < 8)
1194 sai->dma_params.maxburst = 1;
1195 /* Buswidth will be set by framework at runtime */
1196 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1197
1198 if (STM_SAI_IS_PLAYBACK(sai))
1199 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1200 else
1201 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1202
1203 /* Next settings are not relevant for spdif mode */
1204 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1205 return 0;
1206
1207 cr1_mask = SAI_XCR1_RX_TX;
1208 if (STM_SAI_IS_CAPTURE(sai))
1209 cr1 |= SAI_XCR1_RX_TX;
1210
1211 /* Configure synchronization */
1212 if (sai->sync == SAI_SYNC_EXTERNAL) {
1213 /* Configure synchro client and provider */
1214 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
1215 sai->synco, sai->synci);
1216 if (ret)
1217 return ret;
1218 }
1219
1220 cr1_mask |= SAI_XCR1_SYNCEN_MASK;
1221 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
1222
1223 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
1224}
1225
1226static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1227 .set_sysclk = stm32_sai_set_sysclk,
1228 .set_fmt = stm32_sai_set_dai_fmt,
1229 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1230 .startup = stm32_sai_startup,
1231 .hw_params = stm32_sai_hw_params,
1232 .trigger = stm32_sai_trigger,
1233 .shutdown = stm32_sai_shutdown,
1234};
1235
1236static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
1237 int channel, unsigned long hwoff,
1238 void *buf, unsigned long bytes)
1239{
1240 struct snd_pcm_runtime *runtime = substream->runtime;
1241 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1242 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
1243 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1244 int *ptr = (int *)(runtime->dma_area + hwoff +
1245 channel * (runtime->dma_bytes / runtime->channels));
1246 ssize_t cnt = bytes_to_samples(runtime, bytes);
1247 unsigned int frm_cnt = sai->spdif_frm_cnt;
1248 unsigned int byte;
1249 unsigned int mask;
1250
1251 do {
1252 *ptr = ((*ptr >> 8) & 0x00ffffff);
1253
1254 /* Set channel status bit */
1255 byte = frm_cnt >> 3;
1256 mask = 1 << (frm_cnt - (byte << 3));
1257 if (sai->iec958.status[byte] & mask)
1258 *ptr |= 0x04000000;
1259 ptr++;
1260
1261 if (!(cnt % 2))
1262 frm_cnt++;
1263
1264 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
1265 frm_cnt = 0;
1266 } while (--cnt);
1267 sai->spdif_frm_cnt = frm_cnt;
1268
1269 return 0;
1270}
1271
1272/* No support of mmap in S/PDIF mode */
1273static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
1274 .info = SNDRV_PCM_INFO_INTERLEAVED,
1275 .buffer_bytes_max = 8 * PAGE_SIZE,
1276 .period_bytes_min = 1024,
1277 .period_bytes_max = PAGE_SIZE,
1278 .periods_min = 2,
1279 .periods_max = 8,
1280};
1281
1282static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1283 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1284 .buffer_bytes_max = 8 * PAGE_SIZE,
1285 .period_bytes_min = 1024, /* 5ms at 48kHz */
1286 .period_bytes_max = PAGE_SIZE,
1287 .periods_min = 2,
1288 .periods_max = 8,
1289};
1290
1291static struct snd_soc_dai_driver stm32_sai_playback_dai = {
1292 .probe = stm32_sai_dai_probe,
1293 .pcm_new = stm32_sai_pcm_new,
1294 .id = 1, /* avoid call to fmt_single_name() */
1295 .playback = {
1296 .channels_min = 1,
1297 .channels_max = 2,
1298 .rate_min = 8000,
1299 .rate_max = 192000,
1300 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1301 /* DMA does not support 24 bits transfers */
1302 .formats =
1303 SNDRV_PCM_FMTBIT_S8 |
1304 SNDRV_PCM_FMTBIT_S16_LE |
1305 SNDRV_PCM_FMTBIT_S32_LE,
1306 },
1307 .ops = &stm32_sai_pcm_dai_ops,
1308};
1309
1310static struct snd_soc_dai_driver stm32_sai_capture_dai = {
1311 .probe = stm32_sai_dai_probe,
1312 .id = 1, /* avoid call to fmt_single_name() */
1313 .capture = {
1314 .channels_min = 1,
1315 .channels_max = 2,
1316 .rate_min = 8000,
1317 .rate_max = 192000,
1318 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1319 /* DMA does not support 24 bits transfers */
1320 .formats =
1321 SNDRV_PCM_FMTBIT_S8 |
1322 SNDRV_PCM_FMTBIT_S16_LE |
1323 SNDRV_PCM_FMTBIT_S32_LE,
1324 },
1325 .ops = &stm32_sai_pcm_dai_ops,
1326};
1327
1328static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1329 .pcm_hardware = &stm32_sai_pcm_hw,
1330 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1331};
1332
1333static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1334 .pcm_hardware = &stm32_sai_pcm_hw_spdif,
1335 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1336 .process = stm32_sai_pcm_process_spdif,
1337};
1338
1339static const struct snd_soc_component_driver stm32_component = {
1340 .name = "stm32-sai",
1341};
1342
1343static const struct of_device_id stm32_sai_sub_ids[] = {
1344 { .compatible = "st,stm32-sai-sub-a",
1345 .data = (void *)STM_SAI_A_ID},
1346 { .compatible = "st,stm32-sai-sub-b",
1347 .data = (void *)STM_SAI_B_ID},
1348 {}
1349};
1350MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1351
1352static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1353 struct stm32_sai_sub_data *sai)
1354{
1355 struct device_node *np = pdev->dev.of_node;
1356 struct resource *res;
1357 void __iomem *base;
1358 struct of_phandle_args args;
1359 int ret;
1360
1361 if (!np)
1362 return -ENODEV;
1363
1364 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1365 if (IS_ERR(base))
1366 return PTR_ERR(base);
1367
1368 sai->phys_addr = res->start;
1369
1370 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1371 /* Note: PDM registers not available for sub-block B */
1372 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
1373 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1374
1375 /*
1376 * Do not manage peripheral clock through regmap framework as this
1377 * can lead to circular locking issue with sai master clock provider.
1378 * Manage peripheral clock directly in driver instead.
1379 */
1380 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1381 sai->regmap_config);
1382 if (IS_ERR(sai->regmap)) {
1383 if (PTR_ERR(sai->regmap) != -EPROBE_DEFER)
1384 dev_err(&pdev->dev, "Regmap init error %ld\n",
1385 PTR_ERR(sai->regmap));
1386 return PTR_ERR(sai->regmap);
1387 }
1388
1389 /* Get direction property */
1390 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1391 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1392 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1393 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1394 } else {
1395 dev_err(&pdev->dev, "Unsupported direction\n");
1396 return -EINVAL;
1397 }
1398
1399 /* Get spdif iec60958 property */
1400 sai->spdif = false;
1401 if (of_get_property(np, "st,iec60958", NULL)) {
1402 if (!STM_SAI_HAS_SPDIF(sai) ||
1403 sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1404 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1405 return -EINVAL;
1406 }
1407 stm32_sai_init_iec958_status(sai);
1408 sai->spdif = true;
1409 sai->master = true;
1410 }
1411
1412 /* Get synchronization property */
1413 args.np = NULL;
1414 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1415 if (ret < 0 && ret != -ENOENT) {
1416 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1417 return ret;
1418 }
1419
1420 sai->sync = SAI_SYNC_NONE;
1421 if (args.np) {
1422 if (args.np == np) {
1423 dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
1424 of_node_put(args.np);
1425 return -EINVAL;
1426 }
1427
1428 sai->np_sync_provider = of_get_parent(args.np);
1429 if (!sai->np_sync_provider) {
1430 dev_err(&pdev->dev, "%pOFn parent node not found\n",
1431 np);
1432 of_node_put(args.np);
1433 return -ENODEV;
1434 }
1435
1436 sai->sync = SAI_SYNC_INTERNAL;
1437 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1438 if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1439 dev_err(&pdev->dev,
1440 "External synchro not supported\n");
1441 of_node_put(args.np);
1442 return -EINVAL;
1443 }
1444 sai->sync = SAI_SYNC_EXTERNAL;
1445
1446 sai->synci = args.args[0];
1447 if (sai->synci < 1 ||
1448 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1449 dev_err(&pdev->dev, "Wrong SAI index\n");
1450 of_node_put(args.np);
1451 return -EINVAL;
1452 }
1453
1454 if (of_property_match_string(args.np, "compatible",
1455 "st,stm32-sai-sub-a") >= 0)
1456 sai->synco = STM_SAI_SYNC_OUT_A;
1457
1458 if (of_property_match_string(args.np, "compatible",
1459 "st,stm32-sai-sub-b") >= 0)
1460 sai->synco = STM_SAI_SYNC_OUT_B;
1461
1462 if (!sai->synco) {
1463 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1464 of_node_put(args.np);
1465 return -EINVAL;
1466 }
1467 }
1468
1469 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1470 pdev->name, args.np->full_name);
1471 }
1472
1473 of_node_put(args.np);
1474 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1475 if (IS_ERR(sai->sai_ck)) {
1476 if (PTR_ERR(sai->sai_ck) != -EPROBE_DEFER)
1477 dev_err(&pdev->dev, "Missing kernel clock sai_ck: %ld\n",
1478 PTR_ERR(sai->sai_ck));
1479 return PTR_ERR(sai->sai_ck);
1480 }
1481
1482 ret = clk_prepare(sai->pdata->pclk);
1483 if (ret < 0)
1484 return ret;
1485
1486 if (STM_SAI_IS_F4(sai->pdata))
1487 return 0;
1488
1489 /* Register mclk provider if requested */
1490 if (of_find_property(np, "#clock-cells", NULL)) {
1491 ret = stm32_sai_add_mclk_provider(sai);
1492 if (ret < 0)
1493 return ret;
1494 } else {
1495 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK");
1496 if (IS_ERR(sai->sai_mclk)) {
1497 if (PTR_ERR(sai->sai_mclk) != -ENOENT)
1498 return PTR_ERR(sai->sai_mclk);
1499 sai->sai_mclk = NULL;
1500 }
1501 }
1502
1503 return 0;
1504}
1505
1506static int stm32_sai_sub_probe(struct platform_device *pdev)
1507{
1508 struct stm32_sai_sub_data *sai;
1509 const struct of_device_id *of_id;
1510 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1511 int ret;
1512
1513 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1514 if (!sai)
1515 return -ENOMEM;
1516
1517 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
1518 if (!of_id)
1519 return -EINVAL;
1520 sai->id = (uintptr_t)of_id->data;
1521
1522 sai->pdev = pdev;
1523 mutex_init(&sai->ctrl_lock);
1524 spin_lock_init(&sai->irq_lock);
1525 platform_set_drvdata(pdev, sai);
1526
1527 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1528 if (!sai->pdata) {
1529 dev_err(&pdev->dev, "Parent device data not available\n");
1530 return -EINVAL;
1531 }
1532
1533 ret = stm32_sai_sub_parse_of(pdev, sai);
1534 if (ret)
1535 return ret;
1536
1537 if (STM_SAI_IS_PLAYBACK(sai))
1538 sai->cpu_dai_drv = stm32_sai_playback_dai;
1539 else
1540 sai->cpu_dai_drv = stm32_sai_capture_dai;
1541 sai->cpu_dai_drv.name = dev_name(&pdev->dev);
1542
1543 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1544 IRQF_SHARED, dev_name(&pdev->dev), sai);
1545 if (ret) {
1546 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1547 return ret;
1548 }
1549
1550 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1551 conf = &stm32_sai_pcm_config_spdif;
1552
1553 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1554 if (ret) {
1555 if (ret != -EPROBE_DEFER)
1556 dev_err(&pdev->dev, "Could not register pcm dma\n");
1557 return ret;
1558 }
1559
1560 ret = snd_soc_register_component(&pdev->dev, &stm32_component,
1561 &sai->cpu_dai_drv, 1);
1562 if (ret) {
1563 snd_dmaengine_pcm_unregister(&pdev->dev);
1564 return ret;
1565 }
1566
1567 pm_runtime_enable(&pdev->dev);
1568
1569 return 0;
1570}
1571
1572static int stm32_sai_sub_remove(struct platform_device *pdev)
1573{
1574 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
1575
1576 clk_unprepare(sai->pdata->pclk);
1577 snd_dmaengine_pcm_unregister(&pdev->dev);
1578 snd_soc_unregister_component(&pdev->dev);
1579 pm_runtime_disable(&pdev->dev);
1580
1581 return 0;
1582}
1583
1584#ifdef CONFIG_PM_SLEEP
1585static int stm32_sai_sub_suspend(struct device *dev)
1586{
1587 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1588 int ret;
1589
1590 ret = clk_enable(sai->pdata->pclk);
1591 if (ret < 0)
1592 return ret;
1593
1594 regcache_cache_only(sai->regmap, true);
1595 regcache_mark_dirty(sai->regmap);
1596
1597 clk_disable(sai->pdata->pclk);
1598
1599 return 0;
1600}
1601
1602static int stm32_sai_sub_resume(struct device *dev)
1603{
1604 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1605 int ret;
1606
1607 ret = clk_enable(sai->pdata->pclk);
1608 if (ret < 0)
1609 return ret;
1610
1611 regcache_cache_only(sai->regmap, false);
1612 ret = regcache_sync(sai->regmap);
1613
1614 clk_disable(sai->pdata->pclk);
1615
1616 return ret;
1617}
1618#endif /* CONFIG_PM_SLEEP */
1619
1620static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
1621 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
1622};
1623
1624static struct platform_driver stm32_sai_sub_driver = {
1625 .driver = {
1626 .name = "st,stm32-sai-sub",
1627 .of_match_table = stm32_sai_sub_ids,
1628 .pm = &stm32_sai_sub_pm_ops,
1629 },
1630 .probe = stm32_sai_sub_probe,
1631 .remove = stm32_sai_sub_remove,
1632};
1633
1634module_platform_driver(stm32_sai_sub_driver);
1635
1636MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1637MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1638MODULE_ALIAS("platform:st,stm32-sai-sub");
1639MODULE_LICENSE("GPL v2");