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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2// Copyright 2018 NXP
3
4#include <linux/bitfield.h>
5#include <linux/clk.h>
6#include <linux/device.h>
7#include <linux/interrupt.h>
8#include <linux/kobject.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/sysfs.h>
18#include <linux/types.h>
19#include <linux/dma/imx-dma.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm.h>
22#include <sound/soc.h>
23#include <sound/tlv.h>
24#include <sound/core.h>
25
26#include "fsl_micfil.h"
27#include "fsl_utils.h"
28
29#define MICFIL_OSR_DEFAULT 16
30
31#define MICFIL_NUM_RATES 7
32#define MICFIL_CLK_SRC_NUM 3
33/* clock source ids */
34#define MICFIL_AUDIO_PLL1 0
35#define MICFIL_AUDIO_PLL2 1
36#define MICFIL_CLK_EXT3 2
37
38enum quality {
39 QUALITY_HIGH,
40 QUALITY_MEDIUM,
41 QUALITY_LOW,
42 QUALITY_VLOW0,
43 QUALITY_VLOW1,
44 QUALITY_VLOW2,
45};
46
47struct fsl_micfil {
48 struct platform_device *pdev;
49 struct regmap *regmap;
50 const struct fsl_micfil_soc_data *soc;
51 struct clk *busclk;
52 struct clk *mclk;
53 struct clk *pll8k_clk;
54 struct clk *pll11k_clk;
55 struct clk *clk_src[MICFIL_CLK_SRC_NUM];
56 struct snd_dmaengine_dai_dma_data dma_params_rx;
57 struct sdma_peripheral_config sdmacfg;
58 struct snd_soc_card *card;
59 struct snd_pcm_hw_constraint_list constraint_rates;
60 unsigned int constraint_rates_list[MICFIL_NUM_RATES];
61 unsigned int dataline;
62 char name[32];
63 int irq[MICFIL_IRQ_LINES];
64 enum quality quality;
65 int dc_remover;
66 int vad_init_mode;
67 int vad_enabled;
68 int vad_detected;
69 struct fsl_micfil_verid verid;
70 struct fsl_micfil_param param;
71 bool mclk_flag; /* mclk enable flag */
72};
73
74struct fsl_micfil_soc_data {
75 unsigned int fifos;
76 unsigned int fifo_depth;
77 unsigned int dataline;
78 bool imx;
79 bool use_edma;
80 bool use_verid;
81 bool volume_sx;
82 u64 formats;
83};
84
85static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
86 .imx = true,
87 .fifos = 8,
88 .fifo_depth = 8,
89 .dataline = 0xf,
90 .formats = SNDRV_PCM_FMTBIT_S16_LE,
91 .volume_sx = true,
92};
93
94static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
95 .imx = true,
96 .fifos = 8,
97 .fifo_depth = 32,
98 .dataline = 0xf,
99 .formats = SNDRV_PCM_FMTBIT_S32_LE,
100 .volume_sx = false,
101};
102
103static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
104 .imx = true,
105 .fifos = 8,
106 .fifo_depth = 32,
107 .dataline = 0xf,
108 .formats = SNDRV_PCM_FMTBIT_S32_LE,
109 .use_edma = true,
110 .use_verid = true,
111 .volume_sx = false,
112};
113
114static const struct of_device_id fsl_micfil_dt_ids[] = {
115 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
116 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
117 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
118 {}
119};
120MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
121
122static const char * const micfil_quality_select_texts[] = {
123 [QUALITY_HIGH] = "High",
124 [QUALITY_MEDIUM] = "Medium",
125 [QUALITY_LOW] = "Low",
126 [QUALITY_VLOW0] = "VLow0",
127 [QUALITY_VLOW1] = "Vlow1",
128 [QUALITY_VLOW2] = "Vlow2",
129};
130
131static const struct soc_enum fsl_micfil_quality_enum =
132 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
133 micfil_quality_select_texts);
134
135static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
136
137static int micfil_set_quality(struct fsl_micfil *micfil)
138{
139 u32 qsel;
140
141 switch (micfil->quality) {
142 case QUALITY_HIGH:
143 qsel = MICFIL_QSEL_HIGH_QUALITY;
144 break;
145 case QUALITY_MEDIUM:
146 qsel = MICFIL_QSEL_MEDIUM_QUALITY;
147 break;
148 case QUALITY_LOW:
149 qsel = MICFIL_QSEL_LOW_QUALITY;
150 break;
151 case QUALITY_VLOW0:
152 qsel = MICFIL_QSEL_VLOW0_QUALITY;
153 break;
154 case QUALITY_VLOW1:
155 qsel = MICFIL_QSEL_VLOW1_QUALITY;
156 break;
157 case QUALITY_VLOW2:
158 qsel = MICFIL_QSEL_VLOW2_QUALITY;
159 break;
160 default:
161 return -EINVAL;
162 }
163
164 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
165 MICFIL_CTRL2_QSEL,
166 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
167}
168
169static int micfil_quality_get(struct snd_kcontrol *kcontrol,
170 struct snd_ctl_elem_value *ucontrol)
171{
172 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
173 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
174
175 ucontrol->value.integer.value[0] = micfil->quality;
176
177 return 0;
178}
179
180static int micfil_quality_set(struct snd_kcontrol *kcontrol,
181 struct snd_ctl_elem_value *ucontrol)
182{
183 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
184 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
185
186 micfil->quality = ucontrol->value.integer.value[0];
187
188 return micfil_set_quality(micfil);
189}
190
191static const char * const micfil_hwvad_enable[] = {
192 "Disable (Record only)",
193 "Enable (Record with Vad)",
194};
195
196static const char * const micfil_hwvad_init_mode[] = {
197 "Envelope mode", "Energy mode",
198};
199
200static const char * const micfil_hwvad_hpf_texts[] = {
201 "Filter bypass",
202 "Cut-off @1750Hz",
203 "Cut-off @215Hz",
204 "Cut-off @102Hz",
205};
206
207/*
208 * DC Remover Control
209 * Filter Bypassed 1 1
210 * Cut-off @21Hz 0 0
211 * Cut-off @83Hz 0 1
212 * Cut-off @152HZ 1 0
213 */
214static const char * const micfil_dc_remover_texts[] = {
215 "Cut-off @21Hz", "Cut-off @83Hz",
216 "Cut-off @152Hz", "Bypass",
217};
218
219static const struct soc_enum hwvad_enable_enum =
220 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
221 micfil_hwvad_enable);
222static const struct soc_enum hwvad_init_mode_enum =
223 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
224 micfil_hwvad_init_mode);
225static const struct soc_enum hwvad_hpf_enum =
226 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
227 ARRAY_SIZE(micfil_hwvad_hpf_texts),
228 micfil_hwvad_hpf_texts);
229static const struct soc_enum fsl_micfil_dc_remover_enum =
230 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
231 micfil_dc_remover_texts);
232
233static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
234 struct snd_ctl_elem_value *ucontrol)
235{
236 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
237 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
238 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
239 unsigned int *item = ucontrol->value.enumerated.item;
240 int val = snd_soc_enum_item_to_val(e, item[0]);
241 int i = 0, ret = 0;
242 u32 reg_val = 0;
243
244 if (val < 0 || val > 3)
245 return -EINVAL;
246
247 micfil->dc_remover = val;
248
249 /* Calculate total value for all channels */
250 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
251 reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
252
253 /* Update DC Remover mode for all channels */
254 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
255 MICFIL_DC_CTRL_CONFIG, reg_val);
256 if (ret < 0)
257 return ret;
258
259 return 0;
260}
261
262static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
263 struct snd_ctl_elem_value *ucontrol)
264{
265 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
266 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
267
268 ucontrol->value.enumerated.item[0] = micfil->dc_remover;
269
270 return 0;
271}
272
273static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
274 struct snd_ctl_elem_value *ucontrol)
275{
276 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
277 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
278 unsigned int *item = ucontrol->value.enumerated.item;
279 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
280 int val = snd_soc_enum_item_to_val(e, item[0]);
281
282 micfil->vad_enabled = val;
283
284 return 0;
285}
286
287static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
288 struct snd_ctl_elem_value *ucontrol)
289{
290 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
291 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
292
293 ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
294
295 return 0;
296}
297
298static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
299 struct snd_ctl_elem_value *ucontrol)
300{
301 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
302 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
303 unsigned int *item = ucontrol->value.enumerated.item;
304 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
305 int val = snd_soc_enum_item_to_val(e, item[0]);
306
307 /* 0 - Envelope-based Mode
308 * 1 - Energy-based Mode
309 */
310 micfil->vad_init_mode = val;
311
312 return 0;
313}
314
315static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
316 struct snd_ctl_elem_value *ucontrol)
317{
318 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
319 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
320
321 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
322
323 return 0;
324}
325
326static int hwvad_detected(struct snd_kcontrol *kcontrol,
327 struct snd_ctl_elem_value *ucontrol)
328{
329 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
330 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
331
332 ucontrol->value.enumerated.item[0] = micfil->vad_detected;
333
334 return 0;
335}
336
337static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = {
338 SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
339 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv),
340 SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
341 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv),
342 SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
343 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv),
344 SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
345 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv),
346 SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
347 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv),
348 SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
349 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv),
350 SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
351 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv),
352 SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
353 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv),
354};
355
356static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {
357 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
358 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
359 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
360 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
361 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
362 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
363 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
364 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
365 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
366 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
367 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
368 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
369 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
370 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
371 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
372 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
373};
374
375static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
376 SOC_ENUM_EXT("MICFIL Quality Select",
377 fsl_micfil_quality_enum,
378 micfil_quality_get, micfil_quality_set),
379 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
380 hwvad_get_enable, hwvad_put_enable),
381 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
382 hwvad_get_init_mode, hwvad_put_init_mode),
383 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
384 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
385 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
386 REG_MICFIL_VAD0_ZCD, 2, 1, 0),
387 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
388 micfil_get_dc_remover_state, micfil_put_dc_remover_state),
389 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
390 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
391 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
392 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
393 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
394 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
395 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
396 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
397 SOC_SINGLE("HWVAD ZCD And Behavior Switch",
398 REG_MICFIL_VAD0_ZCD, 4, 1, 0),
399 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),
400};
401
402static int fsl_micfil_use_verid(struct device *dev)
403{
404 struct fsl_micfil *micfil = dev_get_drvdata(dev);
405 unsigned int val;
406 int ret;
407
408 if (!micfil->soc->use_verid)
409 return 0;
410
411 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
412 if (ret < 0)
413 return ret;
414
415 dev_dbg(dev, "VERID: 0x%016X\n", val);
416
417 micfil->verid.version = val &
418 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
419 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
420 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
421
422 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
423 if (ret < 0)
424 return ret;
425
426 dev_dbg(dev, "PARAM: 0x%016X\n", val);
427
428 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
429 MICFIL_PARAM_NUM_HWVAD_SHIFT;
430 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
431 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
432 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
433 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
434 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
435 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
436 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
437 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
438 MICFIL_PARAM_FIFO_PTRWID_SHIFT;
439 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
440 MICFIL_PARAM_NPAIR_SHIFT;
441
442 return 0;
443}
444
445/* The SRES is a self-negated bit which provides the CPU with the
446 * capability to initialize the PDM Interface module through the
447 * slave-bus interface. This bit always reads as zero, and this
448 * bit is only effective when MDIS is cleared
449 */
450static int fsl_micfil_reset(struct device *dev)
451{
452 struct fsl_micfil *micfil = dev_get_drvdata(dev);
453 int ret;
454
455 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
456 MICFIL_CTRL1_MDIS);
457 if (ret)
458 return ret;
459
460 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
461 MICFIL_CTRL1_SRES);
462 if (ret)
463 return ret;
464
465 /*
466 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
467 * as non-volatile register, so SRES still remain in regmap
468 * cache after set, that every update of REG_MICFIL_CTRL1,
469 * software reset happens. so clear it explicitly.
470 */
471 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
472 MICFIL_CTRL1_SRES);
473 if (ret)
474 return ret;
475
476 /*
477 * Set SRES should clear CHnF flags, But even add delay here
478 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
479 */
480 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
481 if (ret)
482 return ret;
483
484 return 0;
485}
486
487static int fsl_micfil_startup(struct snd_pcm_substream *substream,
488 struct snd_soc_dai *dai)
489{
490 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
491 unsigned int rates[MICFIL_NUM_RATES] = {8000, 11025, 16000, 22050, 32000, 44100, 48000};
492 int i, j, k = 0;
493 u64 clk_rate;
494
495 if (!micfil) {
496 dev_err(dai->dev, "micfil dai priv_data not set\n");
497 return -EINVAL;
498 }
499
500 micfil->constraint_rates.list = micfil->constraint_rates_list;
501 micfil->constraint_rates.count = 0;
502
503 for (j = 0; j < MICFIL_NUM_RATES; j++) {
504 for (i = 0; i < MICFIL_CLK_SRC_NUM; i++) {
505 clk_rate = clk_get_rate(micfil->clk_src[i]);
506 if (clk_rate != 0 && do_div(clk_rate, rates[j]) == 0) {
507 micfil->constraint_rates_list[k++] = rates[j];
508 micfil->constraint_rates.count++;
509 break;
510 }
511 }
512 }
513
514 if (micfil->constraint_rates.count > 0)
515 snd_pcm_hw_constraint_list(substream->runtime, 0,
516 SNDRV_PCM_HW_PARAM_RATE,
517 &micfil->constraint_rates);
518
519 return 0;
520}
521
522/* Enable/disable hwvad interrupts */
523static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
524{
525 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
526 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
527
528 /* Voice Activity Detector Error Interruption */
529 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
530 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
531
532 /* Voice Activity Detector Interruption */
533 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
534 MICFIL_VAD0_CTRL1_IE, vadie_reg);
535
536 return 0;
537}
538
539/* Configuration done only in energy-based initialization mode */
540static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
541{
542 /* Keep the VADFRENDIS bitfield cleared. */
543 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
544 MICFIL_VAD0_CTRL2_FRENDIS);
545
546 /* Keep the VADPREFEN bitfield cleared. */
547 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
548 MICFIL_VAD0_CTRL2_PREFEN);
549
550 /* Keep the VADSFILEN bitfield cleared. */
551 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
552 MICFIL_VAD0_SCONFIG_SFILEN);
553
554 /* Keep the VADSMAXEN bitfield cleared. */
555 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
556 MICFIL_VAD0_SCONFIG_SMAXEN);
557
558 /* Keep the VADNFILAUTO bitfield asserted. */
559 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
560 MICFIL_VAD0_NCONFIG_NFILAUT);
561
562 /* Keep the VADNMINEN bitfield cleared. */
563 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
564 MICFIL_VAD0_NCONFIG_NMINEN);
565
566 /* Keep the VADNDECEN bitfield cleared. */
567 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
568 MICFIL_VAD0_NCONFIG_NDECEN);
569
570 /* Keep the VADNOREN bitfield cleared. */
571 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
572 MICFIL_VAD0_NCONFIG_NOREN);
573
574 return 0;
575}
576
577/* Configuration done only in envelope-based initialization mode */
578static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
579{
580 /* Assert the VADFRENDIS bitfield */
581 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
582 MICFIL_VAD0_CTRL2_FRENDIS);
583
584 /* Assert the VADPREFEN bitfield. */
585 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
586 MICFIL_VAD0_CTRL2_PREFEN);
587
588 /* Assert the VADSFILEN bitfield. */
589 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
590 MICFIL_VAD0_SCONFIG_SFILEN);
591
592 /* Assert the VADSMAXEN bitfield. */
593 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
594 MICFIL_VAD0_SCONFIG_SMAXEN);
595
596 /* Clear the VADNFILAUTO bitfield */
597 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
598 MICFIL_VAD0_NCONFIG_NFILAUT);
599
600 /* Assert the VADNMINEN bitfield. */
601 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
602 MICFIL_VAD0_NCONFIG_NMINEN);
603
604 /* Assert the VADNDECEN bitfield. */
605 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
606 MICFIL_VAD0_NCONFIG_NDECEN);
607
608 /* Assert VADNOREN bitfield. */
609 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
610 MICFIL_VAD0_NCONFIG_NOREN);
611
612 return 0;
613}
614
615/*
616 * Hardware Voice Active Detection: The HWVAD takes data from the input
617 * of a selected PDM microphone to detect if there is any
618 * voice activity. When a voice activity is detected, an interrupt could
619 * be delivered to the system. Initialization in section 8.4:
620 * Can work in two modes:
621 * -> Eneveope-based mode (section 8.4.1)
622 * -> Energy-based mode (section 8.4.2)
623 *
624 * It is important to remark that the HWVAD detector could be enabled
625 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL
626 * bit in STAT register is cleared
627 */
628static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
629{
630 int ret;
631
632 micfil->vad_detected = 0;
633
634 /* envelope-based specific initialization */
635 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
636 ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
637 else
638 ret = fsl_micfil_init_hwvad_energy_mode(micfil);
639 if (ret)
640 return ret;
641
642 /* Voice Activity Detector Internal Filters Initialization*/
643 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
644 MICFIL_VAD0_CTRL1_ST10);
645
646 /* Voice Activity Detector Internal Filter */
647 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
648 MICFIL_VAD0_CTRL1_ST10);
649
650 /* Enable Interrupts */
651 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
652 if (ret)
653 return ret;
654
655 /* Voice Activity Detector Reset */
656 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
657 MICFIL_VAD0_CTRL1_RST);
658
659 /* Voice Activity Detector Enabled */
660 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
661 MICFIL_VAD0_CTRL1_EN);
662
663 return 0;
664}
665
666static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
667{
668 struct device *dev = &micfil->pdev->dev;
669 int ret = 0;
670
671 /* Disable HWVAD */
672 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
673 MICFIL_VAD0_CTRL1_EN);
674
675 /* Disable hwvad interrupts */
676 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
677 if (ret)
678 dev_err(dev, "Failed to disable interrupts\n");
679
680 return ret;
681}
682
683static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
684 struct snd_soc_dai *dai)
685{
686 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
687 struct device *dev = &micfil->pdev->dev;
688 int ret;
689
690 switch (cmd) {
691 case SNDRV_PCM_TRIGGER_START:
692 case SNDRV_PCM_TRIGGER_RESUME:
693 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
694 ret = fsl_micfil_reset(dev);
695 if (ret) {
696 dev_err(dev, "failed to soft reset\n");
697 return ret;
698 }
699
700 /* DMA Interrupt Selection - DISEL bits
701 * 00 - DMA and IRQ disabled
702 * 01 - DMA req enabled
703 * 10 - IRQ enabled
704 * 11 - reserved
705 */
706 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
707 MICFIL_CTRL1_DISEL,
708 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
709 if (ret)
710 return ret;
711
712 /* Enable the module */
713 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
714 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
715 if (ret)
716 return ret;
717
718 if (micfil->vad_enabled)
719 fsl_micfil_hwvad_enable(micfil);
720
721 break;
722 case SNDRV_PCM_TRIGGER_STOP:
723 case SNDRV_PCM_TRIGGER_SUSPEND:
724 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
725 if (micfil->vad_enabled)
726 fsl_micfil_hwvad_disable(micfil);
727
728 /* Disable the module */
729 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
730 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
731 if (ret)
732 return ret;
733
734 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
735 MICFIL_CTRL1_DISEL,
736 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
737 if (ret)
738 return ret;
739 break;
740 default:
741 return -EINVAL;
742 }
743 return 0;
744}
745
746static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
747{
748 struct device *dev = &micfil->pdev->dev;
749 u64 ratio = sample_rate;
750 struct clk *clk;
751 int ret;
752
753 /* Get root clock */
754 clk = micfil->mclk;
755
756 /* Disable clock first, for it was enabled by pm_runtime */
757 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
758 micfil->pll11k_clk, ratio);
759 ret = clk_prepare_enable(clk);
760 if (ret)
761 return ret;
762
763 return 0;
764}
765
766static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
767 struct snd_pcm_hw_params *params,
768 struct snd_soc_dai *dai)
769{
770 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
771 unsigned int channels = params_channels(params);
772 unsigned int rate = params_rate(params);
773 int clk_div = 8;
774 int osr = MICFIL_OSR_DEFAULT;
775 int ret;
776
777 /* 1. Disable the module */
778 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
779 MICFIL_CTRL1_PDMIEN);
780 if (ret)
781 return ret;
782
783 /* enable channels */
784 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
785 0xFF, ((1 << channels) - 1));
786 if (ret)
787 return ret;
788
789 ret = fsl_micfil_reparent_rootclk(micfil, rate);
790 if (ret)
791 return ret;
792
793 micfil->mclk_flag = true;
794
795 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
796 if (ret)
797 return ret;
798
799 ret = micfil_set_quality(micfil);
800 if (ret)
801 return ret;
802
803 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
804 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
805 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
806 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
807
808 /* Configure CIC OSR in VADCICOSR */
809 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
810 MICFIL_VAD0_CTRL1_CICOSR,
811 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
812
813 /* Configure source channel in VADCHSEL */
814 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
815 MICFIL_VAD0_CTRL1_CHSEL,
816 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
817
818 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
819 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
820 micfil->sdmacfg.n_fifos_src = channels;
821 micfil->sdmacfg.sw_done = true;
822 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
823 if (micfil->soc->use_edma)
824 micfil->dma_params_rx.maxburst = channels;
825
826 return 0;
827}
828
829static int fsl_micfil_hw_free(struct snd_pcm_substream *substream,
830 struct snd_soc_dai *dai)
831{
832 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
833
834 clk_disable_unprepare(micfil->mclk);
835 micfil->mclk_flag = false;
836
837 return 0;
838}
839
840static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
841{
842 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
843 struct device *dev = cpu_dai->dev;
844 unsigned int val = 0;
845 int ret, i;
846
847 micfil->quality = QUALITY_VLOW0;
848 micfil->card = cpu_dai->component->card;
849
850 /* set default gain to 2 */
851 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
852
853 /* set DC Remover in bypass mode*/
854 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
855 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
856 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
857 MICFIL_DC_CTRL_CONFIG, val);
858 if (ret) {
859 dev_err(dev, "failed to set DC Remover mode bits\n");
860 return ret;
861 }
862 micfil->dc_remover = MICFIL_DC_BYPASS;
863
864 snd_soc_dai_init_dma_data(cpu_dai, NULL,
865 &micfil->dma_params_rx);
866
867 /* FIFO Watermark Control - FIFOWMK*/
868 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
869 MICFIL_FIFO_CTRL_FIFOWMK,
870 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
871 if (ret)
872 return ret;
873
874 return 0;
875}
876
877static int fsl_micfil_component_probe(struct snd_soc_component *component)
878{
879 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component);
880
881 if (micfil->soc->volume_sx)
882 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls,
883 ARRAY_SIZE(fsl_micfil_volume_sx_controls));
884 else
885 snd_soc_add_component_controls(component, fsl_micfil_volume_controls,
886 ARRAY_SIZE(fsl_micfil_volume_controls));
887
888 return 0;
889}
890
891static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
892 .probe = fsl_micfil_dai_probe,
893 .startup = fsl_micfil_startup,
894 .trigger = fsl_micfil_trigger,
895 .hw_params = fsl_micfil_hw_params,
896 .hw_free = fsl_micfil_hw_free,
897};
898
899static struct snd_soc_dai_driver fsl_micfil_dai = {
900 .capture = {
901 .stream_name = "CPU-Capture",
902 .channels_min = 1,
903 .channels_max = 8,
904 .rates = SNDRV_PCM_RATE_8000_48000,
905 .formats = SNDRV_PCM_FMTBIT_S16_LE,
906 },
907 .ops = &fsl_micfil_dai_ops,
908};
909
910static const struct snd_soc_component_driver fsl_micfil_component = {
911 .name = "fsl-micfil-dai",
912 .probe = fsl_micfil_component_probe,
913 .controls = fsl_micfil_snd_controls,
914 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
915 .legacy_dai_naming = 1,
916};
917
918/* REGMAP */
919static const struct reg_default fsl_micfil_reg_defaults[] = {
920 {REG_MICFIL_CTRL1, 0x00000000},
921 {REG_MICFIL_CTRL2, 0x00000000},
922 {REG_MICFIL_STAT, 0x00000000},
923 {REG_MICFIL_FIFO_CTRL, 0x0000001F},
924 {REG_MICFIL_FIFO_STAT, 0x00000000},
925 {REG_MICFIL_DATACH0, 0x00000000},
926 {REG_MICFIL_DATACH1, 0x00000000},
927 {REG_MICFIL_DATACH2, 0x00000000},
928 {REG_MICFIL_DATACH3, 0x00000000},
929 {REG_MICFIL_DATACH4, 0x00000000},
930 {REG_MICFIL_DATACH5, 0x00000000},
931 {REG_MICFIL_DATACH6, 0x00000000},
932 {REG_MICFIL_DATACH7, 0x00000000},
933 {REG_MICFIL_DC_CTRL, 0x00000000},
934 {REG_MICFIL_OUT_CTRL, 0x00000000},
935 {REG_MICFIL_OUT_STAT, 0x00000000},
936 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
937 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
938 {REG_MICFIL_VAD0_STAT, 0x00000000},
939 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
940 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
941 {REG_MICFIL_VAD0_NDATA, 0x00000000},
942 {REG_MICFIL_VAD0_ZCD, 0x00000004},
943};
944
945static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
946{
947 struct fsl_micfil *micfil = dev_get_drvdata(dev);
948
949 switch (reg) {
950 case REG_MICFIL_CTRL1:
951 case REG_MICFIL_CTRL2:
952 case REG_MICFIL_STAT:
953 case REG_MICFIL_FIFO_CTRL:
954 case REG_MICFIL_FIFO_STAT:
955 case REG_MICFIL_DATACH0:
956 case REG_MICFIL_DATACH1:
957 case REG_MICFIL_DATACH2:
958 case REG_MICFIL_DATACH3:
959 case REG_MICFIL_DATACH4:
960 case REG_MICFIL_DATACH5:
961 case REG_MICFIL_DATACH6:
962 case REG_MICFIL_DATACH7:
963 case REG_MICFIL_DC_CTRL:
964 case REG_MICFIL_OUT_CTRL:
965 case REG_MICFIL_OUT_STAT:
966 case REG_MICFIL_VAD0_CTRL1:
967 case REG_MICFIL_VAD0_CTRL2:
968 case REG_MICFIL_VAD0_STAT:
969 case REG_MICFIL_VAD0_SCONFIG:
970 case REG_MICFIL_VAD0_NCONFIG:
971 case REG_MICFIL_VAD0_NDATA:
972 case REG_MICFIL_VAD0_ZCD:
973 return true;
974 case REG_MICFIL_FSYNC_CTRL:
975 case REG_MICFIL_VERID:
976 case REG_MICFIL_PARAM:
977 if (micfil->soc->use_verid)
978 return true;
979 fallthrough;
980 default:
981 return false;
982 }
983}
984
985static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
986{
987 struct fsl_micfil *micfil = dev_get_drvdata(dev);
988
989 switch (reg) {
990 case REG_MICFIL_CTRL1:
991 case REG_MICFIL_CTRL2:
992 case REG_MICFIL_STAT: /* Write 1 to Clear */
993 case REG_MICFIL_FIFO_CTRL:
994 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
995 case REG_MICFIL_DC_CTRL:
996 case REG_MICFIL_OUT_CTRL:
997 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
998 case REG_MICFIL_VAD0_CTRL1:
999 case REG_MICFIL_VAD0_CTRL2:
1000 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
1001 case REG_MICFIL_VAD0_SCONFIG:
1002 case REG_MICFIL_VAD0_NCONFIG:
1003 case REG_MICFIL_VAD0_ZCD:
1004 return true;
1005 case REG_MICFIL_FSYNC_CTRL:
1006 if (micfil->soc->use_verid)
1007 return true;
1008 fallthrough;
1009 default:
1010 return false;
1011 }
1012}
1013
1014static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
1015{
1016 switch (reg) {
1017 case REG_MICFIL_STAT:
1018 case REG_MICFIL_FIFO_STAT:
1019 case REG_MICFIL_DATACH0:
1020 case REG_MICFIL_DATACH1:
1021 case REG_MICFIL_DATACH2:
1022 case REG_MICFIL_DATACH3:
1023 case REG_MICFIL_DATACH4:
1024 case REG_MICFIL_DATACH5:
1025 case REG_MICFIL_DATACH6:
1026 case REG_MICFIL_DATACH7:
1027 case REG_MICFIL_OUT_STAT:
1028 case REG_MICFIL_VERID:
1029 case REG_MICFIL_PARAM:
1030 case REG_MICFIL_VAD0_STAT:
1031 case REG_MICFIL_VAD0_NDATA:
1032 return true;
1033 default:
1034 return false;
1035 }
1036}
1037
1038static const struct regmap_config fsl_micfil_regmap_config = {
1039 .reg_bits = 32,
1040 .reg_stride = 4,
1041 .val_bits = 32,
1042
1043 .max_register = REG_MICFIL_VAD0_ZCD,
1044 .reg_defaults = fsl_micfil_reg_defaults,
1045 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
1046 .readable_reg = fsl_micfil_readable_reg,
1047 .volatile_reg = fsl_micfil_volatile_reg,
1048 .writeable_reg = fsl_micfil_writeable_reg,
1049 .cache_type = REGCACHE_MAPLE,
1050};
1051
1052/* END OF REGMAP */
1053
1054static irqreturn_t micfil_isr(int irq, void *devid)
1055{
1056 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1057 struct platform_device *pdev = micfil->pdev;
1058 u32 stat_reg;
1059 u32 fifo_stat_reg;
1060 u32 ctrl1_reg;
1061 bool dma_enabled;
1062 int i;
1063
1064 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1065 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
1066 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1067
1068 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
1069
1070 /* Channel 0-7 Output Data Flags */
1071 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
1072 if (stat_reg & MICFIL_STAT_CHXF(i))
1073 dev_dbg(&pdev->dev,
1074 "Data available in Data Channel %d\n", i);
1075 /* if DMA is not enabled, field must be written with 1
1076 * to clear
1077 */
1078 if (!dma_enabled)
1079 regmap_write_bits(micfil->regmap,
1080 REG_MICFIL_STAT,
1081 MICFIL_STAT_CHXF(i),
1082 MICFIL_STAT_CHXF(i));
1083 }
1084
1085 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
1086 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
1087 dev_dbg(&pdev->dev,
1088 "FIFO Overflow Exception flag for channel %d\n",
1089 i);
1090
1091 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
1092 dev_dbg(&pdev->dev,
1093 "FIFO Underflow Exception flag for channel %d\n",
1094 i);
1095 }
1096
1097 return IRQ_HANDLED;
1098}
1099
1100static irqreturn_t micfil_err_isr(int irq, void *devid)
1101{
1102 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1103 struct platform_device *pdev = micfil->pdev;
1104 u32 fifo_stat_reg;
1105 u32 out_stat_reg;
1106 u32 stat_reg;
1107
1108 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1109
1110 if (stat_reg & MICFIL_STAT_BSY_FIL)
1111 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
1112
1113 if (stat_reg & MICFIL_STAT_FIR_RDY)
1114 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
1115
1116 if (stat_reg & MICFIL_STAT_LOWFREQF) {
1117 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
1118 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
1119 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF);
1120 }
1121
1122 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1123 regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT,
1124 fifo_stat_reg, fifo_stat_reg);
1125
1126 regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg);
1127 regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT,
1128 out_stat_reg, out_stat_reg);
1129
1130 return IRQ_HANDLED;
1131}
1132
1133static irqreturn_t voice_detected_fn(int irq, void *devid)
1134{
1135 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1136 struct snd_kcontrol *kctl;
1137
1138 if (!micfil->card)
1139 return IRQ_HANDLED;
1140
1141 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
1142 if (!kctl)
1143 return IRQ_HANDLED;
1144
1145 if (micfil->vad_detected)
1146 snd_ctl_notify(micfil->card->snd_card,
1147 SNDRV_CTL_EVENT_MASK_VALUE,
1148 &kctl->id);
1149
1150 return IRQ_HANDLED;
1151}
1152
1153static irqreturn_t hwvad_isr(int irq, void *devid)
1154{
1155 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1156 struct device *dev = &micfil->pdev->dev;
1157 u32 vad0_reg;
1158 int ret;
1159
1160 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1161
1162 /*
1163 * The only difference between MICFIL_VAD0_STAT_EF and
1164 * MICFIL_VAD0_STAT_IF is that the former requires Write
1165 * 1 to Clear. Since both flags are set, it is enough
1166 * to only read one of them
1167 */
1168 if (vad0_reg & MICFIL_VAD0_STAT_IF) {
1169 /* Write 1 to clear */
1170 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
1171 MICFIL_VAD0_STAT_IF,
1172 MICFIL_VAD0_STAT_IF);
1173
1174 micfil->vad_detected = 1;
1175 }
1176
1177 ret = fsl_micfil_hwvad_disable(micfil);
1178 if (ret)
1179 dev_err(dev, "Failed to disable hwvad\n");
1180
1181 return IRQ_WAKE_THREAD;
1182}
1183
1184static irqreturn_t hwvad_err_isr(int irq, void *devid)
1185{
1186 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1187 struct device *dev = &micfil->pdev->dev;
1188 u32 vad0_reg;
1189
1190 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1191
1192 if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
1193 dev_dbg(dev, "voice activity input overflow/underflow detected\n");
1194
1195 return IRQ_HANDLED;
1196}
1197
1198static int fsl_micfil_runtime_suspend(struct device *dev);
1199static int fsl_micfil_runtime_resume(struct device *dev);
1200
1201static int fsl_micfil_probe(struct platform_device *pdev)
1202{
1203 struct device_node *np = pdev->dev.of_node;
1204 struct fsl_micfil *micfil;
1205 struct resource *res;
1206 void __iomem *regs;
1207 int ret, i;
1208
1209 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
1210 if (!micfil)
1211 return -ENOMEM;
1212
1213 micfil->pdev = pdev;
1214 strscpy(micfil->name, np->name, sizeof(micfil->name));
1215
1216 micfil->soc = of_device_get_match_data(&pdev->dev);
1217
1218 /* ipg_clk is used to control the registers
1219 * ipg_clk_app is used to operate the filter
1220 */
1221 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
1222 if (IS_ERR(micfil->mclk)) {
1223 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
1224 PTR_ERR(micfil->mclk));
1225 return PTR_ERR(micfil->mclk);
1226 }
1227
1228 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
1229 if (IS_ERR(micfil->busclk)) {
1230 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
1231 PTR_ERR(micfil->busclk));
1232 return PTR_ERR(micfil->busclk);
1233 }
1234
1235 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
1236 &micfil->pll11k_clk);
1237
1238 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk;
1239 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk;
1240 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3");
1241 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3]))
1242 micfil->clk_src[MICFIL_CLK_EXT3] = NULL;
1243
1244 /* init regmap */
1245 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1246 if (IS_ERR(regs))
1247 return PTR_ERR(regs);
1248
1249 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1250 regs,
1251 &fsl_micfil_regmap_config);
1252 if (IS_ERR(micfil->regmap)) {
1253 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1254 PTR_ERR(micfil->regmap));
1255 return PTR_ERR(micfil->regmap);
1256 }
1257
1258 /* dataline mask for RX */
1259 ret = of_property_read_u32_index(np,
1260 "fsl,dataline",
1261 0,
1262 &micfil->dataline);
1263 if (ret)
1264 micfil->dataline = 1;
1265
1266 if (micfil->dataline & ~micfil->soc->dataline) {
1267 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
1268 micfil->soc->dataline);
1269 return -EINVAL;
1270 }
1271
1272 /* get IRQs */
1273 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
1274 micfil->irq[i] = platform_get_irq(pdev, i);
1275 if (micfil->irq[i] < 0)
1276 return micfil->irq[i];
1277 }
1278
1279 /* Digital Microphone interface interrupt */
1280 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
1281 micfil_isr, IRQF_SHARED,
1282 micfil->name, micfil);
1283 if (ret) {
1284 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
1285 micfil->irq[0]);
1286 return ret;
1287 }
1288
1289 /* Digital Microphone interface error interrupt */
1290 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
1291 micfil_err_isr, IRQF_SHARED,
1292 micfil->name, micfil);
1293 if (ret) {
1294 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
1295 micfil->irq[1]);
1296 return ret;
1297 }
1298
1299 /* Digital Microphone interface voice activity detector event */
1300 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
1301 hwvad_isr, voice_detected_fn,
1302 IRQF_SHARED, micfil->name, micfil);
1303 if (ret) {
1304 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
1305 micfil->irq[0]);
1306 return ret;
1307 }
1308
1309 /* Digital Microphone interface voice activity detector error */
1310 ret = devm_request_irq(&pdev->dev, micfil->irq[3],
1311 hwvad_err_isr, IRQF_SHARED,
1312 micfil->name, micfil);
1313 if (ret) {
1314 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
1315 micfil->irq[1]);
1316 return ret;
1317 }
1318
1319 micfil->dma_params_rx.chan_name = "rx";
1320 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
1321 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1322
1323 platform_set_drvdata(pdev, micfil);
1324
1325 pm_runtime_enable(&pdev->dev);
1326 if (!pm_runtime_enabled(&pdev->dev)) {
1327 ret = fsl_micfil_runtime_resume(&pdev->dev);
1328 if (ret)
1329 goto err_pm_disable;
1330 }
1331
1332 ret = pm_runtime_resume_and_get(&pdev->dev);
1333 if (ret < 0)
1334 goto err_pm_get_sync;
1335
1336 /* Get micfil version */
1337 ret = fsl_micfil_use_verid(&pdev->dev);
1338 if (ret < 0)
1339 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
1340
1341 ret = pm_runtime_put_sync(&pdev->dev);
1342 if (ret < 0 && ret != -ENOSYS)
1343 goto err_pm_get_sync;
1344
1345 regcache_cache_only(micfil->regmap, true);
1346
1347 /*
1348 * Register platform component before registering cpu dai for there
1349 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1350 */
1351 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1352 if (ret) {
1353 dev_err(&pdev->dev, "failed to pcm register\n");
1354 goto err_pm_disable;
1355 }
1356
1357 fsl_micfil_dai.capture.formats = micfil->soc->formats;
1358
1359 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
1360 &fsl_micfil_dai, 1);
1361 if (ret) {
1362 dev_err(&pdev->dev, "failed to register component %s\n",
1363 fsl_micfil_component.name);
1364 goto err_pm_disable;
1365 }
1366
1367 return ret;
1368
1369err_pm_get_sync:
1370 if (!pm_runtime_status_suspended(&pdev->dev))
1371 fsl_micfil_runtime_suspend(&pdev->dev);
1372err_pm_disable:
1373 pm_runtime_disable(&pdev->dev);
1374
1375 return ret;
1376}
1377
1378static void fsl_micfil_remove(struct platform_device *pdev)
1379{
1380 pm_runtime_disable(&pdev->dev);
1381}
1382
1383static int fsl_micfil_runtime_suspend(struct device *dev)
1384{
1385 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1386
1387 regcache_cache_only(micfil->regmap, true);
1388
1389 if (micfil->mclk_flag)
1390 clk_disable_unprepare(micfil->mclk);
1391 clk_disable_unprepare(micfil->busclk);
1392
1393 return 0;
1394}
1395
1396static int fsl_micfil_runtime_resume(struct device *dev)
1397{
1398 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1399 int ret;
1400
1401 ret = clk_prepare_enable(micfil->busclk);
1402 if (ret < 0)
1403 return ret;
1404
1405 if (micfil->mclk_flag) {
1406 ret = clk_prepare_enable(micfil->mclk);
1407 if (ret < 0) {
1408 clk_disable_unprepare(micfil->busclk);
1409 return ret;
1410 }
1411 }
1412
1413 regcache_cache_only(micfil->regmap, false);
1414 regcache_mark_dirty(micfil->regmap);
1415 regcache_sync(micfil->regmap);
1416
1417 return 0;
1418}
1419
1420static const struct dev_pm_ops fsl_micfil_pm_ops = {
1421 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
1422 fsl_micfil_runtime_resume,
1423 NULL)
1424 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1425 pm_runtime_force_resume)
1426};
1427
1428static struct platform_driver fsl_micfil_driver = {
1429 .probe = fsl_micfil_probe,
1430 .remove = fsl_micfil_remove,
1431 .driver = {
1432 .name = "fsl-micfil-dai",
1433 .pm = &fsl_micfil_pm_ops,
1434 .of_match_table = fsl_micfil_dt_ids,
1435 },
1436};
1437module_platform_driver(fsl_micfil_driver);
1438
1439MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
1440MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
1441MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2018 NXP
3
4#include <linux/clk.h>
5#include <linux/device.h>
6#include <linux/interrupt.h>
7#include <linux/kobject.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_irq.h>
13#include <linux/of_platform.h>
14#include <linux/pm_runtime.h>
15#include <linux/regmap.h>
16#include <linux/sysfs.h>
17#include <linux/types.h>
18#include <sound/dmaengine_pcm.h>
19#include <sound/pcm.h>
20#include <sound/soc.h>
21#include <sound/tlv.h>
22#include <sound/core.h>
23
24#include "fsl_micfil.h"
25#include "imx-pcm.h"
26
27#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
28#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
29
30struct fsl_micfil {
31 struct platform_device *pdev;
32 struct regmap *regmap;
33 const struct fsl_micfil_soc_data *soc;
34 struct clk *busclk;
35 struct clk *mclk;
36 struct snd_dmaengine_dai_dma_data dma_params_rx;
37 unsigned int dataline;
38 char name[32];
39 int irq[MICFIL_IRQ_LINES];
40 unsigned int mclk_streams;
41 int quality; /*QUALITY 2-0 bits */
42 bool slave_mode;
43 int channel_gain[8];
44};
45
46struct fsl_micfil_soc_data {
47 unsigned int fifos;
48 unsigned int fifo_depth;
49 unsigned int dataline;
50 bool imx;
51};
52
53static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
54 .imx = true,
55 .fifos = 8,
56 .fifo_depth = 8,
57 .dataline = 0xf,
58};
59
60static const struct of_device_id fsl_micfil_dt_ids[] = {
61 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
62 {}
63};
64MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
65
66/* Table 5. Quality Modes
67 * Medium 0 0 0
68 * High 0 0 1
69 * Very Low 2 1 0 0
70 * Very Low 1 1 0 1
71 * Very Low 0 1 1 0
72 * Low 1 1 1
73 */
74static const char * const micfil_quality_select_texts[] = {
75 "Medium", "High",
76 "N/A", "N/A",
77 "VLow2", "VLow1",
78 "VLow0", "Low",
79};
80
81static const struct soc_enum fsl_micfil_quality_enum =
82 SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
83 MICFIL_CTRL2_QSEL_SHIFT,
84 ARRAY_SIZE(micfil_quality_select_texts),
85 micfil_quality_select_texts);
86
87static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
88
89static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
90 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
91 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
92 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
93 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
94 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
95 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
96 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
97 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
98 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
99 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
100 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
101 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
102 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
103 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
104 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
105 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
106 SOC_ENUM_EXT("MICFIL Quality Select",
107 fsl_micfil_quality_enum,
108 snd_soc_get_enum_double, snd_soc_put_enum_double),
109};
110
111static inline int get_pdm_clk(struct fsl_micfil *micfil,
112 unsigned int rate)
113{
114 u32 ctrl2_reg;
115 int qsel, osr;
116 int bclk;
117
118 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
119 osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
120 >> MICFIL_CTRL2_CICOSR_SHIFT);
121
122 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
123 qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
124
125 switch (qsel) {
126 case MICFIL_HIGH_QUALITY:
127 bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
128 break;
129 case MICFIL_MEDIUM_QUALITY:
130 case MICFIL_VLOW0_QUALITY:
131 bclk = rate * 4 * osr * 1; /* kfactor = 1 */
132 break;
133 case MICFIL_LOW_QUALITY:
134 case MICFIL_VLOW1_QUALITY:
135 bclk = rate * 2 * osr * 2; /* kfactor = 2 */
136 break;
137 case MICFIL_VLOW2_QUALITY:
138 bclk = rate * osr * 4; /* kfactor = 4 */
139 break;
140 default:
141 dev_err(&micfil->pdev->dev,
142 "Please make sure you select a valid quality.\n");
143 bclk = -1;
144 break;
145 }
146
147 return bclk;
148}
149
150static inline int get_clk_div(struct fsl_micfil *micfil,
151 unsigned int rate)
152{
153 u32 ctrl2_reg;
154 long mclk_rate;
155 int clk_div;
156
157 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
158
159 mclk_rate = clk_get_rate(micfil->mclk);
160
161 clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
162
163 return clk_div;
164}
165
166/* The SRES is a self-negated bit which provides the CPU with the
167 * capability to initialize the PDM Interface module through the
168 * slave-bus interface. This bit always reads as zero, and this
169 * bit is only effective when MDIS is cleared
170 */
171static int fsl_micfil_reset(struct device *dev)
172{
173 struct fsl_micfil *micfil = dev_get_drvdata(dev);
174 int ret;
175
176 ret = regmap_update_bits(micfil->regmap,
177 REG_MICFIL_CTRL1,
178 MICFIL_CTRL1_MDIS_MASK,
179 0);
180 if (ret) {
181 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
182 return ret;
183 }
184
185 ret = regmap_update_bits(micfil->regmap,
186 REG_MICFIL_CTRL1,
187 MICFIL_CTRL1_SRES_MASK,
188 MICFIL_CTRL1_SRES);
189 if (ret) {
190 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
191 return ret;
192 }
193
194 return 0;
195}
196
197static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
198 unsigned int freq)
199{
200 struct device *dev = &micfil->pdev->dev;
201 int ret;
202
203 clk_disable_unprepare(micfil->mclk);
204
205 ret = clk_set_rate(micfil->mclk, freq * 1024);
206 if (ret)
207 dev_warn(dev, "failed to set rate (%u): %d\n",
208 freq * 1024, ret);
209
210 clk_prepare_enable(micfil->mclk);
211
212 return ret;
213}
214
215static int fsl_micfil_startup(struct snd_pcm_substream *substream,
216 struct snd_soc_dai *dai)
217{
218 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
219
220 if (!micfil) {
221 dev_err(dai->dev, "micfil dai priv_data not set\n");
222 return -EINVAL;
223 }
224
225 return 0;
226}
227
228static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
229 struct snd_soc_dai *dai)
230{
231 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
232 struct device *dev = &micfil->pdev->dev;
233 int ret;
234
235 switch (cmd) {
236 case SNDRV_PCM_TRIGGER_START:
237 case SNDRV_PCM_TRIGGER_RESUME:
238 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
239 ret = fsl_micfil_reset(dev);
240 if (ret) {
241 dev_err(dev, "failed to soft reset\n");
242 return ret;
243 }
244
245 /* DMA Interrupt Selection - DISEL bits
246 * 00 - DMA and IRQ disabled
247 * 01 - DMA req enabled
248 * 10 - IRQ enabled
249 * 11 - reserved
250 */
251 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
252 MICFIL_CTRL1_DISEL_MASK,
253 (1 << MICFIL_CTRL1_DISEL_SHIFT));
254 if (ret) {
255 dev_err(dev, "failed to update DISEL bits\n");
256 return ret;
257 }
258
259 /* Enable the module */
260 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
261 MICFIL_CTRL1_PDMIEN_MASK,
262 MICFIL_CTRL1_PDMIEN);
263 if (ret) {
264 dev_err(dev, "failed to enable the module\n");
265 return ret;
266 }
267
268 break;
269 case SNDRV_PCM_TRIGGER_STOP:
270 case SNDRV_PCM_TRIGGER_SUSPEND:
271 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
272 /* Disable the module */
273 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
274 MICFIL_CTRL1_PDMIEN_MASK,
275 0);
276 if (ret) {
277 dev_err(dev, "failed to enable the module\n");
278 return ret;
279 }
280
281 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
282 MICFIL_CTRL1_DISEL_MASK,
283 (0 << MICFIL_CTRL1_DISEL_SHIFT));
284 if (ret) {
285 dev_err(dev, "failed to update DISEL bits\n");
286 return ret;
287 }
288 break;
289 default:
290 return -EINVAL;
291 }
292 return 0;
293}
294
295static int fsl_set_clock_params(struct device *dev, unsigned int rate)
296{
297 struct fsl_micfil *micfil = dev_get_drvdata(dev);
298 int clk_div;
299 int ret;
300
301 ret = fsl_micfil_set_mclk_rate(micfil, rate);
302 if (ret < 0)
303 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
304 clk_get_rate(micfil->mclk), rate);
305
306 /* set CICOSR */
307 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
308 MICFIL_CTRL2_CICOSR_MASK,
309 MICFIL_CTRL2_OSR_DEFAULT);
310 if (ret)
311 dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
312 REG_MICFIL_CTRL2);
313
314 /* set CLK_DIV */
315 clk_div = get_clk_div(micfil, rate);
316 if (clk_div < 0)
317 ret = -EINVAL;
318
319 ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
320 MICFIL_CTRL2_CLKDIV_MASK, clk_div);
321 if (ret)
322 dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
323 REG_MICFIL_CTRL2);
324
325 return ret;
326}
327
328static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
329 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *dai)
331{
332 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
333 unsigned int channels = params_channels(params);
334 unsigned int rate = params_rate(params);
335 struct device *dev = &micfil->pdev->dev;
336 int ret;
337
338 /* 1. Disable the module */
339 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
340 MICFIL_CTRL1_PDMIEN_MASK, 0);
341 if (ret) {
342 dev_err(dev, "failed to disable the module\n");
343 return ret;
344 }
345
346 /* enable channels */
347 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
348 0xFF, ((1 << channels) - 1));
349 if (ret) {
350 dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
351 REG_MICFIL_CTRL1);
352 return ret;
353 }
354
355 ret = fsl_set_clock_params(dev, rate);
356 if (ret < 0) {
357 dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
358 return ret;
359 }
360
361 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
362
363 return 0;
364}
365
366static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
367 unsigned int freq, int dir)
368{
369 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
370 struct device *dev = &micfil->pdev->dev;
371
372 int ret;
373
374 if (!freq)
375 return 0;
376
377 ret = fsl_micfil_set_mclk_rate(micfil, freq);
378 if (ret < 0)
379 dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
380 clk_get_rate(micfil->mclk), freq);
381
382 return ret;
383}
384
385static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
386 .startup = fsl_micfil_startup,
387 .trigger = fsl_micfil_trigger,
388 .hw_params = fsl_micfil_hw_params,
389 .set_sysclk = fsl_micfil_set_dai_sysclk,
390};
391
392static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
393{
394 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
395 struct device *dev = cpu_dai->dev;
396 unsigned int val;
397 int ret;
398 int i;
399
400 /* set qsel to medium */
401 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
402 MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
403 if (ret) {
404 dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
405 REG_MICFIL_CTRL2);
406 return ret;
407 }
408
409 /* set default gain to max_gain */
410 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
411 for (i = 0; i < 8; i++)
412 micfil->channel_gain[i] = 0xF;
413
414 snd_soc_dai_init_dma_data(cpu_dai, NULL,
415 &micfil->dma_params_rx);
416
417 /* FIFO Watermark Control - FIFOWMK*/
418 val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
419 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
420 MICFIL_FIFO_CTRL_FIFOWMK_MASK,
421 val);
422 if (ret) {
423 dev_err(dev, "failed to set FIFOWMK\n");
424 return ret;
425 }
426
427 return 0;
428}
429
430static struct snd_soc_dai_driver fsl_micfil_dai = {
431 .probe = fsl_micfil_dai_probe,
432 .capture = {
433 .stream_name = "CPU-Capture",
434 .channels_min = 1,
435 .channels_max = 8,
436 .rates = FSL_MICFIL_RATES,
437 .formats = FSL_MICFIL_FORMATS,
438 },
439 .ops = &fsl_micfil_dai_ops,
440};
441
442static const struct snd_soc_component_driver fsl_micfil_component = {
443 .name = "fsl-micfil-dai",
444 .controls = fsl_micfil_snd_controls,
445 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
446
447};
448
449/* REGMAP */
450static const struct reg_default fsl_micfil_reg_defaults[] = {
451 {REG_MICFIL_CTRL1, 0x00000000},
452 {REG_MICFIL_CTRL2, 0x00000000},
453 {REG_MICFIL_STAT, 0x00000000},
454 {REG_MICFIL_FIFO_CTRL, 0x00000007},
455 {REG_MICFIL_FIFO_STAT, 0x00000000},
456 {REG_MICFIL_DATACH0, 0x00000000},
457 {REG_MICFIL_DATACH1, 0x00000000},
458 {REG_MICFIL_DATACH2, 0x00000000},
459 {REG_MICFIL_DATACH3, 0x00000000},
460 {REG_MICFIL_DATACH4, 0x00000000},
461 {REG_MICFIL_DATACH5, 0x00000000},
462 {REG_MICFIL_DATACH6, 0x00000000},
463 {REG_MICFIL_DATACH7, 0x00000000},
464 {REG_MICFIL_DC_CTRL, 0x00000000},
465 {REG_MICFIL_OUT_CTRL, 0x00000000},
466 {REG_MICFIL_OUT_STAT, 0x00000000},
467 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
468 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
469 {REG_MICFIL_VAD0_STAT, 0x00000000},
470 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
471 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
472 {REG_MICFIL_VAD0_NDATA, 0x00000000},
473 {REG_MICFIL_VAD0_ZCD, 0x00000004},
474};
475
476static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
477{
478 switch (reg) {
479 case REG_MICFIL_CTRL1:
480 case REG_MICFIL_CTRL2:
481 case REG_MICFIL_STAT:
482 case REG_MICFIL_FIFO_CTRL:
483 case REG_MICFIL_FIFO_STAT:
484 case REG_MICFIL_DATACH0:
485 case REG_MICFIL_DATACH1:
486 case REG_MICFIL_DATACH2:
487 case REG_MICFIL_DATACH3:
488 case REG_MICFIL_DATACH4:
489 case REG_MICFIL_DATACH5:
490 case REG_MICFIL_DATACH6:
491 case REG_MICFIL_DATACH7:
492 case REG_MICFIL_DC_CTRL:
493 case REG_MICFIL_OUT_CTRL:
494 case REG_MICFIL_OUT_STAT:
495 case REG_MICFIL_VAD0_CTRL1:
496 case REG_MICFIL_VAD0_CTRL2:
497 case REG_MICFIL_VAD0_STAT:
498 case REG_MICFIL_VAD0_SCONFIG:
499 case REG_MICFIL_VAD0_NCONFIG:
500 case REG_MICFIL_VAD0_NDATA:
501 case REG_MICFIL_VAD0_ZCD:
502 return true;
503 default:
504 return false;
505 }
506}
507
508static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
509{
510 switch (reg) {
511 case REG_MICFIL_CTRL1:
512 case REG_MICFIL_CTRL2:
513 case REG_MICFIL_STAT: /* Write 1 to Clear */
514 case REG_MICFIL_FIFO_CTRL:
515 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
516 case REG_MICFIL_DC_CTRL:
517 case REG_MICFIL_OUT_CTRL:
518 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
519 case REG_MICFIL_VAD0_CTRL1:
520 case REG_MICFIL_VAD0_CTRL2:
521 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
522 case REG_MICFIL_VAD0_SCONFIG:
523 case REG_MICFIL_VAD0_NCONFIG:
524 case REG_MICFIL_VAD0_ZCD:
525 return true;
526 default:
527 return false;
528 }
529}
530
531static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
532{
533 switch (reg) {
534 case REG_MICFIL_STAT:
535 case REG_MICFIL_DATACH0:
536 case REG_MICFIL_DATACH1:
537 case REG_MICFIL_DATACH2:
538 case REG_MICFIL_DATACH3:
539 case REG_MICFIL_DATACH4:
540 case REG_MICFIL_DATACH5:
541 case REG_MICFIL_DATACH6:
542 case REG_MICFIL_DATACH7:
543 case REG_MICFIL_VAD0_STAT:
544 case REG_MICFIL_VAD0_NDATA:
545 return true;
546 default:
547 return false;
548 }
549}
550
551static const struct regmap_config fsl_micfil_regmap_config = {
552 .reg_bits = 32,
553 .reg_stride = 4,
554 .val_bits = 32,
555
556 .max_register = REG_MICFIL_VAD0_ZCD,
557 .reg_defaults = fsl_micfil_reg_defaults,
558 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
559 .readable_reg = fsl_micfil_readable_reg,
560 .volatile_reg = fsl_micfil_volatile_reg,
561 .writeable_reg = fsl_micfil_writeable_reg,
562 .cache_type = REGCACHE_RBTREE,
563};
564
565/* END OF REGMAP */
566
567static irqreturn_t micfil_isr(int irq, void *devid)
568{
569 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
570 struct platform_device *pdev = micfil->pdev;
571 u32 stat_reg;
572 u32 fifo_stat_reg;
573 u32 ctrl1_reg;
574 bool dma_enabled;
575 int i;
576
577 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
578 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
579 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
580
581 dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
582
583 /* Channel 0-7 Output Data Flags */
584 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
585 if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
586 dev_dbg(&pdev->dev,
587 "Data available in Data Channel %d\n", i);
588 /* if DMA is not enabled, field must be written with 1
589 * to clear
590 */
591 if (!dma_enabled)
592 regmap_write_bits(micfil->regmap,
593 REG_MICFIL_STAT,
594 MICFIL_STAT_CHXF_MASK(i),
595 1);
596 }
597
598 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
599 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
600 dev_dbg(&pdev->dev,
601 "FIFO Overflow Exception flag for channel %d\n",
602 i);
603
604 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
605 dev_dbg(&pdev->dev,
606 "FIFO Underflow Exception flag for channel %d\n",
607 i);
608 }
609
610 return IRQ_HANDLED;
611}
612
613static irqreturn_t micfil_err_isr(int irq, void *devid)
614{
615 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
616 struct platform_device *pdev = micfil->pdev;
617 u32 stat_reg;
618
619 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
620
621 if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
622 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
623
624 if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
625 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
626
627 if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
628 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
629 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
630 MICFIL_STAT_LOWFREQF_MASK, 1);
631 }
632
633 return IRQ_HANDLED;
634}
635
636static int fsl_micfil_probe(struct platform_device *pdev)
637{
638 struct device_node *np = pdev->dev.of_node;
639 struct fsl_micfil *micfil;
640 struct resource *res;
641 void __iomem *regs;
642 int ret, i;
643 unsigned long irqflag = 0;
644
645 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
646 if (!micfil)
647 return -ENOMEM;
648
649 micfil->pdev = pdev;
650 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
651
652 micfil->soc = of_device_get_match_data(&pdev->dev);
653
654 /* ipg_clk is used to control the registers
655 * ipg_clk_app is used to operate the filter
656 */
657 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
658 if (IS_ERR(micfil->mclk)) {
659 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
660 PTR_ERR(micfil->mclk));
661 return PTR_ERR(micfil->mclk);
662 }
663
664 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
665 if (IS_ERR(micfil->busclk)) {
666 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
667 PTR_ERR(micfil->busclk));
668 return PTR_ERR(micfil->busclk);
669 }
670
671 /* init regmap */
672 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
673 if (IS_ERR(regs))
674 return PTR_ERR(regs);
675
676 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
677 regs,
678 &fsl_micfil_regmap_config);
679 if (IS_ERR(micfil->regmap)) {
680 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
681 PTR_ERR(micfil->regmap));
682 return PTR_ERR(micfil->regmap);
683 }
684
685 /* dataline mask for RX */
686 ret = of_property_read_u32_index(np,
687 "fsl,dataline",
688 0,
689 &micfil->dataline);
690 if (ret)
691 micfil->dataline = 1;
692
693 if (micfil->dataline & ~micfil->soc->dataline) {
694 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
695 micfil->soc->dataline);
696 return -EINVAL;
697 }
698
699 /* get IRQs */
700 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
701 micfil->irq[i] = platform_get_irq(pdev, i);
702 dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
703 if (micfil->irq[i] < 0)
704 return micfil->irq[i];
705 }
706
707 if (of_property_read_bool(np, "fsl,shared-interrupt"))
708 irqflag = IRQF_SHARED;
709
710 /* Digital Microphone interface interrupt */
711 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
712 micfil_isr, irqflag,
713 micfil->name, micfil);
714 if (ret) {
715 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
716 micfil->irq[0]);
717 return ret;
718 }
719
720 /* Digital Microphone interface error interrupt */
721 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
722 micfil_err_isr, irqflag,
723 micfil->name, micfil);
724 if (ret) {
725 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
726 micfil->irq[1]);
727 return ret;
728 }
729
730 micfil->dma_params_rx.chan_name = "rx";
731 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
732 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
733
734
735 platform_set_drvdata(pdev, micfil);
736
737 pm_runtime_enable(&pdev->dev);
738 regcache_cache_only(micfil->regmap, true);
739
740 /*
741 * Register platform component before registering cpu dai for there
742 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
743 */
744 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
745 if (ret) {
746 dev_err(&pdev->dev, "failed to pcm register\n");
747 return ret;
748 }
749
750 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
751 &fsl_micfil_dai, 1);
752 if (ret) {
753 dev_err(&pdev->dev, "failed to register component %s\n",
754 fsl_micfil_component.name);
755 }
756
757 return ret;
758}
759
760static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
761{
762 struct fsl_micfil *micfil = dev_get_drvdata(dev);
763
764 regcache_cache_only(micfil->regmap, true);
765
766 clk_disable_unprepare(micfil->mclk);
767 clk_disable_unprepare(micfil->busclk);
768
769 return 0;
770}
771
772static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
773{
774 struct fsl_micfil *micfil = dev_get_drvdata(dev);
775 int ret;
776
777 ret = clk_prepare_enable(micfil->busclk);
778 if (ret < 0)
779 return ret;
780
781 ret = clk_prepare_enable(micfil->mclk);
782 if (ret < 0) {
783 clk_disable_unprepare(micfil->busclk);
784 return ret;
785 }
786
787 regcache_cache_only(micfil->regmap, false);
788 regcache_mark_dirty(micfil->regmap);
789 regcache_sync(micfil->regmap);
790
791 return 0;
792}
793
794static int __maybe_unused fsl_micfil_suspend(struct device *dev)
795{
796 pm_runtime_force_suspend(dev);
797
798 return 0;
799}
800
801static int __maybe_unused fsl_micfil_resume(struct device *dev)
802{
803 pm_runtime_force_resume(dev);
804
805 return 0;
806}
807
808static const struct dev_pm_ops fsl_micfil_pm_ops = {
809 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
810 fsl_micfil_runtime_resume,
811 NULL)
812 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
813 fsl_micfil_resume)
814};
815
816static struct platform_driver fsl_micfil_driver = {
817 .probe = fsl_micfil_probe,
818 .driver = {
819 .name = "fsl-micfil-dai",
820 .pm = &fsl_micfil_pm_ops,
821 .of_match_table = fsl_micfil_dt_ids,
822 },
823};
824module_platform_driver(fsl_micfil_driver);
825
826MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
827MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
828MODULE_LICENSE("GPL v2");