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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * rt5651.h -- RT5651 ALSA SoC audio driver
4 *
5 * Copyright 2011 Realtek Microelectronics
6 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 */
8
9#ifndef __RT5651_H__
10#define __RT5651_H__
11
12#include <dt-bindings/sound/rt5651.h>
13
14/* Info */
15#define RT5651_RESET 0x00
16#define RT5651_VERSION_ID 0xfd
17#define RT5651_VENDOR_ID 0xfe
18#define RT5651_DEVICE_ID 0xff
19/* I/O - Output */
20#define RT5651_HP_VOL 0x02
21#define RT5651_LOUT_CTRL1 0x03
22#define RT5651_LOUT_CTRL2 0x05
23/* I/O - Input */
24#define RT5651_IN1_IN2 0x0d
25#define RT5651_IN3 0x0e
26#define RT5651_INL1_INR1_VOL 0x0f
27#define RT5651_INL2_INR2_VOL 0x10
28/* I/O - ADC/DAC/DMIC */
29#define RT5651_DAC1_DIG_VOL 0x19
30#define RT5651_DAC2_DIG_VOL 0x1a
31#define RT5651_DAC2_CTRL 0x1b
32#define RT5651_ADC_DIG_VOL 0x1c
33#define RT5651_ADC_DATA 0x1d
34#define RT5651_ADC_BST_VOL 0x1e
35/* Mixer - D-D */
36#define RT5651_STO1_ADC_MIXER 0x27
37#define RT5651_STO2_ADC_MIXER 0x28
38#define RT5651_AD_DA_MIXER 0x29
39#define RT5651_STO_DAC_MIXER 0x2a
40#define RT5651_DD_MIXER 0x2b
41#define RT5651_DIG_INF_DATA 0x2f
42/* PDM */
43#define RT5651_PDM_CTL 0x30
44#define RT5651_PDM_I2C_CTL1 0x31
45#define RT5651_PDM_I2C_CTL2 0x32
46#define RT5651_PDM_I2C_DATA_W 0x33
47#define RT5651_PDM_I2C_DATA_R 0x34
48/* Mixer - ADC */
49#define RT5651_REC_L1_MIXER 0x3b
50#define RT5651_REC_L2_MIXER 0x3c
51#define RT5651_REC_R1_MIXER 0x3d
52#define RT5651_REC_R2_MIXER 0x3e
53/* Mixer - DAC */
54#define RT5651_HPO_MIXER 0x45
55#define RT5651_OUT_L1_MIXER 0x4d
56#define RT5651_OUT_L2_MIXER 0x4e
57#define RT5651_OUT_L3_MIXER 0x4f
58#define RT5651_OUT_R1_MIXER 0x50
59#define RT5651_OUT_R2_MIXER 0x51
60#define RT5651_OUT_R3_MIXER 0x52
61#define RT5651_LOUT_MIXER 0x53
62/* Power */
63#define RT5651_PWR_DIG1 0x61
64#define RT5651_PWR_DIG2 0x62
65#define RT5651_PWR_ANLG1 0x63
66#define RT5651_PWR_ANLG2 0x64
67#define RT5651_PWR_MIXER 0x65
68#define RT5651_PWR_VOL 0x66
69/* Private Register Control */
70#define RT5651_PRIV_INDEX 0x6a
71#define RT5651_PRIV_DATA 0x6c
72/* Format - ADC/DAC */
73#define RT5651_I2S1_SDP 0x70
74#define RT5651_I2S2_SDP 0x71
75#define RT5651_ADDA_CLK1 0x73
76#define RT5651_ADDA_CLK2 0x74
77#define RT5651_DMIC 0x75
78/* TDM Control */
79#define RT5651_TDM_CTL_1 0x77
80#define RT5651_TDM_CTL_2 0x78
81#define RT5651_TDM_CTL_3 0x79
82/* Function - Analog */
83#define RT5651_GLB_CLK 0x80
84#define RT5651_PLL_CTRL1 0x81
85#define RT5651_PLL_CTRL2 0x82
86#define RT5651_PLL_MODE_1 0x83
87#define RT5651_PLL_MODE_2 0x84
88#define RT5651_PLL_MODE_3 0x85
89#define RT5651_PLL_MODE_4 0x86
90#define RT5651_PLL_MODE_5 0x87
91#define RT5651_PLL_MODE_6 0x89
92#define RT5651_PLL_MODE_7 0x8a
93#define RT5651_DEPOP_M1 0x8e
94#define RT5651_DEPOP_M2 0x8f
95#define RT5651_DEPOP_M3 0x90
96#define RT5651_CHARGE_PUMP 0x91
97#define RT5651_MICBIAS 0x93
98#define RT5651_A_JD_CTL1 0x94
99/* Function - Digital */
100#define RT5651_EQ_CTRL1 0xb0
101#define RT5651_EQ_CTRL2 0xb1
102#define RT5651_ALC_1 0xb4
103#define RT5651_ALC_2 0xb5
104#define RT5651_ALC_3 0xb6
105#define RT5651_JD_CTRL1 0xbb
106#define RT5651_JD_CTRL2 0xbc
107#define RT5651_IRQ_CTRL1 0xbd
108#define RT5651_IRQ_CTRL2 0xbe
109#define RT5651_INT_IRQ_ST 0xbf
110#define RT5651_GPIO_CTRL1 0xc0
111#define RT5651_GPIO_CTRL2 0xc1
112#define RT5651_GPIO_CTRL3 0xc2
113#define RT5651_PGM_REG_ARR1 0xc8
114#define RT5651_PGM_REG_ARR2 0xc9
115#define RT5651_PGM_REG_ARR3 0xca
116#define RT5651_PGM_REG_ARR4 0xcb
117#define RT5651_PGM_REG_ARR5 0xcc
118#define RT5651_SCB_FUNC 0xcd
119#define RT5651_SCB_CTRL 0xce
120#define RT5651_BASE_BACK 0xcf
121#define RT5651_MP3_PLUS1 0xd0
122#define RT5651_MP3_PLUS2 0xd1
123#define RT5651_ADJ_HPF_CTRL1 0xd3
124#define RT5651_ADJ_HPF_CTRL2 0xd4
125#define RT5651_HP_CALIB_AMP_DET 0xd6
126#define RT5651_HP_CALIB2 0xd7
127#define RT5651_SV_ZCD1 0xd9
128#define RT5651_SV_ZCD2 0xda
129#define RT5651_D_MISC 0xfa
130/* Dummy Register */
131#define RT5651_DUMMY2 0xfb
132#define RT5651_DUMMY3 0xfc
133
134
135/* Index of Codec Private Register definition */
136#define RT5651_BIAS_CUR1 0x12
137#define RT5651_BIAS_CUR3 0x14
138#define RT5651_BIAS_CUR4 0x15
139#define RT5651_CLSD_INT_REG1 0x1c
140#define RT5651_CHPUMP_INT_REG1 0x24
141#define RT5651_MAMP_INT_REG2 0x37
142#define RT5651_CHOP_DAC_ADC 0x3d
143#define RT5651_3D_SPK 0x63
144#define RT5651_WND_1 0x6c
145#define RT5651_WND_2 0x6d
146#define RT5651_WND_3 0x6e
147#define RT5651_WND_4 0x6f
148#define RT5651_WND_5 0x70
149#define RT5651_WND_8 0x73
150#define RT5651_DIP_SPK_INF 0x75
151#define RT5651_HP_DCC_INT1 0x77
152#define RT5651_EQ_BW_LOP 0xa0
153#define RT5651_EQ_GN_LOP 0xa1
154#define RT5651_EQ_FC_BP1 0xa2
155#define RT5651_EQ_BW_BP1 0xa3
156#define RT5651_EQ_GN_BP1 0xa4
157#define RT5651_EQ_FC_BP2 0xa5
158#define RT5651_EQ_BW_BP2 0xa6
159#define RT5651_EQ_GN_BP2 0xa7
160#define RT5651_EQ_FC_BP3 0xa8
161#define RT5651_EQ_BW_BP3 0xa9
162#define RT5651_EQ_GN_BP3 0xaa
163#define RT5651_EQ_FC_BP4 0xab
164#define RT5651_EQ_BW_BP4 0xac
165#define RT5651_EQ_GN_BP4 0xad
166#define RT5651_EQ_FC_HIP1 0xae
167#define RT5651_EQ_GN_HIP1 0xaf
168#define RT5651_EQ_FC_HIP2 0xb0
169#define RT5651_EQ_BW_HIP2 0xb1
170#define RT5651_EQ_GN_HIP2 0xb2
171#define RT5651_EQ_PRE_VOL 0xb3
172#define RT5651_EQ_PST_VOL 0xb4
173
174
175/* global definition */
176#define RT5651_L_MUTE (0x1 << 15)
177#define RT5651_L_MUTE_SFT 15
178#define RT5651_VOL_L_MUTE (0x1 << 14)
179#define RT5651_VOL_L_SFT 14
180#define RT5651_R_MUTE (0x1 << 7)
181#define RT5651_R_MUTE_SFT 7
182#define RT5651_VOL_R_MUTE (0x1 << 6)
183#define RT5651_VOL_R_SFT 6
184#define RT5651_L_VOL_MASK (0x3f << 8)
185#define RT5651_L_VOL_SFT 8
186#define RT5651_R_VOL_MASK (0x3f)
187#define RT5651_R_VOL_SFT 0
188
189/* LOUT Control 2(0x05) */
190#define RT5651_EN_DFO (0x1 << 15)
191
192/* IN1 and IN2 Control (0x0d) */
193/* IN3 and IN4 Control (0x0e) */
194#define RT5651_BST_MASK1 (0xf<<12)
195#define RT5651_BST_SFT1 12
196#define RT5651_BST_MASK2 (0xf<<8)
197#define RT5651_BST_SFT2 8
198#define RT5651_IN_DF1 (0x1 << 7)
199#define RT5651_IN_SFT1 7
200#define RT5651_IN_DF2 (0x1 << 6)
201#define RT5651_IN_SFT2 6
202
203/* INL1 and INR1 Volume Control (0x0f) */
204/* INL2 and INR2 Volume Control (0x10) */
205#define RT5651_INL_SEL_MASK (0x1 << 15)
206#define RT5651_INL_SEL_SFT 15
207#define RT5651_INL_SEL_IN4P (0x0 << 15)
208#define RT5651_INL_SEL_MONOP (0x1 << 15)
209#define RT5651_INL_VOL_MASK (0x1f << 8)
210#define RT5651_INL_VOL_SFT 8
211#define RT5651_INR_SEL_MASK (0x1 << 7)
212#define RT5651_INR_SEL_SFT 7
213#define RT5651_INR_SEL_IN4N (0x0 << 7)
214#define RT5651_INR_SEL_MONON (0x1 << 7)
215#define RT5651_INR_VOL_MASK (0x1f)
216#define RT5651_INR_VOL_SFT 0
217
218/* DAC1 Digital Volume (0x19) */
219#define RT5651_DAC_L1_VOL_MASK (0xff << 8)
220#define RT5651_DAC_L1_VOL_SFT 8
221#define RT5651_DAC_R1_VOL_MASK (0xff)
222#define RT5651_DAC_R1_VOL_SFT 0
223
224/* DAC2 Digital Volume (0x1a) */
225#define RT5651_DAC_L2_VOL_MASK (0xff << 8)
226#define RT5651_DAC_L2_VOL_SFT 8
227#define RT5651_DAC_R2_VOL_MASK (0xff)
228#define RT5651_DAC_R2_VOL_SFT 0
229
230/* DAC2 Control (0x1b) */
231#define RT5651_M_DAC_L2_VOL (0x1 << 13)
232#define RT5651_M_DAC_L2_VOL_SFT 13
233#define RT5651_M_DAC_R2_VOL (0x1 << 12)
234#define RT5651_M_DAC_R2_VOL_SFT 12
235#define RT5651_SEL_DAC_L2 (0x1 << 11)
236#define RT5651_IF2_DAC_L2 (0x1 << 11)
237#define RT5651_IF1_DAC_L2 (0x0 << 11)
238#define RT5651_SEL_DAC_L2_SFT 11
239#define RT5651_SEL_DAC_R2 (0x1 << 10)
240#define RT5651_IF2_DAC_R2 (0x1 << 11)
241#define RT5651_IF1_DAC_R2 (0x0 << 11)
242#define RT5651_SEL_DAC_R2_SFT 10
243
244/* ADC Digital Volume Control (0x1c) */
245#define RT5651_ADC_L_VOL_MASK (0x7f << 8)
246#define RT5651_ADC_L_VOL_SFT 8
247#define RT5651_ADC_R_VOL_MASK (0x7f)
248#define RT5651_ADC_R_VOL_SFT 0
249
250/* Mono ADC Digital Volume Control (0x1d) */
251#define RT5651_M_MONO_ADC_L (0x1 << 15)
252#define RT5651_M_MONO_ADC_L_SFT 15
253#define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
254#define RT5651_MONO_ADC_L_VOL_SFT 8
255#define RT5651_M_MONO_ADC_R (0x1 << 7)
256#define RT5651_M_MONO_ADC_R_SFT 7
257#define RT5651_MONO_ADC_R_VOL_MASK (0x7f)
258#define RT5651_MONO_ADC_R_VOL_SFT 0
259
260/* ADC Boost Volume Control (0x1e) */
261#define RT5651_ADC_L_BST_MASK (0x3 << 14)
262#define RT5651_ADC_L_BST_SFT 14
263#define RT5651_ADC_R_BST_MASK (0x3 << 12)
264#define RT5651_ADC_R_BST_SFT 12
265#define RT5651_ADC_COMP_MASK (0x3 << 10)
266#define RT5651_ADC_COMP_SFT 10
267
268/* Stereo ADC1 Mixer Control (0x27) */
269#define RT5651_M_STO1_ADC_L1 (0x1 << 14)
270#define RT5651_M_STO1_ADC_L1_SFT 14
271#define RT5651_M_STO1_ADC_L2 (0x1 << 13)
272#define RT5651_M_STO1_ADC_L2_SFT 13
273#define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
274#define RT5651_STO1_ADC_1_SRC_SFT 12
275#define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
276#define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
277#define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
278#define RT5651_STO1_ADC_2_SRC_SFT 11
279#define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
280#define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
281#define RT5651_M_STO1_ADC_R1 (0x1 << 6)
282#define RT5651_M_STO1_ADC_R1_SFT 6
283#define RT5651_M_STO1_ADC_R2 (0x1 << 5)
284#define RT5651_M_STO1_ADC_R2_SFT 5
285
286/* Stereo ADC2 Mixer Control (0x28) */
287#define RT5651_M_STO2_ADC_L1 (0x1 << 14)
288#define RT5651_M_STO2_ADC_L1_SFT 14
289#define RT5651_M_STO2_ADC_L2 (0x1 << 13)
290#define RT5651_M_STO2_ADC_L2_SFT 13
291#define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
292#define RT5651_STO2_ADC_L1_SRC_SFT 12
293#define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
294#define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
295#define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
296#define RT5651_STO2_ADC_L2_SRC_SFT 11
297#define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
298#define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
299#define RT5651_M_STO2_ADC_R1 (0x1 << 6)
300#define RT5651_M_STO2_ADC_R1_SFT 6
301#define RT5651_M_STO2_ADC_R2 (0x1 << 5)
302#define RT5651_M_STO2_ADC_R2_SFT 5
303#define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
304#define RT5651_STO2_ADC_R1_SRC_SFT 4
305#define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
306#define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
307#define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
308#define RT5651_STO2_ADC_R2_SRC_SFT 3
309#define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
310#define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
311
312/* ADC Mixer to DAC Mixer Control (0x29) */
313#define RT5651_M_ADCMIX_L (0x1 << 15)
314#define RT5651_M_ADCMIX_L_SFT 15
315#define RT5651_M_IF1_DAC_L (0x1 << 14)
316#define RT5651_M_IF1_DAC_L_SFT 14
317#define RT5651_M_ADCMIX_R (0x1 << 7)
318#define RT5651_M_ADCMIX_R_SFT 7
319#define RT5651_M_IF1_DAC_R (0x1 << 6)
320#define RT5651_M_IF1_DAC_R_SFT 6
321
322/* Stereo DAC Mixer Control (0x2a) */
323#define RT5651_M_DAC_L1_MIXL (0x1 << 14)
324#define RT5651_M_DAC_L1_MIXL_SFT 14
325#define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
326#define RT5651_DAC_L1_STO_L_VOL_SFT 13
327#define RT5651_M_DAC_L2_MIXL (0x1 << 12)
328#define RT5651_M_DAC_L2_MIXL_SFT 12
329#define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
330#define RT5651_DAC_L2_STO_L_VOL_SFT 11
331#define RT5651_M_DAC_R1_MIXL (0x1 << 9)
332#define RT5651_M_DAC_R1_MIXL_SFT 9
333#define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
334#define RT5651_DAC_R1_STO_L_VOL_SFT 8
335#define RT5651_M_DAC_R1_MIXR (0x1 << 6)
336#define RT5651_M_DAC_R1_MIXR_SFT 6
337#define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
338#define RT5651_DAC_R1_STO_R_VOL_SFT 5
339#define RT5651_M_DAC_R2_MIXR (0x1 << 4)
340#define RT5651_M_DAC_R2_MIXR_SFT 4
341#define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
342#define RT5651_DAC_R2_STO_R_VOL_SFT 3
343#define RT5651_M_DAC_L1_MIXR (0x1 << 1)
344#define RT5651_M_DAC_L1_MIXR_SFT 1
345#define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
346#define RT5651_DAC_L1_STO_R_VOL_SFT 0
347
348/* DD Mixer Control (0x2b) */
349#define RT5651_M_STO_DD_L1 (0x1 << 14)
350#define RT5651_M_STO_DD_L1_SFT 14
351#define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
352#define RT5651_DAC_DD_L1_VOL_SFT 13
353#define RT5651_M_STO_DD_L2 (0x1 << 12)
354#define RT5651_M_STO_DD_L2_SFT 12
355#define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
356#define RT5651_STO_DD_L2_VOL_SFT 11
357#define RT5651_M_STO_DD_R2_L (0x1 << 10)
358#define RT5651_M_STO_DD_R2_L_SFT 10
359#define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
360#define RT5651_STO_DD_R2_L_VOL_SFT 9
361#define RT5651_M_STO_DD_R1 (0x1 << 6)
362#define RT5651_M_STO_DD_R1_SFT 6
363#define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
364#define RT5651_STO_DD_R1_VOL_SFT 5
365#define RT5651_M_STO_DD_R2 (0x1 << 4)
366#define RT5651_M_STO_DD_R2_SFT 4
367#define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
368#define RT5651_STO_DD_R2_VOL_SFT 3
369#define RT5651_M_STO_DD_L2_R (0x1 << 2)
370#define RT5651_M_STO_DD_L2_R_SFT 2
371#define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
372#define RT5651_STO_DD_L2_R_VOL_SFT 1
373
374/* Digital Mixer Control (0x2c) */
375#define RT5651_M_STO_L_DAC_L (0x1 << 15)
376#define RT5651_M_STO_L_DAC_L_SFT 15
377#define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
378#define RT5651_STO_L_DAC_L_VOL_SFT 14
379#define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
380#define RT5651_M_DAC_L2_DAC_L_SFT 13
381#define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
382#define RT5651_DAC_L2_DAC_L_VOL_SFT 12
383#define RT5651_M_STO_R_DAC_R (0x1 << 11)
384#define RT5651_M_STO_R_DAC_R_SFT 11
385#define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
386#define RT5651_STO_R_DAC_R_VOL_SFT 10
387#define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
388#define RT5651_M_DAC_R2_DAC_R_SFT 9
389#define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
390#define RT5651_DAC_R2_DAC_R_VOL_SFT 8
391
392/* DSP Path Control 1 (0x2d) */
393#define RT5651_RXDP_SRC_MASK (0x1 << 15)
394#define RT5651_RXDP_SRC_SFT 15
395#define RT5651_RXDP_SRC_NOR (0x0 << 15)
396#define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
397#define RT5651_TXDP_SRC_MASK (0x1 << 14)
398#define RT5651_TXDP_SRC_SFT 14
399#define RT5651_TXDP_SRC_NOR (0x0 << 14)
400#define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
401
402/* DSP Path Control 2 (0x2e) */
403#define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
404#define RT5651_DAC_L2_SEL_SFT 14
405#define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
406#define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
407#define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
408#define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
409#define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
410#define RT5651_DAC_R2_SEL_SFT 12
411#define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
412#define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
413#define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
414#define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
415#define RT5651_IF2_ADC_L_SEL_SFT 11
416#define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
417#define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
418#define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
419#define RT5651_IF2_ADC_R_SEL_SFT 10
420#define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
421#define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
422#define RT5651_RXDC_SEL_MASK (0x3 << 8)
423#define RT5651_RXDC_SEL_SFT 8
424#define RT5651_RXDC_SEL_NOR (0x0 << 8)
425#define RT5651_RXDC_SEL_L2R (0x1 << 8)
426#define RT5651_RXDC_SEL_R2L (0x2 << 8)
427#define RT5651_RXDC_SEL_SWAP (0x3 << 8)
428#define RT5651_RXDP_SEL_MASK (0x3 << 6)
429#define RT5651_RXDP_SEL_SFT 6
430#define RT5651_RXDP_SEL_NOR (0x0 << 6)
431#define RT5651_RXDP_SEL_L2R (0x1 << 6)
432#define RT5651_RXDP_SEL_R2L (0x2 << 6)
433#define RT5651_RXDP_SEL_SWAP (0x3 << 6)
434#define RT5651_TXDC_SEL_MASK (0x3 << 4)
435#define RT5651_TXDC_SEL_SFT 4
436#define RT5651_TXDC_SEL_NOR (0x0 << 4)
437#define RT5651_TXDC_SEL_L2R (0x1 << 4)
438#define RT5651_TXDC_SEL_R2L (0x2 << 4)
439#define RT5651_TXDC_SEL_SWAP (0x3 << 4)
440#define RT5651_TXDP_SEL_MASK (0x3 << 2)
441#define RT5651_TXDP_SEL_SFT 2
442#define RT5651_TXDP_SEL_NOR (0x0 << 2)
443#define RT5651_TXDP_SEL_L2R (0x1 << 2)
444#define RT5651_TXDP_SEL_R2L (0x2 << 2)
445#define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
446
447/* Digital Interface Data Control (0x2f) */
448#define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
449#define RT5651_IF2_DAC_SEL_SFT 10
450#define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
451#define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
452#define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
453#define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
454#define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
455#define RT5651_IF2_ADC_SEL_SFT 8
456#define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
457#define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
458#define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
459#define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
460#define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
461#define RT5651_IF2_ADC_SRC_SFT 7
462#define RT5651_IF1_ADC1 (0x0 << 7)
463#define RT5651_IF1_ADC2 (0x1 << 7)
464
465/* PDM Output Control (0x30) */
466#define RT5651_PDM_L_SEL_MASK (0x1 << 15)
467#define RT5651_PDM_L_SEL_SFT 15
468#define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
469#define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
470#define RT5651_M_PDM_L (0x1 << 14)
471#define RT5651_M_PDM_L_SFT 14
472#define RT5651_PDM_R_SEL_MASK (0x1 << 13)
473#define RT5651_PDM_R_SEL_SFT 13
474#define RT5651_PDM_R_SEL_DD_L (0x0 << 13)
475#define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
476#define RT5651_M_PDM_R (0x1 << 12)
477#define RT5651_M_PDM_R_SFT 12
478#define RT5651_PDM_BUSY (0x1 << 6)
479#define RT5651_PDM_BUSY_SFT 6
480#define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
481#define RT5651_PDM_PATTERN_SEL_64 (0x0 << 5)
482#define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
483#define RT5651_PDM_VOL_MASK (0x1 << 4)
484#define RT5651_PDM_VOL_SFT 4
485#define RT5651_PDM_DIV_MASK (0x3)
486#define RT5651_PDM_DIV_SFT 0
487#define RT5651_PDM_DIV_1 0
488#define RT5651_PDM_DIV_2 1
489#define RT5651_PDM_DIV_3 2
490#define RT5651_PDM_DIV_4 3
491
492/* PDM I2C/Data Control 1 (0x31) */
493#define RT5651_PDM_I2C_ID_MASK (0xf << 12)
494#define PT5631_PDM_CMD_EXE (0x1 << 11)
495#define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
496#define RT5651_PDM_I2C_CMD_R (0x0 << 10)
497#define RT5651_PDM_I2C_CMD_W (0x1 << 10)
498#define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
499#define RT5651_PDM_I2C_NORMAL (0x0 << 8)
500#define RT5651_PDM_I2C_BUSY (0x1 << 8)
501
502/* PDM I2C/Data Control 2 (0x32) */
503#define RT5651_PDM_I2C_ADDR (0xff << 8)
504#define RT5651_PDM_I2C_CMD_PATTERN (0xff)
505
506
507/* REC Left Mixer Control 1 (0x3b) */
508#define RT5651_G_LN_L2_RM_L_MASK (0x7 << 13)
509#define RT5651_G_IN_L2_RM_L_SFT 13
510#define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
511#define RT5651_G_IN_L1_RM_L_SFT 10
512#define RT5651_G_BST3_RM_L_MASK (0x7 << 4)
513#define RT5651_G_BST3_RM_L_SFT 4
514#define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
515#define RT5651_G_BST2_RM_L_SFT 1
516
517/* REC Left Mixer Control 2 (0x3c) */
518#define RT5651_G_BST1_RM_L_MASK (0x7 << 13)
519#define RT5651_G_BST1_RM_L_SFT 13
520#define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
521#define RT5651_G_OM_L_RM_L_SFT 10
522#define RT5651_M_IN2_L_RM_L (0x1 << 6)
523#define RT5651_M_IN2_L_RM_L_SFT 6
524#define RT5651_M_IN1_L_RM_L (0x1 << 5)
525#define RT5651_M_IN1_L_RM_L_SFT 5
526#define RT5651_M_BST3_RM_L (0x1 << 3)
527#define RT5651_M_BST3_RM_L_SFT 3
528#define RT5651_M_BST2_RM_L (0x1 << 2)
529#define RT5651_M_BST2_RM_L_SFT 2
530#define RT5651_M_BST1_RM_L (0x1 << 1)
531#define RT5651_M_BST1_RM_L_SFT 1
532#define RT5651_M_OM_L_RM_L (0x1)
533#define RT5651_M_OM_L_RM_L_SFT 0
534
535/* REC Right Mixer Control 1 (0x3d) */
536#define RT5651_G_IN2_R_RM_R_MASK (0x7 << 13)
537#define RT5651_G_IN2_R_RM_R_SFT 13
538#define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
539#define RT5651_G_IN1_R_RM_R_SFT 10
540#define RT5651_G_BST3_RM_R_MASK (0x7 << 4)
541#define RT5651_G_BST3_RM_R_SFT 4
542#define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
543#define RT5651_G_BST2_RM_R_SFT 1
544
545/* REC Right Mixer Control 2 (0x3e) */
546#define RT5651_G_BST1_RM_R_MASK (0x7 << 13)
547#define RT5651_G_BST1_RM_R_SFT 13
548#define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
549#define RT5651_G_OM_R_RM_R_SFT 10
550#define RT5651_M_IN2_R_RM_R (0x1 << 6)
551#define RT5651_M_IN2_R_RM_R_SFT 6
552#define RT5651_M_IN1_R_RM_R (0x1 << 5)
553#define RT5651_M_IN1_R_RM_R_SFT 5
554#define RT5651_M_BST3_RM_R (0x1 << 3)
555#define RT5651_M_BST3_RM_R_SFT 3
556#define RT5651_M_BST2_RM_R (0x1 << 2)
557#define RT5651_M_BST2_RM_R_SFT 2
558#define RT5651_M_BST1_RM_R (0x1 << 1)
559#define RT5651_M_BST1_RM_R_SFT 1
560#define RT5651_M_OM_R_RM_R (0x1)
561#define RT5651_M_OM_R_RM_R_SFT 0
562
563/* HPMIX Control (0x45) */
564#define RT5651_M_DAC1_HM (0x1 << 14)
565#define RT5651_M_DAC1_HM_SFT 14
566#define RT5651_M_HPVOL_HM (0x1 << 13)
567#define RT5651_M_HPVOL_HM_SFT 13
568#define RT5651_G_HPOMIX_MASK (0x1 << 12)
569#define RT5651_G_HPOMIX_SFT 12
570
571/* SPK Left Mixer Control (0x46) */
572#define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
573#define RT5651_G_RM_L_SM_L_SFT 14
574#define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
575#define RT5651_G_IN_L_SM_L_SFT 12
576#define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
577#define RT5651_G_DAC_L1_SM_L_SFT 10
578#define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
579#define RT5651_G_DAC_L2_SM_L_SFT 8
580#define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
581#define RT5651_G_OM_L_SM_L_SFT 6
582#define RT5651_M_RM_L_SM_L (0x1 << 5)
583#define RT5651_M_RM_L_SM_L_SFT 5
584#define RT5651_M_IN_L_SM_L (0x1 << 4)
585#define RT5651_M_IN_L_SM_L_SFT 4
586#define RT5651_M_DAC_L1_SM_L (0x1 << 3)
587#define RT5651_M_DAC_L1_SM_L_SFT 3
588#define RT5651_M_DAC_L2_SM_L (0x1 << 2)
589#define RT5651_M_DAC_L2_SM_L_SFT 2
590#define RT5651_M_OM_L_SM_L (0x1 << 1)
591#define RT5651_M_OM_L_SM_L_SFT 1
592
593/* SPK Right Mixer Control (0x47) */
594#define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
595#define RT5651_G_RM_R_SM_R_SFT 14
596#define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
597#define RT5651_G_IN_R_SM_R_SFT 12
598#define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
599#define RT5651_G_DAC_R1_SM_R_SFT 10
600#define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
601#define RT5651_G_DAC_R2_SM_R_SFT 8
602#define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
603#define RT5651_G_OM_R_SM_R_SFT 6
604#define RT5651_M_RM_R_SM_R (0x1 << 5)
605#define RT5651_M_RM_R_SM_R_SFT 5
606#define RT5651_M_IN_R_SM_R (0x1 << 4)
607#define RT5651_M_IN_R_SM_R_SFT 4
608#define RT5651_M_DAC_R1_SM_R (0x1 << 3)
609#define RT5651_M_DAC_R1_SM_R_SFT 3
610#define RT5651_M_DAC_R2_SM_R (0x1 << 2)
611#define RT5651_M_DAC_R2_SM_R_SFT 2
612#define RT5651_M_OM_R_SM_R (0x1 << 1)
613#define RT5651_M_OM_R_SM_R_SFT 1
614
615/* SPOLMIX Control (0x48) */
616#define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
617#define RT5651_M_DAC_R1_SPM_L_SFT 15
618#define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
619#define RT5651_M_DAC_L1_SPM_L_SFT 14
620#define RT5651_M_SV_R_SPM_L (0x1 << 13)
621#define RT5651_M_SV_R_SPM_L_SFT 13
622#define RT5651_M_SV_L_SPM_L (0x1 << 12)
623#define RT5651_M_SV_L_SPM_L_SFT 12
624#define RT5651_M_BST1_SPM_L (0x1 << 11)
625#define RT5651_M_BST1_SPM_L_SFT 11
626
627/* SPORMIX Control (0x49) */
628#define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
629#define RT5651_M_DAC_R1_SPM_R_SFT 13
630#define RT5651_M_SV_R_SPM_R (0x1 << 12)
631#define RT5651_M_SV_R_SPM_R_SFT 12
632#define RT5651_M_BST1_SPM_R (0x1 << 11)
633#define RT5651_M_BST1_SPM_R_SFT 11
634
635/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
636#define RT5651_SPO_CLSD_RATIO_MASK (0x7)
637#define RT5651_SPO_CLSD_RATIO_SFT 0
638
639/* Mono Output Mixer Control (0x4c) */
640#define RT5651_M_DAC_R2_MM (0x1 << 15)
641#define RT5651_M_DAC_R2_MM_SFT 15
642#define RT5651_M_DAC_L2_MM (0x1 << 14)
643#define RT5651_M_DAC_L2_MM_SFT 14
644#define RT5651_M_OV_R_MM (0x1 << 13)
645#define RT5651_M_OV_R_MM_SFT 13
646#define RT5651_M_OV_L_MM (0x1 << 12)
647#define RT5651_M_OV_L_MM_SFT 12
648#define RT5651_M_BST1_MM (0x1 << 11)
649#define RT5651_M_BST1_MM_SFT 11
650#define RT5651_G_MONOMIX_MASK (0x1 << 10)
651#define RT5651_G_MONOMIX_SFT 10
652
653/* Output Left Mixer Control 1 (0x4d) */
654#define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
655#define RT5651_G_BST2_OM_L_SFT 10
656#define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
657#define RT5651_G_BST1_OM_L_SFT 7
658#define RT5651_G_IN1_L_OM_L_MASK (0x7 << 4)
659#define RT5651_G_IN1_L_OM_L_SFT 4
660#define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
661#define RT5651_G_RM_L_OM_L_SFT 1
662
663/* Output Left Mixer Control 2 (0x4e) */
664#define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
665#define RT5651_G_DAC_L1_OM_L_SFT 7
666#define RT5651_G_IN2_L_OM_L_MASK (0x7 << 4)
667#define RT5651_G_IN2_L_OM_L_SFT 4
668
669/* Output Left Mixer Control 3 (0x4f) */
670#define RT5651_M_IN2_L_OM_L (0x1 << 9)
671#define RT5651_M_IN2_L_OM_L_SFT 9
672#define RT5651_M_BST2_OM_L (0x1 << 6)
673#define RT5651_M_BST2_OM_L_SFT 6
674#define RT5651_M_BST1_OM_L (0x1 << 5)
675#define RT5651_M_BST1_OM_L_SFT 5
676#define RT5651_M_IN1_L_OM_L (0x1 << 4)
677#define RT5651_M_IN1_L_OM_L_SFT 4
678#define RT5651_M_RM_L_OM_L (0x1 << 3)
679#define RT5651_M_RM_L_OM_L_SFT 3
680#define RT5651_M_DAC_L1_OM_L (0x1)
681#define RT5651_M_DAC_L1_OM_L_SFT 0
682
683/* Output Right Mixer Control 1 (0x50) */
684#define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
685#define RT5651_G_BST2_OM_R_SFT 10
686#define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
687#define RT5651_G_BST1_OM_R_SFT 7
688#define RT5651_G_IN1_R_OM_R_MASK (0x7 << 4)
689#define RT5651_G_IN1_R_OM_R_SFT 4
690#define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
691#define RT5651_G_RM_R_OM_R_SFT 1
692
693/* Output Right Mixer Control 2 (0x51) */
694#define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
695#define RT5651_G_DAC_R1_OM_R_SFT 7
696#define RT5651_G_IN2_R_OM_R_MASK (0x7 << 4)
697#define RT5651_G_IN2_R_OM_R_SFT 4
698
699/* Output Right Mixer Control 3 (0x52) */
700#define RT5651_M_IN2_R_OM_R (0x1 << 9)
701#define RT5651_M_IN2_R_OM_R_SFT 9
702#define RT5651_M_BST2_OM_R (0x1 << 6)
703#define RT5651_M_BST2_OM_R_SFT 6
704#define RT5651_M_BST1_OM_R (0x1 << 5)
705#define RT5651_M_BST1_OM_R_SFT 5
706#define RT5651_M_IN1_R_OM_R (0x1 << 4)
707#define RT5651_M_IN1_R_OM_R_SFT 4
708#define RT5651_M_RM_R_OM_R (0x1 << 3)
709#define RT5651_M_RM_R_OM_R_SFT 3
710#define RT5651_M_DAC_R1_OM_R (0x1)
711#define RT5651_M_DAC_R1_OM_R_SFT 0
712
713/* LOUT Mixer Control (0x53) */
714#define RT5651_M_DAC_L1_LM (0x1 << 15)
715#define RT5651_M_DAC_L1_LM_SFT 15
716#define RT5651_M_DAC_R1_LM (0x1 << 14)
717#define RT5651_M_DAC_R1_LM_SFT 14
718#define RT5651_M_OV_L_LM (0x1 << 13)
719#define RT5651_M_OV_L_LM_SFT 13
720#define RT5651_M_OV_R_LM (0x1 << 12)
721#define RT5651_M_OV_R_LM_SFT 12
722#define RT5651_G_LOUTMIX_MASK (0x1 << 11)
723#define RT5651_G_LOUTMIX_SFT 11
724
725/* Power Management for Digital 1 (0x61) */
726#define RT5651_PWR_I2S1 (0x1 << 15)
727#define RT5651_PWR_I2S1_BIT 15
728#define RT5651_PWR_I2S2 (0x1 << 14)
729#define RT5651_PWR_I2S2_BIT 14
730#define RT5651_PWR_DAC_L1 (0x1 << 12)
731#define RT5651_PWR_DAC_L1_BIT 12
732#define RT5651_PWR_DAC_R1 (0x1 << 11)
733#define RT5651_PWR_DAC_R1_BIT 11
734#define RT5651_PWR_ADC_L (0x1 << 2)
735#define RT5651_PWR_ADC_L_BIT 2
736#define RT5651_PWR_ADC_R (0x1 << 1)
737#define RT5651_PWR_ADC_R_BIT 1
738
739/* Power Management for Digital 2 (0x62) */
740#define RT5651_PWR_ADC_STO1_F (0x1 << 15)
741#define RT5651_PWR_ADC_STO1_F_BIT 15
742#define RT5651_PWR_ADC_STO2_F (0x1 << 14)
743#define RT5651_PWR_ADC_STO2_F_BIT 14
744#define RT5651_PWR_DAC_STO1_F (0x1 << 11)
745#define RT5651_PWR_DAC_STO1_F_BIT 11
746#define RT5651_PWR_DAC_STO2_F (0x1 << 10)
747#define RT5651_PWR_DAC_STO2_F_BIT 10
748#define RT5651_PWR_PDM (0x1 << 9)
749#define RT5651_PWR_PDM_BIT 9
750
751/* Power Management for Analog 1 (0x63) */
752#define RT5651_PWR_VREF1 (0x1 << 15)
753#define RT5651_PWR_VREF1_BIT 15
754#define RT5651_PWR_FV1 (0x1 << 14)
755#define RT5651_PWR_FV1_BIT 14
756#define RT5651_PWR_MB (0x1 << 13)
757#define RT5651_PWR_MB_BIT 13
758#define RT5651_PWR_LM (0x1 << 12)
759#define RT5651_PWR_LM_BIT 12
760#define RT5651_PWR_BG (0x1 << 11)
761#define RT5651_PWR_BG_BIT 11
762#define RT5651_PWR_HP_L (0x1 << 7)
763#define RT5651_PWR_HP_L_BIT 7
764#define RT5651_PWR_HP_R (0x1 << 6)
765#define RT5651_PWR_HP_R_BIT 6
766#define RT5651_PWR_HA (0x1 << 5)
767#define RT5651_PWR_HA_BIT 5
768#define RT5651_PWR_VREF2 (0x1 << 4)
769#define RT5651_PWR_VREF2_BIT 4
770#define RT5651_PWR_FV2 (0x1 << 3)
771#define RT5651_PWR_FV2_BIT 3
772#define RT5651_PWR_LDO (0x1 << 2)
773#define RT5651_PWR_LDO_BIT 2
774#define RT5651_PWR_LDO_DVO_MASK (0x3)
775#define RT5651_PWR_LDO_DVO_1_0V 0
776#define RT5651_PWR_LDO_DVO_1_1V 1
777#define RT5651_PWR_LDO_DVO_1_2V 2
778#define RT5651_PWR_LDO_DVO_1_3V 3
779
780/* Power Management for Analog 2 (0x64) */
781#define RT5651_PWR_BST1 (0x1 << 15)
782#define RT5651_PWR_BST1_BIT 15
783#define RT5651_PWR_BST2 (0x1 << 14)
784#define RT5651_PWR_BST2_BIT 14
785#define RT5651_PWR_BST3 (0x1 << 13)
786#define RT5651_PWR_BST3_BIT 13
787#define RT5651_PWR_MB1 (0x1 << 11)
788#define RT5651_PWR_MB1_BIT 11
789#define RT5651_PWR_PLL (0x1 << 9)
790#define RT5651_PWR_PLL_BIT 9
791#define RT5651_PWR_BST1_OP2 (0x1 << 5)
792#define RT5651_PWR_BST1_OP2_BIT 5
793#define RT5651_PWR_BST2_OP2 (0x1 << 4)
794#define RT5651_PWR_BST2_OP2_BIT 4
795#define RT5651_PWR_BST3_OP2 (0x1 << 3)
796#define RT5651_PWR_BST3_OP2_BIT 3
797#define RT5651_PWR_JD_M (0x1 << 2)
798#define RT5651_PWM_JD_M_BIT 2
799#define RT5651_PWR_JD2 (0x1 << 1)
800#define RT5651_PWM_JD2_BIT 1
801#define RT5651_PWR_JD3 (0x1)
802#define RT5651_PWM_JD3_BIT 0
803
804/* Power Management for Mixer (0x65) */
805#define RT5651_PWR_OM_L (0x1 << 15)
806#define RT5651_PWR_OM_L_BIT 15
807#define RT5651_PWR_OM_R (0x1 << 14)
808#define RT5651_PWR_OM_R_BIT 14
809#define RT5651_PWR_RM_L (0x1 << 11)
810#define RT5651_PWR_RM_L_BIT 11
811#define RT5651_PWR_RM_R (0x1 << 10)
812#define RT5651_PWR_RM_R_BIT 10
813
814/* Power Management for Volume (0x66) */
815#define RT5651_PWR_OV_L (0x1 << 13)
816#define RT5651_PWR_OV_L_BIT 13
817#define RT5651_PWR_OV_R (0x1 << 12)
818#define RT5651_PWR_OV_R_BIT 12
819#define RT5651_PWR_HV_L (0x1 << 11)
820#define RT5651_PWR_HV_L_BIT 11
821#define RT5651_PWR_HV_R (0x1 << 10)
822#define RT5651_PWR_HV_R_BIT 10
823#define RT5651_PWR_IN1_L (0x1 << 9)
824#define RT5651_PWR_IN1_L_BIT 9
825#define RT5651_PWR_IN1_R (0x1 << 8)
826#define RT5651_PWR_IN1_R_BIT 8
827#define RT5651_PWR_IN2_L (0x1 << 7)
828#define RT5651_PWR_IN2_L_BIT 7
829#define RT5651_PWR_IN2_R (0x1 << 6)
830#define RT5651_PWR_IN2_R_BIT 6
831
832/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
833#define RT5651_I2S_MS_MASK (0x1 << 15)
834#define RT5651_I2S_MS_SFT 15
835#define RT5651_I2S_MS_M (0x0 << 15)
836#define RT5651_I2S_MS_S (0x1 << 15)
837#define RT5651_I2S_O_CP_MASK (0x3 << 10)
838#define RT5651_I2S_O_CP_SFT 10
839#define RT5651_I2S_O_CP_OFF (0x0 << 10)
840#define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
841#define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
842#define RT5651_I2S_I_CP_MASK (0x3 << 8)
843#define RT5651_I2S_I_CP_SFT 8
844#define RT5651_I2S_I_CP_OFF (0x0 << 8)
845#define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
846#define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
847#define RT5651_I2S_BP_MASK (0x1 << 7)
848#define RT5651_I2S_BP_SFT 7
849#define RT5651_I2S_BP_NOR (0x0 << 7)
850#define RT5651_I2S_BP_INV (0x1 << 7)
851#define RT5651_I2S_DL_MASK (0x3 << 2)
852#define RT5651_I2S_DL_SFT 2
853#define RT5651_I2S_DL_16 (0x0 << 2)
854#define RT5651_I2S_DL_20 (0x1 << 2)
855#define RT5651_I2S_DL_24 (0x2 << 2)
856#define RT5651_I2S_DL_8 (0x3 << 2)
857#define RT5651_I2S_DF_MASK (0x3)
858#define RT5651_I2S_DF_SFT 0
859#define RT5651_I2S_DF_I2S (0x0)
860#define RT5651_I2S_DF_LEFT (0x1)
861#define RT5651_I2S_DF_PCM_A (0x2)
862#define RT5651_I2S_DF_PCM_B (0x3)
863
864/* ADC/DAC Clock Control 1 (0x73) */
865#define RT5651_I2S_PD1_MASK (0x7 << 12)
866#define RT5651_I2S_PD1_SFT 12
867#define RT5651_I2S_PD1_1 (0x0 << 12)
868#define RT5651_I2S_PD1_2 (0x1 << 12)
869#define RT5651_I2S_PD1_3 (0x2 << 12)
870#define RT5651_I2S_PD1_4 (0x3 << 12)
871#define RT5651_I2S_PD1_6 (0x4 << 12)
872#define RT5651_I2S_PD1_8 (0x5 << 12)
873#define RT5651_I2S_PD1_12 (0x6 << 12)
874#define RT5651_I2S_PD1_16 (0x7 << 12)
875#define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
876#define RT5651_I2S_BCLK_MS2_SFT 11
877#define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
878#define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
879#define RT5651_I2S_PD2_MASK (0x7 << 8)
880#define RT5651_I2S_PD2_SFT 8
881#define RT5651_I2S_PD2_1 (0x0 << 8)
882#define RT5651_I2S_PD2_2 (0x1 << 8)
883#define RT5651_I2S_PD2_3 (0x2 << 8)
884#define RT5651_I2S_PD2_4 (0x3 << 8)
885#define RT5651_I2S_PD2_6 (0x4 << 8)
886#define RT5651_I2S_PD2_8 (0x5 << 8)
887#define RT5651_I2S_PD2_12 (0x6 << 8)
888#define RT5651_I2S_PD2_16 (0x7 << 8)
889#define RT5651_DAC_OSR_MASK (0x3 << 2)
890#define RT5651_DAC_OSR_SFT 2
891#define RT5651_DAC_OSR_128 (0x0 << 2)
892#define RT5651_DAC_OSR_64 (0x1 << 2)
893#define RT5651_DAC_OSR_32 (0x2 << 2)
894#define RT5651_DAC_OSR_128_3 (0x3 << 2)
895#define RT5651_ADC_OSR_MASK (0x3)
896#define RT5651_ADC_OSR_SFT 0
897#define RT5651_ADC_OSR_128 (0x0)
898#define RT5651_ADC_OSR_64 (0x1)
899#define RT5651_ADC_OSR_32 (0x2)
900#define RT5651_ADC_OSR_128_3 (0x3)
901
902/* ADC/DAC Clock Control 2 (0x74) */
903#define RT5651_DAHPF_EN (0x1 << 11)
904#define RT5651_DAHPF_EN_SFT 11
905#define RT5651_ADHPF_EN (0x1 << 10)
906#define RT5651_ADHPF_EN_SFT 10
907
908/* Digital Microphone Control (0x75) */
909#define RT5651_DMIC_1_EN_MASK (0x1 << 15)
910#define RT5651_DMIC_1_EN_SFT 15
911#define RT5651_DMIC_1_DIS (0x0 << 15)
912#define RT5651_DMIC_1_EN (0x1 << 15)
913#define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
914#define RT5651_DMIC_1L_LH_SFT 13
915#define RT5651_DMIC_1L_LH_FALLING (0x0 << 13)
916#define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
917#define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
918#define RT5651_DMIC_1R_LH_SFT 12
919#define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
920#define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
921#define RT5651_DMIC_1_DP_MASK (0x3 << 10)
922#define RT5651_DMIC_1_DP_SFT 10
923#define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
924#define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
925#define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
926#define RT5651_DMIC_CLK_MASK (0x7 << 5)
927#define RT5651_DMIC_CLK_SFT 5
928
929/* TDM Control 1 (0x77) */
930#define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
931#define RT5651_TDM_INTEL_SEL_SFT 15
932#define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
933#define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
934#define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
935#define RT5651_TDM_MODE_SEL_SFT 14
936#define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
937#define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
938#define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
939#define RT5651_TDM_CH_NUM_SEL_SFT 12
940#define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
941#define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
942#define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
943#define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
944#define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
945#define RT5651_TDM_CH_LEN_SEL_SFT 10
946#define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
947#define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
948#define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
949#define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
950#define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
951#define RT5651_TDM_ADC_SEL_SFT 9
952#define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
953#define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
954#define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
955#define RT5651_TDM_ADC_START_SEL_SFT 8
956#define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
957#define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
958#define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
959#define RT5651_TDM_I2S_CH2_SEL_SFT 6
960#define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
961#define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
962#define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
963#define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
964#define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
965#define RT5651_TDM_I2S_CH4_SEL_SFT 4
966#define RT5651_TDM_I2S_CH4_SEL_LR (0x0 << 4)
967#define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
968#define RT5651_TDM_I2S_CH4_SEL_LL (0x2 << 4)
969#define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
970#define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
971#define RT5651_TDM_I2S_CH6_SEL_SFT 2
972#define RT5651_TDM_I2S_CH6_SEL_LR (0x0 << 2)
973#define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
974#define RT5651_TDM_I2S_CH6_SEL_LL (0x2 << 2)
975#define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
976#define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
977#define RT5651_TDM_I2S_CH8_SEL_SFT 0
978#define RT5651_TDM_I2S_CH8_SEL_LR (0x0)
979#define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
980#define RT5651_TDM_I2S_CH8_SEL_LL (0x2)
981#define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
982
983/* TDM Control 2 (0x78) */
984#define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
985#define RT5651_TDM_LRCK_POL_SEL_SFT 15
986#define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
987#define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
988#define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
989#define RT5651_TDM_CH_VAL_SEL_SFT 14
990#define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
991#define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
992#define RT5651_TDM_CH_VAL_EN (0x1 << 13)
993#define RT5651_TDM_CH_VAL_SFT 13
994#define RT5651_TDM_LPBK_EN (0x1 << 12)
995#define RT5651_TDM_LPBK_SFT 12
996#define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
997#define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
998#define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
999#define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1000#define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1001#define RT5651_TDM_END_EDGE_SEL_SFT 10
1002#define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1003#define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1004#define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1005#define RT5651_TDM_END_EDGE_EN_SFT 9
1006#define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1007#define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
1008#define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1009#define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1010#define RT5651_M_TDM2_L (0x1 << 7)
1011#define RT5651_M_TDM2_L_SFT 7
1012#define RT5651_M_TDM2_R (0x1 << 6)
1013#define RT5651_M_TDM2_R_SFT 6
1014#define RT5651_M_TDM4_L (0x1 << 5)
1015#define RT5651_M_TDM4_L_SFT 5
1016#define RT5651_M_TDM4_R (0x1 << 4)
1017#define RT5651_M_TDM4_R_SFT 4
1018
1019/* TDM Control 3 (0x79) */
1020#define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1021#define RT5651_CH2_L_SEL_SFT 12
1022#define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1023#define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1024#define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1025#define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1026#define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1027#define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1028#define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1029#define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1030#define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1031#define RT5651_CH2_R_SEL_SFT 8
1032#define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1033#define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1034#define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1035#define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1036#define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1037#define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1038#define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1039#define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1040#define RT5651_CH4_L_SEL_MASK (0x7 << 4)
1041#define RT5651_CH4_L_SEL_SFT 4
1042#define RT5651_CH4_L_SEL_SL0 (0x0 << 4)
1043#define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1044#define RT5651_CH4_L_SEL_SL2 (0x2 << 4)
1045#define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
1046#define RT5651_CH4_L_SEL_SL4 (0x4 << 4)
1047#define RT5651_CH4_L_SEL_SL5 (0x5 << 4)
1048#define RT5651_CH4_L_SEL_SL6 (0x6 << 4)
1049#define RT5651_CH4_L_SEL_SL7 (0x7 << 4)
1050#define RT5651_CH4_R_SEL_MASK (0x7)
1051#define RT5651_CH4_R_SEL_SFT 0
1052#define RT5651_CH4_R_SEL_SL0 (0x0)
1053#define RT5651_CH4_R_SEL_SL1 (0x1)
1054#define RT5651_CH4_R_SEL_SL2 (0x2)
1055#define RT5651_CH4_R_SEL_SL3 (0x3)
1056#define RT5651_CH4_R_SEL_SL4 (0x4)
1057#define RT5651_CH4_R_SEL_SL5 (0x5)
1058#define RT5651_CH4_R_SEL_SL6 (0x6)
1059#define RT5651_CH4_R_SEL_SL7 (0x7)
1060
1061/* Global Clock Control (0x80) */
1062#define RT5651_SCLK_SRC_MASK (0x3 << 14)
1063#define RT5651_SCLK_SRC_SFT 14
1064#define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1065#define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1066#define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1067#define RT5651_PLL1_SRC_MASK (0x3 << 12)
1068#define RT5651_PLL1_SRC_SFT 12
1069#define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1070#define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1071#define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1072#define RT5651_PLL1_PD_MASK (0x1 << 3)
1073#define RT5651_PLL1_PD_SFT 3
1074#define RT5651_PLL1_PD_1 (0x0 << 3)
1075#define RT5651_PLL1_PD_2 (0x1 << 3)
1076
1077#define RT5651_PLL_INP_MAX 40000000
1078#define RT5651_PLL_INP_MIN 256000
1079/* PLL M/N/K Code Control 1 (0x81) */
1080#define RT5651_PLL_N_MAX 0x1ff
1081#define RT5651_PLL_N_MASK (RT5651_PLL_N_MAX << 7)
1082#define RT5651_PLL_N_SFT 7
1083#define RT5651_PLL_K_MAX 0x1f
1084#define RT5651_PLL_K_MASK (RT5651_PLL_K_MAX)
1085#define RT5651_PLL_K_SFT 0
1086
1087/* PLL M/N/K Code Control 2 (0x82) */
1088#define RT5651_PLL_M_MAX 0xf
1089#define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
1090#define RT5651_PLL_M_SFT 12
1091#define RT5651_PLL_M_BP (0x1 << 11)
1092#define RT5651_PLL_M_BP_SFT 11
1093
1094/* PLL tracking mode 1 (0x83) */
1095#define RT5651_STO1_T_MASK (0x1 << 15)
1096#define RT5651_STO1_T_SFT 15
1097#define RT5651_STO1_T_SCLK (0x0 << 15)
1098#define RT5651_STO1_T_LRCK1 (0x1 << 15)
1099#define RT5651_STO2_T_MASK (0x1 << 12)
1100#define RT5651_STO2_T_SFT 12
1101#define RT5651_STO2_T_I2S2 (0x0 << 12)
1102#define RT5651_STO2_T_LRCK2 (0x1 << 12)
1103#define RT5651_ASRC2_REF_MASK (0x1 << 11)
1104#define RT5651_ASRC2_REF_SFT 11
1105#define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1106#define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1107#define RT5651_DMIC_1_M_MASK (0x1 << 9)
1108#define RT5651_DMIC_1_M_SFT 9
1109#define RT5651_DMIC_1_M_NOR (0x0 << 9)
1110#define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1111
1112/* PLL tracking mode 2 (0x84) */
1113#define RT5651_STO1_ASRC_EN (0x1 << 15)
1114#define RT5651_STO1_ASRC_EN_SFT 15
1115#define RT5651_STO2_ASRC_EN (0x1 << 14)
1116#define RT5651_STO2_ASRC_EN_SFT 14
1117#define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1118#define RT5651_STO1_DAC_M_SFT 13
1119#define RT5651_STO1_DAC_M_NOR (0x0 << 13)
1120#define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1121#define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1122#define RT5651_STO2_DAC_M_SFT 12
1123#define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1124#define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1125#define RT5651_ADC_M_MASK (0x1 << 11)
1126#define RT5651_ADC_M_SFT 11
1127#define RT5651_ADC_M_NOR (0x0 << 11)
1128#define RT5651_ADC_M_ASRC (0x1 << 11)
1129#define RT5651_I2S1_R_D_MASK (0x1 << 4)
1130#define RT5651_I2S1_R_D_SFT 4
1131#define RT5651_I2S1_R_D_DIS (0x0 << 4)
1132#define RT5651_I2S1_R_D_EN (0x1 << 4)
1133#define RT5651_I2S2_R_D_MASK (0x1 << 3)
1134#define RT5651_I2S2_R_D_SFT 3
1135#define RT5651_I2S2_R_D_DIS (0x0 << 3)
1136#define RT5651_I2S2_R_D_EN (0x1 << 3)
1137#define RT5651_PRE_SCLK_MASK (0x3)
1138#define RT5651_PRE_SCLK_SFT 0
1139#define RT5651_PRE_SCLK_512 (0x0)
1140#define RT5651_PRE_SCLK_1024 (0x1)
1141#define RT5651_PRE_SCLK_2048 (0x2)
1142
1143/* PLL tracking mode 3 (0x85) */
1144#define RT5651_I2S1_RATE_MASK (0xf << 12)
1145#define RT5651_I2S1_RATE_SFT 12
1146#define RT5651_I2S2_RATE_MASK (0xf << 8)
1147#define RT5651_I2S2_RATE_SFT 8
1148#define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1149#define RT5651_G_ASRC_LP_SFT 3
1150#define RT5651_ASRC_LP_F_M (0x1 << 2)
1151#define RT5651_ASRC_LP_F_SFT 2
1152#define RT5651_ASRC_LP_F_NOR (0x0 << 2)
1153#define RT5651_ASRC_LP_F_SB (0x1 << 2)
1154#define RT5651_FTK_PH_DET_MASK (0x3)
1155#define RT5651_FTK_PH_DET_SFT 0
1156#define RT5651_FTK_PH_DET_DIV1 (0x0)
1157#define RT5651_FTK_PH_DET_DIV2 (0x1)
1158#define RT5651_FTK_PH_DET_DIV4 (0x2)
1159#define RT5651_FTK_PH_DET_DIV8 (0x3)
1160
1161/*PLL tracking mode 6 (0x89) */
1162#define RT5651_I2S1_PD_MASK (0x7 << 12)
1163#define RT5651_I2S1_PD_SFT 12
1164#define RT5651_I2S2_PD_MASK (0x7 << 8)
1165#define RT5651_I2S2_PD_SFT 8
1166
1167/*PLL tracking mode 7 (0x8a) */
1168#define RT5651_FSI1_RATE_MASK (0xf << 12)
1169#define RT5651_FSI1_RATE_SFT 12
1170#define RT5651_FSI2_RATE_MASK (0xf << 8)
1171#define RT5651_FSI2_RATE_SFT 8
1172
1173/* HPOUT Over Current Detection (0x8b) */
1174#define RT5651_HP_OVCD_MASK (0x1 << 10)
1175#define RT5651_HP_OVCD_SFT 10
1176#define RT5651_HP_OVCD_DIS (0x0 << 10)
1177#define RT5651_HP_OVCD_EN (0x1 << 10)
1178#define RT5651_HP_OC_TH_MASK (0x3 << 8)
1179#define RT5651_HP_OC_TH_SFT 8
1180#define RT5651_HP_OC_TH_90 (0x0 << 8)
1181#define RT5651_HP_OC_TH_105 (0x1 << 8)
1182#define RT5651_HP_OC_TH_120 (0x2 << 8)
1183#define RT5651_HP_OC_TH_135 (0x3 << 8)
1184
1185/* Depop Mode Control 1 (0x8e) */
1186#define RT5651_SMT_TRIG_MASK (0x1 << 15)
1187#define RT5651_SMT_TRIG_SFT 15
1188#define RT5651_SMT_TRIG_DIS (0x0 << 15)
1189#define RT5651_SMT_TRIG_EN (0x1 << 15)
1190#define RT5651_HP_L_SMT_MASK (0x1 << 9)
1191#define RT5651_HP_L_SMT_SFT 9
1192#define RT5651_HP_L_SMT_DIS (0x0 << 9)
1193#define RT5651_HP_L_SMT_EN (0x1 << 9)
1194#define RT5651_HP_R_SMT_MASK (0x1 << 8)
1195#define RT5651_HP_R_SMT_SFT 8
1196#define RT5651_HP_R_SMT_DIS (0x0 << 8)
1197#define RT5651_HP_R_SMT_EN (0x1 << 8)
1198#define RT5651_HP_CD_PD_MASK (0x1 << 7)
1199#define RT5651_HP_CD_PD_SFT 7
1200#define RT5651_HP_CD_PD_DIS (0x0 << 7)
1201#define RT5651_HP_CD_PD_EN (0x1 << 7)
1202#define RT5651_RSTN_MASK (0x1 << 6)
1203#define RT5651_RSTN_SFT 6
1204#define RT5651_RSTN_DIS (0x0 << 6)
1205#define RT5651_RSTN_EN (0x1 << 6)
1206#define RT5651_RSTP_MASK (0x1 << 5)
1207#define RT5651_RSTP_SFT 5
1208#define RT5651_RSTP_DIS (0x0 << 5)
1209#define RT5651_RSTP_EN (0x1 << 5)
1210#define RT5651_HP_CO_MASK (0x1 << 4)
1211#define RT5651_HP_CO_SFT 4
1212#define RT5651_HP_CO_DIS (0x0 << 4)
1213#define RT5651_HP_CO_EN (0x1 << 4)
1214#define RT5651_HP_CP_MASK (0x1 << 3)
1215#define RT5651_HP_CP_SFT 3
1216#define RT5651_HP_CP_PD (0x0 << 3)
1217#define RT5651_HP_CP_PU (0x1 << 3)
1218#define RT5651_HP_SG_MASK (0x1 << 2)
1219#define RT5651_HP_SG_SFT 2
1220#define RT5651_HP_SG_DIS (0x0 << 2)
1221#define RT5651_HP_SG_EN (0x1 << 2)
1222#define RT5651_HP_DP_MASK (0x1 << 1)
1223#define RT5651_HP_DP_SFT 1
1224#define RT5651_HP_DP_PD (0x0 << 1)
1225#define RT5651_HP_DP_PU (0x1 << 1)
1226#define RT5651_HP_CB_MASK (0x1)
1227#define RT5651_HP_CB_SFT 0
1228#define RT5651_HP_CB_PD (0x0)
1229#define RT5651_HP_CB_PU (0x1)
1230
1231/* Depop Mode Control 2 (0x8f) */
1232#define RT5651_DEPOP_MASK (0x1 << 13)
1233#define RT5651_DEPOP_SFT 13
1234#define RT5651_DEPOP_AUTO (0x0 << 13)
1235#define RT5651_DEPOP_MAN (0x1 << 13)
1236#define RT5651_RAMP_MASK (0x1 << 12)
1237#define RT5651_RAMP_SFT 12
1238#define RT5651_RAMP_DIS (0x0 << 12)
1239#define RT5651_RAMP_EN (0x1 << 12)
1240#define RT5651_BPS_MASK (0x1 << 11)
1241#define RT5651_BPS_SFT 11
1242#define RT5651_BPS_DIS (0x0 << 11)
1243#define RT5651_BPS_EN (0x1 << 11)
1244#define RT5651_FAST_UPDN_MASK (0x1 << 10)
1245#define RT5651_FAST_UPDN_SFT 10
1246#define RT5651_FAST_UPDN_DIS (0x0 << 10)
1247#define RT5651_FAST_UPDN_EN (0x1 << 10)
1248#define RT5651_MRES_MASK (0x3 << 8)
1249#define RT5651_MRES_SFT 8
1250#define RT5651_MRES_15MO (0x0 << 8)
1251#define RT5651_MRES_25MO (0x1 << 8)
1252#define RT5651_MRES_35MO (0x2 << 8)
1253#define RT5651_MRES_45MO (0x3 << 8)
1254#define RT5651_VLO_MASK (0x1 << 7)
1255#define RT5651_VLO_SFT 7
1256#define RT5651_VLO_3V (0x0 << 7)
1257#define RT5651_VLO_32V (0x1 << 7)
1258#define RT5651_DIG_DP_MASK (0x1 << 6)
1259#define RT5651_DIG_DP_SFT 6
1260#define RT5651_DIG_DP_DIS (0x0 << 6)
1261#define RT5651_DIG_DP_EN (0x1 << 6)
1262#define RT5651_DP_TH_MASK (0x3 << 4)
1263#define RT5651_DP_TH_SFT 4
1264
1265/* Depop Mode Control 3 (0x90) */
1266#define RT5651_CP_SYS_MASK (0x7 << 12)
1267#define RT5651_CP_SYS_SFT 12
1268#define RT5651_CP_FQ1_MASK (0x7 << 8)
1269#define RT5651_CP_FQ1_SFT 8
1270#define RT5651_CP_FQ2_MASK (0x7 << 4)
1271#define RT5651_CP_FQ2_SFT 4
1272#define RT5651_CP_FQ3_MASK (0x7)
1273#define RT5651_CP_FQ3_SFT 0
1274#define RT5651_CP_FQ_1_5_KHZ 0
1275#define RT5651_CP_FQ_3_KHZ 1
1276#define RT5651_CP_FQ_6_KHZ 2
1277#define RT5651_CP_FQ_12_KHZ 3
1278#define RT5651_CP_FQ_24_KHZ 4
1279#define RT5651_CP_FQ_48_KHZ 5
1280#define RT5651_CP_FQ_96_KHZ 6
1281#define RT5651_CP_FQ_192_KHZ 7
1282
1283/* HPOUT charge pump (0x91) */
1284#define RT5651_OSW_L_MASK (0x1 << 11)
1285#define RT5651_OSW_L_SFT 11
1286#define RT5651_OSW_L_DIS (0x0 << 11)
1287#define RT5651_OSW_L_EN (0x1 << 11)
1288#define RT5651_OSW_R_MASK (0x1 << 10)
1289#define RT5651_OSW_R_SFT 10
1290#define RT5651_OSW_R_DIS (0x0 << 10)
1291#define RT5651_OSW_R_EN (0x1 << 10)
1292#define RT5651_PM_HP_MASK (0x3 << 8)
1293#define RT5651_PM_HP_SFT 8
1294#define RT5651_PM_HP_LV (0x0 << 8)
1295#define RT5651_PM_HP_MV (0x1 << 8)
1296#define RT5651_PM_HP_HV (0x2 << 8)
1297#define RT5651_IB_HP_MASK (0x3 << 6)
1298#define RT5651_IB_HP_SFT 6
1299#define RT5651_IB_HP_125IL (0x0 << 6)
1300#define RT5651_IB_HP_25IL (0x1 << 6)
1301#define RT5651_IB_HP_5IL (0x2 << 6)
1302#define RT5651_IB_HP_1IL (0x3 << 6)
1303
1304/* Micbias Control (0x93) */
1305#define RT5651_MIC1_BS_MASK (0x1 << 15)
1306#define RT5651_MIC1_BS_SFT 15
1307#define RT5651_MIC1_BS_9AV (0x0 << 15)
1308#define RT5651_MIC1_BS_75AV (0x1 << 15)
1309#define RT5651_MIC1_CLK_MASK (0x1 << 13)
1310#define RT5651_MIC1_CLK_SFT 13
1311#define RT5651_MIC1_CLK_DIS (0x0 << 13)
1312#define RT5651_MIC1_CLK_EN (0x1 << 13)
1313#define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1314#define RT5651_MIC1_OVCD_SFT 11
1315#define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1316#define RT5651_MIC1_OVCD_EN (0x1 << 11)
1317#define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1318#define RT5651_MIC1_OVTH_SFT 9
1319#define RT5651_MIC1_OVTH_600UA (0x0 << 9)
1320#define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1321#define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
1322#define RT5651_PWR_MB_MASK (0x1 << 5)
1323#define RT5651_PWR_MB_SFT 5
1324#define RT5651_PWR_MB_PD (0x0 << 5)
1325#define RT5651_PWR_MB_PU (0x1 << 5)
1326#define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1327#define RT5651_PWR_CLK12M_SFT 4
1328#define RT5651_PWR_CLK12M_PD (0x0 << 4)
1329#define RT5651_PWR_CLK12M_PU (0x1 << 4)
1330
1331/* Analog JD Control 1 (0x94) */
1332#define RT5651_JD2_CMP_MASK (0x7 << 12)
1333#define RT5651_JD2_CMP_SFT 12
1334#define RT5651_JD_PU (0x1 << 11)
1335#define RT5651_JD_PU_SFT 11
1336#define RT5651_JD_PD (0x1 << 10)
1337#define RT5651_JD_PD_SFT 10
1338#define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1339#define RT5651_JD_MODE_SEL_SFT 8
1340#define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1341#define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1342#define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1343#define RT5651_JD_M_CMP (0x7 << 4)
1344#define RT5651_JD_M_CMP_SFT 4
1345#define RT5651_JD_M_PU (0x1 << 3)
1346#define RT5651_JD_M_PU_SFT 3
1347#define RT5651_JD_M_PD (0x1 << 2)
1348#define RT5651_JD_M_PD_SFT 2
1349#define RT5651_JD_M_MODE_SEL_MASK (0x3)
1350#define RT5651_JD_M_MODE_SEL_SFT 0
1351#define RT5651_JD_M_MODE_SEL_M0 (0x0)
1352#define RT5651_JD_M_MODE_SEL_M1 (0x1)
1353#define RT5651_JD_M_MODE_SEL_M2 (0x2)
1354
1355/* Analog JD Control 2 (0x95) */
1356#define RT5651_JD3_CMP_MASK (0x7 << 12)
1357#define RT5651_JD3_CMP_SFT 12
1358
1359/* EQ Control 1 (0xb0) */
1360#define RT5651_EQ_SRC_MASK (0x1 << 15)
1361#define RT5651_EQ_SRC_SFT 15
1362#define RT5651_EQ_SRC_DAC (0x0 << 15)
1363#define RT5651_EQ_SRC_ADC (0x1 << 15)
1364#define RT5651_EQ_UPD (0x1 << 14)
1365#define RT5651_EQ_UPD_BIT 14
1366#define RT5651_EQ_CD_MASK (0x1 << 13)
1367#define RT5651_EQ_CD_SFT 13
1368#define RT5651_EQ_CD_DIS (0x0 << 13)
1369#define RT5651_EQ_CD_EN (0x1 << 13)
1370#define RT5651_EQ_DITH_MASK (0x3 << 8)
1371#define RT5651_EQ_DITH_SFT 8
1372#define RT5651_EQ_DITH_NOR (0x0 << 8)
1373#define RT5651_EQ_DITH_LSB (0x1 << 8)
1374#define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1375#define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1376#define RT5651_EQ_CD_F (0x1 << 7)
1377#define RT5651_EQ_CD_F_BIT 7
1378#define RT5651_EQ_STA_HP2 (0x1 << 6)
1379#define RT5651_EQ_STA_HP2_BIT 6
1380#define RT5651_EQ_STA_HP1 (0x1 << 5)
1381#define RT5651_EQ_STA_HP1_BIT 5
1382#define RT5651_EQ_STA_BP4 (0x1 << 4)
1383#define RT5651_EQ_STA_BP4_BIT 4
1384#define RT5651_EQ_STA_BP3 (0x1 << 3)
1385#define RT5651_EQ_STA_BP3_BIT 3
1386#define RT5651_EQ_STA_BP2 (0x1 << 2)
1387#define RT5651_EQ_STA_BP2_BIT 2
1388#define RT5651_EQ_STA_BP1 (0x1 << 1)
1389#define RT5651_EQ_STA_BP1_BIT 1
1390#define RT5651_EQ_STA_LP (0x1)
1391#define RT5651_EQ_STA_LP_BIT 0
1392
1393/* EQ Control 2 (0xb1) */
1394#define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1395#define RT5651_EQ_HPF1_M_SFT 8
1396#define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1397#define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1398#define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1399#define RT5651_EQ_LPF1_M_SFT 7
1400#define RT5651_EQ_LPF1_M_LO (0x0 << 7)
1401#define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1402#define RT5651_EQ_HPF2_MASK (0x1 << 6)
1403#define RT5651_EQ_HPF2_SFT 6
1404#define RT5651_EQ_HPF2_DIS (0x0 << 6)
1405#define RT5651_EQ_HPF2_EN (0x1 << 6)
1406#define RT5651_EQ_HPF1_MASK (0x1 << 5)
1407#define RT5651_EQ_HPF1_SFT 5
1408#define RT5651_EQ_HPF1_DIS (0x0 << 5)
1409#define RT5651_EQ_HPF1_EN (0x1 << 5)
1410#define RT5651_EQ_BPF4_MASK (0x1 << 4)
1411#define RT5651_EQ_BPF4_SFT 4
1412#define RT5651_EQ_BPF4_DIS (0x0 << 4)
1413#define RT5651_EQ_BPF4_EN (0x1 << 4)
1414#define RT5651_EQ_BPF3_MASK (0x1 << 3)
1415#define RT5651_EQ_BPF3_SFT 3
1416#define RT5651_EQ_BPF3_DIS (0x0 << 3)
1417#define RT5651_EQ_BPF3_EN (0x1 << 3)
1418#define RT5651_EQ_BPF2_MASK (0x1 << 2)
1419#define RT5651_EQ_BPF2_SFT 2
1420#define RT5651_EQ_BPF2_DIS (0x0 << 2)
1421#define RT5651_EQ_BPF2_EN (0x1 << 2)
1422#define RT5651_EQ_BPF1_MASK (0x1 << 1)
1423#define RT5651_EQ_BPF1_SFT 1
1424#define RT5651_EQ_BPF1_DIS (0x0 << 1)
1425#define RT5651_EQ_BPF1_EN (0x1 << 1)
1426#define RT5651_EQ_LPF_MASK (0x1)
1427#define RT5651_EQ_LPF_SFT 0
1428#define RT5651_EQ_LPF_DIS (0x0)
1429#define RT5651_EQ_LPF_EN (0x1)
1430#define RT5651_EQ_CTRL_MASK (0x7f)
1431
1432/* Memory Test (0xb2) */
1433#define RT5651_MT_MASK (0x1 << 15)
1434#define RT5651_MT_SFT 15
1435#define RT5651_MT_DIS (0x0 << 15)
1436#define RT5651_MT_EN (0x1 << 15)
1437
1438/* ALC Control 1 (0xb4) */
1439#define RT5651_ALC_P_MASK (0x1 << 15)
1440#define RT5651_ALC_P_SFT 15
1441#define RT5651_ALC_P_DAC (0x0 << 15)
1442#define RT5651_ALC_P_ADC (0x1 << 15)
1443#define RT5651_ALC_MASK (0x1 << 14)
1444#define RT5651_ALC_SFT 14
1445#define RT5651_ALC_DIS (0x0 << 14)
1446#define RT5651_ALC_EN (0x1 << 14)
1447#define RT5651_ALC_UPD (0x1 << 13)
1448#define RT5651_ALC_UPD_BIT 13
1449#define RT5651_ALC_AR_MASK (0x1f << 8)
1450#define RT5651_ALC_AR_SFT 8
1451#define RT5651_ALC_R_MASK (0x7 << 5)
1452#define RT5651_ALC_R_SFT 5
1453#define RT5651_ALC_R_48K (0x1 << 5)
1454#define RT5651_ALC_R_96K (0x2 << 5)
1455#define RT5651_ALC_R_192K (0x3 << 5)
1456#define RT5651_ALC_R_441K (0x5 << 5)
1457#define RT5651_ALC_R_882K (0x6 << 5)
1458#define RT5651_ALC_R_1764K (0x7 << 5)
1459#define RT5651_ALC_RC_MASK (0x1f)
1460#define RT5651_ALC_RC_SFT 0
1461
1462/* ALC Control 2 (0xb5) */
1463#define RT5651_ALC_POB_MASK (0x3f << 8)
1464#define RT5651_ALC_POB_SFT 8
1465#define RT5651_ALC_DRC_MASK (0x1 << 7)
1466#define RT5651_ALC_DRC_SFT 7
1467#define RT5651_ALC_DRC_DIS (0x0 << 7)
1468#define RT5651_ALC_DRC_EN (0x1 << 7)
1469#define RT5651_ALC_CPR_MASK (0x3 << 5)
1470#define RT5651_ALC_CPR_SFT 5
1471#define RT5651_ALC_CPR_1_1 (0x0 << 5)
1472#define RT5651_ALC_CPR_1_2 (0x1 << 5)
1473#define RT5651_ALC_CPR_1_4 (0x2 << 5)
1474#define RT5651_ALC_CPR_1_8 (0x3 << 5)
1475#define RT5651_ALC_PRB_MASK (0x1f)
1476#define RT5651_ALC_PRB_SFT 0
1477
1478/* ALC Control 3 (0xb6) */
1479#define RT5651_ALC_NGB_MASK (0xf << 12)
1480#define RT5651_ALC_NGB_SFT 12
1481#define RT5651_ALC_TAR_MASK (0x1f << 7)
1482#define RT5651_ALC_TAR_SFT 7
1483#define RT5651_ALC_NG_MASK (0x1 << 6)
1484#define RT5651_ALC_NG_SFT 6
1485#define RT5651_ALC_NG_DIS (0x0 << 6)
1486#define RT5651_ALC_NG_EN (0x1 << 6)
1487#define RT5651_ALC_NGH_MASK (0x1 << 5)
1488#define RT5651_ALC_NGH_SFT 5
1489#define RT5651_ALC_NGH_DIS (0x0 << 5)
1490#define RT5651_ALC_NGH_EN (0x1 << 5)
1491#define RT5651_ALC_NGT_MASK (0x1f)
1492#define RT5651_ALC_NGT_SFT 0
1493
1494/* Jack Detect Control 1 (0xbb) */
1495#define RT5651_JD_MASK (0x7 << 13)
1496#define RT5651_JD_SFT 13
1497#define RT5651_JD_DIS (0x0 << 13)
1498#define RT5651_JD_GPIO1 (0x1 << 13)
1499#define RT5651_JD_GPIO2 (0x2 << 13)
1500#define RT5651_JD_GPIO3 (0x3 << 13)
1501#define RT5651_JD_GPIO4 (0x4 << 13)
1502#define RT5651_JD_GPIO5 (0x5 << 13)
1503#define RT5651_JD_GPIO6 (0x6 << 13)
1504#define RT5651_JD_HP_MASK (0x1 << 11)
1505#define RT5651_JD_HP_SFT 11
1506#define RT5651_JD_HP_DIS (0x0 << 11)
1507#define RT5651_JD_HP_EN (0x1 << 11)
1508#define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1509#define RT5651_JD_HP_TRG_SFT 10
1510#define RT5651_JD_HP_TRG_LO (0x0 << 10)
1511#define RT5651_JD_HP_TRG_HI (0x1 << 10)
1512#define RT5651_JD_SPL_MASK (0x1 << 9)
1513#define RT5651_JD_SPL_SFT 9
1514#define RT5651_JD_SPL_DIS (0x0 << 9)
1515#define RT5651_JD_SPL_EN (0x1 << 9)
1516#define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1517#define RT5651_JD_SPL_TRG_SFT 8
1518#define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1519#define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1520#define RT5651_JD_SPR_MASK (0x1 << 7)
1521#define RT5651_JD_SPR_SFT 7
1522#define RT5651_JD_SPR_DIS (0x0 << 7)
1523#define RT5651_JD_SPR_EN (0x1 << 7)
1524#define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1525#define RT5651_JD_SPR_TRG_SFT 6
1526#define RT5651_JD_SPR_TRG_LO (0x0 << 6)
1527#define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1528#define RT5651_JD_LO_MASK (0x1 << 3)
1529#define RT5651_JD_LO_SFT 3
1530#define RT5651_JD_LO_DIS (0x0 << 3)
1531#define RT5651_JD_LO_EN (0x1 << 3)
1532#define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1533#define RT5651_JD_LO_TRG_SFT 2
1534#define RT5651_JD_LO_TRG_LO (0x0 << 2)
1535#define RT5651_JD_LO_TRG_HI (0x1 << 2)
1536
1537/* Jack Detect Control 2 (0xbc) */
1538#define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
1539#define RT5651_JD_TRG_SEL_SFT 9
1540#define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
1541#define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1542#define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
1543#define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1544#define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
1545#define RT5651_JD3_IRQ_EN (0x1 << 8)
1546#define RT5651_JD3_IRQ_EN_SFT 8
1547#define RT5651_JD3_EN_STKY (0x1 << 7)
1548#define RT5651_JD3_EN_STKY_SFT 7
1549#define RT5651_JD3_INV (0x1 << 6)
1550#define RT5651_JD3_INV_SFT 6
1551
1552/* IRQ Control 1 (0xbd) */
1553#define RT5651_IRQ_JD_MASK (0x1 << 15)
1554#define RT5651_IRQ_JD_SFT 15
1555#define RT5651_IRQ_JD_BP (0x0 << 15)
1556#define RT5651_IRQ_JD_NOR (0x1 << 15)
1557#define RT5651_JD_STKY_MASK (0x1 << 13)
1558#define RT5651_JD_STKY_SFT 13
1559#define RT5651_JD_STKY_DIS (0x0 << 13)
1560#define RT5651_JD_STKY_EN (0x1 << 13)
1561#define RT5651_JD_P_MASK (0x1 << 11)
1562#define RT5651_JD_P_SFT 11
1563#define RT5651_JD_P_NOR (0x0 << 11)
1564#define RT5651_JD_P_INV (0x1 << 11)
1565#define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1566#define RT5651_JD1_1_IRQ_EN_SFT 9
1567#define RT5651_JD1_1_EN_STKY (0x1 << 8)
1568#define RT5651_JD1_1_EN_STKY_SFT 8
1569#define RT5651_JD1_1_INV (0x1 << 7)
1570#define RT5651_JD1_1_INV_SFT 7
1571#define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1572#define RT5651_JD1_2_IRQ_EN_SFT 6
1573#define RT5651_JD1_2_EN_STKY (0x1 << 5)
1574#define RT5651_JD1_2_EN_STKY_SFT 5
1575#define RT5651_JD1_2_INV (0x1 << 4)
1576#define RT5651_JD1_2_INV_SFT 4
1577#define RT5651_JD2_IRQ_EN (0x1 << 3)
1578#define RT5651_JD2_IRQ_EN_SFT 3
1579#define RT5651_JD2_EN_STKY (0x1 << 2)
1580#define RT5651_JD2_EN_STKY_SFT 2
1581#define RT5651_JD2_INV (0x1 << 1)
1582#define RT5651_JD2_INV_SFT 1
1583
1584/* IRQ Control 2 (0xbe) */
1585#define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1586#define RT5651_IRQ_MB1_OC_SFT 15
1587#define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1588#define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1589#define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1590#define RT5651_MB1_OC_STKY_SFT 11
1591#define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1592#define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1593#define RT5651_MB1_OC_P_MASK (0x1 << 7)
1594#define RT5651_MB1_OC_P_SFT 7
1595#define RT5651_MB1_OC_P_NOR (0x0 << 7)
1596#define RT5651_MB1_OC_P_INV (0x1 << 7)
1597#define RT5651_MB2_OC_P_MASK (0x1 << 6)
1598#define RT5651_MB1_OC_CLR (0x1 << 3)
1599#define RT5651_MB1_OC_CLR_SFT 3
1600#define RT5651_STA_GPIO8 (0x1)
1601#define RT5651_STA_GPIO8_BIT 0
1602
1603/* Internal Status and GPIO status (0xbf) */
1604#define RT5651_STA_JD3 (0x1 << 15)
1605#define RT5651_STA_JD3_BIT 15
1606#define RT5651_STA_JD2 (0x1 << 14)
1607#define RT5651_STA_JD2_BIT 14
1608#define RT5651_STA_JD1_2 (0x1 << 13)
1609#define RT5651_STA_JD1_2_BIT 13
1610#define RT5651_STA_JD1_1 (0x1 << 12)
1611#define RT5651_STA_JD1_1_BIT 12
1612#define RT5651_STA_GP7 (0x1 << 11)
1613#define RT5651_STA_GP7_BIT 11
1614#define RT5651_STA_GP6 (0x1 << 10)
1615#define RT5651_STA_GP6_BIT 10
1616#define RT5651_STA_GP5 (0x1 << 9)
1617#define RT5651_STA_GP5_BIT 9
1618#define RT5651_STA_GP1 (0x1 << 8)
1619#define RT5651_STA_GP1_BIT 8
1620#define RT5651_STA_GP2 (0x1 << 7)
1621#define RT5651_STA_GP2_BIT 7
1622#define RT5651_STA_GP3 (0x1 << 6)
1623#define RT5651_STA_GP3_BIT 6
1624#define RT5651_STA_GP4 (0x1 << 5)
1625#define RT5651_STA_GP4_BIT 5
1626#define RT5651_STA_GP_JD (0x1 << 4)
1627#define RT5651_STA_GP_JD_BIT 4
1628
1629/* GPIO Control 1 (0xc0) */
1630#define RT5651_GP1_PIN_MASK (0x1 << 15)
1631#define RT5651_GP1_PIN_SFT 15
1632#define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1633#define RT5651_GP1_PIN_IRQ (0x1 << 15)
1634#define RT5651_GP2_PIN_MASK (0x1 << 14)
1635#define RT5651_GP2_PIN_SFT 14
1636#define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1637#define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1638#define RT5651_GPIO_M_MASK (0x1 << 9)
1639#define RT5651_GPIO_M_SFT 9
1640#define RT5651_GPIO_M_FLT (0x0 << 9)
1641#define RT5651_GPIO_M_PH (0x1 << 9)
1642#define RT5651_I2S2_SEL_MASK (0x1 << 8)
1643#define RT5651_I2S2_SEL_SFT 8
1644#define RT5651_I2S2_SEL_I2S (0x0 << 8)
1645#define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1646#define RT5651_GP5_PIN_MASK (0x1 << 7)
1647#define RT5651_GP5_PIN_SFT 7
1648#define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
1649#define RT5651_GP5_PIN_IRQ (0x1 << 7)
1650#define RT5651_GP6_PIN_MASK (0x1 << 6)
1651#define RT5651_GP6_PIN_SFT 6
1652#define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
1653#define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1654#define RT5651_GP7_PIN_MASK (0x1 << 5)
1655#define RT5651_GP7_PIN_SFT 5
1656#define RT5651_GP7_PIN_GPIO7 (0x0 << 5)
1657#define RT5651_GP7_PIN_IRQ (0x1 << 5)
1658#define RT5651_GP8_PIN_MASK (0x1 << 4)
1659#define RT5651_GP8_PIN_SFT 4
1660#define RT5651_GP8_PIN_GPIO8 (0x0 << 4)
1661#define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1662#define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1663#define RT5651_GPIO_PDM_SEL_SFT 3
1664#define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
1665#define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1666
1667/* GPIO Control 2 (0xc1) */
1668#define RT5651_GP5_DR_MASK (0x1 << 14)
1669#define RT5651_GP5_DR_SFT 14
1670#define RT5651_GP5_DR_IN (0x0 << 14)
1671#define RT5651_GP5_DR_OUT (0x1 << 14)
1672#define RT5651_GP5_OUT_MASK (0x1 << 13)
1673#define RT5651_GP5_OUT_SFT 13
1674#define RT5651_GP5_OUT_LO (0x0 << 13)
1675#define RT5651_GP5_OUT_HI (0x1 << 13)
1676#define RT5651_GP5_P_MASK (0x1 << 12)
1677#define RT5651_GP5_P_SFT 12
1678#define RT5651_GP5_P_NOR (0x0 << 12)
1679#define RT5651_GP5_P_INV (0x1 << 12)
1680#define RT5651_GP4_DR_MASK (0x1 << 11)
1681#define RT5651_GP4_DR_SFT 11
1682#define RT5651_GP4_DR_IN (0x0 << 11)
1683#define RT5651_GP4_DR_OUT (0x1 << 11)
1684#define RT5651_GP4_OUT_MASK (0x1 << 10)
1685#define RT5651_GP4_OUT_SFT 10
1686#define RT5651_GP4_OUT_LO (0x0 << 10)
1687#define RT5651_GP4_OUT_HI (0x1 << 10)
1688#define RT5651_GP4_P_MASK (0x1 << 9)
1689#define RT5651_GP4_P_SFT 9
1690#define RT5651_GP4_P_NOR (0x0 << 9)
1691#define RT5651_GP4_P_INV (0x1 << 9)
1692#define RT5651_GP3_DR_MASK (0x1 << 8)
1693#define RT5651_GP3_DR_SFT 8
1694#define RT5651_GP3_DR_IN (0x0 << 8)
1695#define RT5651_GP3_DR_OUT (0x1 << 8)
1696#define RT5651_GP3_OUT_MASK (0x1 << 7)
1697#define RT5651_GP3_OUT_SFT 7
1698#define RT5651_GP3_OUT_LO (0x0 << 7)
1699#define RT5651_GP3_OUT_HI (0x1 << 7)
1700#define RT5651_GP3_P_MASK (0x1 << 6)
1701#define RT5651_GP3_P_SFT 6
1702#define RT5651_GP3_P_NOR (0x0 << 6)
1703#define RT5651_GP3_P_INV (0x1 << 6)
1704#define RT5651_GP2_DR_MASK (0x1 << 5)
1705#define RT5651_GP2_DR_SFT 5
1706#define RT5651_GP2_DR_IN (0x0 << 5)
1707#define RT5651_GP2_DR_OUT (0x1 << 5)
1708#define RT5651_GP2_OUT_MASK (0x1 << 4)
1709#define RT5651_GP2_OUT_SFT 4
1710#define RT5651_GP2_OUT_LO (0x0 << 4)
1711#define RT5651_GP2_OUT_HI (0x1 << 4)
1712#define RT5651_GP2_P_MASK (0x1 << 3)
1713#define RT5651_GP2_P_SFT 3
1714#define RT5651_GP2_P_NOR (0x0 << 3)
1715#define RT5651_GP2_P_INV (0x1 << 3)
1716#define RT5651_GP1_DR_MASK (0x1 << 2)
1717#define RT5651_GP1_DR_SFT 2
1718#define RT5651_GP1_DR_IN (0x0 << 2)
1719#define RT5651_GP1_DR_OUT (0x1 << 2)
1720#define RT5651_GP1_OUT_MASK (0x1 << 1)
1721#define RT5651_GP1_OUT_SFT 1
1722#define RT5651_GP1_OUT_LO (0x0 << 1)
1723#define RT5651_GP1_OUT_HI (0x1 << 1)
1724#define RT5651_GP1_P_MASK (0x1)
1725#define RT5651_GP1_P_SFT 0
1726#define RT5651_GP1_P_NOR (0x0)
1727#define RT5651_GP1_P_INV (0x1)
1728
1729/* GPIO Control 3 (0xc2) */
1730#define RT5651_GP8_DR_MASK (0x1 << 8)
1731#define RT5651_GP8_DR_SFT 8
1732#define RT5651_GP8_DR_IN (0x0 << 8)
1733#define RT5651_GP8_DR_OUT (0x1 << 8)
1734#define RT5651_GP8_OUT_MASK (0x1 << 7)
1735#define RT5651_GP8_OUT_SFT 7
1736#define RT5651_GP8_OUT_LO (0x0 << 7)
1737#define RT5651_GP8_OUT_HI (0x1 << 7)
1738#define RT5651_GP8_P_MASK (0x1 << 6)
1739#define RT5651_GP8_P_SFT 6
1740#define RT5651_GP8_P_NOR (0x0 << 6)
1741#define RT5651_GP8_P_INV (0x1 << 6)
1742#define RT5651_GP7_DR_MASK (0x1 << 5)
1743#define RT5651_GP7_DR_SFT 5
1744#define RT5651_GP7_DR_IN (0x0 << 5)
1745#define RT5651_GP7_DR_OUT (0x1 << 5)
1746#define RT5651_GP7_OUT_MASK (0x1 << 4)
1747#define RT5651_GP7_OUT_SFT 4
1748#define RT5651_GP7_OUT_LO (0x0 << 4)
1749#define RT5651_GP7_OUT_HI (0x1 << 4)
1750#define RT5651_GP7_P_MASK (0x1 << 3)
1751#define RT5651_GP7_P_SFT 3
1752#define RT5651_GP7_P_NOR (0x0 << 3)
1753#define RT5651_GP7_P_INV (0x1 << 3)
1754#define RT5651_GP6_DR_MASK (0x1 << 2)
1755#define RT5651_GP6_DR_SFT 2
1756#define RT5651_GP6_DR_IN (0x0 << 2)
1757#define RT5651_GP6_DR_OUT (0x1 << 2)
1758#define RT5651_GP6_OUT_MASK (0x1 << 1)
1759#define RT5651_GP6_OUT_SFT 1
1760#define RT5651_GP6_OUT_LO (0x0 << 1)
1761#define RT5651_GP6_OUT_HI (0x1 << 1)
1762#define RT5651_GP6_P_MASK (0x1)
1763#define RT5651_GP6_P_SFT 0
1764#define RT5651_GP6_P_NOR (0x0)
1765#define RT5651_GP6_P_INV (0x1)
1766
1767/* Scramble Control (0xce) */
1768#define RT5651_SCB_SWAP_MASK (0x1 << 15)
1769#define RT5651_SCB_SWAP_SFT 15
1770#define RT5651_SCB_SWAP_DIS (0x0 << 15)
1771#define RT5651_SCB_SWAP_EN (0x1 << 15)
1772#define RT5651_SCB_MASK (0x1 << 14)
1773#define RT5651_SCB_SFT 14
1774#define RT5651_SCB_DIS (0x0 << 14)
1775#define RT5651_SCB_EN (0x1 << 14)
1776
1777/* Baseback Control (0xcf) */
1778#define RT5651_BB_MASK (0x1 << 15)
1779#define RT5651_BB_SFT 15
1780#define RT5651_BB_DIS (0x0 << 15)
1781#define RT5651_BB_EN (0x1 << 15)
1782#define RT5651_BB_CT_MASK (0x7 << 12)
1783#define RT5651_BB_CT_SFT 12
1784#define RT5651_BB_CT_A (0x0 << 12)
1785#define RT5651_BB_CT_B (0x1 << 12)
1786#define RT5651_BB_CT_C (0x2 << 12)
1787#define RT5651_BB_CT_D (0x3 << 12)
1788#define RT5651_M_BB_L_MASK (0x1 << 9)
1789#define RT5651_M_BB_L_SFT 9
1790#define RT5651_M_BB_R_MASK (0x1 << 8)
1791#define RT5651_M_BB_R_SFT 8
1792#define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1793#define RT5651_M_BB_HPF_L_SFT 7
1794#define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1795#define RT5651_M_BB_HPF_R_SFT 6
1796#define RT5651_G_BB_BST_MASK (0x3f)
1797#define RT5651_G_BB_BST_SFT 0
1798
1799/* MP3 Plus Control 1 (0xd0) */
1800#define RT5651_M_MP3_L_MASK (0x1 << 15)
1801#define RT5651_M_MP3_L_SFT 15
1802#define RT5651_M_MP3_R_MASK (0x1 << 14)
1803#define RT5651_M_MP3_R_SFT 14
1804#define RT5651_M_MP3_MASK (0x1 << 13)
1805#define RT5651_M_MP3_SFT 13
1806#define RT5651_M_MP3_DIS (0x0 << 13)
1807#define RT5651_M_MP3_EN (0x1 << 13)
1808#define RT5651_EG_MP3_MASK (0x1f << 8)
1809#define RT5651_EG_MP3_SFT 8
1810#define RT5651_MP3_HLP_MASK (0x1 << 7)
1811#define RT5651_MP3_HLP_SFT 7
1812#define RT5651_MP3_HLP_DIS (0x0 << 7)
1813#define RT5651_MP3_HLP_EN (0x1 << 7)
1814#define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1815#define RT5651_M_MP3_ORG_L_SFT 6
1816#define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1817#define RT5651_M_MP3_ORG_R_SFT 5
1818
1819/* MP3 Plus Control 2 (0xd1) */
1820#define RT5651_MP3_WT_MASK (0x1 << 13)
1821#define RT5651_MP3_WT_SFT 13
1822#define RT5651_MP3_WT_1_4 (0x0 << 13)
1823#define RT5651_MP3_WT_1_2 (0x1 << 13)
1824#define RT5651_OG_MP3_MASK (0x1f << 8)
1825#define RT5651_OG_MP3_SFT 8
1826#define RT5651_HG_MP3_MASK (0x3f)
1827#define RT5651_HG_MP3_SFT 0
1828
1829/* 3D HP Control 1 (0xd2) */
1830#define RT5651_3D_CF_MASK (0x1 << 15)
1831#define RT5651_3D_CF_SFT 15
1832#define RT5651_3D_CF_DIS (0x0 << 15)
1833#define RT5651_3D_CF_EN (0x1 << 15)
1834#define RT5651_3D_HP_MASK (0x1 << 14)
1835#define RT5651_3D_HP_SFT 14
1836#define RT5651_3D_HP_DIS (0x0 << 14)
1837#define RT5651_3D_HP_EN (0x1 << 14)
1838#define RT5651_3D_BT_MASK (0x1 << 13)
1839#define RT5651_3D_BT_SFT 13
1840#define RT5651_3D_BT_DIS (0x0 << 13)
1841#define RT5651_3D_BT_EN (0x1 << 13)
1842#define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1843#define RT5651_3D_1F_MIX_SFT 11
1844#define RT5651_3D_HP_M_MASK (0x1 << 10)
1845#define RT5651_3D_HP_M_SFT 10
1846#define RT5651_3D_HP_M_SUR (0x0 << 10)
1847#define RT5651_3D_HP_M_FRO (0x1 << 10)
1848#define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1849#define RT5651_M_3D_HRTF_SFT 9
1850#define RT5651_M_3D_D2H_MASK (0x1 << 8)
1851#define RT5651_M_3D_D2H_SFT 8
1852#define RT5651_M_3D_D2R_MASK (0x1 << 7)
1853#define RT5651_M_3D_D2R_SFT 7
1854#define RT5651_M_3D_REVB_MASK (0x1 << 6)
1855#define RT5651_M_3D_REVB_SFT 6
1856
1857/* Adjustable high pass filter control 1 (0xd3) */
1858#define RT5651_2ND_HPF_MASK (0x1 << 15)
1859#define RT5651_2ND_HPF_SFT 15
1860#define RT5651_2ND_HPF_DIS (0x0 << 15)
1861#define RT5651_2ND_HPF_EN (0x1 << 15)
1862#define RT5651_HPF_CF_L_MASK (0x7 << 12)
1863#define RT5651_HPF_CF_L_SFT 12
1864#define RT5651_HPF_CF_R_MASK (0x7 << 8)
1865#define RT5651_HPF_CF_R_SFT 8
1866#define RT5651_ZD_T_MASK (0x3 << 6)
1867#define RT5651_ZD_T_SFT 6
1868#define RT5651_ZD_F_MASK (0x3 << 4)
1869#define RT5651_ZD_F_SFT 4
1870#define RT5651_ZD_F_IM (0x0 << 4)
1871#define RT5651_ZD_F_ZC_IM (0x1 << 4)
1872#define RT5651_ZD_F_ZC_IOD (0x2 << 4)
1873#define RT5651_ZD_F_UN (0x3 << 4)
1874
1875/* Adjustable high pass filter control 2 (0xd4) */
1876#define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1877#define RT5651_HPF_CF_L_NUM_SFT 8
1878#define RT5651_HPF_CF_R_NUM_MASK (0x3f)
1879#define RT5651_HPF_CF_R_NUM_SFT 0
1880
1881/* HP calibration control and Amp detection (0xd6) */
1882#define RT5651_SI_DAC_MASK (0x1 << 11)
1883#define RT5651_SI_DAC_SFT 11
1884#define RT5651_SI_DAC_AUTO (0x0 << 11)
1885#define RT5651_SI_DAC_TEST (0x1 << 11)
1886#define RT5651_DC_CAL_M_MASK (0x1 << 10)
1887#define RT5651_DC_CAL_M_SFT 10
1888#define RT5651_DC_CAL_M_NOR (0x0 << 10)
1889#define RT5651_DC_CAL_M_CAL (0x1 << 10)
1890#define RT5651_DC_CAL_MASK (0x1 << 9)
1891#define RT5651_DC_CAL_SFT 9
1892#define RT5651_DC_CAL_DIS (0x0 << 9)
1893#define RT5651_DC_CAL_EN (0x1 << 9)
1894#define RT5651_HPD_RCV_MASK (0x7 << 6)
1895#define RT5651_HPD_RCV_SFT 6
1896#define RT5651_HPD_PS_MASK (0x1 << 5)
1897#define RT5651_HPD_PS_SFT 5
1898#define RT5651_HPD_PS_DIS (0x0 << 5)
1899#define RT5651_HPD_PS_EN (0x1 << 5)
1900#define RT5651_CAL_M_MASK (0x1 << 4)
1901#define RT5651_CAL_M_SFT 4
1902#define RT5651_CAL_M_DEP (0x0 << 4)
1903#define RT5651_CAL_M_CAL (0x1 << 4)
1904#define RT5651_CAL_MASK (0x1 << 3)
1905#define RT5651_CAL_SFT 3
1906#define RT5651_CAL_DIS (0x0 << 3)
1907#define RT5651_CAL_EN (0x1 << 3)
1908#define RT5651_CAL_TEST_MASK (0x1 << 2)
1909#define RT5651_CAL_TEST_SFT 2
1910#define RT5651_CAL_TEST_DIS (0x0 << 2)
1911#define RT5651_CAL_TEST_EN (0x1 << 2)
1912#define RT5651_CAL_P_MASK (0x3)
1913#define RT5651_CAL_P_SFT 0
1914#define RT5651_CAL_P_NONE (0x0)
1915#define RT5651_CAL_P_CAL (0x1)
1916#define RT5651_CAL_P_DAC_CAL (0x2)
1917
1918/* Soft volume and zero cross control 1 (0xd9) */
1919#define RT5651_SV_MASK (0x1 << 15)
1920#define RT5651_SV_SFT 15
1921#define RT5651_SV_DIS (0x0 << 15)
1922#define RT5651_SV_EN (0x1 << 15)
1923#define RT5651_OUT_SV_MASK (0x1 << 13)
1924#define RT5651_OUT_SV_SFT 13
1925#define RT5651_OUT_SV_DIS (0x0 << 13)
1926#define RT5651_OUT_SV_EN (0x1 << 13)
1927#define RT5651_HP_SV_MASK (0x1 << 12)
1928#define RT5651_HP_SV_SFT 12
1929#define RT5651_HP_SV_DIS (0x0 << 12)
1930#define RT5651_HP_SV_EN (0x1 << 12)
1931#define RT5651_ZCD_DIG_MASK (0x1 << 11)
1932#define RT5651_ZCD_DIG_SFT 11
1933#define RT5651_ZCD_DIG_DIS (0x0 << 11)
1934#define RT5651_ZCD_DIG_EN (0x1 << 11)
1935#define RT5651_ZCD_MASK (0x1 << 10)
1936#define RT5651_ZCD_SFT 10
1937#define RT5651_ZCD_PD (0x0 << 10)
1938#define RT5651_ZCD_PU (0x1 << 10)
1939#define RT5651_M_ZCD_MASK (0x3f << 4)
1940#define RT5651_M_ZCD_SFT 4
1941#define RT5651_M_ZCD_OM_L (0x1 << 7)
1942#define RT5651_M_ZCD_OM_R (0x1 << 6)
1943#define RT5651_M_ZCD_RM_L (0x1 << 5)
1944#define RT5651_M_ZCD_RM_R (0x1 << 4)
1945#define RT5651_SV_DLY_MASK (0xf)
1946#define RT5651_SV_DLY_SFT 0
1947
1948/* Soft volume and zero cross control 2 (0xda) */
1949#define RT5651_ZCD_HP_MASK (0x1 << 15)
1950#define RT5651_ZCD_HP_SFT 15
1951#define RT5651_ZCD_HP_DIS (0x0 << 15)
1952#define RT5651_ZCD_HP_EN (0x1 << 15)
1953
1954/* Digital Misc Control (0xfa) */
1955#define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1956#define RT5651_I2S2_MS_SP_SEL 8
1957#define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1958#define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1959#define RT5651_CLK_DET_EN (0x1 << 3)
1960#define RT5651_CLK_DET_EN_SFT 3
1961#define RT5651_AMP_DET_EN (0x1 << 1)
1962#define RT5651_AMP_DET_EN_SFT 1
1963#define RT5651_D_GATE_EN (0x1)
1964#define RT5651_D_GATE_EN_SFT 0
1965
1966/* Codec Private Register definition */
1967
1968/* MIC Over current threshold scale factor (0x15) */
1969#define RT5651_MIC_OVCD_SF_MASK (0x3 << 8)
1970#define RT5651_MIC_OVCD_SF_SFT 8
1971#define RT5651_MIC_OVCD_SF_0P5 (0x0 << 8)
1972#define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
1973#define RT5651_MIC_OVCD_SF_1P0 (0x2 << 8)
1974#define RT5651_MIC_OVCD_SF_1P5 (0x3 << 8)
1975
1976/* 3D Speaker Control (0x63) */
1977#define RT5651_3D_SPK_MASK (0x1 << 15)
1978#define RT5651_3D_SPK_SFT 15
1979#define RT5651_3D_SPK_DIS (0x0 << 15)
1980#define RT5651_3D_SPK_EN (0x1 << 15)
1981#define RT5651_3D_SPK_M_MASK (0x3 << 13)
1982#define RT5651_3D_SPK_M_SFT 13
1983#define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1984#define RT5651_3D_SPK_CG_SFT 8
1985#define RT5651_3D_SPK_SG_MASK (0x1f)
1986#define RT5651_3D_SPK_SG_SFT 0
1987
1988/* Wind Noise Detection Control 1 (0x6c) */
1989#define RT5651_WND_MASK (0x1 << 15)
1990#define RT5651_WND_SFT 15
1991#define RT5651_WND_DIS (0x0 << 15)
1992#define RT5651_WND_EN (0x1 << 15)
1993
1994/* Wind Noise Detection Control 2 (0x6d) */
1995#define RT5651_WND_FC_NW_MASK (0x3f << 10)
1996#define RT5651_WND_FC_NW_SFT 10
1997#define RT5651_WND_FC_WK_MASK (0x3f << 4)
1998#define RT5651_WND_FC_WK_SFT 4
1999
2000/* Wind Noise Detection Control 3 (0x6e) */
2001#define RT5651_HPF_FC_MASK (0x3f << 6)
2002#define RT5651_HPF_FC_SFT 6
2003#define RT5651_WND_FC_ST_MASK (0x3f)
2004#define RT5651_WND_FC_ST_SFT 0
2005
2006/* Wind Noise Detection Control 4 (0x6f) */
2007#define RT5651_WND_TH_LO_MASK (0x3ff)
2008#define RT5651_WND_TH_LO_SFT 0
2009
2010/* Wind Noise Detection Control 5 (0x70) */
2011#define RT5651_WND_TH_HI_MASK (0x3ff)
2012#define RT5651_WND_TH_HI_SFT 0
2013
2014/* Wind Noise Detection Control 8 (0x73) */
2015#define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2016#define RT5651_WND_WIND_SFT 13
2017#define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2018#define RT5651_WND_STRONG_SFT 12
2019enum {
2020 RT5651_NO_WIND,
2021 RT5651_BREEZE,
2022 RT5651_STORM,
2023};
2024
2025/* Dipole Speaker Interface (0x75) */
2026#define RT5651_DP_ATT_MASK (0x3 << 14)
2027#define RT5651_DP_ATT_SFT 14
2028#define RT5651_DP_SPK_MASK (0x1 << 10)
2029#define RT5651_DP_SPK_SFT 10
2030#define RT5651_DP_SPK_DIS (0x0 << 10)
2031#define RT5651_DP_SPK_EN (0x1 << 10)
2032
2033/* EQ Pre Volume Control (0xb3) */
2034#define RT5651_EQ_PRE_VOL_MASK (0xffff)
2035#define RT5651_EQ_PRE_VOL_SFT 0
2036
2037/* EQ Post Volume Control (0xb4) */
2038#define RT5651_EQ_PST_VOL_MASK (0xffff)
2039#define RT5651_EQ_PST_VOL_SFT 0
2040
2041/* System Clock Source */
2042enum {
2043 RT5651_SCLK_S_MCLK,
2044 RT5651_SCLK_S_PLL1,
2045 RT5651_SCLK_S_RCCLK,
2046};
2047
2048/* PLL1 Source */
2049enum {
2050 RT5651_PLL1_S_MCLK,
2051 RT5651_PLL1_S_BCLK1,
2052 RT5651_PLL1_S_BCLK2,
2053};
2054
2055enum {
2056 RT5651_AIF1,
2057 RT5651_AIF2,
2058 RT5651_AIFS,
2059};
2060
2061struct rt5651_pll_code {
2062 bool m_bp; /* Indicates bypass m code or not. */
2063 int m_code;
2064 int n_code;
2065 int k_code;
2066};
2067
2068struct rt5651_priv {
2069 struct snd_soc_component *component;
2070 struct regmap *regmap;
2071 /* Jack and button detect data */
2072 struct snd_soc_jack *hp_jack;
2073 struct gpio_desc *gpiod_hp_det;
2074 struct work_struct jack_detect_work;
2075 struct delayed_work bp_work;
2076 bool ovcd_irq_enabled;
2077 bool pressed;
2078 bool press_reported;
2079 int press_count;
2080 int release_count;
2081 int poll_count;
2082 unsigned int jd_src;
2083 bool jd_active_high;
2084 unsigned int ovcd_th;
2085 unsigned int ovcd_sf;
2086
2087 int irq;
2088 int sysclk;
2089 int sysclk_src;
2090 int lrck[RT5651_AIFS];
2091 int bclk[RT5651_AIFS];
2092 int master[RT5651_AIFS];
2093
2094 int pll_src;
2095 int pll_in;
2096 int pll_out;
2097
2098 int dmic_en;
2099 bool hp_mute;
2100};
2101
2102#endif /* __RT5651_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * rt5651.h -- RT5651 ALSA SoC audio driver
4 *
5 * Copyright 2011 Realtek Microelectronics
6 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 */
8
9#ifndef __RT5651_H__
10#define __RT5651_H__
11
12#include <dt-bindings/sound/rt5651.h>
13
14/* Info */
15#define RT5651_RESET 0x00
16#define RT5651_VERSION_ID 0xfd
17#define RT5651_VENDOR_ID 0xfe
18#define RT5651_DEVICE_ID 0xff
19/* I/O - Output */
20#define RT5651_HP_VOL 0x02
21#define RT5651_LOUT_CTRL1 0x03
22#define RT5651_LOUT_CTRL2 0x05
23/* I/O - Input */
24#define RT5651_IN1_IN2 0x0d
25#define RT5651_IN3 0x0e
26#define RT5651_INL1_INR1_VOL 0x0f
27#define RT5651_INL2_INR2_VOL 0x10
28/* I/O - ADC/DAC/DMIC */
29#define RT5651_DAC1_DIG_VOL 0x19
30#define RT5651_DAC2_DIG_VOL 0x1a
31#define RT5651_DAC2_CTRL 0x1b
32#define RT5651_ADC_DIG_VOL 0x1c
33#define RT5651_ADC_DATA 0x1d
34#define RT5651_ADC_BST_VOL 0x1e
35/* Mixer - D-D */
36#define RT5651_STO1_ADC_MIXER 0x27
37#define RT5651_STO2_ADC_MIXER 0x28
38#define RT5651_AD_DA_MIXER 0x29
39#define RT5651_STO_DAC_MIXER 0x2a
40#define RT5651_DD_MIXER 0x2b
41#define RT5651_DIG_INF_DATA 0x2f
42/* PDM */
43#define RT5651_PDM_CTL 0x30
44#define RT5651_PDM_I2C_CTL1 0x31
45#define RT5651_PDM_I2C_CTL2 0x32
46#define RT5651_PDM_I2C_DATA_W 0x33
47#define RT5651_PDM_I2C_DATA_R 0x34
48/* Mixer - ADC */
49#define RT5651_REC_L1_MIXER 0x3b
50#define RT5651_REC_L2_MIXER 0x3c
51#define RT5651_REC_R1_MIXER 0x3d
52#define RT5651_REC_R2_MIXER 0x3e
53/* Mixer - DAC */
54#define RT5651_HPO_MIXER 0x45
55#define RT5651_OUT_L1_MIXER 0x4d
56#define RT5651_OUT_L2_MIXER 0x4e
57#define RT5651_OUT_L3_MIXER 0x4f
58#define RT5651_OUT_R1_MIXER 0x50
59#define RT5651_OUT_R2_MIXER 0x51
60#define RT5651_OUT_R3_MIXER 0x52
61#define RT5651_LOUT_MIXER 0x53
62/* Power */
63#define RT5651_PWR_DIG1 0x61
64#define RT5651_PWR_DIG2 0x62
65#define RT5651_PWR_ANLG1 0x63
66#define RT5651_PWR_ANLG2 0x64
67#define RT5651_PWR_MIXER 0x65
68#define RT5651_PWR_VOL 0x66
69/* Private Register Control */
70#define RT5651_PRIV_INDEX 0x6a
71#define RT5651_PRIV_DATA 0x6c
72/* Format - ADC/DAC */
73#define RT5651_I2S1_SDP 0x70
74#define RT5651_I2S2_SDP 0x71
75#define RT5651_ADDA_CLK1 0x73
76#define RT5651_ADDA_CLK2 0x74
77#define RT5651_DMIC 0x75
78/* TDM Control */
79#define RT5651_TDM_CTL_1 0x77
80#define RT5651_TDM_CTL_2 0x78
81#define RT5651_TDM_CTL_3 0x79
82/* Function - Analog */
83#define RT5651_GLB_CLK 0x80
84#define RT5651_PLL_CTRL1 0x81
85#define RT5651_PLL_CTRL2 0x82
86#define RT5651_PLL_MODE_1 0x83
87#define RT5651_PLL_MODE_2 0x84
88#define RT5651_PLL_MODE_3 0x85
89#define RT5651_PLL_MODE_4 0x86
90#define RT5651_PLL_MODE_5 0x87
91#define RT5651_PLL_MODE_6 0x89
92#define RT5651_PLL_MODE_7 0x8a
93#define RT5651_DEPOP_M1 0x8e
94#define RT5651_DEPOP_M2 0x8f
95#define RT5651_DEPOP_M3 0x90
96#define RT5651_CHARGE_PUMP 0x91
97#define RT5651_MICBIAS 0x93
98#define RT5651_A_JD_CTL1 0x94
99/* Function - Digital */
100#define RT5651_EQ_CTRL1 0xb0
101#define RT5651_EQ_CTRL2 0xb1
102#define RT5651_ALC_1 0xb4
103#define RT5651_ALC_2 0xb5
104#define RT5651_ALC_3 0xb6
105#define RT5651_JD_CTRL1 0xbb
106#define RT5651_JD_CTRL2 0xbc
107#define RT5651_IRQ_CTRL1 0xbd
108#define RT5651_IRQ_CTRL2 0xbe
109#define RT5651_INT_IRQ_ST 0xbf
110#define RT5651_GPIO_CTRL1 0xc0
111#define RT5651_GPIO_CTRL2 0xc1
112#define RT5651_GPIO_CTRL3 0xc2
113#define RT5651_PGM_REG_ARR1 0xc8
114#define RT5651_PGM_REG_ARR2 0xc9
115#define RT5651_PGM_REG_ARR3 0xca
116#define RT5651_PGM_REG_ARR4 0xcb
117#define RT5651_PGM_REG_ARR5 0xcc
118#define RT5651_SCB_FUNC 0xcd
119#define RT5651_SCB_CTRL 0xce
120#define RT5651_BASE_BACK 0xcf
121#define RT5651_MP3_PLUS1 0xd0
122#define RT5651_MP3_PLUS2 0xd1
123#define RT5651_ADJ_HPF_CTRL1 0xd3
124#define RT5651_ADJ_HPF_CTRL2 0xd4
125#define RT5651_HP_CALIB_AMP_DET 0xd6
126#define RT5651_HP_CALIB2 0xd7
127#define RT5651_SV_ZCD1 0xd9
128#define RT5651_SV_ZCD2 0xda
129#define RT5651_D_MISC 0xfa
130/* Dummy Register */
131#define RT5651_DUMMY2 0xfb
132#define RT5651_DUMMY3 0xfc
133
134
135/* Index of Codec Private Register definition */
136#define RT5651_BIAS_CUR1 0x12
137#define RT5651_BIAS_CUR3 0x14
138#define RT5651_BIAS_CUR4 0x15
139#define RT5651_CLSD_INT_REG1 0x1c
140#define RT5651_CHPUMP_INT_REG1 0x24
141#define RT5651_MAMP_INT_REG2 0x37
142#define RT5651_CHOP_DAC_ADC 0x3d
143#define RT5651_3D_SPK 0x63
144#define RT5651_WND_1 0x6c
145#define RT5651_WND_2 0x6d
146#define RT5651_WND_3 0x6e
147#define RT5651_WND_4 0x6f
148#define RT5651_WND_5 0x70
149#define RT5651_WND_8 0x73
150#define RT5651_DIP_SPK_INF 0x75
151#define RT5651_HP_DCC_INT1 0x77
152#define RT5651_EQ_BW_LOP 0xa0
153#define RT5651_EQ_GN_LOP 0xa1
154#define RT5651_EQ_FC_BP1 0xa2
155#define RT5651_EQ_BW_BP1 0xa3
156#define RT5651_EQ_GN_BP1 0xa4
157#define RT5651_EQ_FC_BP2 0xa5
158#define RT5651_EQ_BW_BP2 0xa6
159#define RT5651_EQ_GN_BP2 0xa7
160#define RT5651_EQ_FC_BP3 0xa8
161#define RT5651_EQ_BW_BP3 0xa9
162#define RT5651_EQ_GN_BP3 0xaa
163#define RT5651_EQ_FC_BP4 0xab
164#define RT5651_EQ_BW_BP4 0xac
165#define RT5651_EQ_GN_BP4 0xad
166#define RT5651_EQ_FC_HIP1 0xae
167#define RT5651_EQ_GN_HIP1 0xaf
168#define RT5651_EQ_FC_HIP2 0xb0
169#define RT5651_EQ_BW_HIP2 0xb1
170#define RT5651_EQ_GN_HIP2 0xb2
171#define RT5651_EQ_PRE_VOL 0xb3
172#define RT5651_EQ_PST_VOL 0xb4
173
174
175/* global definition */
176#define RT5651_L_MUTE (0x1 << 15)
177#define RT5651_L_MUTE_SFT 15
178#define RT5651_VOL_L_MUTE (0x1 << 14)
179#define RT5651_VOL_L_SFT 14
180#define RT5651_R_MUTE (0x1 << 7)
181#define RT5651_R_MUTE_SFT 7
182#define RT5651_VOL_R_MUTE (0x1 << 6)
183#define RT5651_VOL_R_SFT 6
184#define RT5651_L_VOL_MASK (0x3f << 8)
185#define RT5651_L_VOL_SFT 8
186#define RT5651_R_VOL_MASK (0x3f)
187#define RT5651_R_VOL_SFT 0
188
189/* LOUT Control 2(0x05) */
190#define RT5651_EN_DFO (0x1 << 15)
191
192/* IN1 and IN2 Control (0x0d) */
193/* IN3 and IN4 Control (0x0e) */
194#define RT5651_BST_MASK1 (0xf<<12)
195#define RT5651_BST_SFT1 12
196#define RT5651_BST_MASK2 (0xf<<8)
197#define RT5651_BST_SFT2 8
198#define RT5651_IN_DF1 (0x1 << 7)
199#define RT5651_IN_SFT1 7
200#define RT5651_IN_DF2 (0x1 << 6)
201#define RT5651_IN_SFT2 6
202
203/* INL1 and INR1 Volume Control (0x0f) */
204/* INL2 and INR2 Volume Control (0x10) */
205#define RT5651_INL_SEL_MASK (0x1 << 15)
206#define RT5651_INL_SEL_SFT 15
207#define RT5651_INL_SEL_IN4P (0x0 << 15)
208#define RT5651_INL_SEL_MONOP (0x1 << 15)
209#define RT5651_INL_VOL_MASK (0x1f << 8)
210#define RT5651_INL_VOL_SFT 8
211#define RT5651_INR_SEL_MASK (0x1 << 7)
212#define RT5651_INR_SEL_SFT 7
213#define RT5651_INR_SEL_IN4N (0x0 << 7)
214#define RT5651_INR_SEL_MONON (0x1 << 7)
215#define RT5651_INR_VOL_MASK (0x1f)
216#define RT5651_INR_VOL_SFT 0
217
218/* DAC1 Digital Volume (0x19) */
219#define RT5651_DAC_L1_VOL_MASK (0xff << 8)
220#define RT5651_DAC_L1_VOL_SFT 8
221#define RT5651_DAC_R1_VOL_MASK (0xff)
222#define RT5651_DAC_R1_VOL_SFT 0
223
224/* DAC2 Digital Volume (0x1a) */
225#define RT5651_DAC_L2_VOL_MASK (0xff << 8)
226#define RT5651_DAC_L2_VOL_SFT 8
227#define RT5651_DAC_R2_VOL_MASK (0xff)
228#define RT5651_DAC_R2_VOL_SFT 0
229
230/* DAC2 Control (0x1b) */
231#define RT5651_M_DAC_L2_VOL (0x1 << 13)
232#define RT5651_M_DAC_L2_VOL_SFT 13
233#define RT5651_M_DAC_R2_VOL (0x1 << 12)
234#define RT5651_M_DAC_R2_VOL_SFT 12
235#define RT5651_SEL_DAC_L2 (0x1 << 11)
236#define RT5651_IF2_DAC_L2 (0x1 << 11)
237#define RT5651_IF1_DAC_L2 (0x0 << 11)
238#define RT5651_SEL_DAC_L2_SFT 11
239#define RT5651_SEL_DAC_R2 (0x1 << 10)
240#define RT5651_IF2_DAC_R2 (0x1 << 11)
241#define RT5651_IF1_DAC_R2 (0x0 << 11)
242#define RT5651_SEL_DAC_R2_SFT 10
243
244/* ADC Digital Volume Control (0x1c) */
245#define RT5651_ADC_L_VOL_MASK (0x7f << 8)
246#define RT5651_ADC_L_VOL_SFT 8
247#define RT5651_ADC_R_VOL_MASK (0x7f)
248#define RT5651_ADC_R_VOL_SFT 0
249
250/* Mono ADC Digital Volume Control (0x1d) */
251#define RT5651_M_MONO_ADC_L (0x1 << 15)
252#define RT5651_M_MONO_ADC_L_SFT 15
253#define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
254#define RT5651_MONO_ADC_L_VOL_SFT 8
255#define RT5651_M_MONO_ADC_R (0x1 << 7)
256#define RT5651_M_MONO_ADC_R_SFT 7
257#define RT5651_MONO_ADC_R_VOL_MASK (0x7f)
258#define RT5651_MONO_ADC_R_VOL_SFT 0
259
260/* ADC Boost Volume Control (0x1e) */
261#define RT5651_ADC_L_BST_MASK (0x3 << 14)
262#define RT5651_ADC_L_BST_SFT 14
263#define RT5651_ADC_R_BST_MASK (0x3 << 12)
264#define RT5651_ADC_R_BST_SFT 12
265#define RT5651_ADC_COMP_MASK (0x3 << 10)
266#define RT5651_ADC_COMP_SFT 10
267
268/* Stereo ADC1 Mixer Control (0x27) */
269#define RT5651_M_STO1_ADC_L1 (0x1 << 14)
270#define RT5651_M_STO1_ADC_L1_SFT 14
271#define RT5651_M_STO1_ADC_L2 (0x1 << 13)
272#define RT5651_M_STO1_ADC_L2_SFT 13
273#define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
274#define RT5651_STO1_ADC_1_SRC_SFT 12
275#define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
276#define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
277#define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
278#define RT5651_STO1_ADC_2_SRC_SFT 11
279#define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
280#define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
281#define RT5651_M_STO1_ADC_R1 (0x1 << 6)
282#define RT5651_M_STO1_ADC_R1_SFT 6
283#define RT5651_M_STO1_ADC_R2 (0x1 << 5)
284#define RT5651_M_STO1_ADC_R2_SFT 5
285
286/* Stereo ADC2 Mixer Control (0x28) */
287#define RT5651_M_STO2_ADC_L1 (0x1 << 14)
288#define RT5651_M_STO2_ADC_L1_SFT 14
289#define RT5651_M_STO2_ADC_L2 (0x1 << 13)
290#define RT5651_M_STO2_ADC_L2_SFT 13
291#define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
292#define RT5651_STO2_ADC_L1_SRC_SFT 12
293#define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
294#define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
295#define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
296#define RT5651_STO2_ADC_L2_SRC_SFT 11
297#define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
298#define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
299#define RT5651_M_STO2_ADC_R1 (0x1 << 6)
300#define RT5651_M_STO2_ADC_R1_SFT 6
301#define RT5651_M_STO2_ADC_R2 (0x1 << 5)
302#define RT5651_M_STO2_ADC_R2_SFT 5
303#define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
304#define RT5651_STO2_ADC_R1_SRC_SFT 4
305#define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
306#define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
307#define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
308#define RT5651_STO2_ADC_R2_SRC_SFT 3
309#define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
310#define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
311
312/* ADC Mixer to DAC Mixer Control (0x29) */
313#define RT5651_M_ADCMIX_L (0x1 << 15)
314#define RT5651_M_ADCMIX_L_SFT 15
315#define RT5651_M_IF1_DAC_L (0x1 << 14)
316#define RT5651_M_IF1_DAC_L_SFT 14
317#define RT5651_M_ADCMIX_R (0x1 << 7)
318#define RT5651_M_ADCMIX_R_SFT 7
319#define RT5651_M_IF1_DAC_R (0x1 << 6)
320#define RT5651_M_IF1_DAC_R_SFT 6
321
322/* Stereo DAC Mixer Control (0x2a) */
323#define RT5651_M_DAC_L1_MIXL (0x1 << 14)
324#define RT5651_M_DAC_L1_MIXL_SFT 14
325#define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
326#define RT5651_DAC_L1_STO_L_VOL_SFT 13
327#define RT5651_M_DAC_L2_MIXL (0x1 << 12)
328#define RT5651_M_DAC_L2_MIXL_SFT 12
329#define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
330#define RT5651_DAC_L2_STO_L_VOL_SFT 11
331#define RT5651_M_DAC_R1_MIXL (0x1 << 9)
332#define RT5651_M_DAC_R1_MIXL_SFT 9
333#define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
334#define RT5651_DAC_R1_STO_L_VOL_SFT 8
335#define RT5651_M_DAC_R1_MIXR (0x1 << 6)
336#define RT5651_M_DAC_R1_MIXR_SFT 6
337#define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
338#define RT5651_DAC_R1_STO_R_VOL_SFT 5
339#define RT5651_M_DAC_R2_MIXR (0x1 << 4)
340#define RT5651_M_DAC_R2_MIXR_SFT 4
341#define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
342#define RT5651_DAC_R2_STO_R_VOL_SFT 3
343#define RT5651_M_DAC_L1_MIXR (0x1 << 1)
344#define RT5651_M_DAC_L1_MIXR_SFT 1
345#define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
346#define RT5651_DAC_L1_STO_R_VOL_SFT 0
347
348/* DD Mixer Control (0x2b) */
349#define RT5651_M_STO_DD_L1 (0x1 << 14)
350#define RT5651_M_STO_DD_L1_SFT 14
351#define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
352#define RT5651_DAC_DD_L1_VOL_SFT 13
353#define RT5651_M_STO_DD_L2 (0x1 << 12)
354#define RT5651_M_STO_DD_L2_SFT 12
355#define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
356#define RT5651_STO_DD_L2_VOL_SFT 11
357#define RT5651_M_STO_DD_R2_L (0x1 << 10)
358#define RT5651_M_STO_DD_R2_L_SFT 10
359#define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
360#define RT5651_STO_DD_R2_L_VOL_SFT 9
361#define RT5651_M_STO_DD_R1 (0x1 << 6)
362#define RT5651_M_STO_DD_R1_SFT 6
363#define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
364#define RT5651_STO_DD_R1_VOL_SFT 5
365#define RT5651_M_STO_DD_R2 (0x1 << 4)
366#define RT5651_M_STO_DD_R2_SFT 4
367#define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
368#define RT5651_STO_DD_R2_VOL_SFT 3
369#define RT5651_M_STO_DD_L2_R (0x1 << 2)
370#define RT5651_M_STO_DD_L2_R_SFT 2
371#define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
372#define RT5651_STO_DD_L2_R_VOL_SFT 1
373
374/* Digital Mixer Control (0x2c) */
375#define RT5651_M_STO_L_DAC_L (0x1 << 15)
376#define RT5651_M_STO_L_DAC_L_SFT 15
377#define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
378#define RT5651_STO_L_DAC_L_VOL_SFT 14
379#define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
380#define RT5651_M_DAC_L2_DAC_L_SFT 13
381#define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
382#define RT5651_DAC_L2_DAC_L_VOL_SFT 12
383#define RT5651_M_STO_R_DAC_R (0x1 << 11)
384#define RT5651_M_STO_R_DAC_R_SFT 11
385#define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
386#define RT5651_STO_R_DAC_R_VOL_SFT 10
387#define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
388#define RT5651_M_DAC_R2_DAC_R_SFT 9
389#define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
390#define RT5651_DAC_R2_DAC_R_VOL_SFT 8
391
392/* DSP Path Control 1 (0x2d) */
393#define RT5651_RXDP_SRC_MASK (0x1 << 15)
394#define RT5651_RXDP_SRC_SFT 15
395#define RT5651_RXDP_SRC_NOR (0x0 << 15)
396#define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
397#define RT5651_TXDP_SRC_MASK (0x1 << 14)
398#define RT5651_TXDP_SRC_SFT 14
399#define RT5651_TXDP_SRC_NOR (0x0 << 14)
400#define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
401
402/* DSP Path Control 2 (0x2e) */
403#define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
404#define RT5651_DAC_L2_SEL_SFT 14
405#define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
406#define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
407#define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
408#define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
409#define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
410#define RT5651_DAC_R2_SEL_SFT 12
411#define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
412#define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
413#define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
414#define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
415#define RT5651_IF2_ADC_L_SEL_SFT 11
416#define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
417#define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
418#define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
419#define RT5651_IF2_ADC_R_SEL_SFT 10
420#define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
421#define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
422#define RT5651_RXDC_SEL_MASK (0x3 << 8)
423#define RT5651_RXDC_SEL_SFT 8
424#define RT5651_RXDC_SEL_NOR (0x0 << 8)
425#define RT5651_RXDC_SEL_L2R (0x1 << 8)
426#define RT5651_RXDC_SEL_R2L (0x2 << 8)
427#define RT5651_RXDC_SEL_SWAP (0x3 << 8)
428#define RT5651_RXDP_SEL_MASK (0x3 << 6)
429#define RT5651_RXDP_SEL_SFT 6
430#define RT5651_RXDP_SEL_NOR (0x0 << 6)
431#define RT5651_RXDP_SEL_L2R (0x1 << 6)
432#define RT5651_RXDP_SEL_R2L (0x2 << 6)
433#define RT5651_RXDP_SEL_SWAP (0x3 << 6)
434#define RT5651_TXDC_SEL_MASK (0x3 << 4)
435#define RT5651_TXDC_SEL_SFT 4
436#define RT5651_TXDC_SEL_NOR (0x0 << 4)
437#define RT5651_TXDC_SEL_L2R (0x1 << 4)
438#define RT5651_TXDC_SEL_R2L (0x2 << 4)
439#define RT5651_TXDC_SEL_SWAP (0x3 << 4)
440#define RT5651_TXDP_SEL_MASK (0x3 << 2)
441#define RT5651_TXDP_SEL_SFT 2
442#define RT5651_TXDP_SEL_NOR (0x0 << 2)
443#define RT5651_TXDP_SEL_L2R (0x1 << 2)
444#define RT5651_TXDP_SEL_R2L (0x2 << 2)
445#define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
446
447/* Digital Interface Data Control (0x2f) */
448#define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
449#define RT5651_IF2_DAC_SEL_SFT 10
450#define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
451#define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
452#define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
453#define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
454#define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
455#define RT5651_IF2_ADC_SEL_SFT 8
456#define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
457#define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
458#define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
459#define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
460#define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
461#define RT5651_IF2_ADC_SRC_SFT 7
462#define RT5651_IF1_ADC1 (0x0 << 7)
463#define RT5651_IF1_ADC2 (0x1 << 7)
464
465/* PDM Output Control (0x30) */
466#define RT5651_PDM_L_SEL_MASK (0x1 << 15)
467#define RT5651_PDM_L_SEL_SFT 15
468#define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
469#define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
470#define RT5651_M_PDM_L (0x1 << 14)
471#define RT5651_M_PDM_L_SFT 14
472#define RT5651_PDM_R_SEL_MASK (0x1 << 13)
473#define RT5651_PDM_R_SEL_SFT 13
474#define RT5651_PDM_R_SEL_DD_L (0x0 << 13)
475#define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
476#define RT5651_M_PDM_R (0x1 << 12)
477#define RT5651_M_PDM_R_SFT 12
478#define RT5651_PDM_BUSY (0x1 << 6)
479#define RT5651_PDM_BUSY_SFT 6
480#define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
481#define RT5651_PDM_PATTERN_SEL_64 (0x0 << 5)
482#define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
483#define RT5651_PDM_VOL_MASK (0x1 << 4)
484#define RT5651_PDM_VOL_SFT 4
485#define RT5651_PDM_DIV_MASK (0x3)
486#define RT5651_PDM_DIV_SFT 0
487#define RT5651_PDM_DIV_1 0
488#define RT5651_PDM_DIV_2 1
489#define RT5651_PDM_DIV_3 2
490#define RT5651_PDM_DIV_4 3
491
492/* PDM I2C/Data Control 1 (0x31) */
493#define RT5651_PDM_I2C_ID_MASK (0xf << 12)
494#define PT5631_PDM_CMD_EXE (0x1 << 11)
495#define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
496#define RT5651_PDM_I2C_CMD_R (0x0 << 10)
497#define RT5651_PDM_I2C_CMD_W (0x1 << 10)
498#define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
499#define RT5651_PDM_I2C_NORMAL (0x0 << 8)
500#define RT5651_PDM_I2C_BUSY (0x1 << 8)
501
502/* PDM I2C/Data Control 2 (0x32) */
503#define RT5651_PDM_I2C_ADDR (0xff << 8)
504#define RT5651_PDM_I2C_CMD_PATTERN (0xff)
505
506
507/* REC Left Mixer Control 1 (0x3b) */
508#define RT5651_G_LN_L2_RM_L_MASK (0x7 << 13)
509#define RT5651_G_IN_L2_RM_L_SFT 13
510#define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
511#define RT5651_G_IN_L1_RM_L_SFT 10
512#define RT5651_G_BST3_RM_L_MASK (0x7 << 4)
513#define RT5651_G_BST3_RM_L_SFT 4
514#define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
515#define RT5651_G_BST2_RM_L_SFT 1
516
517/* REC Left Mixer Control 2 (0x3c) */
518#define RT5651_G_BST1_RM_L_MASK (0x7 << 13)
519#define RT5651_G_BST1_RM_L_SFT 13
520#define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
521#define RT5651_G_OM_L_RM_L_SFT 10
522#define RT5651_M_IN2_L_RM_L (0x1 << 6)
523#define RT5651_M_IN2_L_RM_L_SFT 6
524#define RT5651_M_IN1_L_RM_L (0x1 << 5)
525#define RT5651_M_IN1_L_RM_L_SFT 5
526#define RT5651_M_BST3_RM_L (0x1 << 3)
527#define RT5651_M_BST3_RM_L_SFT 3
528#define RT5651_M_BST2_RM_L (0x1 << 2)
529#define RT5651_M_BST2_RM_L_SFT 2
530#define RT5651_M_BST1_RM_L (0x1 << 1)
531#define RT5651_M_BST1_RM_L_SFT 1
532#define RT5651_M_OM_L_RM_L (0x1)
533#define RT5651_M_OM_L_RM_L_SFT 0
534
535/* REC Right Mixer Control 1 (0x3d) */
536#define RT5651_G_IN2_R_RM_R_MASK (0x7 << 13)
537#define RT5651_G_IN2_R_RM_R_SFT 13
538#define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
539#define RT5651_G_IN1_R_RM_R_SFT 10
540#define RT5651_G_BST3_RM_R_MASK (0x7 << 4)
541#define RT5651_G_BST3_RM_R_SFT 4
542#define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
543#define RT5651_G_BST2_RM_R_SFT 1
544
545/* REC Right Mixer Control 2 (0x3e) */
546#define RT5651_G_BST1_RM_R_MASK (0x7 << 13)
547#define RT5651_G_BST1_RM_R_SFT 13
548#define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
549#define RT5651_G_OM_R_RM_R_SFT 10
550#define RT5651_M_IN2_R_RM_R (0x1 << 6)
551#define RT5651_M_IN2_R_RM_R_SFT 6
552#define RT5651_M_IN1_R_RM_R (0x1 << 5)
553#define RT5651_M_IN1_R_RM_R_SFT 5
554#define RT5651_M_BST3_RM_R (0x1 << 3)
555#define RT5651_M_BST3_RM_R_SFT 3
556#define RT5651_M_BST2_RM_R (0x1 << 2)
557#define RT5651_M_BST2_RM_R_SFT 2
558#define RT5651_M_BST1_RM_R (0x1 << 1)
559#define RT5651_M_BST1_RM_R_SFT 1
560#define RT5651_M_OM_R_RM_R (0x1)
561#define RT5651_M_OM_R_RM_R_SFT 0
562
563/* HPMIX Control (0x45) */
564#define RT5651_M_DAC1_HM (0x1 << 14)
565#define RT5651_M_DAC1_HM_SFT 14
566#define RT5651_M_HPVOL_HM (0x1 << 13)
567#define RT5651_M_HPVOL_HM_SFT 13
568#define RT5651_G_HPOMIX_MASK (0x1 << 12)
569#define RT5651_G_HPOMIX_SFT 12
570
571/* SPK Left Mixer Control (0x46) */
572#define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
573#define RT5651_G_RM_L_SM_L_SFT 14
574#define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
575#define RT5651_G_IN_L_SM_L_SFT 12
576#define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
577#define RT5651_G_DAC_L1_SM_L_SFT 10
578#define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
579#define RT5651_G_DAC_L2_SM_L_SFT 8
580#define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
581#define RT5651_G_OM_L_SM_L_SFT 6
582#define RT5651_M_RM_L_SM_L (0x1 << 5)
583#define RT5651_M_RM_L_SM_L_SFT 5
584#define RT5651_M_IN_L_SM_L (0x1 << 4)
585#define RT5651_M_IN_L_SM_L_SFT 4
586#define RT5651_M_DAC_L1_SM_L (0x1 << 3)
587#define RT5651_M_DAC_L1_SM_L_SFT 3
588#define RT5651_M_DAC_L2_SM_L (0x1 << 2)
589#define RT5651_M_DAC_L2_SM_L_SFT 2
590#define RT5651_M_OM_L_SM_L (0x1 << 1)
591#define RT5651_M_OM_L_SM_L_SFT 1
592
593/* SPK Right Mixer Control (0x47) */
594#define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
595#define RT5651_G_RM_R_SM_R_SFT 14
596#define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
597#define RT5651_G_IN_R_SM_R_SFT 12
598#define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
599#define RT5651_G_DAC_R1_SM_R_SFT 10
600#define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
601#define RT5651_G_DAC_R2_SM_R_SFT 8
602#define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
603#define RT5651_G_OM_R_SM_R_SFT 6
604#define RT5651_M_RM_R_SM_R (0x1 << 5)
605#define RT5651_M_RM_R_SM_R_SFT 5
606#define RT5651_M_IN_R_SM_R (0x1 << 4)
607#define RT5651_M_IN_R_SM_R_SFT 4
608#define RT5651_M_DAC_R1_SM_R (0x1 << 3)
609#define RT5651_M_DAC_R1_SM_R_SFT 3
610#define RT5651_M_DAC_R2_SM_R (0x1 << 2)
611#define RT5651_M_DAC_R2_SM_R_SFT 2
612#define RT5651_M_OM_R_SM_R (0x1 << 1)
613#define RT5651_M_OM_R_SM_R_SFT 1
614
615/* SPOLMIX Control (0x48) */
616#define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
617#define RT5651_M_DAC_R1_SPM_L_SFT 15
618#define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
619#define RT5651_M_DAC_L1_SPM_L_SFT 14
620#define RT5651_M_SV_R_SPM_L (0x1 << 13)
621#define RT5651_M_SV_R_SPM_L_SFT 13
622#define RT5651_M_SV_L_SPM_L (0x1 << 12)
623#define RT5651_M_SV_L_SPM_L_SFT 12
624#define RT5651_M_BST1_SPM_L (0x1 << 11)
625#define RT5651_M_BST1_SPM_L_SFT 11
626
627/* SPORMIX Control (0x49) */
628#define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
629#define RT5651_M_DAC_R1_SPM_R_SFT 13
630#define RT5651_M_SV_R_SPM_R (0x1 << 12)
631#define RT5651_M_SV_R_SPM_R_SFT 12
632#define RT5651_M_BST1_SPM_R (0x1 << 11)
633#define RT5651_M_BST1_SPM_R_SFT 11
634
635/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
636#define RT5651_SPO_CLSD_RATIO_MASK (0x7)
637#define RT5651_SPO_CLSD_RATIO_SFT 0
638
639/* Mono Output Mixer Control (0x4c) */
640#define RT5651_M_DAC_R2_MM (0x1 << 15)
641#define RT5651_M_DAC_R2_MM_SFT 15
642#define RT5651_M_DAC_L2_MM (0x1 << 14)
643#define RT5651_M_DAC_L2_MM_SFT 14
644#define RT5651_M_OV_R_MM (0x1 << 13)
645#define RT5651_M_OV_R_MM_SFT 13
646#define RT5651_M_OV_L_MM (0x1 << 12)
647#define RT5651_M_OV_L_MM_SFT 12
648#define RT5651_M_BST1_MM (0x1 << 11)
649#define RT5651_M_BST1_MM_SFT 11
650#define RT5651_G_MONOMIX_MASK (0x1 << 10)
651#define RT5651_G_MONOMIX_SFT 10
652
653/* Output Left Mixer Control 1 (0x4d) */
654#define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
655#define RT5651_G_BST2_OM_L_SFT 10
656#define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
657#define RT5651_G_BST1_OM_L_SFT 7
658#define RT5651_G_IN1_L_OM_L_MASK (0x7 << 4)
659#define RT5651_G_IN1_L_OM_L_SFT 4
660#define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
661#define RT5651_G_RM_L_OM_L_SFT 1
662
663/* Output Left Mixer Control 2 (0x4e) */
664#define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
665#define RT5651_G_DAC_L1_OM_L_SFT 7
666#define RT5651_G_IN2_L_OM_L_MASK (0x7 << 4)
667#define RT5651_G_IN2_L_OM_L_SFT 4
668
669/* Output Left Mixer Control 3 (0x4f) */
670#define RT5651_M_IN2_L_OM_L (0x1 << 9)
671#define RT5651_M_IN2_L_OM_L_SFT 9
672#define RT5651_M_BST2_OM_L (0x1 << 6)
673#define RT5651_M_BST2_OM_L_SFT 6
674#define RT5651_M_BST1_OM_L (0x1 << 5)
675#define RT5651_M_BST1_OM_L_SFT 5
676#define RT5651_M_IN1_L_OM_L (0x1 << 4)
677#define RT5651_M_IN1_L_OM_L_SFT 4
678#define RT5651_M_RM_L_OM_L (0x1 << 3)
679#define RT5651_M_RM_L_OM_L_SFT 3
680#define RT5651_M_DAC_L1_OM_L (0x1)
681#define RT5651_M_DAC_L1_OM_L_SFT 0
682
683/* Output Right Mixer Control 1 (0x50) */
684#define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
685#define RT5651_G_BST2_OM_R_SFT 10
686#define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
687#define RT5651_G_BST1_OM_R_SFT 7
688#define RT5651_G_IN1_R_OM_R_MASK (0x7 << 4)
689#define RT5651_G_IN1_R_OM_R_SFT 4
690#define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
691#define RT5651_G_RM_R_OM_R_SFT 1
692
693/* Output Right Mixer Control 2 (0x51) */
694#define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
695#define RT5651_G_DAC_R1_OM_R_SFT 7
696#define RT5651_G_IN2_R_OM_R_MASK (0x7 << 4)
697#define RT5651_G_IN2_R_OM_R_SFT 4
698
699/* Output Right Mixer Control 3 (0x52) */
700#define RT5651_M_IN2_R_OM_R (0x1 << 9)
701#define RT5651_M_IN2_R_OM_R_SFT 9
702#define RT5651_M_BST2_OM_R (0x1 << 6)
703#define RT5651_M_BST2_OM_R_SFT 6
704#define RT5651_M_BST1_OM_R (0x1 << 5)
705#define RT5651_M_BST1_OM_R_SFT 5
706#define RT5651_M_IN1_R_OM_R (0x1 << 4)
707#define RT5651_M_IN1_R_OM_R_SFT 4
708#define RT5651_M_RM_R_OM_R (0x1 << 3)
709#define RT5651_M_RM_R_OM_R_SFT 3
710#define RT5651_M_DAC_R1_OM_R (0x1)
711#define RT5651_M_DAC_R1_OM_R_SFT 0
712
713/* LOUT Mixer Control (0x53) */
714#define RT5651_M_DAC_L1_LM (0x1 << 15)
715#define RT5651_M_DAC_L1_LM_SFT 15
716#define RT5651_M_DAC_R1_LM (0x1 << 14)
717#define RT5651_M_DAC_R1_LM_SFT 14
718#define RT5651_M_OV_L_LM (0x1 << 13)
719#define RT5651_M_OV_L_LM_SFT 13
720#define RT5651_M_OV_R_LM (0x1 << 12)
721#define RT5651_M_OV_R_LM_SFT 12
722#define RT5651_G_LOUTMIX_MASK (0x1 << 11)
723#define RT5651_G_LOUTMIX_SFT 11
724
725/* Power Management for Digital 1 (0x61) */
726#define RT5651_PWR_I2S1 (0x1 << 15)
727#define RT5651_PWR_I2S1_BIT 15
728#define RT5651_PWR_I2S2 (0x1 << 14)
729#define RT5651_PWR_I2S2_BIT 14
730#define RT5651_PWR_DAC_L1 (0x1 << 12)
731#define RT5651_PWR_DAC_L1_BIT 12
732#define RT5651_PWR_DAC_R1 (0x1 << 11)
733#define RT5651_PWR_DAC_R1_BIT 11
734#define RT5651_PWR_ADC_L (0x1 << 2)
735#define RT5651_PWR_ADC_L_BIT 2
736#define RT5651_PWR_ADC_R (0x1 << 1)
737#define RT5651_PWR_ADC_R_BIT 1
738
739/* Power Management for Digital 2 (0x62) */
740#define RT5651_PWR_ADC_STO1_F (0x1 << 15)
741#define RT5651_PWR_ADC_STO1_F_BIT 15
742#define RT5651_PWR_ADC_STO2_F (0x1 << 14)
743#define RT5651_PWR_ADC_STO2_F_BIT 14
744#define RT5651_PWR_DAC_STO1_F (0x1 << 11)
745#define RT5651_PWR_DAC_STO1_F_BIT 11
746#define RT5651_PWR_DAC_STO2_F (0x1 << 10)
747#define RT5651_PWR_DAC_STO2_F_BIT 10
748#define RT5651_PWR_PDM (0x1 << 9)
749#define RT5651_PWR_PDM_BIT 9
750
751/* Power Management for Analog 1 (0x63) */
752#define RT5651_PWR_VREF1 (0x1 << 15)
753#define RT5651_PWR_VREF1_BIT 15
754#define RT5651_PWR_FV1 (0x1 << 14)
755#define RT5651_PWR_FV1_BIT 14
756#define RT5651_PWR_MB (0x1 << 13)
757#define RT5651_PWR_MB_BIT 13
758#define RT5651_PWR_LM (0x1 << 12)
759#define RT5651_PWR_LM_BIT 12
760#define RT5651_PWR_BG (0x1 << 11)
761#define RT5651_PWR_BG_BIT 11
762#define RT5651_PWR_HP_L (0x1 << 7)
763#define RT5651_PWR_HP_L_BIT 7
764#define RT5651_PWR_HP_R (0x1 << 6)
765#define RT5651_PWR_HP_R_BIT 6
766#define RT5651_PWR_HA (0x1 << 5)
767#define RT5651_PWR_HA_BIT 5
768#define RT5651_PWR_VREF2 (0x1 << 4)
769#define RT5651_PWR_VREF2_BIT 4
770#define RT5651_PWR_FV2 (0x1 << 3)
771#define RT5651_PWR_FV2_BIT 3
772#define RT5651_PWR_LDO (0x1 << 2)
773#define RT5651_PWR_LDO_BIT 2
774#define RT5651_PWR_LDO_DVO_MASK (0x3)
775#define RT5651_PWR_LDO_DVO_1_0V 0
776#define RT5651_PWR_LDO_DVO_1_1V 1
777#define RT5651_PWR_LDO_DVO_1_2V 2
778#define RT5651_PWR_LDO_DVO_1_3V 3
779
780/* Power Management for Analog 2 (0x64) */
781#define RT5651_PWR_BST1 (0x1 << 15)
782#define RT5651_PWR_BST1_BIT 15
783#define RT5651_PWR_BST2 (0x1 << 14)
784#define RT5651_PWR_BST2_BIT 14
785#define RT5651_PWR_BST3 (0x1 << 13)
786#define RT5651_PWR_BST3_BIT 13
787#define RT5651_PWR_MB1 (0x1 << 11)
788#define RT5651_PWR_MB1_BIT 11
789#define RT5651_PWR_PLL (0x1 << 9)
790#define RT5651_PWR_PLL_BIT 9
791#define RT5651_PWR_BST1_OP2 (0x1 << 5)
792#define RT5651_PWR_BST1_OP2_BIT 5
793#define RT5651_PWR_BST2_OP2 (0x1 << 4)
794#define RT5651_PWR_BST2_OP2_BIT 4
795#define RT5651_PWR_BST3_OP2 (0x1 << 3)
796#define RT5651_PWR_BST3_OP2_BIT 3
797#define RT5651_PWR_JD_M (0x1 << 2)
798#define RT5651_PWM_JD_M_BIT 2
799#define RT5651_PWR_JD2 (0x1 << 1)
800#define RT5651_PWM_JD2_BIT 1
801#define RT5651_PWR_JD3 (0x1)
802#define RT5651_PWM_JD3_BIT 0
803
804/* Power Management for Mixer (0x65) */
805#define RT5651_PWR_OM_L (0x1 << 15)
806#define RT5651_PWR_OM_L_BIT 15
807#define RT5651_PWR_OM_R (0x1 << 14)
808#define RT5651_PWR_OM_R_BIT 14
809#define RT5651_PWR_RM_L (0x1 << 11)
810#define RT5651_PWR_RM_L_BIT 11
811#define RT5651_PWR_RM_R (0x1 << 10)
812#define RT5651_PWR_RM_R_BIT 10
813
814/* Power Management for Volume (0x66) */
815#define RT5651_PWR_OV_L (0x1 << 13)
816#define RT5651_PWR_OV_L_BIT 13
817#define RT5651_PWR_OV_R (0x1 << 12)
818#define RT5651_PWR_OV_R_BIT 12
819#define RT5651_PWR_HV_L (0x1 << 11)
820#define RT5651_PWR_HV_L_BIT 11
821#define RT5651_PWR_HV_R (0x1 << 10)
822#define RT5651_PWR_HV_R_BIT 10
823#define RT5651_PWR_IN1_L (0x1 << 9)
824#define RT5651_PWR_IN1_L_BIT 9
825#define RT5651_PWR_IN1_R (0x1 << 8)
826#define RT5651_PWR_IN1_R_BIT 8
827#define RT5651_PWR_IN2_L (0x1 << 7)
828#define RT5651_PWR_IN2_L_BIT 7
829#define RT5651_PWR_IN2_R (0x1 << 6)
830#define RT5651_PWR_IN2_R_BIT 6
831
832/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
833#define RT5651_I2S_MS_MASK (0x1 << 15)
834#define RT5651_I2S_MS_SFT 15
835#define RT5651_I2S_MS_M (0x0 << 15)
836#define RT5651_I2S_MS_S (0x1 << 15)
837#define RT5651_I2S_O_CP_MASK (0x3 << 10)
838#define RT5651_I2S_O_CP_SFT 10
839#define RT5651_I2S_O_CP_OFF (0x0 << 10)
840#define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
841#define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
842#define RT5651_I2S_I_CP_MASK (0x3 << 8)
843#define RT5651_I2S_I_CP_SFT 8
844#define RT5651_I2S_I_CP_OFF (0x0 << 8)
845#define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
846#define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
847#define RT5651_I2S_BP_MASK (0x1 << 7)
848#define RT5651_I2S_BP_SFT 7
849#define RT5651_I2S_BP_NOR (0x0 << 7)
850#define RT5651_I2S_BP_INV (0x1 << 7)
851#define RT5651_I2S_DL_MASK (0x3 << 2)
852#define RT5651_I2S_DL_SFT 2
853#define RT5651_I2S_DL_16 (0x0 << 2)
854#define RT5651_I2S_DL_20 (0x1 << 2)
855#define RT5651_I2S_DL_24 (0x2 << 2)
856#define RT5651_I2S_DL_8 (0x3 << 2)
857#define RT5651_I2S_DF_MASK (0x3)
858#define RT5651_I2S_DF_SFT 0
859#define RT5651_I2S_DF_I2S (0x0)
860#define RT5651_I2S_DF_LEFT (0x1)
861#define RT5651_I2S_DF_PCM_A (0x2)
862#define RT5651_I2S_DF_PCM_B (0x3)
863
864/* ADC/DAC Clock Control 1 (0x73) */
865#define RT5651_I2S_PD1_MASK (0x7 << 12)
866#define RT5651_I2S_PD1_SFT 12
867#define RT5651_I2S_PD1_1 (0x0 << 12)
868#define RT5651_I2S_PD1_2 (0x1 << 12)
869#define RT5651_I2S_PD1_3 (0x2 << 12)
870#define RT5651_I2S_PD1_4 (0x3 << 12)
871#define RT5651_I2S_PD1_6 (0x4 << 12)
872#define RT5651_I2S_PD1_8 (0x5 << 12)
873#define RT5651_I2S_PD1_12 (0x6 << 12)
874#define RT5651_I2S_PD1_16 (0x7 << 12)
875#define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
876#define RT5651_I2S_BCLK_MS2_SFT 11
877#define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
878#define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
879#define RT5651_I2S_PD2_MASK (0x7 << 8)
880#define RT5651_I2S_PD2_SFT 8
881#define RT5651_I2S_PD2_1 (0x0 << 8)
882#define RT5651_I2S_PD2_2 (0x1 << 8)
883#define RT5651_I2S_PD2_3 (0x2 << 8)
884#define RT5651_I2S_PD2_4 (0x3 << 8)
885#define RT5651_I2S_PD2_6 (0x4 << 8)
886#define RT5651_I2S_PD2_8 (0x5 << 8)
887#define RT5651_I2S_PD2_12 (0x6 << 8)
888#define RT5651_I2S_PD2_16 (0x7 << 8)
889#define RT5651_DAC_OSR_MASK (0x3 << 2)
890#define RT5651_DAC_OSR_SFT 2
891#define RT5651_DAC_OSR_128 (0x0 << 2)
892#define RT5651_DAC_OSR_64 (0x1 << 2)
893#define RT5651_DAC_OSR_32 (0x2 << 2)
894#define RT5651_DAC_OSR_128_3 (0x3 << 2)
895#define RT5651_ADC_OSR_MASK (0x3)
896#define RT5651_ADC_OSR_SFT 0
897#define RT5651_ADC_OSR_128 (0x0)
898#define RT5651_ADC_OSR_64 (0x1)
899#define RT5651_ADC_OSR_32 (0x2)
900#define RT5651_ADC_OSR_128_3 (0x3)
901
902/* ADC/DAC Clock Control 2 (0x74) */
903#define RT5651_DAHPF_EN (0x1 << 11)
904#define RT5651_DAHPF_EN_SFT 11
905#define RT5651_ADHPF_EN (0x1 << 10)
906#define RT5651_ADHPF_EN_SFT 10
907
908/* Digital Microphone Control (0x75) */
909#define RT5651_DMIC_1_EN_MASK (0x1 << 15)
910#define RT5651_DMIC_1_EN_SFT 15
911#define RT5651_DMIC_1_DIS (0x0 << 15)
912#define RT5651_DMIC_1_EN (0x1 << 15)
913#define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
914#define RT5651_DMIC_1L_LH_SFT 13
915#define RT5651_DMIC_1L_LH_FALLING (0x0 << 13)
916#define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
917#define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
918#define RT5651_DMIC_1R_LH_SFT 12
919#define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
920#define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
921#define RT5651_DMIC_1_DP_MASK (0x3 << 10)
922#define RT5651_DMIC_1_DP_SFT 10
923#define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
924#define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
925#define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
926#define RT5651_DMIC_CLK_MASK (0x7 << 5)
927#define RT5651_DMIC_CLK_SFT 5
928
929/* TDM Control 1 (0x77) */
930#define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
931#define RT5651_TDM_INTEL_SEL_SFT 15
932#define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
933#define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
934#define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
935#define RT5651_TDM_MODE_SEL_SFT 14
936#define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
937#define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
938#define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
939#define RT5651_TDM_CH_NUM_SEL_SFT 12
940#define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
941#define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
942#define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
943#define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
944#define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
945#define RT5651_TDM_CH_LEN_SEL_SFT 10
946#define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
947#define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
948#define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
949#define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
950#define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
951#define RT5651_TDM_ADC_SEL_SFT 9
952#define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
953#define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
954#define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
955#define RT5651_TDM_ADC_START_SEL_SFT 8
956#define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
957#define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
958#define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
959#define RT5651_TDM_I2S_CH2_SEL_SFT 6
960#define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
961#define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
962#define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
963#define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
964#define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
965#define RT5651_TDM_I2S_CH4_SEL_SFT 4
966#define RT5651_TDM_I2S_CH4_SEL_LR (0x0 << 4)
967#define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
968#define RT5651_TDM_I2S_CH4_SEL_LL (0x2 << 4)
969#define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
970#define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
971#define RT5651_TDM_I2S_CH6_SEL_SFT 2
972#define RT5651_TDM_I2S_CH6_SEL_LR (0x0 << 2)
973#define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
974#define RT5651_TDM_I2S_CH6_SEL_LL (0x2 << 2)
975#define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
976#define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
977#define RT5651_TDM_I2S_CH8_SEL_SFT 0
978#define RT5651_TDM_I2S_CH8_SEL_LR (0x0)
979#define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
980#define RT5651_TDM_I2S_CH8_SEL_LL (0x2)
981#define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
982
983/* TDM Control 2 (0x78) */
984#define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
985#define RT5651_TDM_LRCK_POL_SEL_SFT 15
986#define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
987#define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
988#define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
989#define RT5651_TDM_CH_VAL_SEL_SFT 14
990#define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
991#define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
992#define RT5651_TDM_CH_VAL_EN (0x1 << 13)
993#define RT5651_TDM_CH_VAL_SFT 13
994#define RT5651_TDM_LPBK_EN (0x1 << 12)
995#define RT5651_TDM_LPBK_SFT 12
996#define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
997#define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
998#define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
999#define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1000#define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1001#define RT5651_TDM_END_EDGE_SEL_SFT 10
1002#define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1003#define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1004#define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1005#define RT5651_TDM_END_EDGE_EN_SFT 9
1006#define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1007#define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
1008#define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1009#define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1010#define RT5651_M_TDM2_L (0x1 << 7)
1011#define RT5651_M_TDM2_L_SFT 7
1012#define RT5651_M_TDM2_R (0x1 << 6)
1013#define RT5651_M_TDM2_R_SFT 6
1014#define RT5651_M_TDM4_L (0x1 << 5)
1015#define RT5651_M_TDM4_L_SFT 5
1016#define RT5651_M_TDM4_R (0x1 << 4)
1017#define RT5651_M_TDM4_R_SFT 4
1018
1019/* TDM Control 3 (0x79) */
1020#define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1021#define RT5651_CH2_L_SEL_SFT 12
1022#define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1023#define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1024#define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1025#define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1026#define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1027#define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1028#define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1029#define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1030#define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1031#define RT5651_CH2_R_SEL_SFT 8
1032#define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1033#define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1034#define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1035#define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1036#define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1037#define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1038#define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1039#define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1040#define RT5651_CH4_L_SEL_MASK (0x7 << 4)
1041#define RT5651_CH4_L_SEL_SFT 4
1042#define RT5651_CH4_L_SEL_SL0 (0x0 << 4)
1043#define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1044#define RT5651_CH4_L_SEL_SL2 (0x2 << 4)
1045#define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
1046#define RT5651_CH4_L_SEL_SL4 (0x4 << 4)
1047#define RT5651_CH4_L_SEL_SL5 (0x5 << 4)
1048#define RT5651_CH4_L_SEL_SL6 (0x6 << 4)
1049#define RT5651_CH4_L_SEL_SL7 (0x7 << 4)
1050#define RT5651_CH4_R_SEL_MASK (0x7)
1051#define RT5651_CH4_R_SEL_SFT 0
1052#define RT5651_CH4_R_SEL_SL0 (0x0)
1053#define RT5651_CH4_R_SEL_SL1 (0x1)
1054#define RT5651_CH4_R_SEL_SL2 (0x2)
1055#define RT5651_CH4_R_SEL_SL3 (0x3)
1056#define RT5651_CH4_R_SEL_SL4 (0x4)
1057#define RT5651_CH4_R_SEL_SL5 (0x5)
1058#define RT5651_CH4_R_SEL_SL6 (0x6)
1059#define RT5651_CH4_R_SEL_SL7 (0x7)
1060
1061/* Global Clock Control (0x80) */
1062#define RT5651_SCLK_SRC_MASK (0x3 << 14)
1063#define RT5651_SCLK_SRC_SFT 14
1064#define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1065#define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1066#define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1067#define RT5651_PLL1_SRC_MASK (0x3 << 12)
1068#define RT5651_PLL1_SRC_SFT 12
1069#define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1070#define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1071#define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1072#define RT5651_PLL1_PD_MASK (0x1 << 3)
1073#define RT5651_PLL1_PD_SFT 3
1074#define RT5651_PLL1_PD_1 (0x0 << 3)
1075#define RT5651_PLL1_PD_2 (0x1 << 3)
1076
1077#define RT5651_PLL_INP_MAX 40000000
1078#define RT5651_PLL_INP_MIN 256000
1079/* PLL M/N/K Code Control 1 (0x81) */
1080#define RT5651_PLL_N_MAX 0x1ff
1081#define RT5651_PLL_N_MASK (RT5651_PLL_N_MAX << 7)
1082#define RT5651_PLL_N_SFT 7
1083#define RT5651_PLL_K_MAX 0x1f
1084#define RT5651_PLL_K_MASK (RT5651_PLL_K_MAX)
1085#define RT5651_PLL_K_SFT 0
1086
1087/* PLL M/N/K Code Control 2 (0x82) */
1088#define RT5651_PLL_M_MAX 0xf
1089#define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
1090#define RT5651_PLL_M_SFT 12
1091#define RT5651_PLL_M_BP (0x1 << 11)
1092#define RT5651_PLL_M_BP_SFT 11
1093
1094/* PLL tracking mode 1 (0x83) */
1095#define RT5651_STO1_T_MASK (0x1 << 15)
1096#define RT5651_STO1_T_SFT 15
1097#define RT5651_STO1_T_SCLK (0x0 << 15)
1098#define RT5651_STO1_T_LRCK1 (0x1 << 15)
1099#define RT5651_STO2_T_MASK (0x1 << 12)
1100#define RT5651_STO2_T_SFT 12
1101#define RT5651_STO2_T_I2S2 (0x0 << 12)
1102#define RT5651_STO2_T_LRCK2 (0x1 << 12)
1103#define RT5651_ASRC2_REF_MASK (0x1 << 11)
1104#define RT5651_ASRC2_REF_SFT 11
1105#define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1106#define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1107#define RT5651_DMIC_1_M_MASK (0x1 << 9)
1108#define RT5651_DMIC_1_M_SFT 9
1109#define RT5651_DMIC_1_M_NOR (0x0 << 9)
1110#define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1111
1112/* PLL tracking mode 2 (0x84) */
1113#define RT5651_STO1_ASRC_EN (0x1 << 15)
1114#define RT5651_STO1_ASRC_EN_SFT 15
1115#define RT5651_STO2_ASRC_EN (0x1 << 14)
1116#define RT5651_STO2_ASRC_EN_SFT 14
1117#define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1118#define RT5651_STO1_DAC_M_SFT 13
1119#define RT5651_STO1_DAC_M_NOR (0x0 << 13)
1120#define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1121#define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1122#define RT5651_STO2_DAC_M_SFT 12
1123#define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1124#define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1125#define RT5651_ADC_M_MASK (0x1 << 11)
1126#define RT5651_ADC_M_SFT 11
1127#define RT5651_ADC_M_NOR (0x0 << 11)
1128#define RT5651_ADC_M_ASRC (0x1 << 11)
1129#define RT5651_I2S1_R_D_MASK (0x1 << 4)
1130#define RT5651_I2S1_R_D_SFT 4
1131#define RT5651_I2S1_R_D_DIS (0x0 << 4)
1132#define RT5651_I2S1_R_D_EN (0x1 << 4)
1133#define RT5651_I2S2_R_D_MASK (0x1 << 3)
1134#define RT5651_I2S2_R_D_SFT 3
1135#define RT5651_I2S2_R_D_DIS (0x0 << 3)
1136#define RT5651_I2S2_R_D_EN (0x1 << 3)
1137#define RT5651_PRE_SCLK_MASK (0x3)
1138#define RT5651_PRE_SCLK_SFT 0
1139#define RT5651_PRE_SCLK_512 (0x0)
1140#define RT5651_PRE_SCLK_1024 (0x1)
1141#define RT5651_PRE_SCLK_2048 (0x2)
1142
1143/* PLL tracking mode 3 (0x85) */
1144#define RT5651_I2S1_RATE_MASK (0xf << 12)
1145#define RT5651_I2S1_RATE_SFT 12
1146#define RT5651_I2S2_RATE_MASK (0xf << 8)
1147#define RT5651_I2S2_RATE_SFT 8
1148#define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1149#define RT5651_G_ASRC_LP_SFT 3
1150#define RT5651_ASRC_LP_F_M (0x1 << 2)
1151#define RT5651_ASRC_LP_F_SFT 2
1152#define RT5651_ASRC_LP_F_NOR (0x0 << 2)
1153#define RT5651_ASRC_LP_F_SB (0x1 << 2)
1154#define RT5651_FTK_PH_DET_MASK (0x3)
1155#define RT5651_FTK_PH_DET_SFT 0
1156#define RT5651_FTK_PH_DET_DIV1 (0x0)
1157#define RT5651_FTK_PH_DET_DIV2 (0x1)
1158#define RT5651_FTK_PH_DET_DIV4 (0x2)
1159#define RT5651_FTK_PH_DET_DIV8 (0x3)
1160
1161/*PLL tracking mode 6 (0x89) */
1162#define RT5651_I2S1_PD_MASK (0x7 << 12)
1163#define RT5651_I2S1_PD_SFT 12
1164#define RT5651_I2S2_PD_MASK (0x7 << 8)
1165#define RT5651_I2S2_PD_SFT 8
1166
1167/*PLL tracking mode 7 (0x8a) */
1168#define RT5651_FSI1_RATE_MASK (0xf << 12)
1169#define RT5651_FSI1_RATE_SFT 12
1170#define RT5651_FSI2_RATE_MASK (0xf << 8)
1171#define RT5651_FSI2_RATE_SFT 8
1172
1173/* HPOUT Over Current Detection (0x8b) */
1174#define RT5651_HP_OVCD_MASK (0x1 << 10)
1175#define RT5651_HP_OVCD_SFT 10
1176#define RT5651_HP_OVCD_DIS (0x0 << 10)
1177#define RT5651_HP_OVCD_EN (0x1 << 10)
1178#define RT5651_HP_OC_TH_MASK (0x3 << 8)
1179#define RT5651_HP_OC_TH_SFT 8
1180#define RT5651_HP_OC_TH_90 (0x0 << 8)
1181#define RT5651_HP_OC_TH_105 (0x1 << 8)
1182#define RT5651_HP_OC_TH_120 (0x2 << 8)
1183#define RT5651_HP_OC_TH_135 (0x3 << 8)
1184
1185/* Depop Mode Control 1 (0x8e) */
1186#define RT5651_SMT_TRIG_MASK (0x1 << 15)
1187#define RT5651_SMT_TRIG_SFT 15
1188#define RT5651_SMT_TRIG_DIS (0x0 << 15)
1189#define RT5651_SMT_TRIG_EN (0x1 << 15)
1190#define RT5651_HP_L_SMT_MASK (0x1 << 9)
1191#define RT5651_HP_L_SMT_SFT 9
1192#define RT5651_HP_L_SMT_DIS (0x0 << 9)
1193#define RT5651_HP_L_SMT_EN (0x1 << 9)
1194#define RT5651_HP_R_SMT_MASK (0x1 << 8)
1195#define RT5651_HP_R_SMT_SFT 8
1196#define RT5651_HP_R_SMT_DIS (0x0 << 8)
1197#define RT5651_HP_R_SMT_EN (0x1 << 8)
1198#define RT5651_HP_CD_PD_MASK (0x1 << 7)
1199#define RT5651_HP_CD_PD_SFT 7
1200#define RT5651_HP_CD_PD_DIS (0x0 << 7)
1201#define RT5651_HP_CD_PD_EN (0x1 << 7)
1202#define RT5651_RSTN_MASK (0x1 << 6)
1203#define RT5651_RSTN_SFT 6
1204#define RT5651_RSTN_DIS (0x0 << 6)
1205#define RT5651_RSTN_EN (0x1 << 6)
1206#define RT5651_RSTP_MASK (0x1 << 5)
1207#define RT5651_RSTP_SFT 5
1208#define RT5651_RSTP_DIS (0x0 << 5)
1209#define RT5651_RSTP_EN (0x1 << 5)
1210#define RT5651_HP_CO_MASK (0x1 << 4)
1211#define RT5651_HP_CO_SFT 4
1212#define RT5651_HP_CO_DIS (0x0 << 4)
1213#define RT5651_HP_CO_EN (0x1 << 4)
1214#define RT5651_HP_CP_MASK (0x1 << 3)
1215#define RT5651_HP_CP_SFT 3
1216#define RT5651_HP_CP_PD (0x0 << 3)
1217#define RT5651_HP_CP_PU (0x1 << 3)
1218#define RT5651_HP_SG_MASK (0x1 << 2)
1219#define RT5651_HP_SG_SFT 2
1220#define RT5651_HP_SG_DIS (0x0 << 2)
1221#define RT5651_HP_SG_EN (0x1 << 2)
1222#define RT5651_HP_DP_MASK (0x1 << 1)
1223#define RT5651_HP_DP_SFT 1
1224#define RT5651_HP_DP_PD (0x0 << 1)
1225#define RT5651_HP_DP_PU (0x1 << 1)
1226#define RT5651_HP_CB_MASK (0x1)
1227#define RT5651_HP_CB_SFT 0
1228#define RT5651_HP_CB_PD (0x0)
1229#define RT5651_HP_CB_PU (0x1)
1230
1231/* Depop Mode Control 2 (0x8f) */
1232#define RT5651_DEPOP_MASK (0x1 << 13)
1233#define RT5651_DEPOP_SFT 13
1234#define RT5651_DEPOP_AUTO (0x0 << 13)
1235#define RT5651_DEPOP_MAN (0x1 << 13)
1236#define RT5651_RAMP_MASK (0x1 << 12)
1237#define RT5651_RAMP_SFT 12
1238#define RT5651_RAMP_DIS (0x0 << 12)
1239#define RT5651_RAMP_EN (0x1 << 12)
1240#define RT5651_BPS_MASK (0x1 << 11)
1241#define RT5651_BPS_SFT 11
1242#define RT5651_BPS_DIS (0x0 << 11)
1243#define RT5651_BPS_EN (0x1 << 11)
1244#define RT5651_FAST_UPDN_MASK (0x1 << 10)
1245#define RT5651_FAST_UPDN_SFT 10
1246#define RT5651_FAST_UPDN_DIS (0x0 << 10)
1247#define RT5651_FAST_UPDN_EN (0x1 << 10)
1248#define RT5651_MRES_MASK (0x3 << 8)
1249#define RT5651_MRES_SFT 8
1250#define RT5651_MRES_15MO (0x0 << 8)
1251#define RT5651_MRES_25MO (0x1 << 8)
1252#define RT5651_MRES_35MO (0x2 << 8)
1253#define RT5651_MRES_45MO (0x3 << 8)
1254#define RT5651_VLO_MASK (0x1 << 7)
1255#define RT5651_VLO_SFT 7
1256#define RT5651_VLO_3V (0x0 << 7)
1257#define RT5651_VLO_32V (0x1 << 7)
1258#define RT5651_DIG_DP_MASK (0x1 << 6)
1259#define RT5651_DIG_DP_SFT 6
1260#define RT5651_DIG_DP_DIS (0x0 << 6)
1261#define RT5651_DIG_DP_EN (0x1 << 6)
1262#define RT5651_DP_TH_MASK (0x3 << 4)
1263#define RT5651_DP_TH_SFT 4
1264
1265/* Depop Mode Control 3 (0x90) */
1266#define RT5651_CP_SYS_MASK (0x7 << 12)
1267#define RT5651_CP_SYS_SFT 12
1268#define RT5651_CP_FQ1_MASK (0x7 << 8)
1269#define RT5651_CP_FQ1_SFT 8
1270#define RT5651_CP_FQ2_MASK (0x7 << 4)
1271#define RT5651_CP_FQ2_SFT 4
1272#define RT5651_CP_FQ3_MASK (0x7)
1273#define RT5651_CP_FQ3_SFT 0
1274#define RT5651_CP_FQ_1_5_KHZ 0
1275#define RT5651_CP_FQ_3_KHZ 1
1276#define RT5651_CP_FQ_6_KHZ 2
1277#define RT5651_CP_FQ_12_KHZ 3
1278#define RT5651_CP_FQ_24_KHZ 4
1279#define RT5651_CP_FQ_48_KHZ 5
1280#define RT5651_CP_FQ_96_KHZ 6
1281#define RT5651_CP_FQ_192_KHZ 7
1282
1283/* HPOUT charge pump (0x91) */
1284#define RT5651_OSW_L_MASK (0x1 << 11)
1285#define RT5651_OSW_L_SFT 11
1286#define RT5651_OSW_L_DIS (0x0 << 11)
1287#define RT5651_OSW_L_EN (0x1 << 11)
1288#define RT5651_OSW_R_MASK (0x1 << 10)
1289#define RT5651_OSW_R_SFT 10
1290#define RT5651_OSW_R_DIS (0x0 << 10)
1291#define RT5651_OSW_R_EN (0x1 << 10)
1292#define RT5651_PM_HP_MASK (0x3 << 8)
1293#define RT5651_PM_HP_SFT 8
1294#define RT5651_PM_HP_LV (0x0 << 8)
1295#define RT5651_PM_HP_MV (0x1 << 8)
1296#define RT5651_PM_HP_HV (0x2 << 8)
1297#define RT5651_IB_HP_MASK (0x3 << 6)
1298#define RT5651_IB_HP_SFT 6
1299#define RT5651_IB_HP_125IL (0x0 << 6)
1300#define RT5651_IB_HP_25IL (0x1 << 6)
1301#define RT5651_IB_HP_5IL (0x2 << 6)
1302#define RT5651_IB_HP_1IL (0x3 << 6)
1303
1304/* Micbias Control (0x93) */
1305#define RT5651_MIC1_BS_MASK (0x1 << 15)
1306#define RT5651_MIC1_BS_SFT 15
1307#define RT5651_MIC1_BS_9AV (0x0 << 15)
1308#define RT5651_MIC1_BS_75AV (0x1 << 15)
1309#define RT5651_MIC1_CLK_MASK (0x1 << 13)
1310#define RT5651_MIC1_CLK_SFT 13
1311#define RT5651_MIC1_CLK_DIS (0x0 << 13)
1312#define RT5651_MIC1_CLK_EN (0x1 << 13)
1313#define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1314#define RT5651_MIC1_OVCD_SFT 11
1315#define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1316#define RT5651_MIC1_OVCD_EN (0x1 << 11)
1317#define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1318#define RT5651_MIC1_OVTH_SFT 9
1319#define RT5651_MIC1_OVTH_600UA (0x0 << 9)
1320#define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1321#define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
1322#define RT5651_PWR_MB_MASK (0x1 << 5)
1323#define RT5651_PWR_MB_SFT 5
1324#define RT5651_PWR_MB_PD (0x0 << 5)
1325#define RT5651_PWR_MB_PU (0x1 << 5)
1326#define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1327#define RT5651_PWR_CLK12M_SFT 4
1328#define RT5651_PWR_CLK12M_PD (0x0 << 4)
1329#define RT5651_PWR_CLK12M_PU (0x1 << 4)
1330
1331/* Analog JD Control 1 (0x94) */
1332#define RT5651_JD2_CMP_MASK (0x7 << 12)
1333#define RT5651_JD2_CMP_SFT 12
1334#define RT5651_JD_PU (0x1 << 11)
1335#define RT5651_JD_PU_SFT 11
1336#define RT5651_JD_PD (0x1 << 10)
1337#define RT5651_JD_PD_SFT 10
1338#define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1339#define RT5651_JD_MODE_SEL_SFT 8
1340#define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1341#define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1342#define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1343#define RT5651_JD_M_CMP (0x7 << 4)
1344#define RT5651_JD_M_CMP_SFT 4
1345#define RT5651_JD_M_PU (0x1 << 3)
1346#define RT5651_JD_M_PU_SFT 3
1347#define RT5651_JD_M_PD (0x1 << 2)
1348#define RT5651_JD_M_PD_SFT 2
1349#define RT5651_JD_M_MODE_SEL_MASK (0x3)
1350#define RT5651_JD_M_MODE_SEL_SFT 0
1351#define RT5651_JD_M_MODE_SEL_M0 (0x0)
1352#define RT5651_JD_M_MODE_SEL_M1 (0x1)
1353#define RT5651_JD_M_MODE_SEL_M2 (0x2)
1354
1355/* Analog JD Control 2 (0x95) */
1356#define RT5651_JD3_CMP_MASK (0x7 << 12)
1357#define RT5651_JD3_CMP_SFT 12
1358
1359/* EQ Control 1 (0xb0) */
1360#define RT5651_EQ_SRC_MASK (0x1 << 15)
1361#define RT5651_EQ_SRC_SFT 15
1362#define RT5651_EQ_SRC_DAC (0x0 << 15)
1363#define RT5651_EQ_SRC_ADC (0x1 << 15)
1364#define RT5651_EQ_UPD (0x1 << 14)
1365#define RT5651_EQ_UPD_BIT 14
1366#define RT5651_EQ_CD_MASK (0x1 << 13)
1367#define RT5651_EQ_CD_SFT 13
1368#define RT5651_EQ_CD_DIS (0x0 << 13)
1369#define RT5651_EQ_CD_EN (0x1 << 13)
1370#define RT5651_EQ_DITH_MASK (0x3 << 8)
1371#define RT5651_EQ_DITH_SFT 8
1372#define RT5651_EQ_DITH_NOR (0x0 << 8)
1373#define RT5651_EQ_DITH_LSB (0x1 << 8)
1374#define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1375#define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1376#define RT5651_EQ_CD_F (0x1 << 7)
1377#define RT5651_EQ_CD_F_BIT 7
1378#define RT5651_EQ_STA_HP2 (0x1 << 6)
1379#define RT5651_EQ_STA_HP2_BIT 6
1380#define RT5651_EQ_STA_HP1 (0x1 << 5)
1381#define RT5651_EQ_STA_HP1_BIT 5
1382#define RT5651_EQ_STA_BP4 (0x1 << 4)
1383#define RT5651_EQ_STA_BP4_BIT 4
1384#define RT5651_EQ_STA_BP3 (0x1 << 3)
1385#define RT5651_EQ_STA_BP3_BIT 3
1386#define RT5651_EQ_STA_BP2 (0x1 << 2)
1387#define RT5651_EQ_STA_BP2_BIT 2
1388#define RT5651_EQ_STA_BP1 (0x1 << 1)
1389#define RT5651_EQ_STA_BP1_BIT 1
1390#define RT5651_EQ_STA_LP (0x1)
1391#define RT5651_EQ_STA_LP_BIT 0
1392
1393/* EQ Control 2 (0xb1) */
1394#define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1395#define RT5651_EQ_HPF1_M_SFT 8
1396#define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1397#define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1398#define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1399#define RT5651_EQ_LPF1_M_SFT 7
1400#define RT5651_EQ_LPF1_M_LO (0x0 << 7)
1401#define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1402#define RT5651_EQ_HPF2_MASK (0x1 << 6)
1403#define RT5651_EQ_HPF2_SFT 6
1404#define RT5651_EQ_HPF2_DIS (0x0 << 6)
1405#define RT5651_EQ_HPF2_EN (0x1 << 6)
1406#define RT5651_EQ_HPF1_MASK (0x1 << 5)
1407#define RT5651_EQ_HPF1_SFT 5
1408#define RT5651_EQ_HPF1_DIS (0x0 << 5)
1409#define RT5651_EQ_HPF1_EN (0x1 << 5)
1410#define RT5651_EQ_BPF4_MASK (0x1 << 4)
1411#define RT5651_EQ_BPF4_SFT 4
1412#define RT5651_EQ_BPF4_DIS (0x0 << 4)
1413#define RT5651_EQ_BPF4_EN (0x1 << 4)
1414#define RT5651_EQ_BPF3_MASK (0x1 << 3)
1415#define RT5651_EQ_BPF3_SFT 3
1416#define RT5651_EQ_BPF3_DIS (0x0 << 3)
1417#define RT5651_EQ_BPF3_EN (0x1 << 3)
1418#define RT5651_EQ_BPF2_MASK (0x1 << 2)
1419#define RT5651_EQ_BPF2_SFT 2
1420#define RT5651_EQ_BPF2_DIS (0x0 << 2)
1421#define RT5651_EQ_BPF2_EN (0x1 << 2)
1422#define RT5651_EQ_BPF1_MASK (0x1 << 1)
1423#define RT5651_EQ_BPF1_SFT 1
1424#define RT5651_EQ_BPF1_DIS (0x0 << 1)
1425#define RT5651_EQ_BPF1_EN (0x1 << 1)
1426#define RT5651_EQ_LPF_MASK (0x1)
1427#define RT5651_EQ_LPF_SFT 0
1428#define RT5651_EQ_LPF_DIS (0x0)
1429#define RT5651_EQ_LPF_EN (0x1)
1430#define RT5651_EQ_CTRL_MASK (0x7f)
1431
1432/* Memory Test (0xb2) */
1433#define RT5651_MT_MASK (0x1 << 15)
1434#define RT5651_MT_SFT 15
1435#define RT5651_MT_DIS (0x0 << 15)
1436#define RT5651_MT_EN (0x1 << 15)
1437
1438/* ALC Control 1 (0xb4) */
1439#define RT5651_ALC_P_MASK (0x1 << 15)
1440#define RT5651_ALC_P_SFT 15
1441#define RT5651_ALC_P_DAC (0x0 << 15)
1442#define RT5651_ALC_P_ADC (0x1 << 15)
1443#define RT5651_ALC_MASK (0x1 << 14)
1444#define RT5651_ALC_SFT 14
1445#define RT5651_ALC_DIS (0x0 << 14)
1446#define RT5651_ALC_EN (0x1 << 14)
1447#define RT5651_ALC_UPD (0x1 << 13)
1448#define RT5651_ALC_UPD_BIT 13
1449#define RT5651_ALC_AR_MASK (0x1f << 8)
1450#define RT5651_ALC_AR_SFT 8
1451#define RT5651_ALC_R_MASK (0x7 << 5)
1452#define RT5651_ALC_R_SFT 5
1453#define RT5651_ALC_R_48K (0x1 << 5)
1454#define RT5651_ALC_R_96K (0x2 << 5)
1455#define RT5651_ALC_R_192K (0x3 << 5)
1456#define RT5651_ALC_R_441K (0x5 << 5)
1457#define RT5651_ALC_R_882K (0x6 << 5)
1458#define RT5651_ALC_R_1764K (0x7 << 5)
1459#define RT5651_ALC_RC_MASK (0x1f)
1460#define RT5651_ALC_RC_SFT 0
1461
1462/* ALC Control 2 (0xb5) */
1463#define RT5651_ALC_POB_MASK (0x3f << 8)
1464#define RT5651_ALC_POB_SFT 8
1465#define RT5651_ALC_DRC_MASK (0x1 << 7)
1466#define RT5651_ALC_DRC_SFT 7
1467#define RT5651_ALC_DRC_DIS (0x0 << 7)
1468#define RT5651_ALC_DRC_EN (0x1 << 7)
1469#define RT5651_ALC_CPR_MASK (0x3 << 5)
1470#define RT5651_ALC_CPR_SFT 5
1471#define RT5651_ALC_CPR_1_1 (0x0 << 5)
1472#define RT5651_ALC_CPR_1_2 (0x1 << 5)
1473#define RT5651_ALC_CPR_1_4 (0x2 << 5)
1474#define RT5651_ALC_CPR_1_8 (0x3 << 5)
1475#define RT5651_ALC_PRB_MASK (0x1f)
1476#define RT5651_ALC_PRB_SFT 0
1477
1478/* ALC Control 3 (0xb6) */
1479#define RT5651_ALC_NGB_MASK (0xf << 12)
1480#define RT5651_ALC_NGB_SFT 12
1481#define RT5651_ALC_TAR_MASK (0x1f << 7)
1482#define RT5651_ALC_TAR_SFT 7
1483#define RT5651_ALC_NG_MASK (0x1 << 6)
1484#define RT5651_ALC_NG_SFT 6
1485#define RT5651_ALC_NG_DIS (0x0 << 6)
1486#define RT5651_ALC_NG_EN (0x1 << 6)
1487#define RT5651_ALC_NGH_MASK (0x1 << 5)
1488#define RT5651_ALC_NGH_SFT 5
1489#define RT5651_ALC_NGH_DIS (0x0 << 5)
1490#define RT5651_ALC_NGH_EN (0x1 << 5)
1491#define RT5651_ALC_NGT_MASK (0x1f)
1492#define RT5651_ALC_NGT_SFT 0
1493
1494/* Jack Detect Control 1 (0xbb) */
1495#define RT5651_JD_MASK (0x7 << 13)
1496#define RT5651_JD_SFT 13
1497#define RT5651_JD_DIS (0x0 << 13)
1498#define RT5651_JD_GPIO1 (0x1 << 13)
1499#define RT5651_JD_GPIO2 (0x2 << 13)
1500#define RT5651_JD_GPIO3 (0x3 << 13)
1501#define RT5651_JD_GPIO4 (0x4 << 13)
1502#define RT5651_JD_GPIO5 (0x5 << 13)
1503#define RT5651_JD_GPIO6 (0x6 << 13)
1504#define RT5651_JD_HP_MASK (0x1 << 11)
1505#define RT5651_JD_HP_SFT 11
1506#define RT5651_JD_HP_DIS (0x0 << 11)
1507#define RT5651_JD_HP_EN (0x1 << 11)
1508#define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1509#define RT5651_JD_HP_TRG_SFT 10
1510#define RT5651_JD_HP_TRG_LO (0x0 << 10)
1511#define RT5651_JD_HP_TRG_HI (0x1 << 10)
1512#define RT5651_JD_SPL_MASK (0x1 << 9)
1513#define RT5651_JD_SPL_SFT 9
1514#define RT5651_JD_SPL_DIS (0x0 << 9)
1515#define RT5651_JD_SPL_EN (0x1 << 9)
1516#define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1517#define RT5651_JD_SPL_TRG_SFT 8
1518#define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1519#define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1520#define RT5651_JD_SPR_MASK (0x1 << 7)
1521#define RT5651_JD_SPR_SFT 7
1522#define RT5651_JD_SPR_DIS (0x0 << 7)
1523#define RT5651_JD_SPR_EN (0x1 << 7)
1524#define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1525#define RT5651_JD_SPR_TRG_SFT 6
1526#define RT5651_JD_SPR_TRG_LO (0x0 << 6)
1527#define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1528#define RT5651_JD_LO_MASK (0x1 << 3)
1529#define RT5651_JD_LO_SFT 3
1530#define RT5651_JD_LO_DIS (0x0 << 3)
1531#define RT5651_JD_LO_EN (0x1 << 3)
1532#define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1533#define RT5651_JD_LO_TRG_SFT 2
1534#define RT5651_JD_LO_TRG_LO (0x0 << 2)
1535#define RT5651_JD_LO_TRG_HI (0x1 << 2)
1536
1537/* Jack Detect Control 2 (0xbc) */
1538#define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
1539#define RT5651_JD_TRG_SEL_SFT 9
1540#define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
1541#define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1542#define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
1543#define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1544#define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
1545#define RT5651_JD3_IRQ_EN (0x1 << 8)
1546#define RT5651_JD3_IRQ_EN_SFT 8
1547#define RT5651_JD3_EN_STKY (0x1 << 7)
1548#define RT5651_JD3_EN_STKY_SFT 7
1549#define RT5651_JD3_INV (0x1 << 6)
1550#define RT5651_JD3_INV_SFT 6
1551
1552/* IRQ Control 1 (0xbd) */
1553#define RT5651_IRQ_JD_MASK (0x1 << 15)
1554#define RT5651_IRQ_JD_SFT 15
1555#define RT5651_IRQ_JD_BP (0x0 << 15)
1556#define RT5651_IRQ_JD_NOR (0x1 << 15)
1557#define RT5651_JD_STKY_MASK (0x1 << 13)
1558#define RT5651_JD_STKY_SFT 13
1559#define RT5651_JD_STKY_DIS (0x0 << 13)
1560#define RT5651_JD_STKY_EN (0x1 << 13)
1561#define RT5651_JD_P_MASK (0x1 << 11)
1562#define RT5651_JD_P_SFT 11
1563#define RT5651_JD_P_NOR (0x0 << 11)
1564#define RT5651_JD_P_INV (0x1 << 11)
1565#define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1566#define RT5651_JD1_1_IRQ_EN_SFT 9
1567#define RT5651_JD1_1_EN_STKY (0x1 << 8)
1568#define RT5651_JD1_1_EN_STKY_SFT 8
1569#define RT5651_JD1_1_INV (0x1 << 7)
1570#define RT5651_JD1_1_INV_SFT 7
1571#define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1572#define RT5651_JD1_2_IRQ_EN_SFT 6
1573#define RT5651_JD1_2_EN_STKY (0x1 << 5)
1574#define RT5651_JD1_2_EN_STKY_SFT 5
1575#define RT5651_JD1_2_INV (0x1 << 4)
1576#define RT5651_JD1_2_INV_SFT 4
1577#define RT5651_JD2_IRQ_EN (0x1 << 3)
1578#define RT5651_JD2_IRQ_EN_SFT 3
1579#define RT5651_JD2_EN_STKY (0x1 << 2)
1580#define RT5651_JD2_EN_STKY_SFT 2
1581#define RT5651_JD2_INV (0x1 << 1)
1582#define RT5651_JD2_INV_SFT 1
1583
1584/* IRQ Control 2 (0xbe) */
1585#define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1586#define RT5651_IRQ_MB1_OC_SFT 15
1587#define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1588#define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1589#define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1590#define RT5651_MB1_OC_STKY_SFT 11
1591#define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1592#define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1593#define RT5651_MB1_OC_P_MASK (0x1 << 7)
1594#define RT5651_MB1_OC_P_SFT 7
1595#define RT5651_MB1_OC_P_NOR (0x0 << 7)
1596#define RT5651_MB1_OC_P_INV (0x1 << 7)
1597#define RT5651_MB2_OC_P_MASK (0x1 << 6)
1598#define RT5651_MB1_OC_CLR (0x1 << 3)
1599#define RT5651_MB1_OC_CLR_SFT 3
1600#define RT5651_STA_GPIO8 (0x1)
1601#define RT5651_STA_GPIO8_BIT 0
1602
1603/* Internal Status and GPIO status (0xbf) */
1604#define RT5651_STA_JD3 (0x1 << 15)
1605#define RT5651_STA_JD3_BIT 15
1606#define RT5651_STA_JD2 (0x1 << 14)
1607#define RT5651_STA_JD2_BIT 14
1608#define RT5651_STA_JD1_2 (0x1 << 13)
1609#define RT5651_STA_JD1_2_BIT 13
1610#define RT5651_STA_JD1_1 (0x1 << 12)
1611#define RT5651_STA_JD1_1_BIT 12
1612#define RT5651_STA_GP7 (0x1 << 11)
1613#define RT5651_STA_GP7_BIT 11
1614#define RT5651_STA_GP6 (0x1 << 10)
1615#define RT5651_STA_GP6_BIT 10
1616#define RT5651_STA_GP5 (0x1 << 9)
1617#define RT5651_STA_GP5_BIT 9
1618#define RT5651_STA_GP1 (0x1 << 8)
1619#define RT5651_STA_GP1_BIT 8
1620#define RT5651_STA_GP2 (0x1 << 7)
1621#define RT5651_STA_GP2_BIT 7
1622#define RT5651_STA_GP3 (0x1 << 6)
1623#define RT5651_STA_GP3_BIT 6
1624#define RT5651_STA_GP4 (0x1 << 5)
1625#define RT5651_STA_GP4_BIT 5
1626#define RT5651_STA_GP_JD (0x1 << 4)
1627#define RT5651_STA_GP_JD_BIT 4
1628
1629/* GPIO Control 1 (0xc0) */
1630#define RT5651_GP1_PIN_MASK (0x1 << 15)
1631#define RT5651_GP1_PIN_SFT 15
1632#define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1633#define RT5651_GP1_PIN_IRQ (0x1 << 15)
1634#define RT5651_GP2_PIN_MASK (0x1 << 14)
1635#define RT5651_GP2_PIN_SFT 14
1636#define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1637#define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1638#define RT5651_GPIO_M_MASK (0x1 << 9)
1639#define RT5651_GPIO_M_SFT 9
1640#define RT5651_GPIO_M_FLT (0x0 << 9)
1641#define RT5651_GPIO_M_PH (0x1 << 9)
1642#define RT5651_I2S2_SEL_MASK (0x1 << 8)
1643#define RT5651_I2S2_SEL_SFT 8
1644#define RT5651_I2S2_SEL_I2S (0x0 << 8)
1645#define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1646#define RT5651_GP5_PIN_MASK (0x1 << 7)
1647#define RT5651_GP5_PIN_SFT 7
1648#define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
1649#define RT5651_GP5_PIN_IRQ (0x1 << 7)
1650#define RT5651_GP6_PIN_MASK (0x1 << 6)
1651#define RT5651_GP6_PIN_SFT 6
1652#define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
1653#define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1654#define RT5651_GP7_PIN_MASK (0x1 << 5)
1655#define RT5651_GP7_PIN_SFT 5
1656#define RT5651_GP7_PIN_GPIO7 (0x0 << 5)
1657#define RT5651_GP7_PIN_IRQ (0x1 << 5)
1658#define RT5651_GP8_PIN_MASK (0x1 << 4)
1659#define RT5651_GP8_PIN_SFT 4
1660#define RT5651_GP8_PIN_GPIO8 (0x0 << 4)
1661#define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1662#define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1663#define RT5651_GPIO_PDM_SEL_SFT 3
1664#define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
1665#define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1666
1667/* GPIO Control 2 (0xc1) */
1668#define RT5651_GP5_DR_MASK (0x1 << 14)
1669#define RT5651_GP5_DR_SFT 14
1670#define RT5651_GP5_DR_IN (0x0 << 14)
1671#define RT5651_GP5_DR_OUT (0x1 << 14)
1672#define RT5651_GP5_OUT_MASK (0x1 << 13)
1673#define RT5651_GP5_OUT_SFT 13
1674#define RT5651_GP5_OUT_LO (0x0 << 13)
1675#define RT5651_GP5_OUT_HI (0x1 << 13)
1676#define RT5651_GP5_P_MASK (0x1 << 12)
1677#define RT5651_GP5_P_SFT 12
1678#define RT5651_GP5_P_NOR (0x0 << 12)
1679#define RT5651_GP5_P_INV (0x1 << 12)
1680#define RT5651_GP4_DR_MASK (0x1 << 11)
1681#define RT5651_GP4_DR_SFT 11
1682#define RT5651_GP4_DR_IN (0x0 << 11)
1683#define RT5651_GP4_DR_OUT (0x1 << 11)
1684#define RT5651_GP4_OUT_MASK (0x1 << 10)
1685#define RT5651_GP4_OUT_SFT 10
1686#define RT5651_GP4_OUT_LO (0x0 << 10)
1687#define RT5651_GP4_OUT_HI (0x1 << 10)
1688#define RT5651_GP4_P_MASK (0x1 << 9)
1689#define RT5651_GP4_P_SFT 9
1690#define RT5651_GP4_P_NOR (0x0 << 9)
1691#define RT5651_GP4_P_INV (0x1 << 9)
1692#define RT5651_GP3_DR_MASK (0x1 << 8)
1693#define RT5651_GP3_DR_SFT 8
1694#define RT5651_GP3_DR_IN (0x0 << 8)
1695#define RT5651_GP3_DR_OUT (0x1 << 8)
1696#define RT5651_GP3_OUT_MASK (0x1 << 7)
1697#define RT5651_GP3_OUT_SFT 7
1698#define RT5651_GP3_OUT_LO (0x0 << 7)
1699#define RT5651_GP3_OUT_HI (0x1 << 7)
1700#define RT5651_GP3_P_MASK (0x1 << 6)
1701#define RT5651_GP3_P_SFT 6
1702#define RT5651_GP3_P_NOR (0x0 << 6)
1703#define RT5651_GP3_P_INV (0x1 << 6)
1704#define RT5651_GP2_DR_MASK (0x1 << 5)
1705#define RT5651_GP2_DR_SFT 5
1706#define RT5651_GP2_DR_IN (0x0 << 5)
1707#define RT5651_GP2_DR_OUT (0x1 << 5)
1708#define RT5651_GP2_OUT_MASK (0x1 << 4)
1709#define RT5651_GP2_OUT_SFT 4
1710#define RT5651_GP2_OUT_LO (0x0 << 4)
1711#define RT5651_GP2_OUT_HI (0x1 << 4)
1712#define RT5651_GP2_P_MASK (0x1 << 3)
1713#define RT5651_GP2_P_SFT 3
1714#define RT5651_GP2_P_NOR (0x0 << 3)
1715#define RT5651_GP2_P_INV (0x1 << 3)
1716#define RT5651_GP1_DR_MASK (0x1 << 2)
1717#define RT5651_GP1_DR_SFT 2
1718#define RT5651_GP1_DR_IN (0x0 << 2)
1719#define RT5651_GP1_DR_OUT (0x1 << 2)
1720#define RT5651_GP1_OUT_MASK (0x1 << 1)
1721#define RT5651_GP1_OUT_SFT 1
1722#define RT5651_GP1_OUT_LO (0x0 << 1)
1723#define RT5651_GP1_OUT_HI (0x1 << 1)
1724#define RT5651_GP1_P_MASK (0x1)
1725#define RT5651_GP1_P_SFT 0
1726#define RT5651_GP1_P_NOR (0x0)
1727#define RT5651_GP1_P_INV (0x1)
1728
1729/* GPIO Control 3 (0xc2) */
1730#define RT5651_GP8_DR_MASK (0x1 << 8)
1731#define RT5651_GP8_DR_SFT 8
1732#define RT5651_GP8_DR_IN (0x0 << 8)
1733#define RT5651_GP8_DR_OUT (0x1 << 8)
1734#define RT5651_GP8_OUT_MASK (0x1 << 7)
1735#define RT5651_GP8_OUT_SFT 7
1736#define RT5651_GP8_OUT_LO (0x0 << 7)
1737#define RT5651_GP8_OUT_HI (0x1 << 7)
1738#define RT5651_GP8_P_MASK (0x1 << 6)
1739#define RT5651_GP8_P_SFT 6
1740#define RT5651_GP8_P_NOR (0x0 << 6)
1741#define RT5651_GP8_P_INV (0x1 << 6)
1742#define RT5651_GP7_DR_MASK (0x1 << 5)
1743#define RT5651_GP7_DR_SFT 5
1744#define RT5651_GP7_DR_IN (0x0 << 5)
1745#define RT5651_GP7_DR_OUT (0x1 << 5)
1746#define RT5651_GP7_OUT_MASK (0x1 << 4)
1747#define RT5651_GP7_OUT_SFT 4
1748#define RT5651_GP7_OUT_LO (0x0 << 4)
1749#define RT5651_GP7_OUT_HI (0x1 << 4)
1750#define RT5651_GP7_P_MASK (0x1 << 3)
1751#define RT5651_GP7_P_SFT 3
1752#define RT5651_GP7_P_NOR (0x0 << 3)
1753#define RT5651_GP7_P_INV (0x1 << 3)
1754#define RT5651_GP6_DR_MASK (0x1 << 2)
1755#define RT5651_GP6_DR_SFT 2
1756#define RT5651_GP6_DR_IN (0x0 << 2)
1757#define RT5651_GP6_DR_OUT (0x1 << 2)
1758#define RT5651_GP6_OUT_MASK (0x1 << 1)
1759#define RT5651_GP6_OUT_SFT 1
1760#define RT5651_GP6_OUT_LO (0x0 << 1)
1761#define RT5651_GP6_OUT_HI (0x1 << 1)
1762#define RT5651_GP6_P_MASK (0x1)
1763#define RT5651_GP6_P_SFT 0
1764#define RT5651_GP6_P_NOR (0x0)
1765#define RT5651_GP6_P_INV (0x1)
1766
1767/* Scramble Control (0xce) */
1768#define RT5651_SCB_SWAP_MASK (0x1 << 15)
1769#define RT5651_SCB_SWAP_SFT 15
1770#define RT5651_SCB_SWAP_DIS (0x0 << 15)
1771#define RT5651_SCB_SWAP_EN (0x1 << 15)
1772#define RT5651_SCB_MASK (0x1 << 14)
1773#define RT5651_SCB_SFT 14
1774#define RT5651_SCB_DIS (0x0 << 14)
1775#define RT5651_SCB_EN (0x1 << 14)
1776
1777/* Baseback Control (0xcf) */
1778#define RT5651_BB_MASK (0x1 << 15)
1779#define RT5651_BB_SFT 15
1780#define RT5651_BB_DIS (0x0 << 15)
1781#define RT5651_BB_EN (0x1 << 15)
1782#define RT5651_BB_CT_MASK (0x7 << 12)
1783#define RT5651_BB_CT_SFT 12
1784#define RT5651_BB_CT_A (0x0 << 12)
1785#define RT5651_BB_CT_B (0x1 << 12)
1786#define RT5651_BB_CT_C (0x2 << 12)
1787#define RT5651_BB_CT_D (0x3 << 12)
1788#define RT5651_M_BB_L_MASK (0x1 << 9)
1789#define RT5651_M_BB_L_SFT 9
1790#define RT5651_M_BB_R_MASK (0x1 << 8)
1791#define RT5651_M_BB_R_SFT 8
1792#define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1793#define RT5651_M_BB_HPF_L_SFT 7
1794#define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1795#define RT5651_M_BB_HPF_R_SFT 6
1796#define RT5651_G_BB_BST_MASK (0x3f)
1797#define RT5651_G_BB_BST_SFT 0
1798
1799/* MP3 Plus Control 1 (0xd0) */
1800#define RT5651_M_MP3_L_MASK (0x1 << 15)
1801#define RT5651_M_MP3_L_SFT 15
1802#define RT5651_M_MP3_R_MASK (0x1 << 14)
1803#define RT5651_M_MP3_R_SFT 14
1804#define RT5651_M_MP3_MASK (0x1 << 13)
1805#define RT5651_M_MP3_SFT 13
1806#define RT5651_M_MP3_DIS (0x0 << 13)
1807#define RT5651_M_MP3_EN (0x1 << 13)
1808#define RT5651_EG_MP3_MASK (0x1f << 8)
1809#define RT5651_EG_MP3_SFT 8
1810#define RT5651_MP3_HLP_MASK (0x1 << 7)
1811#define RT5651_MP3_HLP_SFT 7
1812#define RT5651_MP3_HLP_DIS (0x0 << 7)
1813#define RT5651_MP3_HLP_EN (0x1 << 7)
1814#define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1815#define RT5651_M_MP3_ORG_L_SFT 6
1816#define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1817#define RT5651_M_MP3_ORG_R_SFT 5
1818
1819/* MP3 Plus Control 2 (0xd1) */
1820#define RT5651_MP3_WT_MASK (0x1 << 13)
1821#define RT5651_MP3_WT_SFT 13
1822#define RT5651_MP3_WT_1_4 (0x0 << 13)
1823#define RT5651_MP3_WT_1_2 (0x1 << 13)
1824#define RT5651_OG_MP3_MASK (0x1f << 8)
1825#define RT5651_OG_MP3_SFT 8
1826#define RT5651_HG_MP3_MASK (0x3f)
1827#define RT5651_HG_MP3_SFT 0
1828
1829/* 3D HP Control 1 (0xd2) */
1830#define RT5651_3D_CF_MASK (0x1 << 15)
1831#define RT5651_3D_CF_SFT 15
1832#define RT5651_3D_CF_DIS (0x0 << 15)
1833#define RT5651_3D_CF_EN (0x1 << 15)
1834#define RT5651_3D_HP_MASK (0x1 << 14)
1835#define RT5651_3D_HP_SFT 14
1836#define RT5651_3D_HP_DIS (0x0 << 14)
1837#define RT5651_3D_HP_EN (0x1 << 14)
1838#define RT5651_3D_BT_MASK (0x1 << 13)
1839#define RT5651_3D_BT_SFT 13
1840#define RT5651_3D_BT_DIS (0x0 << 13)
1841#define RT5651_3D_BT_EN (0x1 << 13)
1842#define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1843#define RT5651_3D_1F_MIX_SFT 11
1844#define RT5651_3D_HP_M_MASK (0x1 << 10)
1845#define RT5651_3D_HP_M_SFT 10
1846#define RT5651_3D_HP_M_SUR (0x0 << 10)
1847#define RT5651_3D_HP_M_FRO (0x1 << 10)
1848#define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1849#define RT5651_M_3D_HRTF_SFT 9
1850#define RT5651_M_3D_D2H_MASK (0x1 << 8)
1851#define RT5651_M_3D_D2H_SFT 8
1852#define RT5651_M_3D_D2R_MASK (0x1 << 7)
1853#define RT5651_M_3D_D2R_SFT 7
1854#define RT5651_M_3D_REVB_MASK (0x1 << 6)
1855#define RT5651_M_3D_REVB_SFT 6
1856
1857/* Adjustable high pass filter control 1 (0xd3) */
1858#define RT5651_2ND_HPF_MASK (0x1 << 15)
1859#define RT5651_2ND_HPF_SFT 15
1860#define RT5651_2ND_HPF_DIS (0x0 << 15)
1861#define RT5651_2ND_HPF_EN (0x1 << 15)
1862#define RT5651_HPF_CF_L_MASK (0x7 << 12)
1863#define RT5651_HPF_CF_L_SFT 12
1864#define RT5651_HPF_CF_R_MASK (0x7 << 8)
1865#define RT5651_HPF_CF_R_SFT 8
1866#define RT5651_ZD_T_MASK (0x3 << 6)
1867#define RT5651_ZD_T_SFT 6
1868#define RT5651_ZD_F_MASK (0x3 << 4)
1869#define RT5651_ZD_F_SFT 4
1870#define RT5651_ZD_F_IM (0x0 << 4)
1871#define RT5651_ZD_F_ZC_IM (0x1 << 4)
1872#define RT5651_ZD_F_ZC_IOD (0x2 << 4)
1873#define RT5651_ZD_F_UN (0x3 << 4)
1874
1875/* Adjustable high pass filter control 2 (0xd4) */
1876#define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1877#define RT5651_HPF_CF_L_NUM_SFT 8
1878#define RT5651_HPF_CF_R_NUM_MASK (0x3f)
1879#define RT5651_HPF_CF_R_NUM_SFT 0
1880
1881/* HP calibration control and Amp detection (0xd6) */
1882#define RT5651_SI_DAC_MASK (0x1 << 11)
1883#define RT5651_SI_DAC_SFT 11
1884#define RT5651_SI_DAC_AUTO (0x0 << 11)
1885#define RT5651_SI_DAC_TEST (0x1 << 11)
1886#define RT5651_DC_CAL_M_MASK (0x1 << 10)
1887#define RT5651_DC_CAL_M_SFT 10
1888#define RT5651_DC_CAL_M_NOR (0x0 << 10)
1889#define RT5651_DC_CAL_M_CAL (0x1 << 10)
1890#define RT5651_DC_CAL_MASK (0x1 << 9)
1891#define RT5651_DC_CAL_SFT 9
1892#define RT5651_DC_CAL_DIS (0x0 << 9)
1893#define RT5651_DC_CAL_EN (0x1 << 9)
1894#define RT5651_HPD_RCV_MASK (0x7 << 6)
1895#define RT5651_HPD_RCV_SFT 6
1896#define RT5651_HPD_PS_MASK (0x1 << 5)
1897#define RT5651_HPD_PS_SFT 5
1898#define RT5651_HPD_PS_DIS (0x0 << 5)
1899#define RT5651_HPD_PS_EN (0x1 << 5)
1900#define RT5651_CAL_M_MASK (0x1 << 4)
1901#define RT5651_CAL_M_SFT 4
1902#define RT5651_CAL_M_DEP (0x0 << 4)
1903#define RT5651_CAL_M_CAL (0x1 << 4)
1904#define RT5651_CAL_MASK (0x1 << 3)
1905#define RT5651_CAL_SFT 3
1906#define RT5651_CAL_DIS (0x0 << 3)
1907#define RT5651_CAL_EN (0x1 << 3)
1908#define RT5651_CAL_TEST_MASK (0x1 << 2)
1909#define RT5651_CAL_TEST_SFT 2
1910#define RT5651_CAL_TEST_DIS (0x0 << 2)
1911#define RT5651_CAL_TEST_EN (0x1 << 2)
1912#define RT5651_CAL_P_MASK (0x3)
1913#define RT5651_CAL_P_SFT 0
1914#define RT5651_CAL_P_NONE (0x0)
1915#define RT5651_CAL_P_CAL (0x1)
1916#define RT5651_CAL_P_DAC_CAL (0x2)
1917
1918/* Soft volume and zero cross control 1 (0xd9) */
1919#define RT5651_SV_MASK (0x1 << 15)
1920#define RT5651_SV_SFT 15
1921#define RT5651_SV_DIS (0x0 << 15)
1922#define RT5651_SV_EN (0x1 << 15)
1923#define RT5651_OUT_SV_MASK (0x1 << 13)
1924#define RT5651_OUT_SV_SFT 13
1925#define RT5651_OUT_SV_DIS (0x0 << 13)
1926#define RT5651_OUT_SV_EN (0x1 << 13)
1927#define RT5651_HP_SV_MASK (0x1 << 12)
1928#define RT5651_HP_SV_SFT 12
1929#define RT5651_HP_SV_DIS (0x0 << 12)
1930#define RT5651_HP_SV_EN (0x1 << 12)
1931#define RT5651_ZCD_DIG_MASK (0x1 << 11)
1932#define RT5651_ZCD_DIG_SFT 11
1933#define RT5651_ZCD_DIG_DIS (0x0 << 11)
1934#define RT5651_ZCD_DIG_EN (0x1 << 11)
1935#define RT5651_ZCD_MASK (0x1 << 10)
1936#define RT5651_ZCD_SFT 10
1937#define RT5651_ZCD_PD (0x0 << 10)
1938#define RT5651_ZCD_PU (0x1 << 10)
1939#define RT5651_M_ZCD_MASK (0x3f << 4)
1940#define RT5651_M_ZCD_SFT 4
1941#define RT5651_M_ZCD_OM_L (0x1 << 7)
1942#define RT5651_M_ZCD_OM_R (0x1 << 6)
1943#define RT5651_M_ZCD_RM_L (0x1 << 5)
1944#define RT5651_M_ZCD_RM_R (0x1 << 4)
1945#define RT5651_SV_DLY_MASK (0xf)
1946#define RT5651_SV_DLY_SFT 0
1947
1948/* Soft volume and zero cross control 2 (0xda) */
1949#define RT5651_ZCD_HP_MASK (0x1 << 15)
1950#define RT5651_ZCD_HP_SFT 15
1951#define RT5651_ZCD_HP_DIS (0x0 << 15)
1952#define RT5651_ZCD_HP_EN (0x1 << 15)
1953
1954/* Digital Misc Control (0xfa) */
1955#define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1956#define RT5651_I2S2_MS_SP_SEL 8
1957#define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1958#define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1959#define RT5651_CLK_DET_EN (0x1 << 3)
1960#define RT5651_CLK_DET_EN_SFT 3
1961#define RT5651_AMP_DET_EN (0x1 << 1)
1962#define RT5651_AMP_DET_EN_SFT 1
1963#define RT5651_D_GATE_EN (0x1)
1964#define RT5651_D_GATE_EN_SFT 0
1965
1966/* Codec Private Register definition */
1967
1968/* MIC Over current threshold scale factor (0x15) */
1969#define RT5651_MIC_OVCD_SF_MASK (0x3 << 8)
1970#define RT5651_MIC_OVCD_SF_SFT 8
1971#define RT5651_MIC_OVCD_SF_0P5 (0x0 << 8)
1972#define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
1973#define RT5651_MIC_OVCD_SF_1P0 (0x2 << 8)
1974#define RT5651_MIC_OVCD_SF_1P5 (0x3 << 8)
1975
1976/* 3D Speaker Control (0x63) */
1977#define RT5651_3D_SPK_MASK (0x1 << 15)
1978#define RT5651_3D_SPK_SFT 15
1979#define RT5651_3D_SPK_DIS (0x0 << 15)
1980#define RT5651_3D_SPK_EN (0x1 << 15)
1981#define RT5651_3D_SPK_M_MASK (0x3 << 13)
1982#define RT5651_3D_SPK_M_SFT 13
1983#define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1984#define RT5651_3D_SPK_CG_SFT 8
1985#define RT5651_3D_SPK_SG_MASK (0x1f)
1986#define RT5651_3D_SPK_SG_SFT 0
1987
1988/* Wind Noise Detection Control 1 (0x6c) */
1989#define RT5651_WND_MASK (0x1 << 15)
1990#define RT5651_WND_SFT 15
1991#define RT5651_WND_DIS (0x0 << 15)
1992#define RT5651_WND_EN (0x1 << 15)
1993
1994/* Wind Noise Detection Control 2 (0x6d) */
1995#define RT5651_WND_FC_NW_MASK (0x3f << 10)
1996#define RT5651_WND_FC_NW_SFT 10
1997#define RT5651_WND_FC_WK_MASK (0x3f << 4)
1998#define RT5651_WND_FC_WK_SFT 4
1999
2000/* Wind Noise Detection Control 3 (0x6e) */
2001#define RT5651_HPF_FC_MASK (0x3f << 6)
2002#define RT5651_HPF_FC_SFT 6
2003#define RT5651_WND_FC_ST_MASK (0x3f)
2004#define RT5651_WND_FC_ST_SFT 0
2005
2006/* Wind Noise Detection Control 4 (0x6f) */
2007#define RT5651_WND_TH_LO_MASK (0x3ff)
2008#define RT5651_WND_TH_LO_SFT 0
2009
2010/* Wind Noise Detection Control 5 (0x70) */
2011#define RT5651_WND_TH_HI_MASK (0x3ff)
2012#define RT5651_WND_TH_HI_SFT 0
2013
2014/* Wind Noise Detection Control 8 (0x73) */
2015#define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2016#define RT5651_WND_WIND_SFT 13
2017#define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2018#define RT5651_WND_STRONG_SFT 12
2019enum {
2020 RT5651_NO_WIND,
2021 RT5651_BREEZE,
2022 RT5651_STORM,
2023};
2024
2025/* Dipole Speaker Interface (0x75) */
2026#define RT5651_DP_ATT_MASK (0x3 << 14)
2027#define RT5651_DP_ATT_SFT 14
2028#define RT5651_DP_SPK_MASK (0x1 << 10)
2029#define RT5651_DP_SPK_SFT 10
2030#define RT5651_DP_SPK_DIS (0x0 << 10)
2031#define RT5651_DP_SPK_EN (0x1 << 10)
2032
2033/* EQ Pre Volume Control (0xb3) */
2034#define RT5651_EQ_PRE_VOL_MASK (0xffff)
2035#define RT5651_EQ_PRE_VOL_SFT 0
2036
2037/* EQ Post Volume Control (0xb4) */
2038#define RT5651_EQ_PST_VOL_MASK (0xffff)
2039#define RT5651_EQ_PST_VOL_SFT 0
2040
2041/* System Clock Source */
2042enum {
2043 RT5651_SCLK_S_MCLK,
2044 RT5651_SCLK_S_PLL1,
2045 RT5651_SCLK_S_RCCLK,
2046};
2047
2048/* PLL1 Source */
2049enum {
2050 RT5651_PLL1_S_MCLK,
2051 RT5651_PLL1_S_BCLK1,
2052 RT5651_PLL1_S_BCLK2,
2053};
2054
2055enum {
2056 RT5651_AIF1,
2057 RT5651_AIF2,
2058 RT5651_AIFS,
2059};
2060
2061struct rt5651_pll_code {
2062 bool m_bp; /* Indicates bypass m code or not. */
2063 int m_code;
2064 int n_code;
2065 int k_code;
2066};
2067
2068struct rt5651_priv {
2069 struct snd_soc_component *component;
2070 struct regmap *regmap;
2071 /* Jack and button detect data */
2072 struct snd_soc_jack *hp_jack;
2073 struct gpio_desc *gpiod_hp_det;
2074 struct work_struct jack_detect_work;
2075 struct delayed_work bp_work;
2076 bool ovcd_irq_enabled;
2077 bool pressed;
2078 bool press_reported;
2079 int press_count;
2080 int release_count;
2081 int poll_count;
2082 unsigned int jd_src;
2083 bool jd_active_high;
2084 unsigned int ovcd_th;
2085 unsigned int ovcd_sf;
2086
2087 int irq;
2088 int sysclk;
2089 int sysclk_src;
2090 int lrck[RT5651_AIFS];
2091 int bclk[RT5651_AIFS];
2092 int master[RT5651_AIFS];
2093
2094 int pll_src;
2095 int pll_in;
2096 int pll_out;
2097
2098 int dmic_en;
2099 bool hp_mute;
2100};
2101
2102#endif /* __RT5651_H__ */