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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) ST-Ericsson SA 2012
4 *
5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
6 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
7 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
8 * for ST-Ericsson.
9 *
10 * Based on the early work done by:
11 * Mikko J. Lehto <mikko.lehto@symbio.com>,
12 * Mikko Sarmanne <mikko.sarmanne@symbio.com>,
13 * for ST-Ericsson.
14 */
15
16#ifndef AB8500_CODEC_REGISTERS_H
17#define AB8500_CODEC_REGISTERS_H
18
19#define AB8500_SUPPORTED_RATE (SNDRV_PCM_RATE_48000)
20#define AB8500_SUPPORTED_FMT (SNDRV_PCM_FMTBIT_S16_LE)
21
22/* AB8500 interface slot offset definitions */
23
24#define AB8500_AD_DATA0_OFFSET 0
25#define AB8500_DA_DATA0_OFFSET 8
26#define AB8500_AD_DATA1_OFFSET 16
27#define AB8500_DA_DATA1_OFFSET 24
28
29/* AB8500 audio bank (0x0d) register definitions */
30
31#define AB8500_POWERUP 0x00
32#define AB8500_AUDSWRESET 0x01
33#define AB8500_ADPATHENA 0x02
34#define AB8500_DAPATHENA 0x03
35#define AB8500_ANACONF1 0x04
36#define AB8500_ANACONF2 0x05
37#define AB8500_DIGMICCONF 0x06
38#define AB8500_ANACONF3 0x07
39#define AB8500_ANACONF4 0x08
40#define AB8500_DAPATHCONF 0x09
41#define AB8500_MUTECONF 0x0A
42#define AB8500_SHORTCIRCONF 0x0B
43#define AB8500_ANACONF5 0x0C
44#define AB8500_ENVCPCONF 0x0D
45#define AB8500_SIGENVCONF 0x0E
46#define AB8500_PWMGENCONF1 0x0F
47#define AB8500_PWMGENCONF2 0x10
48#define AB8500_PWMGENCONF3 0x11
49#define AB8500_PWMGENCONF4 0x12
50#define AB8500_PWMGENCONF5 0x13
51#define AB8500_ANAGAIN1 0x14
52#define AB8500_ANAGAIN2 0x15
53#define AB8500_ANAGAIN3 0x16
54#define AB8500_ANAGAIN4 0x17
55#define AB8500_DIGLINHSLGAIN 0x18
56#define AB8500_DIGLINHSRGAIN 0x19
57#define AB8500_ADFILTCONF 0x1A
58#define AB8500_DIGIFCONF1 0x1B
59#define AB8500_DIGIFCONF2 0x1C
60#define AB8500_DIGIFCONF3 0x1D
61#define AB8500_DIGIFCONF4 0x1E
62#define AB8500_ADSLOTSEL1 0x1F
63#define AB8500_ADSLOTSEL2 0x20
64#define AB8500_ADSLOTSEL3 0x21
65#define AB8500_ADSLOTSEL4 0x22
66#define AB8500_ADSLOTSEL5 0x23
67#define AB8500_ADSLOTSEL6 0x24
68#define AB8500_ADSLOTSEL7 0x25
69#define AB8500_ADSLOTSEL8 0x26
70#define AB8500_ADSLOTSEL9 0x27
71#define AB8500_ADSLOTSEL10 0x28
72#define AB8500_ADSLOTSEL11 0x29
73#define AB8500_ADSLOTSEL12 0x2A
74#define AB8500_ADSLOTSEL13 0x2B
75#define AB8500_ADSLOTSEL14 0x2C
76#define AB8500_ADSLOTSEL15 0x2D
77#define AB8500_ADSLOTSEL16 0x2E
78#define AB8500_ADSLOTSEL(slot) (AB8500_ADSLOTSEL1 + (slot >> 1))
79#define AB8500_ADSLOTHIZCTRL1 0x2F
80#define AB8500_ADSLOTHIZCTRL2 0x30
81#define AB8500_ADSLOTHIZCTRL3 0x31
82#define AB8500_ADSLOTHIZCTRL4 0x32
83#define AB8500_DASLOTCONF1 0x33
84#define AB8500_DASLOTCONF2 0x34
85#define AB8500_DASLOTCONF3 0x35
86#define AB8500_DASLOTCONF4 0x36
87#define AB8500_DASLOTCONF5 0x37
88#define AB8500_DASLOTCONF6 0x38
89#define AB8500_DASLOTCONF7 0x39
90#define AB8500_DASLOTCONF8 0x3A
91#define AB8500_CLASSDCONF1 0x3B
92#define AB8500_CLASSDCONF2 0x3C
93#define AB8500_CLASSDCONF3 0x3D
94#define AB8500_DMICFILTCONF 0x3E
95#define AB8500_DIGMULTCONF1 0x3F
96#define AB8500_DIGMULTCONF2 0x40
97#define AB8500_ADDIGGAIN1 0x41
98#define AB8500_ADDIGGAIN2 0x42
99#define AB8500_ADDIGGAIN3 0x43
100#define AB8500_ADDIGGAIN4 0x44
101#define AB8500_ADDIGGAIN5 0x45
102#define AB8500_ADDIGGAIN6 0x46
103#define AB8500_DADIGGAIN1 0x47
104#define AB8500_DADIGGAIN2 0x48
105#define AB8500_DADIGGAIN3 0x49
106#define AB8500_DADIGGAIN4 0x4A
107#define AB8500_DADIGGAIN5 0x4B
108#define AB8500_DADIGGAIN6 0x4C
109#define AB8500_ADDIGLOOPGAIN1 0x4D
110#define AB8500_ADDIGLOOPGAIN2 0x4E
111#define AB8500_HSLEARDIGGAIN 0x4F
112#define AB8500_HSRDIGGAIN 0x50
113#define AB8500_SIDFIRGAIN1 0x51
114#define AB8500_SIDFIRGAIN2 0x52
115#define AB8500_ANCCONF1 0x53
116#define AB8500_ANCCONF2 0x54
117#define AB8500_ANCCONF3 0x55
118#define AB8500_ANCCONF4 0x56
119#define AB8500_ANCCONF5 0x57
120#define AB8500_ANCCONF6 0x58
121#define AB8500_ANCCONF7 0x59
122#define AB8500_ANCCONF8 0x5A
123#define AB8500_ANCCONF9 0x5B
124#define AB8500_ANCCONF10 0x5C
125#define AB8500_ANCCONF11 0x5D
126#define AB8500_ANCCONF12 0x5E
127#define AB8500_ANCCONF13 0x5F
128#define AB8500_ANCCONF14 0x60
129#define AB8500_SIDFIRADR 0x61
130#define AB8500_SIDFIRCOEF1 0x62
131#define AB8500_SIDFIRCOEF2 0x63
132#define AB8500_SIDFIRCONF 0x64
133#define AB8500_AUDINTMASK1 0x65
134#define AB8500_AUDINTSOURCE1 0x66
135#define AB8500_AUDINTMASK2 0x67
136#define AB8500_AUDINTSOURCE2 0x68
137#define AB8500_FIFOCONF1 0x69
138#define AB8500_FIFOCONF2 0x6A
139#define AB8500_FIFOCONF3 0x6B
140#define AB8500_FIFOCONF4 0x6C
141#define AB8500_FIFOCONF5 0x6D
142#define AB8500_FIFOCONF6 0x6E
143#define AB8500_AUDREV 0x6F
144
145#define AB8500_FIRST_REG AB8500_POWERUP
146#define AB8500_LAST_REG AB8500_AUDREV
147#define AB8500_CACHEREGNUM (AB8500_LAST_REG + 1)
148
149#define AB8500_MASK_ALL 0xFF
150#define AB8500_MASK_SLOT(slot) ((slot & 1) ? 0xF0 : 0x0F)
151#define AB8500_MASK_NONE 0x00
152
153/* AB8500_POWERUP */
154#define AB8500_POWERUP_POWERUP 7
155#define AB8500_POWERUP_ENANA 3
156
157/* AB8500_AUDSWRESET */
158#define AB8500_AUDSWRESET_SWRESET 7
159
160/* AB8500_ADPATHENA */
161#define AB8500_ADPATHENA_ENAD12 7
162#define AB8500_ADPATHENA_ENAD34 5
163#define AB8500_ADPATHENA_ENAD5768 3
164
165/* AB8500_DAPATHENA */
166#define AB8500_DAPATHENA_ENDA1 7
167#define AB8500_DAPATHENA_ENDA2 6
168#define AB8500_DAPATHENA_ENDA3 5
169#define AB8500_DAPATHENA_ENDA4 4
170#define AB8500_DAPATHENA_ENDA5 3
171#define AB8500_DAPATHENA_ENDA6 2
172
173/* AB8500_ANACONF1 */
174#define AB8500_ANACONF1_HSLOWPOW 7
175#define AB8500_ANACONF1_DACLOWPOW1 6
176#define AB8500_ANACONF1_DACLOWPOW0 5
177#define AB8500_ANACONF1_EARDACLOWPOW 4
178#define AB8500_ANACONF1_EARSELCM 2
179#define AB8500_ANACONF1_HSHPEN 1
180#define AB8500_ANACONF1_EARDRVLOWPOW 0
181
182/* AB8500_ANACONF2 */
183#define AB8500_ANACONF2_ENMIC1 7
184#define AB8500_ANACONF2_ENMIC2 6
185#define AB8500_ANACONF2_ENLINL 5
186#define AB8500_ANACONF2_ENLINR 4
187#define AB8500_ANACONF2_MUTMIC1 3
188#define AB8500_ANACONF2_MUTMIC2 2
189#define AB8500_ANACONF2_MUTLINL 1
190#define AB8500_ANACONF2_MUTLINR 0
191
192/* AB8500_DIGMICCONF */
193#define AB8500_DIGMICCONF_ENDMIC1 7
194#define AB8500_DIGMICCONF_ENDMIC2 6
195#define AB8500_DIGMICCONF_ENDMIC3 5
196#define AB8500_DIGMICCONF_ENDMIC4 4
197#define AB8500_DIGMICCONF_ENDMIC5 3
198#define AB8500_DIGMICCONF_ENDMIC6 2
199#define AB8500_DIGMICCONF_HSFADSPEED 0
200
201/* AB8500_ANACONF3 */
202#define AB8500_ANACONF3_MIC1SEL 7
203#define AB8500_ANACONF3_LINRSEL 6
204#define AB8500_ANACONF3_ENDRVHSL 5
205#define AB8500_ANACONF3_ENDRVHSR 4
206#define AB8500_ANACONF3_ENADCMIC 2
207#define AB8500_ANACONF3_ENADCLINL 1
208#define AB8500_ANACONF3_ENADCLINR 0
209
210/* AB8500_ANACONF4 */
211#define AB8500_ANACONF4_DISPDVSS 7
212#define AB8500_ANACONF4_ENEAR 6
213#define AB8500_ANACONF4_ENHSL 5
214#define AB8500_ANACONF4_ENHSR 4
215#define AB8500_ANACONF4_ENHFL 3
216#define AB8500_ANACONF4_ENHFR 2
217#define AB8500_ANACONF4_ENVIB1 1
218#define AB8500_ANACONF4_ENVIB2 0
219
220/* AB8500_DAPATHCONF */
221#define AB8500_DAPATHCONF_ENDACEAR 6
222#define AB8500_DAPATHCONF_ENDACHSL 5
223#define AB8500_DAPATHCONF_ENDACHSR 4
224#define AB8500_DAPATHCONF_ENDACHFL 3
225#define AB8500_DAPATHCONF_ENDACHFR 2
226#define AB8500_DAPATHCONF_ENDACVIB1 1
227#define AB8500_DAPATHCONF_ENDACVIB2 0
228
229/* AB8500_MUTECONF */
230#define AB8500_MUTECONF_MUTEAR 6
231#define AB8500_MUTECONF_MUTHSL 5
232#define AB8500_MUTECONF_MUTHSR 4
233#define AB8500_MUTECONF_MUTDACEAR 2
234#define AB8500_MUTECONF_MUTDACHSL 1
235#define AB8500_MUTECONF_MUTDACHSR 0
236
237/* AB8500_SHORTCIRCONF */
238#define AB8500_SHORTCIRCONF_ENSHORTPWD 7
239#define AB8500_SHORTCIRCONF_EARSHORTDIS 6
240#define AB8500_SHORTCIRCONF_HSSHORTDIS 5
241#define AB8500_SHORTCIRCONF_HSPULLDEN 4
242#define AB8500_SHORTCIRCONF_HSOSCEN 2
243#define AB8500_SHORTCIRCONF_HSFADDIS 1
244#define AB8500_SHORTCIRCONF_HSZCDDIS 0
245/* Zero cross should be disabled */
246
247/* AB8500_ANACONF5 */
248#define AB8500_ANACONF5_ENCPHS 7
249#define AB8500_ANACONF5_HSLDACTOLOL 5
250#define AB8500_ANACONF5_HSRDACTOLOR 4
251#define AB8500_ANACONF5_ENLOL 3
252#define AB8500_ANACONF5_ENLOR 2
253#define AB8500_ANACONF5_HSAUTOEN 0
254
255/* AB8500_ENVCPCONF */
256#define AB8500_ENVCPCONF_ENVDETHTHRE 4
257#define AB8500_ENVCPCONF_ENVDETLTHRE 0
258#define AB8500_ENVCPCONF_ENVDETHTHRE_MAX 0x0F
259#define AB8500_ENVCPCONF_ENVDETLTHRE_MAX 0x0F
260
261/* AB8500_SIGENVCONF */
262#define AB8500_SIGENVCONF_CPLVEN 5
263#define AB8500_SIGENVCONF_ENVDETCPEN 4
264#define AB8500_SIGENVCONF_ENVDETTIME 0
265#define AB8500_SIGENVCONF_ENVDETTIME_MAX 0x0F
266
267/* AB8500_PWMGENCONF1 */
268#define AB8500_PWMGENCONF1_PWMTOVIB1 7
269#define AB8500_PWMGENCONF1_PWMTOVIB2 6
270#define AB8500_PWMGENCONF1_PWM1CTRL 5
271#define AB8500_PWMGENCONF1_PWM2CTRL 4
272#define AB8500_PWMGENCONF1_PWM1NCTRL 3
273#define AB8500_PWMGENCONF1_PWM1PCTRL 2
274#define AB8500_PWMGENCONF1_PWM2NCTRL 1
275#define AB8500_PWMGENCONF1_PWM2PCTRL 0
276
277/* AB8500_PWMGENCONF2 */
278/* AB8500_PWMGENCONF3 */
279/* AB8500_PWMGENCONF4 */
280/* AB8500_PWMGENCONF5 */
281#define AB8500_PWMGENCONFX_PWMVIBXPOL 7
282#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC 0
283#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX 0x64
284
285/* AB8500_ANAGAIN1 */
286/* AB8500_ANAGAIN2 */
287#define AB8500_ANAGAINX_ENSEMICX 7
288#define AB8500_ANAGAINX_LOWPOWMICX 6
289#define AB8500_ANAGAINX_MICXGAIN 0
290#define AB8500_ANAGAINX_MICXGAIN_MAX 0x1F
291
292/* AB8500_ANAGAIN3 */
293#define AB8500_ANAGAIN3_HSLGAIN 4
294#define AB8500_ANAGAIN3_HSRGAIN 0
295#define AB8500_ANAGAIN3_HSXGAIN_MAX 0x0F
296
297/* AB8500_ANAGAIN4 */
298#define AB8500_ANAGAIN4_LINLGAIN 4
299#define AB8500_ANAGAIN4_LINRGAIN 0
300#define AB8500_ANAGAIN4_LINXGAIN_MAX 0x0F
301
302/* AB8500_DIGLINHSLGAIN */
303/* AB8500_DIGLINHSRGAIN */
304#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN 0
305#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX 0x13
306
307/* AB8500_ADFILTCONF */
308#define AB8500_ADFILTCONF_AD1NH 7
309#define AB8500_ADFILTCONF_AD2NH 6
310#define AB8500_ADFILTCONF_AD3NH 5
311#define AB8500_ADFILTCONF_AD4NH 4
312#define AB8500_ADFILTCONF_AD1VOICE 3
313#define AB8500_ADFILTCONF_AD2VOICE 2
314#define AB8500_ADFILTCONF_AD3VOICE 1
315#define AB8500_ADFILTCONF_AD4VOICE 0
316
317/* AB8500_DIGIFCONF1 */
318#define AB8500_DIGIFCONF1_ENMASTGEN 7
319#define AB8500_DIGIFCONF1_IF1BITCLKOS1 6
320#define AB8500_DIGIFCONF1_IF1BITCLKOS0 5
321#define AB8500_DIGIFCONF1_ENFSBITCLK1 4
322#define AB8500_DIGIFCONF1_IF0BITCLKOS1 2
323#define AB8500_DIGIFCONF1_IF0BITCLKOS0 1
324#define AB8500_DIGIFCONF1_ENFSBITCLK0 0
325
326/* AB8500_DIGIFCONF2 */
327#define AB8500_DIGIFCONF2_FSYNC0P 6
328#define AB8500_DIGIFCONF2_BITCLK0P 5
329#define AB8500_DIGIFCONF2_IF0DEL 4
330#define AB8500_DIGIFCONF2_IF0FORMAT1 3
331#define AB8500_DIGIFCONF2_IF0FORMAT0 2
332#define AB8500_DIGIFCONF2_IF0WL1 1
333#define AB8500_DIGIFCONF2_IF0WL0 0
334
335/* AB8500_DIGIFCONF3 */
336#define AB8500_DIGIFCONF3_IF0DATOIF1AD 7
337#define AB8500_DIGIFCONF3_IF0CLKTOIF1CLK 6
338#define AB8500_DIGIFCONF3_IF1MASTER 5
339#define AB8500_DIGIFCONF3_IF1DATOIF0AD 3
340#define AB8500_DIGIFCONF3_IF1CLKTOIF0CLK 2
341#define AB8500_DIGIFCONF3_IF0MASTER 1
342#define AB8500_DIGIFCONF3_IF0BFIFOEN 0
343
344/* AB8500_DIGIFCONF4 */
345#define AB8500_DIGIFCONF4_FSYNC1P 6
346#define AB8500_DIGIFCONF4_BITCLK1P 5
347#define AB8500_DIGIFCONF4_IF1DEL 4
348#define AB8500_DIGIFCONF4_IF1FORMAT1 3
349#define AB8500_DIGIFCONF4_IF1FORMAT0 2
350#define AB8500_DIGIFCONF4_IF1WL1 1
351#define AB8500_DIGIFCONF4_IF1WL0 0
352
353/* AB8500_ADSLOTSELX */
354#define AB8500_AD_OUT1 0x0
355#define AB8500_AD_OUT2 0x1
356#define AB8500_AD_OUT3 0x2
357#define AB8500_AD_OUT4 0x3
358#define AB8500_AD_OUT5 0x4
359#define AB8500_AD_OUT6 0x5
360#define AB8500_AD_OUT7 0x6
361#define AB8500_AD_OUT8 0x7
362#define AB8500_ZEROES 0x8
363#define AB8500_TRISTATE 0xF
364#define AB8500_ADSLOTSELX_EVEN_SHIFT 0
365#define AB8500_ADSLOTSELX_ODD_SHIFT 4
366#define AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(out, slot) \
367 ((out) << (((slot) & 1) ? \
368 AB8500_ADSLOTSELX_ODD_SHIFT : AB8500_ADSLOTSELX_EVEN_SHIFT))
369
370/* AB8500_ADSLOTHIZCTRL1 */
371/* AB8500_ADSLOTHIZCTRL2 */
372/* AB8500_ADSLOTHIZCTRL3 */
373/* AB8500_ADSLOTHIZCTRL4 */
374/* AB8500_DASLOTCONF1 */
375#define AB8500_DASLOTCONF1_DA12VOICE 7
376#define AB8500_DASLOTCONF1_SWAPDA12_34 6
377#define AB8500_DASLOTCONF1_DAI7TOADO1 5
378
379/* AB8500_DASLOTCONF2 */
380#define AB8500_DASLOTCONF2_DAI8TOADO2 5
381
382/* AB8500_DASLOTCONF3 */
383#define AB8500_DASLOTCONF3_DA34VOICE 7
384#define AB8500_DASLOTCONF3_DAI7TOADO3 5
385
386/* AB8500_DASLOTCONF4 */
387#define AB8500_DASLOTCONF4_DAI8TOADO4 5
388
389/* AB8500_DASLOTCONF5 */
390#define AB8500_DASLOTCONF5_DA56VOICE 7
391#define AB8500_DASLOTCONF5_DAI7TOADO5 5
392
393/* AB8500_DASLOTCONF6 */
394#define AB8500_DASLOTCONF6_DAI8TOADO6 5
395
396/* AB8500_DASLOTCONF7 */
397#define AB8500_DASLOTCONF7_DAI8TOADO7 5
398
399/* AB8500_DASLOTCONF8 */
400#define AB8500_DASLOTCONF8_DAI7TOADO8 5
401
402#define AB8500_DASLOTCONFX_SLTODAX_SHIFT 0
403#define AB8500_DASLOTCONFX_SLTODAX_MASK 0x1F
404
405/* AB8500_CLASSDCONF1 */
406#define AB8500_CLASSDCONF1_PARLHF 7
407#define AB8500_CLASSDCONF1_PARLVIB 6
408#define AB8500_CLASSDCONF1_VIB1SWAPEN 3
409#define AB8500_CLASSDCONF1_VIB2SWAPEN 2
410#define AB8500_CLASSDCONF1_HFLSWAPEN 1
411#define AB8500_CLASSDCONF1_HFRSWAPEN 0
412
413/* AB8500_CLASSDCONF2 */
414#define AB8500_CLASSDCONF2_FIRBYP3 7
415#define AB8500_CLASSDCONF2_FIRBYP2 6
416#define AB8500_CLASSDCONF2_FIRBYP1 5
417#define AB8500_CLASSDCONF2_FIRBYP0 4
418#define AB8500_CLASSDCONF2_HIGHVOLEN3 3
419#define AB8500_CLASSDCONF2_HIGHVOLEN2 2
420#define AB8500_CLASSDCONF2_HIGHVOLEN1 1
421#define AB8500_CLASSDCONF2_HIGHVOLEN0 0
422
423/* AB8500_CLASSDCONF3 */
424#define AB8500_CLASSDCONF3_DITHHPGAIN 4
425#define AB8500_CLASSDCONF3_DITHHPGAIN_MAX 0x0A
426#define AB8500_CLASSDCONF3_DITHWGAIN 0
427#define AB8500_CLASSDCONF3_DITHWGAIN_MAX 0x0A
428
429/* AB8500_DMICFILTCONF */
430#define AB8500_DMICFILTCONF_ANCINSEL 7
431#define AB8500_DMICFILTCONF_DA3TOEAR 6
432#define AB8500_DMICFILTCONF_DMIC1SINC3 5
433#define AB8500_DMICFILTCONF_DMIC2SINC3 4
434#define AB8500_DMICFILTCONF_DMIC3SINC3 3
435#define AB8500_DMICFILTCONF_DMIC4SINC3 2
436#define AB8500_DMICFILTCONF_DMIC5SINC3 1
437#define AB8500_DMICFILTCONF_DMIC6SINC3 0
438
439/* AB8500_DIGMULTCONF1 */
440#define AB8500_DIGMULTCONF1_DATOHSLEN 7
441#define AB8500_DIGMULTCONF1_DATOHSREN 6
442#define AB8500_DIGMULTCONF1_AD1SEL 5
443#define AB8500_DIGMULTCONF1_AD2SEL 4
444#define AB8500_DIGMULTCONF1_AD3SEL 3
445#define AB8500_DIGMULTCONF1_AD5SEL 2
446#define AB8500_DIGMULTCONF1_AD6SEL 1
447#define AB8500_DIGMULTCONF1_ANCSEL 0
448
449/* AB8500_DIGMULTCONF2 */
450#define AB8500_DIGMULTCONF2_DATOHFREN 7
451#define AB8500_DIGMULTCONF2_DATOHFLEN 6
452#define AB8500_DIGMULTCONF2_HFRSEL 5
453#define AB8500_DIGMULTCONF2_HFLSEL 4
454#define AB8500_DIGMULTCONF2_FIRSID1SEL 2
455#define AB8500_DIGMULTCONF2_FIRSID2SEL 0
456
457/* AB8500_ADDIGGAIN1 */
458/* AB8500_ADDIGGAIN2 */
459/* AB8500_ADDIGGAIN3 */
460/* AB8500_ADDIGGAIN4 */
461/* AB8500_ADDIGGAIN5 */
462/* AB8500_ADDIGGAIN6 */
463#define AB8500_ADDIGGAINX_FADEDISADX 6
464#define AB8500_ADDIGGAINX_ADXGAIN_MAX 0x3F
465
466/* AB8500_DADIGGAIN1 */
467/* AB8500_DADIGGAIN2 */
468/* AB8500_DADIGGAIN3 */
469/* AB8500_DADIGGAIN4 */
470/* AB8500_DADIGGAIN5 */
471/* AB8500_DADIGGAIN6 */
472#define AB8500_DADIGGAINX_FADEDISDAX 6
473#define AB8500_DADIGGAINX_DAXGAIN_MAX 0x3F
474
475/* AB8500_ADDIGLOOPGAIN1 */
476/* AB8500_ADDIGLOOPGAIN2 */
477#define AB8500_ADDIGLOOPGAINX_FADEDISADXL 6
478#define AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX 0x3F
479
480/* AB8500_HSLEARDIGGAIN */
481#define AB8500_HSLEARDIGGAIN_HSSINC1 7
482#define AB8500_HSLEARDIGGAIN_FADEDISHSL 4
483#define AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX 0x09
484
485/* AB8500_HSRDIGGAIN */
486#define AB8500_HSRDIGGAIN_FADESPEED 6
487#define AB8500_HSRDIGGAIN_FADEDISHSR 4
488#define AB8500_HSRDIGGAIN_HSRDGAIN_MAX 0x09
489
490/* AB8500_SIDFIRGAIN1 */
491/* AB8500_SIDFIRGAIN2 */
492#define AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX 0x1F
493
494/* AB8500_ANCCONF1 */
495#define AB8500_ANCCONF1_ANCIIRUPDATE 3
496#define AB8500_ANCCONF1_ENANC 2
497#define AB8500_ANCCONF1_ANCIIRINIT 1
498#define AB8500_ANCCONF1_ANCFIRUPDATE 0
499
500/* AB8500_ANCCONF2 */
501#define AB8500_ANCCONF2_SHIFT 5
502#define AB8500_ANCCONF2_MIN -0x10
503#define AB8500_ANCCONF2_MAX 0xF
504
505/* AB8500_ANCCONF3 */
506#define AB8500_ANCCONF3_SHIFT 5
507#define AB8500_ANCCONF3_MIN -0x10
508#define AB8500_ANCCONF3_MAX 0xF
509
510/* AB8500_ANCCONF4 */
511#define AB8500_ANCCONF4_SHIFT 5
512#define AB8500_ANCCONF4_MIN -0x10
513#define AB8500_ANCCONF4_MAX 0xF
514
515/* AB8500_ANC_FIR_COEFFS */
516#define AB8500_ANC_FIR_COEFF_MIN -0x8000
517#define AB8500_ANC_FIR_COEFF_MAX 0x7FFF
518#define AB8500_ANC_FIR_COEFFS 15
519
520/* AB8500_ANC_IIR_COEFFS */
521#define AB8500_ANC_IIR_COEFF_MIN -0x800000
522#define AB8500_ANC_IIR_COEFF_MAX 0x7FFFFF
523#define AB8500_ANC_IIR_COEFFS 24
524/* AB8500_ANC_WARP_DELAY */
525#define AB8500_ANC_WARP_DELAY_SHIFT 16
526#define AB8500_ANC_WARP_DELAY_MIN 0x0000
527#define AB8500_ANC_WARP_DELAY_MAX 0xFFFF
528
529/* AB8500_ANCCONF11 */
530/* AB8500_ANCCONF12 */
531/* AB8500_ANCCONF13 */
532/* AB8500_ANCCONF14 */
533
534/* AB8500_SIDFIRADR */
535#define AB8500_SIDFIRADR_FIRSIDSET 7
536#define AB8500_SIDFIRADR_ADDRESS_SHIFT 0
537#define AB8500_SIDFIRADR_ADDRESS_MAX 0x7F
538
539/* AB8500_SIDFIRCOEF1 */
540/* AB8500_SIDFIRCOEF2 */
541#define AB8500_SID_FIR_COEFF_MIN 0
542#define AB8500_SID_FIR_COEFF_MAX 0xFFFF
543#define AB8500_SID_FIR_COEFFS 128
544
545/* AB8500_SIDFIRCONF */
546#define AB8500_SIDFIRCONF_ENFIRSIDS 2
547#define AB8500_SIDFIRCONF_FIRSIDSTOIF1 1
548#define AB8500_SIDFIRCONF_FIRSIDBUSY 0
549
550/* AB8500_AUDINTMASK1 */
551/* AB8500_AUDINTSOURCE1 */
552/* AB8500_AUDINTMASK2 */
553/* AB8500_AUDINTSOURCE2 */
554
555/* AB8500_FIFOCONF1 */
556#define AB8500_FIFOCONF1_BFIFOMASK 0x80
557#define AB8500_FIFOCONF1_BFIFO19M2 0x40
558#define AB8500_FIFOCONF1_BFIFOINT_SHIFT 0
559#define AB8500_FIFOCONF1_BFIFOINT_MAX 0x3F
560
561/* AB8500_FIFOCONF2 */
562#define AB8500_FIFOCONF2_BFIFOTX_SHIFT 0
563#define AB8500_FIFOCONF2_BFIFOTX_MAX 0xFF
564
565/* AB8500_FIFOCONF3 */
566#define AB8500_FIFOCONF3_BFIFOEXSL_SHIFT 5
567#define AB8500_FIFOCONF3_BFIFOEXSL_MAX 0x5
568#define AB8500_FIFOCONF3_PREBITCLK0_SHIFT 2
569#define AB8500_FIFOCONF3_PREBITCLK0_MAX 0x7
570#define AB8500_FIFOCONF3_BFIFOMAST_SHIFT 1
571#define AB8500_FIFOCONF3_BFIFORUN_SHIFT 0
572
573/* AB8500_FIFOCONF4 */
574#define AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT 0
575#define AB8500_FIFOCONF4_BFIFOFRAMSW_MAX 0xFF
576
577/* AB8500_FIFOCONF5 */
578#define AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT 0
579#define AB8500_FIFOCONF5_BFIFOWAKEUP_MAX 0xFF
580
581/* AB8500_FIFOCONF6 */
582#define AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT 0
583#define AB8500_FIFOCONF6_BFIFOSAMPLE_MAX 0xFF
584
585/* AB8500_AUDREV */
586
587#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) ST-Ericsson SA 2012
4 *
5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
6 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
7 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
8 * for ST-Ericsson.
9 *
10 * Based on the early work done by:
11 * Mikko J. Lehto <mikko.lehto@symbio.com>,
12 * Mikko Sarmanne <mikko.sarmanne@symbio.com>,
13 * for ST-Ericsson.
14 *
15 * License terms:
16 */
17
18#ifndef AB8500_CODEC_REGISTERS_H
19#define AB8500_CODEC_REGISTERS_H
20
21#define AB8500_SUPPORTED_RATE (SNDRV_PCM_RATE_48000)
22#define AB8500_SUPPORTED_FMT (SNDRV_PCM_FMTBIT_S16_LE)
23
24/* AB8500 interface slot offset definitions */
25
26#define AB8500_AD_DATA0_OFFSET 0
27#define AB8500_DA_DATA0_OFFSET 8
28#define AB8500_AD_DATA1_OFFSET 16
29#define AB8500_DA_DATA1_OFFSET 24
30
31/* AB8500 audio bank (0x0d) register definitions */
32
33#define AB8500_POWERUP 0x00
34#define AB8500_AUDSWRESET 0x01
35#define AB8500_ADPATHENA 0x02
36#define AB8500_DAPATHENA 0x03
37#define AB8500_ANACONF1 0x04
38#define AB8500_ANACONF2 0x05
39#define AB8500_DIGMICCONF 0x06
40#define AB8500_ANACONF3 0x07
41#define AB8500_ANACONF4 0x08
42#define AB8500_DAPATHCONF 0x09
43#define AB8500_MUTECONF 0x0A
44#define AB8500_SHORTCIRCONF 0x0B
45#define AB8500_ANACONF5 0x0C
46#define AB8500_ENVCPCONF 0x0D
47#define AB8500_SIGENVCONF 0x0E
48#define AB8500_PWMGENCONF1 0x0F
49#define AB8500_PWMGENCONF2 0x10
50#define AB8500_PWMGENCONF3 0x11
51#define AB8500_PWMGENCONF4 0x12
52#define AB8500_PWMGENCONF5 0x13
53#define AB8500_ANAGAIN1 0x14
54#define AB8500_ANAGAIN2 0x15
55#define AB8500_ANAGAIN3 0x16
56#define AB8500_ANAGAIN4 0x17
57#define AB8500_DIGLINHSLGAIN 0x18
58#define AB8500_DIGLINHSRGAIN 0x19
59#define AB8500_ADFILTCONF 0x1A
60#define AB8500_DIGIFCONF1 0x1B
61#define AB8500_DIGIFCONF2 0x1C
62#define AB8500_DIGIFCONF3 0x1D
63#define AB8500_DIGIFCONF4 0x1E
64#define AB8500_ADSLOTSEL1 0x1F
65#define AB8500_ADSLOTSEL2 0x20
66#define AB8500_ADSLOTSEL3 0x21
67#define AB8500_ADSLOTSEL4 0x22
68#define AB8500_ADSLOTSEL5 0x23
69#define AB8500_ADSLOTSEL6 0x24
70#define AB8500_ADSLOTSEL7 0x25
71#define AB8500_ADSLOTSEL8 0x26
72#define AB8500_ADSLOTSEL9 0x27
73#define AB8500_ADSLOTSEL10 0x28
74#define AB8500_ADSLOTSEL11 0x29
75#define AB8500_ADSLOTSEL12 0x2A
76#define AB8500_ADSLOTSEL13 0x2B
77#define AB8500_ADSLOTSEL14 0x2C
78#define AB8500_ADSLOTSEL15 0x2D
79#define AB8500_ADSLOTSEL16 0x2E
80#define AB8500_ADSLOTSEL(slot) (AB8500_ADSLOTSEL1 + (slot >> 1))
81#define AB8500_ADSLOTHIZCTRL1 0x2F
82#define AB8500_ADSLOTHIZCTRL2 0x30
83#define AB8500_ADSLOTHIZCTRL3 0x31
84#define AB8500_ADSLOTHIZCTRL4 0x32
85#define AB8500_DASLOTCONF1 0x33
86#define AB8500_DASLOTCONF2 0x34
87#define AB8500_DASLOTCONF3 0x35
88#define AB8500_DASLOTCONF4 0x36
89#define AB8500_DASLOTCONF5 0x37
90#define AB8500_DASLOTCONF6 0x38
91#define AB8500_DASLOTCONF7 0x39
92#define AB8500_DASLOTCONF8 0x3A
93#define AB8500_CLASSDCONF1 0x3B
94#define AB8500_CLASSDCONF2 0x3C
95#define AB8500_CLASSDCONF3 0x3D
96#define AB8500_DMICFILTCONF 0x3E
97#define AB8500_DIGMULTCONF1 0x3F
98#define AB8500_DIGMULTCONF2 0x40
99#define AB8500_ADDIGGAIN1 0x41
100#define AB8500_ADDIGGAIN2 0x42
101#define AB8500_ADDIGGAIN3 0x43
102#define AB8500_ADDIGGAIN4 0x44
103#define AB8500_ADDIGGAIN5 0x45
104#define AB8500_ADDIGGAIN6 0x46
105#define AB8500_DADIGGAIN1 0x47
106#define AB8500_DADIGGAIN2 0x48
107#define AB8500_DADIGGAIN3 0x49
108#define AB8500_DADIGGAIN4 0x4A
109#define AB8500_DADIGGAIN5 0x4B
110#define AB8500_DADIGGAIN6 0x4C
111#define AB8500_ADDIGLOOPGAIN1 0x4D
112#define AB8500_ADDIGLOOPGAIN2 0x4E
113#define AB8500_HSLEARDIGGAIN 0x4F
114#define AB8500_HSRDIGGAIN 0x50
115#define AB8500_SIDFIRGAIN1 0x51
116#define AB8500_SIDFIRGAIN2 0x52
117#define AB8500_ANCCONF1 0x53
118#define AB8500_ANCCONF2 0x54
119#define AB8500_ANCCONF3 0x55
120#define AB8500_ANCCONF4 0x56
121#define AB8500_ANCCONF5 0x57
122#define AB8500_ANCCONF6 0x58
123#define AB8500_ANCCONF7 0x59
124#define AB8500_ANCCONF8 0x5A
125#define AB8500_ANCCONF9 0x5B
126#define AB8500_ANCCONF10 0x5C
127#define AB8500_ANCCONF11 0x5D
128#define AB8500_ANCCONF12 0x5E
129#define AB8500_ANCCONF13 0x5F
130#define AB8500_ANCCONF14 0x60
131#define AB8500_SIDFIRADR 0x61
132#define AB8500_SIDFIRCOEF1 0x62
133#define AB8500_SIDFIRCOEF2 0x63
134#define AB8500_SIDFIRCONF 0x64
135#define AB8500_AUDINTMASK1 0x65
136#define AB8500_AUDINTSOURCE1 0x66
137#define AB8500_AUDINTMASK2 0x67
138#define AB8500_AUDINTSOURCE2 0x68
139#define AB8500_FIFOCONF1 0x69
140#define AB8500_FIFOCONF2 0x6A
141#define AB8500_FIFOCONF3 0x6B
142#define AB8500_FIFOCONF4 0x6C
143#define AB8500_FIFOCONF5 0x6D
144#define AB8500_FIFOCONF6 0x6E
145#define AB8500_AUDREV 0x6F
146
147#define AB8500_FIRST_REG AB8500_POWERUP
148#define AB8500_LAST_REG AB8500_AUDREV
149#define AB8500_CACHEREGNUM (AB8500_LAST_REG + 1)
150
151#define AB8500_MASK_ALL 0xFF
152#define AB8500_MASK_SLOT(slot) ((slot & 1) ? 0xF0 : 0x0F)
153#define AB8500_MASK_NONE 0x00
154
155/* AB8500_POWERUP */
156#define AB8500_POWERUP_POWERUP 7
157#define AB8500_POWERUP_ENANA 3
158
159/* AB8500_AUDSWRESET */
160#define AB8500_AUDSWRESET_SWRESET 7
161
162/* AB8500_ADPATHENA */
163#define AB8500_ADPATHENA_ENAD12 7
164#define AB8500_ADPATHENA_ENAD34 5
165#define AB8500_ADPATHENA_ENAD5768 3
166
167/* AB8500_DAPATHENA */
168#define AB8500_DAPATHENA_ENDA1 7
169#define AB8500_DAPATHENA_ENDA2 6
170#define AB8500_DAPATHENA_ENDA3 5
171#define AB8500_DAPATHENA_ENDA4 4
172#define AB8500_DAPATHENA_ENDA5 3
173#define AB8500_DAPATHENA_ENDA6 2
174
175/* AB8500_ANACONF1 */
176#define AB8500_ANACONF1_HSLOWPOW 7
177#define AB8500_ANACONF1_DACLOWPOW1 6
178#define AB8500_ANACONF1_DACLOWPOW0 5
179#define AB8500_ANACONF1_EARDACLOWPOW 4
180#define AB8500_ANACONF1_EARSELCM 2
181#define AB8500_ANACONF1_HSHPEN 1
182#define AB8500_ANACONF1_EARDRVLOWPOW 0
183
184/* AB8500_ANACONF2 */
185#define AB8500_ANACONF2_ENMIC1 7
186#define AB8500_ANACONF2_ENMIC2 6
187#define AB8500_ANACONF2_ENLINL 5
188#define AB8500_ANACONF2_ENLINR 4
189#define AB8500_ANACONF2_MUTMIC1 3
190#define AB8500_ANACONF2_MUTMIC2 2
191#define AB8500_ANACONF2_MUTLINL 1
192#define AB8500_ANACONF2_MUTLINR 0
193
194/* AB8500_DIGMICCONF */
195#define AB8500_DIGMICCONF_ENDMIC1 7
196#define AB8500_DIGMICCONF_ENDMIC2 6
197#define AB8500_DIGMICCONF_ENDMIC3 5
198#define AB8500_DIGMICCONF_ENDMIC4 4
199#define AB8500_DIGMICCONF_ENDMIC5 3
200#define AB8500_DIGMICCONF_ENDMIC6 2
201#define AB8500_DIGMICCONF_HSFADSPEED 0
202
203/* AB8500_ANACONF3 */
204#define AB8500_ANACONF3_MIC1SEL 7
205#define AB8500_ANACONF3_LINRSEL 6
206#define AB8500_ANACONF3_ENDRVHSL 5
207#define AB8500_ANACONF3_ENDRVHSR 4
208#define AB8500_ANACONF3_ENADCMIC 2
209#define AB8500_ANACONF3_ENADCLINL 1
210#define AB8500_ANACONF3_ENADCLINR 0
211
212/* AB8500_ANACONF4 */
213#define AB8500_ANACONF4_DISPDVSS 7
214#define AB8500_ANACONF4_ENEAR 6
215#define AB8500_ANACONF4_ENHSL 5
216#define AB8500_ANACONF4_ENHSR 4
217#define AB8500_ANACONF4_ENHFL 3
218#define AB8500_ANACONF4_ENHFR 2
219#define AB8500_ANACONF4_ENVIB1 1
220#define AB8500_ANACONF4_ENVIB2 0
221
222/* AB8500_DAPATHCONF */
223#define AB8500_DAPATHCONF_ENDACEAR 6
224#define AB8500_DAPATHCONF_ENDACHSL 5
225#define AB8500_DAPATHCONF_ENDACHSR 4
226#define AB8500_DAPATHCONF_ENDACHFL 3
227#define AB8500_DAPATHCONF_ENDACHFR 2
228#define AB8500_DAPATHCONF_ENDACVIB1 1
229#define AB8500_DAPATHCONF_ENDACVIB2 0
230
231/* AB8500_MUTECONF */
232#define AB8500_MUTECONF_MUTEAR 6
233#define AB8500_MUTECONF_MUTHSL 5
234#define AB8500_MUTECONF_MUTHSR 4
235#define AB8500_MUTECONF_MUTDACEAR 2
236#define AB8500_MUTECONF_MUTDACHSL 1
237#define AB8500_MUTECONF_MUTDACHSR 0
238
239/* AB8500_SHORTCIRCONF */
240#define AB8500_SHORTCIRCONF_ENSHORTPWD 7
241#define AB8500_SHORTCIRCONF_EARSHORTDIS 6
242#define AB8500_SHORTCIRCONF_HSSHORTDIS 5
243#define AB8500_SHORTCIRCONF_HSPULLDEN 4
244#define AB8500_SHORTCIRCONF_HSOSCEN 2
245#define AB8500_SHORTCIRCONF_HSFADDIS 1
246#define AB8500_SHORTCIRCONF_HSZCDDIS 0
247/* Zero cross should be disabled */
248
249/* AB8500_ANACONF5 */
250#define AB8500_ANACONF5_ENCPHS 7
251#define AB8500_ANACONF5_HSLDACTOLOL 5
252#define AB8500_ANACONF5_HSRDACTOLOR 4
253#define AB8500_ANACONF5_ENLOL 3
254#define AB8500_ANACONF5_ENLOR 2
255#define AB8500_ANACONF5_HSAUTOEN 0
256
257/* AB8500_ENVCPCONF */
258#define AB8500_ENVCPCONF_ENVDETHTHRE 4
259#define AB8500_ENVCPCONF_ENVDETLTHRE 0
260#define AB8500_ENVCPCONF_ENVDETHTHRE_MAX 0x0F
261#define AB8500_ENVCPCONF_ENVDETLTHRE_MAX 0x0F
262
263/* AB8500_SIGENVCONF */
264#define AB8500_SIGENVCONF_CPLVEN 5
265#define AB8500_SIGENVCONF_ENVDETCPEN 4
266#define AB8500_SIGENVCONF_ENVDETTIME 0
267#define AB8500_SIGENVCONF_ENVDETTIME_MAX 0x0F
268
269/* AB8500_PWMGENCONF1 */
270#define AB8500_PWMGENCONF1_PWMTOVIB1 7
271#define AB8500_PWMGENCONF1_PWMTOVIB2 6
272#define AB8500_PWMGENCONF1_PWM1CTRL 5
273#define AB8500_PWMGENCONF1_PWM2CTRL 4
274#define AB8500_PWMGENCONF1_PWM1NCTRL 3
275#define AB8500_PWMGENCONF1_PWM1PCTRL 2
276#define AB8500_PWMGENCONF1_PWM2NCTRL 1
277#define AB8500_PWMGENCONF1_PWM2PCTRL 0
278
279/* AB8500_PWMGENCONF2 */
280/* AB8500_PWMGENCONF3 */
281/* AB8500_PWMGENCONF4 */
282/* AB8500_PWMGENCONF5 */
283#define AB8500_PWMGENCONFX_PWMVIBXPOL 7
284#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC 0
285#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX 0x64
286
287/* AB8500_ANAGAIN1 */
288/* AB8500_ANAGAIN2 */
289#define AB8500_ANAGAINX_ENSEMICX 7
290#define AB8500_ANAGAINX_LOWPOWMICX 6
291#define AB8500_ANAGAINX_MICXGAIN 0
292#define AB8500_ANAGAINX_MICXGAIN_MAX 0x1F
293
294/* AB8500_ANAGAIN3 */
295#define AB8500_ANAGAIN3_HSLGAIN 4
296#define AB8500_ANAGAIN3_HSRGAIN 0
297#define AB8500_ANAGAIN3_HSXGAIN_MAX 0x0F
298
299/* AB8500_ANAGAIN4 */
300#define AB8500_ANAGAIN4_LINLGAIN 4
301#define AB8500_ANAGAIN4_LINRGAIN 0
302#define AB8500_ANAGAIN4_LINXGAIN_MAX 0x0F
303
304/* AB8500_DIGLINHSLGAIN */
305/* AB8500_DIGLINHSRGAIN */
306#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN 0
307#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX 0x13
308
309/* AB8500_ADFILTCONF */
310#define AB8500_ADFILTCONF_AD1NH 7
311#define AB8500_ADFILTCONF_AD2NH 6
312#define AB8500_ADFILTCONF_AD3NH 5
313#define AB8500_ADFILTCONF_AD4NH 4
314#define AB8500_ADFILTCONF_AD1VOICE 3
315#define AB8500_ADFILTCONF_AD2VOICE 2
316#define AB8500_ADFILTCONF_AD3VOICE 1
317#define AB8500_ADFILTCONF_AD4VOICE 0
318
319/* AB8500_DIGIFCONF1 */
320#define AB8500_DIGIFCONF1_ENMASTGEN 7
321#define AB8500_DIGIFCONF1_IF1BITCLKOS1 6
322#define AB8500_DIGIFCONF1_IF1BITCLKOS0 5
323#define AB8500_DIGIFCONF1_ENFSBITCLK1 4
324#define AB8500_DIGIFCONF1_IF0BITCLKOS1 2
325#define AB8500_DIGIFCONF1_IF0BITCLKOS0 1
326#define AB8500_DIGIFCONF1_ENFSBITCLK0 0
327
328/* AB8500_DIGIFCONF2 */
329#define AB8500_DIGIFCONF2_FSYNC0P 6
330#define AB8500_DIGIFCONF2_BITCLK0P 5
331#define AB8500_DIGIFCONF2_IF0DEL 4
332#define AB8500_DIGIFCONF2_IF0FORMAT1 3
333#define AB8500_DIGIFCONF2_IF0FORMAT0 2
334#define AB8500_DIGIFCONF2_IF0WL1 1
335#define AB8500_DIGIFCONF2_IF0WL0 0
336
337/* AB8500_DIGIFCONF3 */
338#define AB8500_DIGIFCONF3_IF0DATOIF1AD 7
339#define AB8500_DIGIFCONF3_IF0CLKTOIF1CLK 6
340#define AB8500_DIGIFCONF3_IF1MASTER 5
341#define AB8500_DIGIFCONF3_IF1DATOIF0AD 3
342#define AB8500_DIGIFCONF3_IF1CLKTOIF0CLK 2
343#define AB8500_DIGIFCONF3_IF0MASTER 1
344#define AB8500_DIGIFCONF3_IF0BFIFOEN 0
345
346/* AB8500_DIGIFCONF4 */
347#define AB8500_DIGIFCONF4_FSYNC1P 6
348#define AB8500_DIGIFCONF4_BITCLK1P 5
349#define AB8500_DIGIFCONF4_IF1DEL 4
350#define AB8500_DIGIFCONF4_IF1FORMAT1 3
351#define AB8500_DIGIFCONF4_IF1FORMAT0 2
352#define AB8500_DIGIFCONF4_IF1WL1 1
353#define AB8500_DIGIFCONF4_IF1WL0 0
354
355/* AB8500_ADSLOTSELX */
356#define AB8500_AD_OUT1 0x0
357#define AB8500_AD_OUT2 0x1
358#define AB8500_AD_OUT3 0x2
359#define AB8500_AD_OUT4 0x3
360#define AB8500_AD_OUT5 0x4
361#define AB8500_AD_OUT6 0x5
362#define AB8500_AD_OUT7 0x6
363#define AB8500_AD_OUT8 0x7
364#define AB8500_ZEROES 0x8
365#define AB8500_TRISTATE 0xF
366#define AB8500_ADSLOTSELX_EVEN_SHIFT 0
367#define AB8500_ADSLOTSELX_ODD_SHIFT 4
368#define AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(out, slot) \
369 ((out) << (((slot) & 1) ? \
370 AB8500_ADSLOTSELX_ODD_SHIFT : AB8500_ADSLOTSELX_EVEN_SHIFT))
371
372/* AB8500_ADSLOTHIZCTRL1 */
373/* AB8500_ADSLOTHIZCTRL2 */
374/* AB8500_ADSLOTHIZCTRL3 */
375/* AB8500_ADSLOTHIZCTRL4 */
376/* AB8500_DASLOTCONF1 */
377#define AB8500_DASLOTCONF1_DA12VOICE 7
378#define AB8500_DASLOTCONF1_SWAPDA12_34 6
379#define AB8500_DASLOTCONF1_DAI7TOADO1 5
380
381/* AB8500_DASLOTCONF2 */
382#define AB8500_DASLOTCONF2_DAI8TOADO2 5
383
384/* AB8500_DASLOTCONF3 */
385#define AB8500_DASLOTCONF3_DA34VOICE 7
386#define AB8500_DASLOTCONF3_DAI7TOADO3 5
387
388/* AB8500_DASLOTCONF4 */
389#define AB8500_DASLOTCONF4_DAI8TOADO4 5
390
391/* AB8500_DASLOTCONF5 */
392#define AB8500_DASLOTCONF5_DA56VOICE 7
393#define AB8500_DASLOTCONF5_DAI7TOADO5 5
394
395/* AB8500_DASLOTCONF6 */
396#define AB8500_DASLOTCONF6_DAI8TOADO6 5
397
398/* AB8500_DASLOTCONF7 */
399#define AB8500_DASLOTCONF7_DAI8TOADO7 5
400
401/* AB8500_DASLOTCONF8 */
402#define AB8500_DASLOTCONF8_DAI7TOADO8 5
403
404#define AB8500_DASLOTCONFX_SLTODAX_SHIFT 0
405#define AB8500_DASLOTCONFX_SLTODAX_MASK 0x1F
406
407/* AB8500_CLASSDCONF1 */
408#define AB8500_CLASSDCONF1_PARLHF 7
409#define AB8500_CLASSDCONF1_PARLVIB 6
410#define AB8500_CLASSDCONF1_VIB1SWAPEN 3
411#define AB8500_CLASSDCONF1_VIB2SWAPEN 2
412#define AB8500_CLASSDCONF1_HFLSWAPEN 1
413#define AB8500_CLASSDCONF1_HFRSWAPEN 0
414
415/* AB8500_CLASSDCONF2 */
416#define AB8500_CLASSDCONF2_FIRBYP3 7
417#define AB8500_CLASSDCONF2_FIRBYP2 6
418#define AB8500_CLASSDCONF2_FIRBYP1 5
419#define AB8500_CLASSDCONF2_FIRBYP0 4
420#define AB8500_CLASSDCONF2_HIGHVOLEN3 3
421#define AB8500_CLASSDCONF2_HIGHVOLEN2 2
422#define AB8500_CLASSDCONF2_HIGHVOLEN1 1
423#define AB8500_CLASSDCONF2_HIGHVOLEN0 0
424
425/* AB8500_CLASSDCONF3 */
426#define AB8500_CLASSDCONF3_DITHHPGAIN 4
427#define AB8500_CLASSDCONF3_DITHHPGAIN_MAX 0x0A
428#define AB8500_CLASSDCONF3_DITHWGAIN 0
429#define AB8500_CLASSDCONF3_DITHWGAIN_MAX 0x0A
430
431/* AB8500_DMICFILTCONF */
432#define AB8500_DMICFILTCONF_ANCINSEL 7
433#define AB8500_DMICFILTCONF_DA3TOEAR 6
434#define AB8500_DMICFILTCONF_DMIC1SINC3 5
435#define AB8500_DMICFILTCONF_DMIC2SINC3 4
436#define AB8500_DMICFILTCONF_DMIC3SINC3 3
437#define AB8500_DMICFILTCONF_DMIC4SINC3 2
438#define AB8500_DMICFILTCONF_DMIC5SINC3 1
439#define AB8500_DMICFILTCONF_DMIC6SINC3 0
440
441/* AB8500_DIGMULTCONF1 */
442#define AB8500_DIGMULTCONF1_DATOHSLEN 7
443#define AB8500_DIGMULTCONF1_DATOHSREN 6
444#define AB8500_DIGMULTCONF1_AD1SEL 5
445#define AB8500_DIGMULTCONF1_AD2SEL 4
446#define AB8500_DIGMULTCONF1_AD3SEL 3
447#define AB8500_DIGMULTCONF1_AD5SEL 2
448#define AB8500_DIGMULTCONF1_AD6SEL 1
449#define AB8500_DIGMULTCONF1_ANCSEL 0
450
451/* AB8500_DIGMULTCONF2 */
452#define AB8500_DIGMULTCONF2_DATOHFREN 7
453#define AB8500_DIGMULTCONF2_DATOHFLEN 6
454#define AB8500_DIGMULTCONF2_HFRSEL 5
455#define AB8500_DIGMULTCONF2_HFLSEL 4
456#define AB8500_DIGMULTCONF2_FIRSID1SEL 2
457#define AB8500_DIGMULTCONF2_FIRSID2SEL 0
458
459/* AB8500_ADDIGGAIN1 */
460/* AB8500_ADDIGGAIN2 */
461/* AB8500_ADDIGGAIN3 */
462/* AB8500_ADDIGGAIN4 */
463/* AB8500_ADDIGGAIN5 */
464/* AB8500_ADDIGGAIN6 */
465#define AB8500_ADDIGGAINX_FADEDISADX 6
466#define AB8500_ADDIGGAINX_ADXGAIN_MAX 0x3F
467
468/* AB8500_DADIGGAIN1 */
469/* AB8500_DADIGGAIN2 */
470/* AB8500_DADIGGAIN3 */
471/* AB8500_DADIGGAIN4 */
472/* AB8500_DADIGGAIN5 */
473/* AB8500_DADIGGAIN6 */
474#define AB8500_DADIGGAINX_FADEDISDAX 6
475#define AB8500_DADIGGAINX_DAXGAIN_MAX 0x3F
476
477/* AB8500_ADDIGLOOPGAIN1 */
478/* AB8500_ADDIGLOOPGAIN2 */
479#define AB8500_ADDIGLOOPGAINX_FADEDISADXL 6
480#define AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX 0x3F
481
482/* AB8500_HSLEARDIGGAIN */
483#define AB8500_HSLEARDIGGAIN_HSSINC1 7
484#define AB8500_HSLEARDIGGAIN_FADEDISHSL 4
485#define AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX 0x09
486
487/* AB8500_HSRDIGGAIN */
488#define AB8500_HSRDIGGAIN_FADESPEED 6
489#define AB8500_HSRDIGGAIN_FADEDISHSR 4
490#define AB8500_HSRDIGGAIN_HSRDGAIN_MAX 0x09
491
492/* AB8500_SIDFIRGAIN1 */
493/* AB8500_SIDFIRGAIN2 */
494#define AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX 0x1F
495
496/* AB8500_ANCCONF1 */
497#define AB8500_ANCCONF1_ANCIIRUPDATE 3
498#define AB8500_ANCCONF1_ENANC 2
499#define AB8500_ANCCONF1_ANCIIRINIT 1
500#define AB8500_ANCCONF1_ANCFIRUPDATE 0
501
502/* AB8500_ANCCONF2 */
503#define AB8500_ANCCONF2_SHIFT 5
504#define AB8500_ANCCONF2_MIN -0x10
505#define AB8500_ANCCONF2_MAX 0xF
506
507/* AB8500_ANCCONF3 */
508#define AB8500_ANCCONF3_SHIFT 5
509#define AB8500_ANCCONF3_MIN -0x10
510#define AB8500_ANCCONF3_MAX 0xF
511
512/* AB8500_ANCCONF4 */
513#define AB8500_ANCCONF4_SHIFT 5
514#define AB8500_ANCCONF4_MIN -0x10
515#define AB8500_ANCCONF4_MAX 0xF
516
517/* AB8500_ANC_FIR_COEFFS */
518#define AB8500_ANC_FIR_COEFF_MIN -0x8000
519#define AB8500_ANC_FIR_COEFF_MAX 0x7FFF
520#define AB8500_ANC_FIR_COEFFS 15
521
522/* AB8500_ANC_IIR_COEFFS */
523#define AB8500_ANC_IIR_COEFF_MIN -0x800000
524#define AB8500_ANC_IIR_COEFF_MAX 0x7FFFFF
525#define AB8500_ANC_IIR_COEFFS 24
526/* AB8500_ANC_WARP_DELAY */
527#define AB8500_ANC_WARP_DELAY_SHIFT 16
528#define AB8500_ANC_WARP_DELAY_MIN 0x0000
529#define AB8500_ANC_WARP_DELAY_MAX 0xFFFF
530
531/* AB8500_ANCCONF11 */
532/* AB8500_ANCCONF12 */
533/* AB8500_ANCCONF13 */
534/* AB8500_ANCCONF14 */
535
536/* AB8500_SIDFIRADR */
537#define AB8500_SIDFIRADR_FIRSIDSET 7
538#define AB8500_SIDFIRADR_ADDRESS_SHIFT 0
539#define AB8500_SIDFIRADR_ADDRESS_MAX 0x7F
540
541/* AB8500_SIDFIRCOEF1 */
542/* AB8500_SIDFIRCOEF2 */
543#define AB8500_SID_FIR_COEFF_MIN 0
544#define AB8500_SID_FIR_COEFF_MAX 0xFFFF
545#define AB8500_SID_FIR_COEFFS 128
546
547/* AB8500_SIDFIRCONF */
548#define AB8500_SIDFIRCONF_ENFIRSIDS 2
549#define AB8500_SIDFIRCONF_FIRSIDSTOIF1 1
550#define AB8500_SIDFIRCONF_FIRSIDBUSY 0
551
552/* AB8500_AUDINTMASK1 */
553/* AB8500_AUDINTSOURCE1 */
554/* AB8500_AUDINTMASK2 */
555/* AB8500_AUDINTSOURCE2 */
556
557/* AB8500_FIFOCONF1 */
558#define AB8500_FIFOCONF1_BFIFOMASK 0x80
559#define AB8500_FIFOCONF1_BFIFO19M2 0x40
560#define AB8500_FIFOCONF1_BFIFOINT_SHIFT 0
561#define AB8500_FIFOCONF1_BFIFOINT_MAX 0x3F
562
563/* AB8500_FIFOCONF2 */
564#define AB8500_FIFOCONF2_BFIFOTX_SHIFT 0
565#define AB8500_FIFOCONF2_BFIFOTX_MAX 0xFF
566
567/* AB8500_FIFOCONF3 */
568#define AB8500_FIFOCONF3_BFIFOEXSL_SHIFT 5
569#define AB8500_FIFOCONF3_BFIFOEXSL_MAX 0x5
570#define AB8500_FIFOCONF3_PREBITCLK0_SHIFT 2
571#define AB8500_FIFOCONF3_PREBITCLK0_MAX 0x7
572#define AB8500_FIFOCONF3_BFIFOMAST_SHIFT 1
573#define AB8500_FIFOCONF3_BFIFORUN_SHIFT 0
574
575/* AB8500_FIFOCONF4 */
576#define AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT 0
577#define AB8500_FIFOCONF4_BFIFOFRAMSW_MAX 0xFF
578
579/* AB8500_FIFOCONF5 */
580#define AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT 0
581#define AB8500_FIFOCONF5_BFIFOWAKEUP_MAX 0xFF
582
583/* AB8500_FIFOCONF6 */
584#define AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT 0
585#define AB8500_FIFOCONF6_BFIFOSAMPLE_MAX 0xFF
586
587/* AB8500_AUDREV */
588
589#endif