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1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 */
6
7#include <linux/ethtool.h>
8#include <linux/kernel.h>
9#include <linux/mii.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/delay.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/bitfield.h>
17#include <linux/nvmem-consumer.h>
18
19#include <dt-bindings/net/ti-dp83867.h>
20
21#define DP83867_PHY_ID 0x2000a231
22#define DP83867_DEVADDR 0x1f
23
24#define MII_DP83867_PHYCTRL 0x10
25#define MII_DP83867_PHYSTS 0x11
26#define MII_DP83867_MICR 0x12
27#define MII_DP83867_ISR 0x13
28#define DP83867_CFG2 0x14
29#define DP83867_LEDCR1 0x18
30#define DP83867_LEDCR2 0x19
31#define DP83867_CFG3 0x1e
32#define DP83867_CTRL 0x1f
33
34/* Extended Registers */
35#define DP83867_FLD_THR_CFG 0x002e
36#define DP83867_CFG4 0x0031
37#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
38#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
39#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
40#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
41#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
42
43#define DP83867_RGMIICTL 0x0032
44#define DP83867_STRAP_STS1 0x006E
45#define DP83867_STRAP_STS2 0x006f
46#define DP83867_RGMIIDCTL 0x0086
47#define DP83867_DSP_FFE_CFG 0x012c
48#define DP83867_RXFCFG 0x0134
49#define DP83867_RXFPMD1 0x0136
50#define DP83867_RXFPMD2 0x0137
51#define DP83867_RXFPMD3 0x0138
52#define DP83867_RXFSOP1 0x0139
53#define DP83867_RXFSOP2 0x013A
54#define DP83867_RXFSOP3 0x013B
55#define DP83867_IO_MUX_CFG 0x0170
56#define DP83867_SGMIICTL 0x00D3
57#define DP83867_10M_SGMII_CFG 0x016F
58#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
59
60#define DP83867_SW_RESET BIT(15)
61#define DP83867_SW_RESTART BIT(14)
62
63/* MICR Interrupt bits */
64#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
65#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
66#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
67#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
68#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
69#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
70#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
71#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
72#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
73#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
74#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
75#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
76
77/* RGMIICTL bits */
78#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
79#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
80
81/* SGMIICTL bits */
82#define DP83867_SGMII_TYPE BIT(14)
83
84/* RXFCFG bits*/
85#define DP83867_WOL_MAGIC_EN BIT(0)
86#define DP83867_WOL_BCAST_EN BIT(2)
87#define DP83867_WOL_UCAST_EN BIT(4)
88#define DP83867_WOL_SEC_EN BIT(5)
89#define DP83867_WOL_ENH_MAC BIT(7)
90
91/* STRAP_STS1 bits */
92#define DP83867_STRAP_STS1_RESERVED BIT(11)
93
94/* STRAP_STS2 bits */
95#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
96#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
97#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
98#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
99#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
100#define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
101
102/* PHY CTRL bits */
103#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
104#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
105#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
106#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
107#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
108#define DP83867_PHYCR_RESERVED_MASK BIT(11)
109#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
110
111/* RGMIIDCTL bits */
112#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
113#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
114#define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
115#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
116#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
117#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
118
119/* IO_MUX_CFG bits */
120#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
121#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
122#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
123#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
124#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
125#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
126
127/* PHY STS bits */
128#define DP83867_PHYSTS_1000 BIT(15)
129#define DP83867_PHYSTS_100 BIT(14)
130#define DP83867_PHYSTS_DUPLEX BIT(13)
131#define DP83867_PHYSTS_LINK BIT(10)
132
133/* CFG2 bits */
134#define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
135#define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
136#define DP83867_DOWNSHIFT_1_COUNT_VAL 0
137#define DP83867_DOWNSHIFT_2_COUNT_VAL 1
138#define DP83867_DOWNSHIFT_4_COUNT_VAL 2
139#define DP83867_DOWNSHIFT_8_COUNT_VAL 3
140#define DP83867_DOWNSHIFT_1_COUNT 1
141#define DP83867_DOWNSHIFT_2_COUNT 2
142#define DP83867_DOWNSHIFT_4_COUNT 4
143#define DP83867_DOWNSHIFT_8_COUNT 8
144#define DP83867_SGMII_AUTONEG_EN BIT(7)
145
146/* CFG3 bits */
147#define DP83867_CFG3_INT_OE BIT(7)
148#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
149
150/* CFG4 bits */
151#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
152
153/* FLD_THR_CFG */
154#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
155
156#define DP83867_LED_COUNT 4
157
158/* LED_DRV bits */
159#define DP83867_LED_DRV_EN(x) BIT((x) * 4)
160#define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1)
161#define DP83867_LED_POLARITY(x) BIT((x) * 4 + 2)
162
163#define DP83867_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4))
164#define DP83867_LED_FN_MASK(idx) (0xf << ((idx) * 4))
165#define DP83867_LED_FN_RX_ERR 0xe /* Receive Error */
166#define DP83867_LED_FN_RX_TX_ERR 0xd /* Receive Error or Transmit Error */
167#define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */
168#define DP83867_LED_FN_FULL_DUPLEX 0xa /* Full duplex */
169#define DP83867_LED_FN_LINK_100_1000_BT 0x9 /* 100/1000BT link established */
170#define DP83867_LED_FN_LINK_10_100_BT 0x8 /* 10/100BT link established */
171#define DP83867_LED_FN_LINK_10_BT 0x7 /* 10BT link established */
172#define DP83867_LED_FN_LINK_100_BTX 0x6 /* 100 BTX link established */
173#define DP83867_LED_FN_LINK_1000_BT 0x5 /* 1000 BT link established */
174#define DP83867_LED_FN_COLLISION 0x4 /* Collision detected */
175#define DP83867_LED_FN_RX 0x3 /* Receive activity */
176#define DP83867_LED_FN_TX 0x2 /* Transmit activity */
177#define DP83867_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
178#define DP83867_LED_FN_LINK 0x0 /* Link established */
179
180enum {
181 DP83867_PORT_MIRROING_KEEP,
182 DP83867_PORT_MIRROING_EN,
183 DP83867_PORT_MIRROING_DIS,
184};
185
186struct dp83867_private {
187 u32 rx_id_delay;
188 u32 tx_id_delay;
189 u32 tx_fifo_depth;
190 u32 rx_fifo_depth;
191 int io_impedance;
192 int port_mirroring;
193 bool rxctrl_strap_quirk;
194 bool set_clk_output;
195 u32 clk_output_sel;
196 bool sgmii_ref_clk_en;
197};
198
199static int dp83867_ack_interrupt(struct phy_device *phydev)
200{
201 int err = phy_read(phydev, MII_DP83867_ISR);
202
203 if (err < 0)
204 return err;
205
206 return 0;
207}
208
209static int dp83867_set_wol(struct phy_device *phydev,
210 struct ethtool_wolinfo *wol)
211{
212 struct net_device *ndev = phydev->attached_dev;
213 u16 val_rxcfg, val_micr;
214 const u8 *mac;
215
216 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
217 val_micr = phy_read(phydev, MII_DP83867_MICR);
218
219 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
220 WAKE_BCAST)) {
221 val_rxcfg |= DP83867_WOL_ENH_MAC;
222 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
223
224 if (wol->wolopts & WAKE_MAGIC) {
225 mac = (const u8 *)ndev->dev_addr;
226
227 if (!is_valid_ether_addr(mac))
228 return -EINVAL;
229
230 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
231 (mac[1] << 8 | mac[0]));
232 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
233 (mac[3] << 8 | mac[2]));
234 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
235 (mac[5] << 8 | mac[4]));
236
237 val_rxcfg |= DP83867_WOL_MAGIC_EN;
238 } else {
239 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
240 }
241
242 if (wol->wolopts & WAKE_MAGICSECURE) {
243 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
244 (wol->sopass[1] << 8) | wol->sopass[0]);
245 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
246 (wol->sopass[3] << 8) | wol->sopass[2]);
247 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
248 (wol->sopass[5] << 8) | wol->sopass[4]);
249
250 val_rxcfg |= DP83867_WOL_SEC_EN;
251 } else {
252 val_rxcfg &= ~DP83867_WOL_SEC_EN;
253 }
254
255 if (wol->wolopts & WAKE_UCAST)
256 val_rxcfg |= DP83867_WOL_UCAST_EN;
257 else
258 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
259
260 if (wol->wolopts & WAKE_BCAST)
261 val_rxcfg |= DP83867_WOL_BCAST_EN;
262 else
263 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
264 } else {
265 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
266 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
267 }
268
269 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
270 phy_write(phydev, MII_DP83867_MICR, val_micr);
271
272 return 0;
273}
274
275static void dp83867_get_wol(struct phy_device *phydev,
276 struct ethtool_wolinfo *wol)
277{
278 u16 value, sopass_val;
279
280 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
281 WAKE_MAGICSECURE);
282 wol->wolopts = 0;
283
284 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
285
286 if (value & DP83867_WOL_UCAST_EN)
287 wol->wolopts |= WAKE_UCAST;
288
289 if (value & DP83867_WOL_BCAST_EN)
290 wol->wolopts |= WAKE_BCAST;
291
292 if (value & DP83867_WOL_MAGIC_EN)
293 wol->wolopts |= WAKE_MAGIC;
294
295 if (value & DP83867_WOL_SEC_EN) {
296 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
297 DP83867_RXFSOP1);
298 wol->sopass[0] = (sopass_val & 0xff);
299 wol->sopass[1] = (sopass_val >> 8);
300
301 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
302 DP83867_RXFSOP2);
303 wol->sopass[2] = (sopass_val & 0xff);
304 wol->sopass[3] = (sopass_val >> 8);
305
306 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
307 DP83867_RXFSOP3);
308 wol->sopass[4] = (sopass_val & 0xff);
309 wol->sopass[5] = (sopass_val >> 8);
310
311 wol->wolopts |= WAKE_MAGICSECURE;
312 }
313
314 if (!(value & DP83867_WOL_ENH_MAC))
315 wol->wolopts = 0;
316}
317
318static int dp83867_config_intr(struct phy_device *phydev)
319{
320 int micr_status, err;
321
322 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
323 err = dp83867_ack_interrupt(phydev);
324 if (err)
325 return err;
326
327 micr_status = phy_read(phydev, MII_DP83867_MICR);
328 if (micr_status < 0)
329 return micr_status;
330
331 micr_status |=
332 (MII_DP83867_MICR_AN_ERR_INT_EN |
333 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
334 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
335 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
336 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
337 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
338
339 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
340 } else {
341 micr_status = 0x0;
342 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
343 if (err)
344 return err;
345
346 err = dp83867_ack_interrupt(phydev);
347 }
348
349 return err;
350}
351
352static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
353{
354 int irq_status, irq_enabled;
355
356 irq_status = phy_read(phydev, MII_DP83867_ISR);
357 if (irq_status < 0) {
358 phy_error(phydev);
359 return IRQ_NONE;
360 }
361
362 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
363 if (irq_enabled < 0) {
364 phy_error(phydev);
365 return IRQ_NONE;
366 }
367
368 if (!(irq_status & irq_enabled))
369 return IRQ_NONE;
370
371 phy_trigger_machine(phydev);
372
373 return IRQ_HANDLED;
374}
375
376static int dp83867_read_status(struct phy_device *phydev)
377{
378 int status = phy_read(phydev, MII_DP83867_PHYSTS);
379 int ret;
380
381 ret = genphy_read_status(phydev);
382 if (ret)
383 return ret;
384
385 if (status < 0)
386 return status;
387
388 if (status & DP83867_PHYSTS_DUPLEX)
389 phydev->duplex = DUPLEX_FULL;
390 else
391 phydev->duplex = DUPLEX_HALF;
392
393 if (status & DP83867_PHYSTS_1000)
394 phydev->speed = SPEED_1000;
395 else if (status & DP83867_PHYSTS_100)
396 phydev->speed = SPEED_100;
397 else
398 phydev->speed = SPEED_10;
399
400 return 0;
401}
402
403static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
404{
405 int val, cnt, enable, count;
406
407 val = phy_read(phydev, DP83867_CFG2);
408 if (val < 0)
409 return val;
410
411 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
412 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
413
414 switch (cnt) {
415 case DP83867_DOWNSHIFT_1_COUNT_VAL:
416 count = DP83867_DOWNSHIFT_1_COUNT;
417 break;
418 case DP83867_DOWNSHIFT_2_COUNT_VAL:
419 count = DP83867_DOWNSHIFT_2_COUNT;
420 break;
421 case DP83867_DOWNSHIFT_4_COUNT_VAL:
422 count = DP83867_DOWNSHIFT_4_COUNT;
423 break;
424 case DP83867_DOWNSHIFT_8_COUNT_VAL:
425 count = DP83867_DOWNSHIFT_8_COUNT;
426 break;
427 default:
428 return -EINVAL;
429 }
430
431 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
432
433 return 0;
434}
435
436static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
437{
438 int val, count;
439
440 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
441 return -E2BIG;
442
443 if (!cnt)
444 return phy_clear_bits(phydev, DP83867_CFG2,
445 DP83867_DOWNSHIFT_EN);
446
447 switch (cnt) {
448 case DP83867_DOWNSHIFT_1_COUNT:
449 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
450 break;
451 case DP83867_DOWNSHIFT_2_COUNT:
452 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
453 break;
454 case DP83867_DOWNSHIFT_4_COUNT:
455 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
456 break;
457 case DP83867_DOWNSHIFT_8_COUNT:
458 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
459 break;
460 default:
461 phydev_err(phydev,
462 "Downshift count must be 1, 2, 4 or 8\n");
463 return -EINVAL;
464 }
465
466 val = DP83867_DOWNSHIFT_EN;
467 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
468
469 return phy_modify(phydev, DP83867_CFG2,
470 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
471 val);
472}
473
474static int dp83867_get_tunable(struct phy_device *phydev,
475 struct ethtool_tunable *tuna, void *data)
476{
477 switch (tuna->id) {
478 case ETHTOOL_PHY_DOWNSHIFT:
479 return dp83867_get_downshift(phydev, data);
480 default:
481 return -EOPNOTSUPP;
482 }
483}
484
485static int dp83867_set_tunable(struct phy_device *phydev,
486 struct ethtool_tunable *tuna, const void *data)
487{
488 switch (tuna->id) {
489 case ETHTOOL_PHY_DOWNSHIFT:
490 return dp83867_set_downshift(phydev, *(const u8 *)data);
491 default:
492 return -EOPNOTSUPP;
493 }
494}
495
496static int dp83867_config_port_mirroring(struct phy_device *phydev)
497{
498 struct dp83867_private *dp83867 = phydev->priv;
499
500 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
501 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
502 DP83867_CFG4_PORT_MIRROR_EN);
503 else
504 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
505 DP83867_CFG4_PORT_MIRROR_EN);
506 return 0;
507}
508
509static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
510{
511 struct dp83867_private *dp83867 = phydev->priv;
512
513 /* Existing behavior was to use default pin strapping delay in rgmii
514 * mode, but rgmii should have meant no delay. Warn existing users.
515 */
516 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
517 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
518 DP83867_STRAP_STS2);
519 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
520 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
521 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
522 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
523
524 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
525 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
526 phydev_warn(phydev,
527 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
528 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
529 txskew, rxskew);
530 }
531
532 /* RX delay *must* be specified if internal delay of RX is used. */
533 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
534 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
535 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
536 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
537 return -EINVAL;
538 }
539
540 /* TX delay *must* be specified if internal delay of TX is used. */
541 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
542 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
543 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
544 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
545 return -EINVAL;
546 }
547
548 return 0;
549}
550
551#if IS_ENABLED(CONFIG_OF_MDIO)
552static int dp83867_of_init_io_impedance(struct phy_device *phydev)
553{
554 struct dp83867_private *dp83867 = phydev->priv;
555 struct device *dev = &phydev->mdio.dev;
556 struct device_node *of_node = dev->of_node;
557 struct nvmem_cell *cell;
558 u8 *buf, val;
559 int ret;
560
561 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
562 if (IS_ERR(cell)) {
563 ret = PTR_ERR(cell);
564 if (ret != -ENOENT && ret != -EOPNOTSUPP)
565 return phydev_err_probe(phydev, ret,
566 "failed to get nvmem cell io_impedance_ctrl\n");
567
568 /* If no nvmem cell, check for the boolean properties. */
569 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
570 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
571 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
572 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
573 else
574 dp83867->io_impedance = -1; /* leave at default */
575
576 return 0;
577 }
578
579 buf = nvmem_cell_read(cell, NULL);
580 nvmem_cell_put(cell);
581
582 if (IS_ERR(buf))
583 return PTR_ERR(buf);
584
585 val = *buf;
586 kfree(buf);
587
588 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
589 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
590 return -ERANGE;
591 }
592 dp83867->io_impedance = val;
593
594 return 0;
595}
596
597static int dp83867_of_init(struct phy_device *phydev)
598{
599 struct dp83867_private *dp83867 = phydev->priv;
600 struct device *dev = &phydev->mdio.dev;
601 struct device_node *of_node = dev->of_node;
602 int ret;
603
604 if (!of_node)
605 return -ENODEV;
606
607 /* Optional configuration */
608 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
609 &dp83867->clk_output_sel);
610 /* If not set, keep default */
611 if (!ret) {
612 dp83867->set_clk_output = true;
613 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
614 * DP83867_CLK_O_SEL_OFF.
615 */
616 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
617 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
618 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
619 dp83867->clk_output_sel);
620 return -EINVAL;
621 }
622 }
623
624 ret = dp83867_of_init_io_impedance(phydev);
625 if (ret)
626 return ret;
627
628 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
629 "ti,dp83867-rxctrl-strap-quirk");
630
631 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
632 "ti,sgmii-ref-clock-output-enable");
633
634 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
635 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
636 &dp83867->rx_id_delay);
637 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
638 phydev_err(phydev,
639 "ti,rx-internal-delay value of %u out of range\n",
640 dp83867->rx_id_delay);
641 return -EINVAL;
642 }
643
644 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
645 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
646 &dp83867->tx_id_delay);
647 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
648 phydev_err(phydev,
649 "ti,tx-internal-delay value of %u out of range\n",
650 dp83867->tx_id_delay);
651 return -EINVAL;
652 }
653
654 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
655 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
656
657 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
658 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
659
660 ret = of_property_read_u32(of_node, "ti,fifo-depth",
661 &dp83867->tx_fifo_depth);
662 if (ret) {
663 ret = of_property_read_u32(of_node, "tx-fifo-depth",
664 &dp83867->tx_fifo_depth);
665 if (ret)
666 dp83867->tx_fifo_depth =
667 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
668 }
669
670 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
671 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
672 dp83867->tx_fifo_depth);
673 return -EINVAL;
674 }
675
676 ret = of_property_read_u32(of_node, "rx-fifo-depth",
677 &dp83867->rx_fifo_depth);
678 if (ret)
679 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
680
681 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
682 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
683 dp83867->rx_fifo_depth);
684 return -EINVAL;
685 }
686
687 return 0;
688}
689#else
690static int dp83867_of_init(struct phy_device *phydev)
691{
692 struct dp83867_private *dp83867 = phydev->priv;
693 u16 delay;
694
695 /* For non-OF device, the RX and TX ID values are either strapped
696 * or take from default value. So, we init RX & TX ID values here
697 * so that the RGMIIDCTL is configured correctly later in
698 * dp83867_config_init();
699 */
700 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
701 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
702 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
703 DP83867_RGMII_TX_CLK_DELAY_MAX;
704
705 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
706 * same here or else the default '0' means highest IO impedance
707 * which is wrong.
708 */
709 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
710
711 /* For non-OF device, the RX and TX FIFO depths are taken from
712 * default value. So, we init RX & TX FIFO depths here
713 * so that it is configured correctly later in dp83867_config_init();
714 */
715 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
716 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
717
718 return 0;
719}
720#endif /* CONFIG_OF_MDIO */
721
722static int dp83867_suspend(struct phy_device *phydev)
723{
724 /* Disable PHY Interrupts */
725 if (phy_interrupt_is_valid(phydev)) {
726 phydev->interrupts = PHY_INTERRUPT_DISABLED;
727 dp83867_config_intr(phydev);
728 }
729
730 return genphy_suspend(phydev);
731}
732
733static int dp83867_resume(struct phy_device *phydev)
734{
735 /* Enable PHY Interrupts */
736 if (phy_interrupt_is_valid(phydev)) {
737 phydev->interrupts = PHY_INTERRUPT_ENABLED;
738 dp83867_config_intr(phydev);
739 }
740
741 genphy_resume(phydev);
742
743 return 0;
744}
745
746static int dp83867_probe(struct phy_device *phydev)
747{
748 struct dp83867_private *dp83867;
749
750 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
751 GFP_KERNEL);
752 if (!dp83867)
753 return -ENOMEM;
754
755 phydev->priv = dp83867;
756
757 return dp83867_of_init(phydev);
758}
759
760static int dp83867_config_init(struct phy_device *phydev)
761{
762 struct dp83867_private *dp83867 = phydev->priv;
763 int ret, val, bs;
764 u16 delay;
765
766 /* Force speed optimization for the PHY even if it strapped */
767 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
768 DP83867_DOWNSHIFT_EN);
769 if (ret)
770 return ret;
771
772 ret = dp83867_verify_rgmii_cfg(phydev);
773 if (ret)
774 return ret;
775
776 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
777 if (dp83867->rxctrl_strap_quirk)
778 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
779 BIT(7));
780
781 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
782 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
783 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
784 * be set to 0x2. This may causes the PHY link to be unstable -
785 * the default value 0x1 need to be restored.
786 */
787 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
788 DP83867_FLD_THR_CFG,
789 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
790 0x1);
791 if (ret)
792 return ret;
793 }
794
795 if (phy_interface_is_rgmii(phydev) ||
796 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
797 val = phy_read(phydev, MII_DP83867_PHYCTRL);
798 if (val < 0)
799 return val;
800
801 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
802 val |= (dp83867->tx_fifo_depth <<
803 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
804
805 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
806 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
807 val |= (dp83867->rx_fifo_depth <<
808 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
809 }
810
811 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
812 if (ret)
813 return ret;
814 }
815
816 if (phy_interface_is_rgmii(phydev)) {
817 val = phy_read(phydev, MII_DP83867_PHYCTRL);
818 if (val < 0)
819 return val;
820
821 /* The code below checks if "port mirroring" N/A MODE4 has been
822 * enabled during power on bootstrap.
823 *
824 * Such N/A mode enabled by mistake can put PHY IC in some
825 * internal testing mode and disable RGMII transmission.
826 *
827 * In this particular case one needs to check STRAP_STS1
828 * register's bit 11 (marked as RESERVED).
829 */
830
831 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
832 if (bs & DP83867_STRAP_STS1_RESERVED)
833 val &= ~DP83867_PHYCR_RESERVED_MASK;
834
835 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
836 if (ret)
837 return ret;
838
839 /* If rgmii mode with no internal delay is selected, we do NOT use
840 * aligned mode as one might expect. Instead we use the PHY's default
841 * based on pin strapping. And the "mode 0" default is to *use*
842 * internal delay with a value of 7 (2.00 ns).
843 *
844 * Set up RGMII delays
845 */
846 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
847
848 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
849 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
850 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
851
852 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
853 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
854
855 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
856 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
857
858 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
859
860 delay = 0;
861 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
862 delay |= dp83867->rx_id_delay;
863 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
864 delay |= dp83867->tx_id_delay <<
865 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
866
867 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
868 delay);
869 }
870
871 /* If specified, set io impedance */
872 if (dp83867->io_impedance >= 0)
873 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
874 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
875 dp83867->io_impedance);
876
877 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
878 /* For support SPEED_10 in SGMII mode
879 * DP83867_10M_SGMII_RATE_ADAPT bit
880 * has to be cleared by software. That
881 * does not affect SPEED_100 and
882 * SPEED_1000.
883 */
884 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
885 DP83867_10M_SGMII_CFG,
886 DP83867_10M_SGMII_RATE_ADAPT_MASK,
887 0);
888 if (ret)
889 return ret;
890
891 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
892 * are 01). That is not enough to finalize autoneg on some
893 * devices. Increase this timer duration to maximum 16ms.
894 */
895 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
896 DP83867_CFG4,
897 DP83867_CFG4_SGMII_ANEG_MASK,
898 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
899
900 if (ret)
901 return ret;
902
903 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
904 /* SGMII type is set to 4-wire mode by default.
905 * If we place appropriate property in dts (see above)
906 * switch on 6-wire mode.
907 */
908 if (dp83867->sgmii_ref_clk_en)
909 val |= DP83867_SGMII_TYPE;
910 else
911 val &= ~DP83867_SGMII_TYPE;
912 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
913
914 /* This is a SW workaround for link instability if RX_CTRL is
915 * not strapped to mode 3 or 4 in HW. This is required for SGMII
916 * in addition to clearing bit 7, handled above.
917 */
918 if (dp83867->rxctrl_strap_quirk)
919 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
920 BIT(8));
921 }
922
923 val = phy_read(phydev, DP83867_CFG3);
924 /* Enable Interrupt output INT_OE in CFG3 register */
925 if (phy_interrupt_is_valid(phydev))
926 val |= DP83867_CFG3_INT_OE;
927
928 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
929 phy_write(phydev, DP83867_CFG3, val);
930
931 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
932 dp83867_config_port_mirroring(phydev);
933
934 /* Clock output selection if muxing property is set */
935 if (dp83867->set_clk_output) {
936 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
937
938 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
939 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
940 } else {
941 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
942 val = dp83867->clk_output_sel <<
943 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
944 }
945
946 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
947 mask, val);
948 }
949
950 return 0;
951}
952
953static int dp83867_phy_reset(struct phy_device *phydev)
954{
955 int err;
956
957 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
958 if (err < 0)
959 return err;
960
961 usleep_range(10, 20);
962
963 err = phy_modify(phydev, MII_DP83867_PHYCTRL,
964 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
965 if (err < 0)
966 return err;
967
968 /* Configure the DSP Feedforward Equalizer Configuration register to
969 * improve short cable (< 1 meter) performance. This will not affect
970 * long cable performance.
971 */
972 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,
973 0x0e81);
974 if (err < 0)
975 return err;
976
977 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
978 if (err < 0)
979 return err;
980
981 usleep_range(10, 20);
982
983 return 0;
984}
985
986static void dp83867_link_change_notify(struct phy_device *phydev)
987{
988 /* There is a limitation in DP83867 PHY device where SGMII AN is
989 * only triggered once after the device is booted up. Even after the
990 * PHY TPI is down and up again, SGMII AN is not triggered and
991 * hence no new in-band message from PHY to MAC side SGMII.
992 * This could cause an issue during power up, when PHY is up prior
993 * to MAC. At this condition, once MAC side SGMII is up, MAC side
994 * SGMII wouldn`t receive new in-band message from TI PHY with
995 * correct link status, speed and duplex info.
996 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
997 * whenever there is a link change.
998 */
999 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1000 int val = 0;
1001
1002 val = phy_clear_bits(phydev, DP83867_CFG2,
1003 DP83867_SGMII_AUTONEG_EN);
1004 if (val < 0)
1005 return;
1006
1007 phy_set_bits(phydev, DP83867_CFG2,
1008 DP83867_SGMII_AUTONEG_EN);
1009 }
1010}
1011
1012static int dp83867_loopback(struct phy_device *phydev, bool enable)
1013{
1014 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
1015 enable ? BMCR_LOOPBACK : 0);
1016}
1017
1018static int
1019dp83867_led_brightness_set(struct phy_device *phydev,
1020 u8 index, enum led_brightness brightness)
1021{
1022 u32 val;
1023
1024 if (index >= DP83867_LED_COUNT)
1025 return -EINVAL;
1026
1027 /* DRV_EN==1: output is DRV_VAL */
1028 val = DP83867_LED_DRV_EN(index);
1029
1030 if (brightness)
1031 val |= DP83867_LED_DRV_VAL(index);
1032
1033 return phy_modify(phydev, DP83867_LEDCR2,
1034 DP83867_LED_DRV_VAL(index) |
1035 DP83867_LED_DRV_EN(index),
1036 val);
1037}
1038
1039static int dp83867_led_mode(u8 index, unsigned long rules)
1040{
1041 if (index >= DP83867_LED_COUNT)
1042 return -EINVAL;
1043
1044 switch (rules) {
1045 case BIT(TRIGGER_NETDEV_LINK):
1046 return DP83867_LED_FN_LINK;
1047 case BIT(TRIGGER_NETDEV_LINK_10):
1048 return DP83867_LED_FN_LINK_10_BT;
1049 case BIT(TRIGGER_NETDEV_LINK_100):
1050 return DP83867_LED_FN_LINK_100_BTX;
1051 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
1052 return DP83867_LED_FN_FULL_DUPLEX;
1053 case BIT(TRIGGER_NETDEV_TX):
1054 return DP83867_LED_FN_TX;
1055 case BIT(TRIGGER_NETDEV_RX):
1056 return DP83867_LED_FN_RX;
1057 case BIT(TRIGGER_NETDEV_LINK_1000):
1058 return DP83867_LED_FN_LINK_1000_BT;
1059 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1060 return DP83867_LED_FN_RX_TX;
1061 case BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000):
1062 return DP83867_LED_FN_LINK_100_1000_BT;
1063 case BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100):
1064 return DP83867_LED_FN_LINK_10_100_BT;
1065 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1066 return DP83867_LED_FN_LINK_RX_TX;
1067 default:
1068 return -EOPNOTSUPP;
1069 }
1070}
1071
1072static int dp83867_led_hw_is_supported(struct phy_device *phydev, u8 index,
1073 unsigned long rules)
1074{
1075 int ret;
1076
1077 ret = dp83867_led_mode(index, rules);
1078 if (ret < 0)
1079 return ret;
1080
1081 return 0;
1082}
1083
1084static int dp83867_led_hw_control_set(struct phy_device *phydev, u8 index,
1085 unsigned long rules)
1086{
1087 int mode, ret;
1088
1089 mode = dp83867_led_mode(index, rules);
1090 if (mode < 0)
1091 return mode;
1092
1093 ret = phy_modify(phydev, DP83867_LEDCR1, DP83867_LED_FN_MASK(index),
1094 DP83867_LED_FN(index, mode));
1095 if (ret)
1096 return ret;
1097
1098 return phy_modify(phydev, DP83867_LEDCR2, DP83867_LED_DRV_EN(index), 0);
1099}
1100
1101static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index,
1102 unsigned long *rules)
1103{
1104 int val;
1105
1106 val = phy_read(phydev, DP83867_LEDCR1);
1107 if (val < 0)
1108 return val;
1109
1110 val &= DP83867_LED_FN_MASK(index);
1111 val >>= index * 4;
1112
1113 switch (val) {
1114 case DP83867_LED_FN_LINK:
1115 *rules = BIT(TRIGGER_NETDEV_LINK);
1116 break;
1117 case DP83867_LED_FN_LINK_10_BT:
1118 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1119 break;
1120 case DP83867_LED_FN_LINK_100_BTX:
1121 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1122 break;
1123 case DP83867_LED_FN_FULL_DUPLEX:
1124 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1125 break;
1126 case DP83867_LED_FN_TX:
1127 *rules = BIT(TRIGGER_NETDEV_TX);
1128 break;
1129 case DP83867_LED_FN_RX:
1130 *rules = BIT(TRIGGER_NETDEV_RX);
1131 break;
1132 case DP83867_LED_FN_LINK_1000_BT:
1133 *rules = BIT(TRIGGER_NETDEV_LINK_1000);
1134 break;
1135 case DP83867_LED_FN_RX_TX:
1136 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1137 break;
1138 case DP83867_LED_FN_LINK_100_1000_BT:
1139 *rules = BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000);
1140 break;
1141 case DP83867_LED_FN_LINK_10_100_BT:
1142 *rules = BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100);
1143 break;
1144 case DP83867_LED_FN_LINK_RX_TX:
1145 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1146 BIT(TRIGGER_NETDEV_RX);
1147 break;
1148 default:
1149 *rules = 0;
1150 break;
1151 }
1152
1153 return 0;
1154}
1155
1156static int dp83867_led_polarity_set(struct phy_device *phydev, int index,
1157 unsigned long modes)
1158{
1159 /* Default active high */
1160 u16 polarity = DP83867_LED_POLARITY(index);
1161 u32 mode;
1162
1163 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
1164 switch (mode) {
1165 case PHY_LED_ACTIVE_LOW:
1166 polarity = 0;
1167 break;
1168 default:
1169 return -EINVAL;
1170 }
1171 }
1172 return phy_modify(phydev, DP83867_LEDCR2,
1173 DP83867_LED_POLARITY(index), polarity);
1174}
1175
1176static struct phy_driver dp83867_driver[] = {
1177 {
1178 .phy_id = DP83867_PHY_ID,
1179 .phy_id_mask = 0xfffffff0,
1180 .name = "TI DP83867",
1181 /* PHY_GBIT_FEATURES */
1182
1183 .probe = dp83867_probe,
1184 .config_init = dp83867_config_init,
1185 .soft_reset = dp83867_phy_reset,
1186
1187 .read_status = dp83867_read_status,
1188 .get_tunable = dp83867_get_tunable,
1189 .set_tunable = dp83867_set_tunable,
1190
1191 .get_wol = dp83867_get_wol,
1192 .set_wol = dp83867_set_wol,
1193
1194 /* IRQ related */
1195 .config_intr = dp83867_config_intr,
1196 .handle_interrupt = dp83867_handle_interrupt,
1197
1198 .suspend = dp83867_suspend,
1199 .resume = dp83867_resume,
1200
1201 .link_change_notify = dp83867_link_change_notify,
1202 .set_loopback = dp83867_loopback,
1203
1204 .led_brightness_set = dp83867_led_brightness_set,
1205 .led_hw_is_supported = dp83867_led_hw_is_supported,
1206 .led_hw_control_set = dp83867_led_hw_control_set,
1207 .led_hw_control_get = dp83867_led_hw_control_get,
1208 .led_polarity_set = dp83867_led_polarity_set,
1209 },
1210};
1211module_phy_driver(dp83867_driver);
1212
1213static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
1214 { DP83867_PHY_ID, 0xfffffff0 },
1215 { }
1216};
1217
1218MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
1219
1220MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
1221MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1222MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 */
6
7#include <linux/ethtool.h>
8#include <linux/kernel.h>
9#include <linux/mii.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/phy.h>
13#include <linux/delay.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/bitfield.h>
17
18#include <dt-bindings/net/ti-dp83867.h>
19
20#define DP83867_PHY_ID 0x2000a231
21#define DP83867_DEVADDR 0x1f
22
23#define MII_DP83867_PHYCTRL 0x10
24#define MII_DP83867_PHYSTS 0x11
25#define MII_DP83867_MICR 0x12
26#define MII_DP83867_ISR 0x13
27#define DP83867_CFG2 0x14
28#define DP83867_CFG3 0x1e
29#define DP83867_CTRL 0x1f
30
31/* Extended Registers */
32#define DP83867_FLD_THR_CFG 0x002e
33#define DP83867_CFG4 0x0031
34#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
35#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
36#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
37#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
38#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
39
40#define DP83867_RGMIICTL 0x0032
41#define DP83867_STRAP_STS1 0x006E
42#define DP83867_STRAP_STS2 0x006f
43#define DP83867_RGMIIDCTL 0x0086
44#define DP83867_RXFCFG 0x0134
45#define DP83867_RXFPMD1 0x0136
46#define DP83867_RXFPMD2 0x0137
47#define DP83867_RXFPMD3 0x0138
48#define DP83867_RXFSOP1 0x0139
49#define DP83867_RXFSOP2 0x013A
50#define DP83867_RXFSOP3 0x013B
51#define DP83867_IO_MUX_CFG 0x0170
52#define DP83867_SGMIICTL 0x00D3
53#define DP83867_10M_SGMII_CFG 0x016F
54#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
55
56#define DP83867_SW_RESET BIT(15)
57#define DP83867_SW_RESTART BIT(14)
58
59/* MICR Interrupt bits */
60#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
61#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
62#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
63#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
64#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
65#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
66#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
67#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
68#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
69#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
70#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
71#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
72
73/* RGMIICTL bits */
74#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
75#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
76
77/* SGMIICTL bits */
78#define DP83867_SGMII_TYPE BIT(14)
79
80/* RXFCFG bits*/
81#define DP83867_WOL_MAGIC_EN BIT(0)
82#define DP83867_WOL_BCAST_EN BIT(2)
83#define DP83867_WOL_UCAST_EN BIT(4)
84#define DP83867_WOL_SEC_EN BIT(5)
85#define DP83867_WOL_ENH_MAC BIT(7)
86
87/* STRAP_STS1 bits */
88#define DP83867_STRAP_STS1_RESERVED BIT(11)
89
90/* STRAP_STS2 bits */
91#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
92#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
93#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
94#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
95#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
96#define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
97
98/* PHY CTRL bits */
99#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
100#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
101#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
102#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
103#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
104#define DP83867_PHYCR_RESERVED_MASK BIT(11)
105#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
106
107/* RGMIIDCTL bits */
108#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
109#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
110#define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
111#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
112#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
113#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
114
115/* IO_MUX_CFG bits */
116#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
117#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
118#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
119#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
120#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
121#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
122
123/* PHY STS bits */
124#define DP83867_PHYSTS_1000 BIT(15)
125#define DP83867_PHYSTS_100 BIT(14)
126#define DP83867_PHYSTS_DUPLEX BIT(13)
127#define DP83867_PHYSTS_LINK BIT(10)
128
129/* CFG2 bits */
130#define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
131#define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
132#define DP83867_DOWNSHIFT_1_COUNT_VAL 0
133#define DP83867_DOWNSHIFT_2_COUNT_VAL 1
134#define DP83867_DOWNSHIFT_4_COUNT_VAL 2
135#define DP83867_DOWNSHIFT_8_COUNT_VAL 3
136#define DP83867_DOWNSHIFT_1_COUNT 1
137#define DP83867_DOWNSHIFT_2_COUNT 2
138#define DP83867_DOWNSHIFT_4_COUNT 4
139#define DP83867_DOWNSHIFT_8_COUNT 8
140
141/* CFG3 bits */
142#define DP83867_CFG3_INT_OE BIT(7)
143#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
144
145/* CFG4 bits */
146#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
147
148/* FLD_THR_CFG */
149#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
150
151enum {
152 DP83867_PORT_MIRROING_KEEP,
153 DP83867_PORT_MIRROING_EN,
154 DP83867_PORT_MIRROING_DIS,
155};
156
157struct dp83867_private {
158 u32 rx_id_delay;
159 u32 tx_id_delay;
160 u32 tx_fifo_depth;
161 u32 rx_fifo_depth;
162 int io_impedance;
163 int port_mirroring;
164 bool rxctrl_strap_quirk;
165 bool set_clk_output;
166 u32 clk_output_sel;
167 bool sgmii_ref_clk_en;
168};
169
170static int dp83867_ack_interrupt(struct phy_device *phydev)
171{
172 int err = phy_read(phydev, MII_DP83867_ISR);
173
174 if (err < 0)
175 return err;
176
177 return 0;
178}
179
180static int dp83867_set_wol(struct phy_device *phydev,
181 struct ethtool_wolinfo *wol)
182{
183 struct net_device *ndev = phydev->attached_dev;
184 u16 val_rxcfg, val_micr;
185 u8 *mac;
186
187 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
188 val_micr = phy_read(phydev, MII_DP83867_MICR);
189
190 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
191 WAKE_BCAST)) {
192 val_rxcfg |= DP83867_WOL_ENH_MAC;
193 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
194
195 if (wol->wolopts & WAKE_MAGIC) {
196 mac = (u8 *)ndev->dev_addr;
197
198 if (!is_valid_ether_addr(mac))
199 return -EINVAL;
200
201 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
202 (mac[1] << 8 | mac[0]));
203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
204 (mac[3] << 8 | mac[2]));
205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
206 (mac[5] << 8 | mac[4]));
207
208 val_rxcfg |= DP83867_WOL_MAGIC_EN;
209 } else {
210 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
211 }
212
213 if (wol->wolopts & WAKE_MAGICSECURE) {
214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
215 (wol->sopass[1] << 8) | wol->sopass[0]);
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
217 (wol->sopass[3] << 8) | wol->sopass[2]);
218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
219 (wol->sopass[5] << 8) | wol->sopass[4]);
220
221 val_rxcfg |= DP83867_WOL_SEC_EN;
222 } else {
223 val_rxcfg &= ~DP83867_WOL_SEC_EN;
224 }
225
226 if (wol->wolopts & WAKE_UCAST)
227 val_rxcfg |= DP83867_WOL_UCAST_EN;
228 else
229 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
230
231 if (wol->wolopts & WAKE_BCAST)
232 val_rxcfg |= DP83867_WOL_BCAST_EN;
233 else
234 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
235 } else {
236 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
237 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
238 }
239
240 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
241 phy_write(phydev, MII_DP83867_MICR, val_micr);
242
243 return 0;
244}
245
246static void dp83867_get_wol(struct phy_device *phydev,
247 struct ethtool_wolinfo *wol)
248{
249 u16 value, sopass_val;
250
251 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
252 WAKE_MAGICSECURE);
253 wol->wolopts = 0;
254
255 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
256
257 if (value & DP83867_WOL_UCAST_EN)
258 wol->wolopts |= WAKE_UCAST;
259
260 if (value & DP83867_WOL_BCAST_EN)
261 wol->wolopts |= WAKE_BCAST;
262
263 if (value & DP83867_WOL_MAGIC_EN)
264 wol->wolopts |= WAKE_MAGIC;
265
266 if (value & DP83867_WOL_SEC_EN) {
267 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
268 DP83867_RXFSOP1);
269 wol->sopass[0] = (sopass_val & 0xff);
270 wol->sopass[1] = (sopass_val >> 8);
271
272 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
273 DP83867_RXFSOP2);
274 wol->sopass[2] = (sopass_val & 0xff);
275 wol->sopass[3] = (sopass_val >> 8);
276
277 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
278 DP83867_RXFSOP3);
279 wol->sopass[4] = (sopass_val & 0xff);
280 wol->sopass[5] = (sopass_val >> 8);
281
282 wol->wolopts |= WAKE_MAGICSECURE;
283 }
284
285 if (!(value & DP83867_WOL_ENH_MAC))
286 wol->wolopts = 0;
287}
288
289static int dp83867_config_intr(struct phy_device *phydev)
290{
291 int micr_status, err;
292
293 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
294 err = dp83867_ack_interrupt(phydev);
295 if (err)
296 return err;
297
298 micr_status = phy_read(phydev, MII_DP83867_MICR);
299 if (micr_status < 0)
300 return micr_status;
301
302 micr_status |=
303 (MII_DP83867_MICR_AN_ERR_INT_EN |
304 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
305 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
306 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
307 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
308 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
309
310 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
311 } else {
312 micr_status = 0x0;
313 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
314 if (err)
315 return err;
316
317 err = dp83867_ack_interrupt(phydev);
318 }
319
320 return err;
321}
322
323static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
324{
325 int irq_status, irq_enabled;
326
327 irq_status = phy_read(phydev, MII_DP83867_ISR);
328 if (irq_status < 0) {
329 phy_error(phydev);
330 return IRQ_NONE;
331 }
332
333 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
334 if (irq_enabled < 0) {
335 phy_error(phydev);
336 return IRQ_NONE;
337 }
338
339 if (!(irq_status & irq_enabled))
340 return IRQ_NONE;
341
342 phy_trigger_machine(phydev);
343
344 return IRQ_HANDLED;
345}
346
347static int dp83867_read_status(struct phy_device *phydev)
348{
349 int status = phy_read(phydev, MII_DP83867_PHYSTS);
350 int ret;
351
352 ret = genphy_read_status(phydev);
353 if (ret)
354 return ret;
355
356 if (status < 0)
357 return status;
358
359 if (status & DP83867_PHYSTS_DUPLEX)
360 phydev->duplex = DUPLEX_FULL;
361 else
362 phydev->duplex = DUPLEX_HALF;
363
364 if (status & DP83867_PHYSTS_1000)
365 phydev->speed = SPEED_1000;
366 else if (status & DP83867_PHYSTS_100)
367 phydev->speed = SPEED_100;
368 else
369 phydev->speed = SPEED_10;
370
371 return 0;
372}
373
374static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
375{
376 int val, cnt, enable, count;
377
378 val = phy_read(phydev, DP83867_CFG2);
379 if (val < 0)
380 return val;
381
382 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
383 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
384
385 switch (cnt) {
386 case DP83867_DOWNSHIFT_1_COUNT_VAL:
387 count = DP83867_DOWNSHIFT_1_COUNT;
388 break;
389 case DP83867_DOWNSHIFT_2_COUNT_VAL:
390 count = DP83867_DOWNSHIFT_2_COUNT;
391 break;
392 case DP83867_DOWNSHIFT_4_COUNT_VAL:
393 count = DP83867_DOWNSHIFT_4_COUNT;
394 break;
395 case DP83867_DOWNSHIFT_8_COUNT_VAL:
396 count = DP83867_DOWNSHIFT_8_COUNT;
397 break;
398 default:
399 return -EINVAL;
400 }
401
402 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
403
404 return 0;
405}
406
407static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
408{
409 int val, count;
410
411 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
412 return -E2BIG;
413
414 if (!cnt)
415 return phy_clear_bits(phydev, DP83867_CFG2,
416 DP83867_DOWNSHIFT_EN);
417
418 switch (cnt) {
419 case DP83867_DOWNSHIFT_1_COUNT:
420 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
421 break;
422 case DP83867_DOWNSHIFT_2_COUNT:
423 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
424 break;
425 case DP83867_DOWNSHIFT_4_COUNT:
426 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
427 break;
428 case DP83867_DOWNSHIFT_8_COUNT:
429 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
430 break;
431 default:
432 phydev_err(phydev,
433 "Downshift count must be 1, 2, 4 or 8\n");
434 return -EINVAL;
435 }
436
437 val = DP83867_DOWNSHIFT_EN;
438 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
439
440 return phy_modify(phydev, DP83867_CFG2,
441 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
442 val);
443}
444
445static int dp83867_get_tunable(struct phy_device *phydev,
446 struct ethtool_tunable *tuna, void *data)
447{
448 switch (tuna->id) {
449 case ETHTOOL_PHY_DOWNSHIFT:
450 return dp83867_get_downshift(phydev, data);
451 default:
452 return -EOPNOTSUPP;
453 }
454}
455
456static int dp83867_set_tunable(struct phy_device *phydev,
457 struct ethtool_tunable *tuna, const void *data)
458{
459 switch (tuna->id) {
460 case ETHTOOL_PHY_DOWNSHIFT:
461 return dp83867_set_downshift(phydev, *(const u8 *)data);
462 default:
463 return -EOPNOTSUPP;
464 }
465}
466
467static int dp83867_config_port_mirroring(struct phy_device *phydev)
468{
469 struct dp83867_private *dp83867 =
470 (struct dp83867_private *)phydev->priv;
471
472 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
473 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
474 DP83867_CFG4_PORT_MIRROR_EN);
475 else
476 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
477 DP83867_CFG4_PORT_MIRROR_EN);
478 return 0;
479}
480
481static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
482{
483 struct dp83867_private *dp83867 = phydev->priv;
484
485 /* Existing behavior was to use default pin strapping delay in rgmii
486 * mode, but rgmii should have meant no delay. Warn existing users.
487 */
488 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
489 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
490 DP83867_STRAP_STS2);
491 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
492 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
493 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
494 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
495
496 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
497 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
498 phydev_warn(phydev,
499 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
500 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
501 txskew, rxskew);
502 }
503
504 /* RX delay *must* be specified if internal delay of RX is used. */
505 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
506 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
507 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
508 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
509 return -EINVAL;
510 }
511
512 /* TX delay *must* be specified if internal delay of TX is used. */
513 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
514 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
515 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
516 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
517 return -EINVAL;
518 }
519
520 return 0;
521}
522
523#if IS_ENABLED(CONFIG_OF_MDIO)
524static int dp83867_of_init(struct phy_device *phydev)
525{
526 struct dp83867_private *dp83867 = phydev->priv;
527 struct device *dev = &phydev->mdio.dev;
528 struct device_node *of_node = dev->of_node;
529 int ret;
530
531 if (!of_node)
532 return -ENODEV;
533
534 /* Optional configuration */
535 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
536 &dp83867->clk_output_sel);
537 /* If not set, keep default */
538 if (!ret) {
539 dp83867->set_clk_output = true;
540 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
541 * DP83867_CLK_O_SEL_OFF.
542 */
543 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
544 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
545 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
546 dp83867->clk_output_sel);
547 return -EINVAL;
548 }
549 }
550
551 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
552 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
553 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
554 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
555 else
556 dp83867->io_impedance = -1; /* leave at default */
557
558 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
559 "ti,dp83867-rxctrl-strap-quirk");
560
561 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
562 "ti,sgmii-ref-clock-output-enable");
563
564 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
565 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
566 &dp83867->rx_id_delay);
567 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
568 phydev_err(phydev,
569 "ti,rx-internal-delay value of %u out of range\n",
570 dp83867->rx_id_delay);
571 return -EINVAL;
572 }
573
574 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
575 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
576 &dp83867->tx_id_delay);
577 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
578 phydev_err(phydev,
579 "ti,tx-internal-delay value of %u out of range\n",
580 dp83867->tx_id_delay);
581 return -EINVAL;
582 }
583
584 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
585 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
586
587 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
588 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
589
590 ret = of_property_read_u32(of_node, "ti,fifo-depth",
591 &dp83867->tx_fifo_depth);
592 if (ret) {
593 ret = of_property_read_u32(of_node, "tx-fifo-depth",
594 &dp83867->tx_fifo_depth);
595 if (ret)
596 dp83867->tx_fifo_depth =
597 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
598 }
599
600 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
601 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
602 dp83867->tx_fifo_depth);
603 return -EINVAL;
604 }
605
606 ret = of_property_read_u32(of_node, "rx-fifo-depth",
607 &dp83867->rx_fifo_depth);
608 if (ret)
609 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
610
611 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
612 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
613 dp83867->rx_fifo_depth);
614 return -EINVAL;
615 }
616
617 return 0;
618}
619#else
620static int dp83867_of_init(struct phy_device *phydev)
621{
622 return 0;
623}
624#endif /* CONFIG_OF_MDIO */
625
626static int dp83867_probe(struct phy_device *phydev)
627{
628 struct dp83867_private *dp83867;
629
630 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
631 GFP_KERNEL);
632 if (!dp83867)
633 return -ENOMEM;
634
635 phydev->priv = dp83867;
636
637 return dp83867_of_init(phydev);
638}
639
640static int dp83867_config_init(struct phy_device *phydev)
641{
642 struct dp83867_private *dp83867 = phydev->priv;
643 int ret, val, bs;
644 u16 delay;
645
646 /* Force speed optimization for the PHY even if it strapped */
647 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
648 DP83867_DOWNSHIFT_EN);
649 if (ret)
650 return ret;
651
652 ret = dp83867_verify_rgmii_cfg(phydev);
653 if (ret)
654 return ret;
655
656 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
657 if (dp83867->rxctrl_strap_quirk)
658 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
659 BIT(7));
660
661 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
662 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
663 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
664 * be set to 0x2. This may causes the PHY link to be unstable -
665 * the default value 0x1 need to be restored.
666 */
667 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
668 DP83867_FLD_THR_CFG,
669 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
670 0x1);
671 if (ret)
672 return ret;
673 }
674
675 if (phy_interface_is_rgmii(phydev) ||
676 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
677 val = phy_read(phydev, MII_DP83867_PHYCTRL);
678 if (val < 0)
679 return val;
680
681 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
682 val |= (dp83867->tx_fifo_depth <<
683 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
684
685 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
686 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
687 val |= (dp83867->rx_fifo_depth <<
688 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
689 }
690
691 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
692 if (ret)
693 return ret;
694 }
695
696 if (phy_interface_is_rgmii(phydev)) {
697 val = phy_read(phydev, MII_DP83867_PHYCTRL);
698 if (val < 0)
699 return val;
700
701 /* The code below checks if "port mirroring" N/A MODE4 has been
702 * enabled during power on bootstrap.
703 *
704 * Such N/A mode enabled by mistake can put PHY IC in some
705 * internal testing mode and disable RGMII transmission.
706 *
707 * In this particular case one needs to check STRAP_STS1
708 * register's bit 11 (marked as RESERVED).
709 */
710
711 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
712 if (bs & DP83867_STRAP_STS1_RESERVED)
713 val &= ~DP83867_PHYCR_RESERVED_MASK;
714
715 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
716 if (ret)
717 return ret;
718
719 /* If rgmii mode with no internal delay is selected, we do NOT use
720 * aligned mode as one might expect. Instead we use the PHY's default
721 * based on pin strapping. And the "mode 0" default is to *use*
722 * internal delay with a value of 7 (2.00 ns).
723 *
724 * Set up RGMII delays
725 */
726 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
727
728 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
729 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
730 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
731
732 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
733 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
734
735 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
736 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
737
738 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
739
740 delay = 0;
741 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
742 delay |= dp83867->rx_id_delay;
743 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
744 delay |= dp83867->tx_id_delay <<
745 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
746
747 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
748 delay);
749 }
750
751 /* If specified, set io impedance */
752 if (dp83867->io_impedance >= 0)
753 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
754 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
755 dp83867->io_impedance);
756
757 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
758 /* For support SPEED_10 in SGMII mode
759 * DP83867_10M_SGMII_RATE_ADAPT bit
760 * has to be cleared by software. That
761 * does not affect SPEED_100 and
762 * SPEED_1000.
763 */
764 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
765 DP83867_10M_SGMII_CFG,
766 DP83867_10M_SGMII_RATE_ADAPT_MASK,
767 0);
768 if (ret)
769 return ret;
770
771 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
772 * are 01). That is not enough to finalize autoneg on some
773 * devices. Increase this timer duration to maximum 16ms.
774 */
775 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
776 DP83867_CFG4,
777 DP83867_CFG4_SGMII_ANEG_MASK,
778 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
779
780 if (ret)
781 return ret;
782
783 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
784 /* SGMII type is set to 4-wire mode by default.
785 * If we place appropriate property in dts (see above)
786 * switch on 6-wire mode.
787 */
788 if (dp83867->sgmii_ref_clk_en)
789 val |= DP83867_SGMII_TYPE;
790 else
791 val &= ~DP83867_SGMII_TYPE;
792 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
793 }
794
795 val = phy_read(phydev, DP83867_CFG3);
796 /* Enable Interrupt output INT_OE in CFG3 register */
797 if (phy_interrupt_is_valid(phydev))
798 val |= DP83867_CFG3_INT_OE;
799
800 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
801 phy_write(phydev, DP83867_CFG3, val);
802
803 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
804 dp83867_config_port_mirroring(phydev);
805
806 /* Clock output selection if muxing property is set */
807 if (dp83867->set_clk_output) {
808 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
809
810 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
811 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
812 } else {
813 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
814 val = dp83867->clk_output_sel <<
815 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
816 }
817
818 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
819 mask, val);
820 }
821
822 return 0;
823}
824
825static int dp83867_phy_reset(struct phy_device *phydev)
826{
827 int err;
828
829 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
830 if (err < 0)
831 return err;
832
833 usleep_range(10, 20);
834
835 return phy_modify(phydev, MII_DP83867_PHYCTRL,
836 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
837}
838
839static struct phy_driver dp83867_driver[] = {
840 {
841 .phy_id = DP83867_PHY_ID,
842 .phy_id_mask = 0xfffffff0,
843 .name = "TI DP83867",
844 /* PHY_GBIT_FEATURES */
845
846 .probe = dp83867_probe,
847 .config_init = dp83867_config_init,
848 .soft_reset = dp83867_phy_reset,
849
850 .read_status = dp83867_read_status,
851 .get_tunable = dp83867_get_tunable,
852 .set_tunable = dp83867_set_tunable,
853
854 .get_wol = dp83867_get_wol,
855 .set_wol = dp83867_set_wol,
856
857 /* IRQ related */
858 .config_intr = dp83867_config_intr,
859 .handle_interrupt = dp83867_handle_interrupt,
860
861 .suspend = genphy_suspend,
862 .resume = genphy_resume,
863 },
864};
865module_phy_driver(dp83867_driver);
866
867static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
868 { DP83867_PHY_ID, 0xfffffff0 },
869 { }
870};
871
872MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
873
874MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
875MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
876MODULE_LICENSE("GPL v2");