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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2021 Linaro Ltd. */
4
5#include <linux/log2.h>
6
7#include "gsi.h"
8#include "ipa_data.h"
9#include "ipa_endpoint.h"
10#include "ipa_mem.h"
11
12/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */
13enum ipa_resource_type {
14 /* Source resource types; first must have value 0 */
15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20
21 /* Destination resource types; first must have value 0 */
22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
23 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24};
25
26/* Resource groups used for an SoC having IPA v4.5 */
27enum ipa_rsrc_group_id {
28 /* Source resource group identifiers */
29 IPA_RSRC_GROUP_SRC_UNUSED_0 = 0,
30 IPA_RSRC_GROUP_SRC_UL_DL,
31 IPA_RSRC_GROUP_SRC_UNUSED_2,
32 IPA_RSRC_GROUP_SRC_UNUSED_3,
33 IPA_RSRC_GROUP_SRC_UC_RX_Q,
34 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
35
36 /* Destination resource group identifiers */
37 IPA_RSRC_GROUP_DST_UNUSED_0 = 0,
38 IPA_RSRC_GROUP_DST_UL_DL_DPL,
39 IPA_RSRC_GROUP_DST_UNUSED_2,
40 IPA_RSRC_GROUP_DST_UNUSED_3,
41 IPA_RSRC_GROUP_DST_UC,
42 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
43};
44
45/* QSB configuration data for an SoC having IPA v4.5 */
46static const struct ipa_qsb_data ipa_qsb_data[] = {
47 [IPA_QSB_MASTER_DDR] = {
48 .max_writes = 8,
49 .max_reads = 0, /* no limit (hardware max) */
50 .max_reads_beats = 120,
51 },
52 [IPA_QSB_MASTER_PCIE] = {
53 .max_writes = 8,
54 .max_reads = 12,
55 /* no outstanding read byte (beat) limit */
56 },
57};
58
59/* Endpoint configuration data for an SoC having IPA v4.5 */
60static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
61 [IPA_ENDPOINT_AP_COMMAND_TX] = {
62 .ee_id = GSI_EE_AP,
63 .channel_id = 9,
64 .endpoint_id = 7,
65 .toward_ipa = true,
66 .channel = {
67 .tre_count = 256,
68 .event_count = 256,
69 .tlv_count = 20,
70 },
71 .endpoint = {
72 .config = {
73 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
74 .dma_mode = true,
75 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
76 .tx = {
77 .seq_type = IPA_SEQ_DMA,
78 },
79 },
80 },
81 },
82 [IPA_ENDPOINT_AP_LAN_RX] = {
83 .ee_id = GSI_EE_AP,
84 .channel_id = 10,
85 .endpoint_id = 16,
86 .toward_ipa = false,
87 .channel = {
88 .tre_count = 256,
89 .event_count = 256,
90 .tlv_count = 9,
91 },
92 .endpoint = {
93 .config = {
94 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
95 .aggregation = true,
96 .status_enable = true,
97 .rx = {
98 .pad_align = ilog2(sizeof(u32)),
99 },
100 },
101 },
102 },
103 [IPA_ENDPOINT_AP_MODEM_TX] = {
104 .ee_id = GSI_EE_AP,
105 .channel_id = 7,
106 .endpoint_id = 2,
107 .toward_ipa = true,
108 .channel = {
109 .tre_count = 512,
110 .event_count = 512,
111 .tlv_count = 16,
112 },
113 .endpoint = {
114 .filter_support = true,
115 .config = {
116 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
117 .qmap = true,
118 .status_enable = true,
119 .tx = {
120 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
121 .status_endpoint =
122 IPA_ENDPOINT_MODEM_AP_RX,
123 },
124 },
125 },
126 },
127 [IPA_ENDPOINT_AP_MODEM_RX] = {
128 .ee_id = GSI_EE_AP,
129 .channel_id = 1,
130 .endpoint_id = 14,
131 .toward_ipa = false,
132 .channel = {
133 .tre_count = 256,
134 .event_count = 256,
135 .tlv_count = 9,
136 },
137 .endpoint = {
138 .config = {
139 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
140 .qmap = true,
141 .aggregation = true,
142 .rx = {
143 .aggr_close_eof = true,
144 },
145 },
146 },
147 },
148 [IPA_ENDPOINT_MODEM_AP_TX] = {
149 .ee_id = GSI_EE_MODEM,
150 .channel_id = 0,
151 .endpoint_id = 5,
152 .toward_ipa = true,
153 .endpoint = {
154 .filter_support = true,
155 },
156 },
157 [IPA_ENDPOINT_MODEM_AP_RX] = {
158 .ee_id = GSI_EE_MODEM,
159 .channel_id = 7,
160 .endpoint_id = 21,
161 .toward_ipa = false,
162 },
163 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
164 .ee_id = GSI_EE_MODEM,
165 .channel_id = 2,
166 .endpoint_id = 8,
167 .toward_ipa = true,
168 .endpoint = {
169 .filter_support = true,
170 },
171 },
172};
173
174/* Source resource configuration data for an SoC having IPA v4.5 */
175static const struct ipa_resource ipa_resource_src[] = {
176 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
177 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
178 .min = 1, .max = 11,
179 },
180 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
181 .min = 1, .max = 63,
182 },
183 },
184 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
185 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
186 .min = 14, .max = 14,
187 },
188 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
189 .min = 3, .max = 3,
190 },
191 },
192 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
193 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
194 .min = 18, .max = 18,
195 },
196 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
197 .min = 8, .max = 8,
198 },
199 },
200 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
201 .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = {
202 .min = 0, .max = 63,
203 },
204 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
205 .min = 0, .max = 63,
206 },
207 .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = {
208 .min = 0, .max = 63,
209 },
210 .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = {
211 .min = 0, .max = 63,
212 },
213 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
214 .min = 0, .max = 63,
215 },
216 },
217 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
218 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
219 .min = 24, .max = 24,
220 },
221 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
222 .min = 8, .max = 8,
223 },
224 },
225};
226
227/* Destination resource configuration data for an SoC having IPA v4.5 */
228static const struct ipa_resource ipa_resource_dst[] = {
229 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
230 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
231 .min = 16, .max = 16,
232 },
233 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
234 .min = 2, .max = 2,
235 },
236 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
237 .min = 2, .max = 2,
238 },
239 },
240 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
241 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
242 .min = 2, .max = 63,
243 },
244 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
245 .min = 1, .max = 2,
246 },
247 .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
248 .min = 1, .max = 2,
249 },
250 .limits[IPA_RSRC_GROUP_DST_UC] = {
251 .min = 0, .max = 2,
252 },
253 },
254};
255
256/* Resource configuration data for an SoC having IPA v4.5 */
257static const struct ipa_resource_data ipa_resource_data = {
258 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
259 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
260 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
261 .resource_src = ipa_resource_src,
262 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
263 .resource_dst = ipa_resource_dst,
264};
265
266/* IPA-resident memory region data for an SoC having IPA v4.5 */
267static const struct ipa_mem ipa_mem_local_data[] = {
268 {
269 .id = IPA_MEM_UC_SHARED,
270 .offset = 0x0000,
271 .size = 0x0080,
272 .canary_count = 0,
273 },
274 {
275 .id = IPA_MEM_UC_INFO,
276 .offset = 0x0080,
277 .size = 0x0200,
278 .canary_count = 0,
279 },
280 {
281 .id = IPA_MEM_V4_FILTER_HASHED,
282 .offset = 0x0288,
283 .size = 0x0078,
284 .canary_count = 2,
285 },
286 {
287 .id = IPA_MEM_V4_FILTER,
288 .offset = 0x0308,
289 .size = 0x0078,
290 .canary_count = 2,
291 },
292 {
293 .id = IPA_MEM_V6_FILTER_HASHED,
294 .offset = 0x0388,
295 .size = 0x0078,
296 .canary_count = 2,
297 },
298 {
299 .id = IPA_MEM_V6_FILTER,
300 .offset = 0x0408,
301 .size = 0x0078,
302 .canary_count = 2,
303 },
304 {
305 .id = IPA_MEM_V4_ROUTE_HASHED,
306 .offset = 0x0488,
307 .size = 0x0078,
308 .canary_count = 2,
309 },
310 {
311 .id = IPA_MEM_V4_ROUTE,
312 .offset = 0x0508,
313 .size = 0x0078,
314 .canary_count = 2,
315 },
316 {
317 .id = IPA_MEM_V6_ROUTE_HASHED,
318 .offset = 0x0588,
319 .size = 0x0078,
320 .canary_count = 2,
321 },
322 {
323 .id = IPA_MEM_V6_ROUTE,
324 .offset = 0x0608,
325 .size = 0x0078,
326 .canary_count = 2,
327 },
328 {
329 .id = IPA_MEM_MODEM_HEADER,
330 .offset = 0x0688,
331 .size = 0x0240,
332 .canary_count = 2,
333 },
334 {
335 .id = IPA_MEM_AP_HEADER,
336 .offset = 0x08c8,
337 .size = 0x0200,
338 .canary_count = 0,
339 },
340 {
341 .id = IPA_MEM_MODEM_PROC_CTX,
342 .offset = 0x0ad0,
343 .size = 0x0b20,
344 .canary_count = 2,
345 },
346 {
347 .id = IPA_MEM_AP_PROC_CTX,
348 .offset = 0x15f0,
349 .size = 0x0200,
350 .canary_count = 0,
351 },
352 {
353 .id = IPA_MEM_NAT_TABLE,
354 .offset = 0x1800,
355 .size = 0x0d00,
356 .canary_count = 4,
357 },
358 {
359 .id = IPA_MEM_STATS_QUOTA_MODEM,
360 .offset = 0x2510,
361 .size = 0x0030,
362 .canary_count = 4,
363 },
364 {
365 .id = IPA_MEM_STATS_QUOTA_AP,
366 .offset = 0x2540,
367 .size = 0x0048,
368 .canary_count = 0,
369 },
370 {
371 .id = IPA_MEM_STATS_TETHERING,
372 .offset = 0x2588,
373 .size = 0x0238,
374 .canary_count = 0,
375 },
376 {
377 .id = IPA_MEM_STATS_FILTER_ROUTE,
378 .offset = 0x27c0,
379 .size = 0x0800,
380 .canary_count = 0,
381 },
382 {
383 .id = IPA_MEM_STATS_DROP,
384 .offset = 0x2fc0,
385 .size = 0x0020,
386 .canary_count = 0,
387 },
388 {
389 .id = IPA_MEM_MODEM,
390 .offset = 0x2fe8,
391 .size = 0x0800,
392 .canary_count = 2,
393 },
394 {
395 .id = IPA_MEM_UC_EVENT_RING,
396 .offset = 0x3800,
397 .size = 0x1000,
398 .canary_count = 1,
399 },
400 {
401 .id = IPA_MEM_PDN_CONFIG,
402 .offset = 0x4800,
403 .size = 0x0050,
404 .canary_count = 0,
405 },
406};
407
408/* Memory configuration data for an SoC having IPA v4.5 */
409static const struct ipa_mem_data ipa_mem_data = {
410 .local_count = ARRAY_SIZE(ipa_mem_local_data),
411 .local = ipa_mem_local_data,
412 .imem_addr = 0x14688000,
413 .imem_size = 0x00003000,
414 .smem_id = 497,
415 .smem_size = 0x00009000,
416};
417
418/* Interconnect rates are in 1000 byte/second units */
419static const struct ipa_interconnect_data ipa_interconnect_data[] = {
420 {
421 .name = "memory-a",
422 .peak_bandwidth = 600000, /* 600 MBps */
423 .average_bandwidth = 150000, /* 150 MBps */
424 },
425 {
426 .name = "memory-b",
427 .peak_bandwidth = 1804000, /* 1.804 GBps */
428 .average_bandwidth = 150000, /* 150 MBps */
429 },
430 /* Average rate is unused for the next two interconnects */
431 {
432 .name = "imem",
433 .peak_bandwidth = 450000, /* 450 MBps */
434 .average_bandwidth = 75000, /* 75 MBps (unused?) */
435 },
436 {
437 .name = "config",
438 .peak_bandwidth = 171400, /* 171.4 MBps */
439 .average_bandwidth = 0, /* unused */
440 },
441};
442
443/* Clock and interconnect configuration data for an SoC having IPA v4.5 */
444static const struct ipa_clock_data ipa_clock_data = {
445 .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */
446 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
447 .interconnect_data = ipa_interconnect_data,
448};
449
450/* Configuration data for an SoC having IPA v4.5 */
451const struct ipa_data ipa_data_v4_5 = {
452 .version = IPA_VERSION_4_5,
453 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
454 .qsb_data = ipa_qsb_data,
455 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
456 .endpoint_data = ipa_gsi_endpoint_data,
457 .resource_data = &ipa_resource_data,
458 .mem_data = &ipa_mem_data,
459 .clock_data = &ipa_clock_data,
460};