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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
4 */
5
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <linux/delay.h>
9#include <linux/module.h>
10#include <linux/printk.h>
11#include <linux/spi/spi.h>
12#include <linux/errno.h>
13#include <linux/gpio/consumer.h>
14#include <linux/phylink.h>
15#include <linux/of.h>
16#include <linux/of_net.h>
17#include <linux/of_mdio.h>
18#include <linux/netdev_features.h>
19#include <linux/netdevice.h>
20#include <linux/if_bridge.h>
21#include <linux/if_ether.h>
22#include <linux/dsa/8021q.h>
23#include <linux/units.h>
24
25#include "sja1105.h"
26#include "sja1105_tas.h"
27
28#define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
29
30/* Configure the optional reset pin and bring up switch */
31static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
32 unsigned int startup_delay)
33{
34 struct gpio_desc *gpio;
35
36 gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
37 if (IS_ERR(gpio))
38 return PTR_ERR(gpio);
39
40 if (!gpio)
41 return 0;
42
43 gpiod_set_value_cansleep(gpio, 1);
44 /* Wait for minimum reset pulse length */
45 msleep(pulse_len);
46 gpiod_set_value_cansleep(gpio, 0);
47 /* Wait until chip is ready after reset */
48 msleep(startup_delay);
49
50 gpiod_put(gpio);
51
52 return 0;
53}
54
55static void
56sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
57 int from, int to, bool allow)
58{
59 if (allow)
60 l2_fwd[from].reach_port |= BIT(to);
61 else
62 l2_fwd[from].reach_port &= ~BIT(to);
63}
64
65static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
66 int from, int to)
67{
68 return !!(l2_fwd[from].reach_port & BIT(to));
69}
70
71static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
72{
73 struct sja1105_vlan_lookup_entry *vlan;
74 int count, i;
75
76 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
77 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
78
79 for (i = 0; i < count; i++)
80 if (vlan[i].vlanid == vid)
81 return i;
82
83 /* Return an invalid entry index if not found */
84 return -1;
85}
86
87static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
88{
89 struct sja1105_private *priv = ds->priv;
90 struct sja1105_mac_config_entry *mac;
91
92 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
93
94 if (mac[port].drpuntag == drop)
95 return 0;
96
97 mac[port].drpuntag = drop;
98
99 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
100 &mac[port], true);
101}
102
103static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
104{
105 struct sja1105_mac_config_entry *mac;
106
107 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
108
109 if (mac[port].vlanid == pvid)
110 return 0;
111
112 mac[port].vlanid = pvid;
113
114 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
115 &mac[port], true);
116}
117
118static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
119{
120 struct dsa_port *dp = dsa_to_port(ds, port);
121 struct net_device *br = dsa_port_bridge_dev_get(dp);
122 struct sja1105_private *priv = ds->priv;
123 struct sja1105_vlan_lookup_entry *vlan;
124 bool drop_untagged = false;
125 int match, rc;
126 u16 pvid;
127
128 if (br && br_vlan_enabled(br))
129 pvid = priv->bridge_pvid[port];
130 else
131 pvid = priv->tag_8021q_pvid[port];
132
133 rc = sja1105_pvid_apply(priv, port, pvid);
134 if (rc)
135 return rc;
136
137 /* Only force dropping of untagged packets when the port is under a
138 * VLAN-aware bridge. When the tag_8021q pvid is used, we are
139 * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
140 * to prevent DSA tag spoofing from the link partner. Untagged packets
141 * are the only ones that should be received with tag_8021q, so
142 * definitely don't drop them.
143 */
144 if (pvid == priv->bridge_pvid[port]) {
145 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
146
147 match = sja1105_is_vlan_configured(priv, pvid);
148
149 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
150 drop_untagged = true;
151 }
152
153 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
154 drop_untagged = true;
155
156 return sja1105_drop_untagged(ds, port, drop_untagged);
157}
158
159static int sja1105_init_mac_settings(struct sja1105_private *priv)
160{
161 struct sja1105_mac_config_entry default_mac = {
162 /* Enable all 8 priority queues on egress.
163 * Every queue i holds top[i] - base[i] frames.
164 * Sum of top[i] - base[i] is 511 (max hardware limit).
165 */
166 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
167 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
168 .enabled = {true, true, true, true, true, true, true, true},
169 /* Keep standard IFG of 12 bytes on egress. */
170 .ifg = 0,
171 /* Always put the MAC speed in automatic mode, where it can be
172 * adjusted at runtime by PHYLINK.
173 */
174 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
175 /* No static correction for 1-step 1588 events */
176 .tp_delin = 0,
177 .tp_delout = 0,
178 /* Disable aging for critical TTEthernet traffic */
179 .maxage = 0xFF,
180 /* Internal VLAN (pvid) to apply to untagged ingress */
181 .vlanprio = 0,
182 .vlanid = 1,
183 .ing_mirr = false,
184 .egr_mirr = false,
185 /* Don't drop traffic with other EtherType than ETH_P_IP */
186 .drpnona664 = false,
187 /* Don't drop double-tagged traffic */
188 .drpdtag = false,
189 /* Don't drop untagged traffic */
190 .drpuntag = false,
191 /* Don't retag 802.1p (VID 0) traffic with the pvid */
192 .retag = false,
193 /* Disable learning and I/O on user ports by default -
194 * STP will enable it.
195 */
196 .dyn_learn = false,
197 .egress = false,
198 .ingress = false,
199 };
200 struct sja1105_mac_config_entry *mac;
201 struct dsa_switch *ds = priv->ds;
202 struct sja1105_table *table;
203 struct dsa_port *dp;
204
205 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
206
207 /* Discard previous MAC Configuration Table */
208 if (table->entry_count) {
209 kfree(table->entries);
210 table->entry_count = 0;
211 }
212
213 table->entries = kcalloc(table->ops->max_entry_count,
214 table->ops->unpacked_entry_size, GFP_KERNEL);
215 if (!table->entries)
216 return -ENOMEM;
217
218 table->entry_count = table->ops->max_entry_count;
219
220 mac = table->entries;
221
222 list_for_each_entry(dp, &ds->dst->ports, list) {
223 if (dp->ds != ds)
224 continue;
225
226 mac[dp->index] = default_mac;
227
228 /* Let sja1105_bridge_stp_state_set() keep address learning
229 * enabled for the DSA ports. CPU ports use software-assisted
230 * learning to ensure that only FDB entries belonging to the
231 * bridge are learned, and that they are learned towards all
232 * CPU ports in a cross-chip topology if multiple CPU ports
233 * exist.
234 */
235 if (dsa_port_is_dsa(dp))
236 dp->learning = true;
237
238 /* Disallow untagged packets from being received on the
239 * CPU and DSA ports.
240 */
241 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
242 mac[dp->index].drpuntag = true;
243 }
244
245 return 0;
246}
247
248static int sja1105_init_mii_settings(struct sja1105_private *priv)
249{
250 struct device *dev = &priv->spidev->dev;
251 struct sja1105_xmii_params_entry *mii;
252 struct dsa_switch *ds = priv->ds;
253 struct sja1105_table *table;
254 int i;
255
256 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
257
258 /* Discard previous xMII Mode Parameters Table */
259 if (table->entry_count) {
260 kfree(table->entries);
261 table->entry_count = 0;
262 }
263
264 table->entries = kcalloc(table->ops->max_entry_count,
265 table->ops->unpacked_entry_size, GFP_KERNEL);
266 if (!table->entries)
267 return -ENOMEM;
268
269 /* Override table based on PHYLINK DT bindings */
270 table->entry_count = table->ops->max_entry_count;
271
272 mii = table->entries;
273
274 for (i = 0; i < ds->num_ports; i++) {
275 sja1105_mii_role_t role = XMII_MAC;
276
277 if (dsa_is_unused_port(priv->ds, i))
278 continue;
279
280 switch (priv->phy_mode[i]) {
281 case PHY_INTERFACE_MODE_INTERNAL:
282 if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
283 goto unsupported;
284
285 mii->xmii_mode[i] = XMII_MODE_MII;
286 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
287 mii->special[i] = true;
288
289 break;
290 case PHY_INTERFACE_MODE_REVMII:
291 role = XMII_PHY;
292 fallthrough;
293 case PHY_INTERFACE_MODE_MII:
294 if (!priv->info->supports_mii[i])
295 goto unsupported;
296
297 mii->xmii_mode[i] = XMII_MODE_MII;
298 break;
299 case PHY_INTERFACE_MODE_REVRMII:
300 role = XMII_PHY;
301 fallthrough;
302 case PHY_INTERFACE_MODE_RMII:
303 if (!priv->info->supports_rmii[i])
304 goto unsupported;
305
306 mii->xmii_mode[i] = XMII_MODE_RMII;
307 break;
308 case PHY_INTERFACE_MODE_RGMII:
309 case PHY_INTERFACE_MODE_RGMII_ID:
310 case PHY_INTERFACE_MODE_RGMII_RXID:
311 case PHY_INTERFACE_MODE_RGMII_TXID:
312 if (!priv->info->supports_rgmii[i])
313 goto unsupported;
314
315 mii->xmii_mode[i] = XMII_MODE_RGMII;
316 break;
317 case PHY_INTERFACE_MODE_SGMII:
318 if (!priv->info->supports_sgmii[i])
319 goto unsupported;
320
321 mii->xmii_mode[i] = XMII_MODE_SGMII;
322 mii->special[i] = true;
323 break;
324 case PHY_INTERFACE_MODE_2500BASEX:
325 if (!priv->info->supports_2500basex[i])
326 goto unsupported;
327
328 mii->xmii_mode[i] = XMII_MODE_SGMII;
329 mii->special[i] = true;
330 break;
331unsupported:
332 default:
333 dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
334 phy_modes(priv->phy_mode[i]), i);
335 return -EINVAL;
336 }
337
338 mii->phy_mac[i] = role;
339 }
340 return 0;
341}
342
343static int sja1105_init_static_fdb(struct sja1105_private *priv)
344{
345 struct sja1105_l2_lookup_entry *l2_lookup;
346 struct sja1105_table *table;
347 int port;
348
349 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
350
351 /* We only populate the FDB table through dynamic L2 Address Lookup
352 * entries, except for a special entry at the end which is a catch-all
353 * for unknown multicast and will be used to control flooding domain.
354 */
355 if (table->entry_count) {
356 kfree(table->entries);
357 table->entry_count = 0;
358 }
359
360 if (!priv->info->can_limit_mcast_flood)
361 return 0;
362
363 table->entries = kcalloc(1, table->ops->unpacked_entry_size,
364 GFP_KERNEL);
365 if (!table->entries)
366 return -ENOMEM;
367
368 table->entry_count = 1;
369 l2_lookup = table->entries;
370
371 /* All L2 multicast addresses have an odd first octet */
372 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
373 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
374 l2_lookup[0].lockeds = true;
375 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
376
377 /* Flood multicast to every port by default */
378 for (port = 0; port < priv->ds->num_ports; port++)
379 if (!dsa_is_unused_port(priv->ds, port))
380 l2_lookup[0].destports |= BIT(port);
381
382 return 0;
383}
384
385static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
386{
387 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
388 /* Learned FDB entries are forgotten after 300 seconds */
389 .maxage = SJA1105_AGEING_TIME_MS(300000),
390 /* All entries within a FDB bin are available for learning */
391 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
392 /* And the P/Q/R/S equivalent setting: */
393 .start_dynspc = 0,
394 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
395 .poly = 0x97,
396 /* Always use Independent VLAN Learning (IVL) */
397 .shared_learn = false,
398 /* Don't discard management traffic based on ENFPORT -
399 * we don't perform SMAC port enforcement anyway, so
400 * what we are setting here doesn't matter.
401 */
402 .no_enf_hostprt = false,
403 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
404 * Maybe correlate with no_linklocal_learn from bridge driver?
405 */
406 .no_mgmt_learn = true,
407 /* P/Q/R/S only */
408 .use_static = true,
409 /* Dynamically learned FDB entries can overwrite other (older)
410 * dynamic FDB entries
411 */
412 .owr_dyn = true,
413 .drpnolearn = true,
414 };
415 struct dsa_switch *ds = priv->ds;
416 int port, num_used_ports = 0;
417 struct sja1105_table *table;
418 u64 max_fdb_entries;
419
420 for (port = 0; port < ds->num_ports; port++)
421 if (!dsa_is_unused_port(ds, port))
422 num_used_ports++;
423
424 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
425
426 for (port = 0; port < ds->num_ports; port++) {
427 if (dsa_is_unused_port(ds, port))
428 continue;
429
430 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
431 }
432
433 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
434
435 if (table->entry_count) {
436 kfree(table->entries);
437 table->entry_count = 0;
438 }
439
440 table->entries = kcalloc(table->ops->max_entry_count,
441 table->ops->unpacked_entry_size, GFP_KERNEL);
442 if (!table->entries)
443 return -ENOMEM;
444
445 table->entry_count = table->ops->max_entry_count;
446
447 /* This table only has a single entry */
448 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
449 default_l2_lookup_params;
450
451 return 0;
452}
453
454/* Set up a default VLAN for untagged traffic injected from the CPU
455 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
456 * All DT-defined ports are members of this VLAN, and there are no
457 * restrictions on forwarding (since the CPU selects the destination).
458 * Frames from this VLAN will always be transmitted as untagged, and
459 * neither the bridge nor the 8021q module cannot create this VLAN ID.
460 */
461static int sja1105_init_static_vlan(struct sja1105_private *priv)
462{
463 struct sja1105_table *table;
464 struct sja1105_vlan_lookup_entry pvid = {
465 .type_entry = SJA1110_VLAN_D_TAG,
466 .ving_mirr = 0,
467 .vegr_mirr = 0,
468 .vmemb_port = 0,
469 .vlan_bc = 0,
470 .tag_port = 0,
471 .vlanid = SJA1105_DEFAULT_VLAN,
472 };
473 struct dsa_switch *ds = priv->ds;
474 int port;
475
476 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
477
478 if (table->entry_count) {
479 kfree(table->entries);
480 table->entry_count = 0;
481 }
482
483 table->entries = kzalloc(table->ops->unpacked_entry_size,
484 GFP_KERNEL);
485 if (!table->entries)
486 return -ENOMEM;
487
488 table->entry_count = 1;
489
490 for (port = 0; port < ds->num_ports; port++) {
491 if (dsa_is_unused_port(ds, port))
492 continue;
493
494 pvid.vmemb_port |= BIT(port);
495 pvid.vlan_bc |= BIT(port);
496 pvid.tag_port &= ~BIT(port);
497
498 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
499 priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
500 priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
501 }
502 }
503
504 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
505 return 0;
506}
507
508static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
509{
510 struct sja1105_l2_forwarding_entry *l2fwd;
511 struct dsa_switch *ds = priv->ds;
512 struct dsa_switch_tree *dst;
513 struct sja1105_table *table;
514 struct dsa_link *dl;
515 int port, tc;
516 int from, to;
517
518 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
519
520 if (table->entry_count) {
521 kfree(table->entries);
522 table->entry_count = 0;
523 }
524
525 table->entries = kcalloc(table->ops->max_entry_count,
526 table->ops->unpacked_entry_size, GFP_KERNEL);
527 if (!table->entries)
528 return -ENOMEM;
529
530 table->entry_count = table->ops->max_entry_count;
531
532 l2fwd = table->entries;
533
534 /* First 5 entries in the L2 Forwarding Table define the forwarding
535 * rules and the VLAN PCP to ingress queue mapping.
536 * Set up the ingress queue mapping first.
537 */
538 for (port = 0; port < ds->num_ports; port++) {
539 if (dsa_is_unused_port(ds, port))
540 continue;
541
542 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
543 l2fwd[port].vlan_pmap[tc] = tc;
544 }
545
546 /* Then manage the forwarding domain for user ports. These can forward
547 * only to the always-on domain (CPU port and DSA links)
548 */
549 for (from = 0; from < ds->num_ports; from++) {
550 if (!dsa_is_user_port(ds, from))
551 continue;
552
553 for (to = 0; to < ds->num_ports; to++) {
554 if (!dsa_is_cpu_port(ds, to) &&
555 !dsa_is_dsa_port(ds, to))
556 continue;
557
558 l2fwd[from].bc_domain |= BIT(to);
559 l2fwd[from].fl_domain |= BIT(to);
560
561 sja1105_port_allow_traffic(l2fwd, from, to, true);
562 }
563 }
564
565 /* Then manage the forwarding domain for DSA links and CPU ports (the
566 * always-on domain). These can send packets to any enabled port except
567 * themselves.
568 */
569 for (from = 0; from < ds->num_ports; from++) {
570 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
571 continue;
572
573 for (to = 0; to < ds->num_ports; to++) {
574 if (dsa_is_unused_port(ds, to))
575 continue;
576
577 if (from == to)
578 continue;
579
580 l2fwd[from].bc_domain |= BIT(to);
581 l2fwd[from].fl_domain |= BIT(to);
582
583 sja1105_port_allow_traffic(l2fwd, from, to, true);
584 }
585 }
586
587 /* In odd topologies ("H" connections where there is a DSA link to
588 * another switch which also has its own CPU port), TX packets can loop
589 * back into the system (they are flooded from CPU port 1 to the DSA
590 * link, and from there to CPU port 2). Prevent this from happening by
591 * cutting RX from DSA links towards our CPU port, if the remote switch
592 * has its own CPU port and therefore doesn't need ours for network
593 * stack termination.
594 */
595 dst = ds->dst;
596
597 list_for_each_entry(dl, &dst->rtable, list) {
598 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
599 continue;
600
601 from = dl->dp->index;
602 to = dsa_upstream_port(ds, from);
603
604 dev_warn(ds->dev,
605 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
606 from, to);
607
608 sja1105_port_allow_traffic(l2fwd, from, to, false);
609
610 l2fwd[from].bc_domain &= ~BIT(to);
611 l2fwd[from].fl_domain &= ~BIT(to);
612 }
613
614 /* Finally, manage the egress flooding domain. All ports start up with
615 * flooding enabled, including the CPU port and DSA links.
616 */
617 for (port = 0; port < ds->num_ports; port++) {
618 if (dsa_is_unused_port(ds, port))
619 continue;
620
621 priv->ucast_egress_floods |= BIT(port);
622 priv->bcast_egress_floods |= BIT(port);
623 }
624
625 /* Next 8 entries define VLAN PCP mapping from ingress to egress.
626 * Create a one-to-one mapping.
627 */
628 for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
629 for (port = 0; port < ds->num_ports; port++) {
630 if (dsa_is_unused_port(ds, port))
631 continue;
632
633 l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
634 }
635
636 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
637 }
638
639 return 0;
640}
641
642static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
643{
644 struct sja1110_pcp_remapping_entry *pcp_remap;
645 struct dsa_switch *ds = priv->ds;
646 struct sja1105_table *table;
647 int port, tc;
648
649 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
650
651 /* Nothing to do for SJA1105 */
652 if (!table->ops->max_entry_count)
653 return 0;
654
655 if (table->entry_count) {
656 kfree(table->entries);
657 table->entry_count = 0;
658 }
659
660 table->entries = kcalloc(table->ops->max_entry_count,
661 table->ops->unpacked_entry_size, GFP_KERNEL);
662 if (!table->entries)
663 return -ENOMEM;
664
665 table->entry_count = table->ops->max_entry_count;
666
667 pcp_remap = table->entries;
668
669 /* Repeat the configuration done for vlan_pmap */
670 for (port = 0; port < ds->num_ports; port++) {
671 if (dsa_is_unused_port(ds, port))
672 continue;
673
674 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
675 pcp_remap[port].egrpcp[tc] = tc;
676 }
677
678 return 0;
679}
680
681static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
682{
683 struct sja1105_l2_forwarding_params_entry *l2fwd_params;
684 struct sja1105_table *table;
685
686 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
687
688 if (table->entry_count) {
689 kfree(table->entries);
690 table->entry_count = 0;
691 }
692
693 table->entries = kcalloc(table->ops->max_entry_count,
694 table->ops->unpacked_entry_size, GFP_KERNEL);
695 if (!table->entries)
696 return -ENOMEM;
697
698 table->entry_count = table->ops->max_entry_count;
699
700 /* This table only has a single entry */
701 l2fwd_params = table->entries;
702
703 /* Disallow dynamic reconfiguration of vlan_pmap */
704 l2fwd_params->max_dynp = 0;
705 /* Use a single memory partition for all ingress queues */
706 l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
707
708 return 0;
709}
710
711void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
712{
713 struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
714 struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
715 struct sja1105_table *table;
716
717 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
718 l2_fwd_params = table->entries;
719 l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
720
721 /* If we have any critical-traffic virtual links, we need to reserve
722 * some frame buffer memory for them. At the moment, hardcode the value
723 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
724 * remaining for best-effort traffic. TODO: figure out a more flexible
725 * way to perform the frame buffer partitioning.
726 */
727 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
728 return;
729
730 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
731 vl_fwd_params = table->entries;
732
733 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
734 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
735}
736
737/* SJA1110 TDMACONFIGIDX values:
738 *
739 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports
740 * -----+----------------+---------------+---------------+---------------
741 * 0 | 0, [5:10] | [1:2] | [3:4] | retag
742 * 1 |0, [5:10], retag| [1:2] | [3:4] | -
743 * 2 | 0, [5:10] | [1:3], retag | 4 | -
744 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -
745 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -
746 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -
747 * 14 | 0, [5:10] | [1:4], retag | - | -
748 * 15 | [5:10] | [0:4], retag | - | -
749 */
750static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
751{
752 struct sja1105_general_params_entry *general_params;
753 struct sja1105_table *table;
754 bool port_1_is_base_tx;
755 bool port_3_is_2500;
756 bool port_4_is_2500;
757 u64 tdmaconfigidx;
758
759 if (priv->info->device_id != SJA1110_DEVICE_ID)
760 return;
761
762 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
763 general_params = table->entries;
764
765 /* All the settings below are "as opposed to SGMII", which is the
766 * other pinmuxing option.
767 */
768 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
769 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
770 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
771
772 if (port_1_is_base_tx)
773 /* Retagging port will operate at 1 Gbps */
774 tdmaconfigidx = 5;
775 else if (port_3_is_2500 && port_4_is_2500)
776 /* Retagging port will operate at 100 Mbps */
777 tdmaconfigidx = 1;
778 else if (port_3_is_2500)
779 /* Retagging port will operate at 1 Gbps */
780 tdmaconfigidx = 3;
781 else if (port_4_is_2500)
782 /* Retagging port will operate at 1 Gbps */
783 tdmaconfigidx = 2;
784 else
785 /* Retagging port will operate at 1 Gbps */
786 tdmaconfigidx = 14;
787
788 general_params->tdmaconfigidx = tdmaconfigidx;
789}
790
791static int sja1105_init_topology(struct sja1105_private *priv,
792 struct sja1105_general_params_entry *general_params)
793{
794 struct dsa_switch *ds = priv->ds;
795 int port;
796
797 /* The host port is the destination for traffic matching mac_fltres1
798 * and mac_fltres0 on all ports except itself. Default to an invalid
799 * value.
800 */
801 general_params->host_port = ds->num_ports;
802
803 /* Link-local traffic received on casc_port will be forwarded
804 * to host_port without embedding the source port and device ID
805 * info in the destination MAC address, and no RX timestamps will be
806 * taken either (presumably because it is a cascaded port and a
807 * downstream SJA switch already did that).
808 * To disable the feature, we need to do different things depending on
809 * switch generation. On SJA1105 we need to set an invalid port, while
810 * on SJA1110 which support multiple cascaded ports, this field is a
811 * bitmask so it must be left zero.
812 */
813 if (!priv->info->multiple_cascade_ports)
814 general_params->casc_port = ds->num_ports;
815
816 for (port = 0; port < ds->num_ports; port++) {
817 bool is_upstream = dsa_is_upstream_port(ds, port);
818 bool is_dsa_link = dsa_is_dsa_port(ds, port);
819
820 /* Upstream ports can be dedicated CPU ports or
821 * upstream-facing DSA links
822 */
823 if (is_upstream) {
824 if (general_params->host_port == ds->num_ports) {
825 general_params->host_port = port;
826 } else {
827 dev_err(ds->dev,
828 "Port %llu is already a host port, configuring %d as one too is not supported\n",
829 general_params->host_port, port);
830 return -EINVAL;
831 }
832 }
833
834 /* Cascade ports are downstream-facing DSA links */
835 if (is_dsa_link && !is_upstream) {
836 if (priv->info->multiple_cascade_ports) {
837 general_params->casc_port |= BIT(port);
838 } else if (general_params->casc_port == ds->num_ports) {
839 general_params->casc_port = port;
840 } else {
841 dev_err(ds->dev,
842 "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
843 general_params->casc_port, port);
844 return -EINVAL;
845 }
846 }
847 }
848
849 if (general_params->host_port == ds->num_ports) {
850 dev_err(ds->dev, "No host port configured\n");
851 return -EINVAL;
852 }
853
854 return 0;
855}
856
857static int sja1105_init_general_params(struct sja1105_private *priv)
858{
859 struct sja1105_general_params_entry default_general_params = {
860 /* Allow dynamic changing of the mirror port */
861 .mirr_ptacu = true,
862 .switchid = priv->ds->index,
863 /* Priority queue for link-local management frames
864 * (both ingress to and egress from CPU - PTP, STP etc)
865 */
866 .hostprio = 7,
867 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
868 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK,
869 .incl_srcpt1 = true,
870 .send_meta1 = true,
871 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
872 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK,
873 .incl_srcpt0 = true,
874 .send_meta0 = true,
875 /* Default to an invalid value */
876 .mirr_port = priv->ds->num_ports,
877 /* No TTEthernet */
878 .vllupformat = SJA1105_VL_FORMAT_PSFP,
879 .vlmarker = 0,
880 .vlmask = 0,
881 /* Only update correctionField for 1-step PTP (L2 transport) */
882 .ignore2stf = 0,
883 /* Forcefully disable VLAN filtering by telling
884 * the switch that VLAN has a different EtherType.
885 */
886 .tpid = ETH_P_SJA1105,
887 .tpid2 = ETH_P_SJA1105,
888 /* Enable the TTEthernet engine on SJA1110 */
889 .tte_en = true,
890 /* Set up the EtherType for control packets on SJA1110 */
891 .header_type = ETH_P_SJA1110,
892 };
893 struct sja1105_general_params_entry *general_params;
894 struct sja1105_table *table;
895 int rc;
896
897 rc = sja1105_init_topology(priv, &default_general_params);
898 if (rc)
899 return rc;
900
901 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
902
903 if (table->entry_count) {
904 kfree(table->entries);
905 table->entry_count = 0;
906 }
907
908 table->entries = kcalloc(table->ops->max_entry_count,
909 table->ops->unpacked_entry_size, GFP_KERNEL);
910 if (!table->entries)
911 return -ENOMEM;
912
913 table->entry_count = table->ops->max_entry_count;
914
915 general_params = table->entries;
916
917 /* This table only has a single entry */
918 general_params[0] = default_general_params;
919
920 sja1110_select_tdmaconfigidx(priv);
921
922 return 0;
923}
924
925static int sja1105_init_avb_params(struct sja1105_private *priv)
926{
927 struct sja1105_avb_params_entry *avb;
928 struct sja1105_table *table;
929
930 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
931
932 /* Discard previous AVB Parameters Table */
933 if (table->entry_count) {
934 kfree(table->entries);
935 table->entry_count = 0;
936 }
937
938 table->entries = kcalloc(table->ops->max_entry_count,
939 table->ops->unpacked_entry_size, GFP_KERNEL);
940 if (!table->entries)
941 return -ENOMEM;
942
943 table->entry_count = table->ops->max_entry_count;
944
945 avb = table->entries;
946
947 /* Configure the MAC addresses for meta frames */
948 avb->destmeta = SJA1105_META_DMAC;
949 avb->srcmeta = SJA1105_META_SMAC;
950 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
951 * default. This is because there might be boards with a hardware
952 * layout where enabling the pin as output might cause an electrical
953 * clash. On E/T the pin is always an output, which the board designers
954 * probably already knew, so even if there are going to be electrical
955 * issues, there's nothing we can do.
956 */
957 avb->cas_master = false;
958
959 return 0;
960}
961
962/* The L2 policing table is 2-stage. The table is looked up for each frame
963 * according to the ingress port, whether it was broadcast or not, and the
964 * classified traffic class (given by VLAN PCP). This portion of the lookup is
965 * fixed, and gives access to the SHARINDX, an indirection register pointing
966 * within the policing table itself, which is used to resolve the policer that
967 * will be used for this frame.
968 *
969 * Stage 1 Stage 2
970 * +------------+--------+ +---------------------------------+
971 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |
972 * +------------+--------+ +---------------------------------+
973 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |
974 * +------------+--------+ +---------------------------------+
975 * ... | Policer 2: Rate, Burst, MTU |
976 * +------------+--------+ +---------------------------------+
977 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |
978 * +------------+--------+ +---------------------------------+
979 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |
980 * +------------+--------+ +---------------------------------+
981 * ... | Policer 5: Rate, Burst, MTU |
982 * +------------+--------+ +---------------------------------+
983 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |
984 * +------------+--------+ +---------------------------------+
985 * ... | Policer 7: Rate, Burst, MTU |
986 * +------------+--------+ +---------------------------------+
987 * |Port 4 TC 7 |SHARINDX| ...
988 * +------------+--------+
989 * |Port 0 BCAST|SHARINDX| ...
990 * +------------+--------+
991 * |Port 1 BCAST|SHARINDX| ...
992 * +------------+--------+
993 * ... ...
994 * +------------+--------+ +---------------------------------+
995 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |
996 * +------------+--------+ +---------------------------------+
997 *
998 * In this driver, we shall use policers 0-4 as statically alocated port
999 * (matchall) policers. So we need to make the SHARINDX for all lookups
1000 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1001 * lookup) equal.
1002 * The remaining policers (40) shall be dynamically allocated for flower
1003 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1004 */
1005#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1006
1007static int sja1105_init_l2_policing(struct sja1105_private *priv)
1008{
1009 struct sja1105_l2_policing_entry *policing;
1010 struct dsa_switch *ds = priv->ds;
1011 struct sja1105_table *table;
1012 int port, tc;
1013
1014 table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1015
1016 /* Discard previous L2 Policing Table */
1017 if (table->entry_count) {
1018 kfree(table->entries);
1019 table->entry_count = 0;
1020 }
1021
1022 table->entries = kcalloc(table->ops->max_entry_count,
1023 table->ops->unpacked_entry_size, GFP_KERNEL);
1024 if (!table->entries)
1025 return -ENOMEM;
1026
1027 table->entry_count = table->ops->max_entry_count;
1028
1029 policing = table->entries;
1030
1031 /* Setup shared indices for the matchall policers */
1032 for (port = 0; port < ds->num_ports; port++) {
1033 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1034 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1035
1036 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1037 policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1038
1039 policing[bcast].sharindx = port;
1040 /* Only SJA1110 has multicast policers */
1041 if (mcast < table->ops->max_entry_count)
1042 policing[mcast].sharindx = port;
1043 }
1044
1045 /* Setup the matchall policer parameters */
1046 for (port = 0; port < ds->num_ports; port++) {
1047 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1048
1049 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1050 mtu += VLAN_HLEN;
1051
1052 policing[port].smax = 65535; /* Burst size in bytes */
1053 policing[port].rate = SJA1105_RATE_MBPS(1000);
1054 policing[port].maxlen = mtu;
1055 policing[port].partition = 0;
1056 }
1057
1058 return 0;
1059}
1060
1061static int sja1105_static_config_load(struct sja1105_private *priv)
1062{
1063 int rc;
1064
1065 sja1105_static_config_free(&priv->static_config);
1066 rc = sja1105_static_config_init(&priv->static_config,
1067 priv->info->static_ops,
1068 priv->info->device_id);
1069 if (rc)
1070 return rc;
1071
1072 /* Build static configuration */
1073 rc = sja1105_init_mac_settings(priv);
1074 if (rc < 0)
1075 return rc;
1076 rc = sja1105_init_mii_settings(priv);
1077 if (rc < 0)
1078 return rc;
1079 rc = sja1105_init_static_fdb(priv);
1080 if (rc < 0)
1081 return rc;
1082 rc = sja1105_init_static_vlan(priv);
1083 if (rc < 0)
1084 return rc;
1085 rc = sja1105_init_l2_lookup_params(priv);
1086 if (rc < 0)
1087 return rc;
1088 rc = sja1105_init_l2_forwarding(priv);
1089 if (rc < 0)
1090 return rc;
1091 rc = sja1105_init_l2_forwarding_params(priv);
1092 if (rc < 0)
1093 return rc;
1094 rc = sja1105_init_l2_policing(priv);
1095 if (rc < 0)
1096 return rc;
1097 rc = sja1105_init_general_params(priv);
1098 if (rc < 0)
1099 return rc;
1100 rc = sja1105_init_avb_params(priv);
1101 if (rc < 0)
1102 return rc;
1103 rc = sja1110_init_pcp_remapping(priv);
1104 if (rc < 0)
1105 return rc;
1106
1107 /* Send initial configuration to hardware via SPI */
1108 return sja1105_static_config_upload(priv);
1109}
1110
1111/* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1112 * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1113 * properties. It has the advantage of working with fixed links and with PHYs
1114 * that apply RGMII delays too, and the MAC driver needs not perform any
1115 * special checks.
1116 *
1117 * Previously we were acting upon the "phy-mode" property when we were
1118 * operating in fixed-link, basically acting as a PHY, but with a reversed
1119 * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1120 * behave as if it is connected to a PHY which has applied RGMII delays in the
1121 * TX direction. So if anything, RX delays should have been added by the MAC,
1122 * but we were adding TX delays.
1123 *
1124 * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1125 * back to the legacy behavior and apply delays on fixed-link ports based on
1126 * the reverse interpretation of the phy-mode. This is a deviation from the
1127 * expected default behavior which is to simply apply no delays. To achieve
1128 * that behavior with the new bindings, it is mandatory to specify
1129 * "{rx,tx}-internal-delay-ps" with a value of 0.
1130 */
1131static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1132 struct device_node *port_dn)
1133{
1134 phy_interface_t phy_mode = priv->phy_mode[port];
1135 struct device *dev = &priv->spidev->dev;
1136 int rx_delay = -1, tx_delay = -1;
1137
1138 if (!phy_interface_mode_is_rgmii(phy_mode))
1139 return 0;
1140
1141 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1142 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1143
1144 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1145 dev_warn(dev,
1146 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1147 "please update device tree to specify \"rx-internal-delay-ps\" and "
1148 "\"tx-internal-delay-ps\"",
1149 port);
1150
1151 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1152 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1153 rx_delay = 2000;
1154
1155 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1156 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1157 tx_delay = 2000;
1158 }
1159
1160 if (rx_delay < 0)
1161 rx_delay = 0;
1162 if (tx_delay < 0)
1163 tx_delay = 0;
1164
1165 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1166 dev_err(dev, "Chip cannot apply RGMII delays\n");
1167 return -EINVAL;
1168 }
1169
1170 if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1171 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1172 (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1173 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1174 dev_err(dev,
1175 "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1176 port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1177 return -ERANGE;
1178 }
1179
1180 priv->rgmii_rx_delay_ps[port] = rx_delay;
1181 priv->rgmii_tx_delay_ps[port] = tx_delay;
1182
1183 return 0;
1184}
1185
1186static int sja1105_parse_ports_node(struct sja1105_private *priv,
1187 struct device_node *ports_node)
1188{
1189 struct device *dev = &priv->spidev->dev;
1190
1191 for_each_available_child_of_node_scoped(ports_node, child) {
1192 struct device_node *phy_node;
1193 phy_interface_t phy_mode;
1194 u32 index;
1195 int err;
1196
1197 /* Get switch port number from DT */
1198 if (of_property_read_u32(child, "reg", &index) < 0) {
1199 dev_err(dev, "Port number not defined in device tree "
1200 "(property \"reg\")\n");
1201 return -ENODEV;
1202 }
1203
1204 /* Get PHY mode from DT */
1205 err = of_get_phy_mode(child, &phy_mode);
1206 if (err) {
1207 dev_err(dev, "Failed to read phy-mode or "
1208 "phy-interface-type property for port %d\n",
1209 index);
1210 return -ENODEV;
1211 }
1212
1213 phy_node = of_parse_phandle(child, "phy-handle", 0);
1214 if (!phy_node) {
1215 if (!of_phy_is_fixed_link(child)) {
1216 dev_err(dev, "phy-handle or fixed-link "
1217 "properties missing!\n");
1218 return -ENODEV;
1219 }
1220 /* phy-handle is missing, but fixed-link isn't.
1221 * So it's a fixed link. Default to PHY role.
1222 */
1223 priv->fixed_link[index] = true;
1224 } else {
1225 of_node_put(phy_node);
1226 }
1227
1228 priv->phy_mode[index] = phy_mode;
1229
1230 err = sja1105_parse_rgmii_delays(priv, index, child);
1231 if (err)
1232 return err;
1233 }
1234
1235 return 0;
1236}
1237
1238static int sja1105_parse_dt(struct sja1105_private *priv)
1239{
1240 struct device *dev = &priv->spidev->dev;
1241 struct device_node *switch_node = dev->of_node;
1242 struct device_node *ports_node;
1243 int rc;
1244
1245 ports_node = of_get_child_by_name(switch_node, "ports");
1246 if (!ports_node)
1247 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1248 if (!ports_node) {
1249 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1250 return -ENODEV;
1251 }
1252
1253 rc = sja1105_parse_ports_node(priv, ports_node);
1254 of_node_put(ports_node);
1255
1256 return rc;
1257}
1258
1259static int sja1105_set_port_speed(struct sja1105_private *priv, int port,
1260 int speed_mbps)
1261{
1262 struct sja1105_mac_config_entry *mac;
1263 u64 speed;
1264
1265 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1266 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1267 * We have to *know* what the MAC looks like. For the sake of keeping
1268 * the code common, we'll use the static configuration tables as a
1269 * reasonable approximation for both E/T and P/Q/R/S.
1270 */
1271 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1272
1273 switch (speed_mbps) {
1274 case SPEED_UNKNOWN:
1275 /* PHYLINK called sja1105_mac_config() to inform us about
1276 * the state->interface, but AN has not completed and the
1277 * speed is not yet valid. UM10944.pdf says that setting
1278 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1279 * ok for power consumption in case AN will never complete -
1280 * otherwise PHYLINK should come back with a new update.
1281 */
1282 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1283 break;
1284 case SPEED_10:
1285 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1286 break;
1287 case SPEED_100:
1288 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1289 break;
1290 case SPEED_1000:
1291 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1292 break;
1293 case SPEED_2500:
1294 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1295 break;
1296 default:
1297 dev_err(priv->ds->dev, "Invalid speed %iMbps\n", speed_mbps);
1298 return -EINVAL;
1299 }
1300
1301 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1302 * table, since this will be used for the clocking setup, and we no
1303 * longer need to store it in the static config (already told hardware
1304 * we want auto during upload phase).
1305 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1306 * we need to configure the PCS only (if even that).
1307 */
1308 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1309 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1310 else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1311 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1312
1313 mac[port].speed = speed;
1314
1315 return 0;
1316}
1317
1318/* Write the MAC Configuration Table entry and, if necessary, the CGU settings,
1319 * after a link speedchange for this port.
1320 */
1321static int sja1105_set_port_config(struct sja1105_private *priv, int port)
1322{
1323 struct sja1105_mac_config_entry *mac;
1324 struct device *dev = priv->ds->dev;
1325 int rc;
1326
1327 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1328 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1329 * We have to *know* what the MAC looks like. For the sake of keeping
1330 * the code common, we'll use the static configuration tables as a
1331 * reasonable approximation for both E/T and P/Q/R/S.
1332 */
1333 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1334
1335 /* Write to the dynamic reconfiguration tables */
1336 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1337 &mac[port], true);
1338 if (rc < 0) {
1339 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1340 return rc;
1341 }
1342
1343 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1344 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1345 * RMII no change of the clock setup is required. Actually, changing
1346 * the clock setup does interrupt the clock signal for a certain time
1347 * which causes trouble for all PHYs relying on this signal.
1348 */
1349 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1350 return 0;
1351
1352 return sja1105_clocking_setup_port(priv, port);
1353}
1354
1355static struct phylink_pcs *
1356sja1105_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
1357{
1358 struct dsa_port *dp = dsa_phylink_to_port(config);
1359 struct sja1105_private *priv = dp->ds->priv;
1360
1361 return priv->pcs[dp->index];
1362}
1363
1364static void sja1105_mac_config(struct phylink_config *config,
1365 unsigned int mode,
1366 const struct phylink_link_state *state)
1367{
1368}
1369
1370static void sja1105_mac_link_down(struct phylink_config *config,
1371 unsigned int mode,
1372 phy_interface_t interface)
1373{
1374 struct dsa_port *dp = dsa_phylink_to_port(config);
1375
1376 sja1105_inhibit_tx(dp->ds->priv, BIT(dp->index), true);
1377}
1378
1379static void sja1105_mac_link_up(struct phylink_config *config,
1380 struct phy_device *phydev,
1381 unsigned int mode,
1382 phy_interface_t interface,
1383 int speed, int duplex,
1384 bool tx_pause, bool rx_pause)
1385{
1386 struct dsa_port *dp = dsa_phylink_to_port(config);
1387 struct sja1105_private *priv = dp->ds->priv;
1388 int port = dp->index;
1389
1390 if (!sja1105_set_port_speed(priv, port, speed))
1391 sja1105_set_port_config(priv, port);
1392
1393 sja1105_inhibit_tx(priv, BIT(port), false);
1394}
1395
1396static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,
1397 struct phylink_config *config)
1398{
1399 struct sja1105_private *priv = ds->priv;
1400 struct sja1105_xmii_params_entry *mii;
1401 phy_interface_t phy_mode;
1402
1403 phy_mode = priv->phy_mode[port];
1404 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
1405 phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
1406 /* Changing the PHY mode on SERDES ports is possible and makes
1407 * sense, because that is done through the XPCS. We allow
1408 * changes between SGMII and 2500base-X.
1409 */
1410 if (priv->info->supports_sgmii[port])
1411 __set_bit(PHY_INTERFACE_MODE_SGMII,
1412 config->supported_interfaces);
1413
1414 if (priv->info->supports_2500basex[port])
1415 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1416 config->supported_interfaces);
1417 } else {
1418 /* The SJA1105 MAC programming model is through the static
1419 * config (the xMII Mode table cannot be dynamically
1420 * reconfigured), and we have to program that early.
1421 */
1422 __set_bit(phy_mode, config->supported_interfaces);
1423 }
1424
1425 /* The MAC does not support pause frames, and also doesn't
1426 * support half-duplex traffic modes.
1427 */
1428 config->mac_capabilities = MAC_10FD | MAC_100FD;
1429
1430 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1431 if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1432 mii->xmii_mode[port] == XMII_MODE_SGMII)
1433 config->mac_capabilities |= MAC_1000FD;
1434
1435 if (priv->info->supports_2500basex[port])
1436 config->mac_capabilities |= MAC_2500FD;
1437}
1438
1439static int
1440sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1441 const struct sja1105_l2_lookup_entry *requested)
1442{
1443 struct sja1105_l2_lookup_entry *l2_lookup;
1444 struct sja1105_table *table;
1445 int i;
1446
1447 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1448 l2_lookup = table->entries;
1449
1450 for (i = 0; i < table->entry_count; i++)
1451 if (l2_lookup[i].macaddr == requested->macaddr &&
1452 l2_lookup[i].vlanid == requested->vlanid &&
1453 l2_lookup[i].destports & BIT(port))
1454 return i;
1455
1456 return -1;
1457}
1458
1459/* We want FDB entries added statically through the bridge command to persist
1460 * across switch resets, which are a common thing during normal SJA1105
1461 * operation. So we have to back them up in the static configuration tables
1462 * and hence apply them on next static config upload... yay!
1463 */
1464static int
1465sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1466 const struct sja1105_l2_lookup_entry *requested,
1467 bool keep)
1468{
1469 struct sja1105_l2_lookup_entry *l2_lookup;
1470 struct sja1105_table *table;
1471 int rc, match;
1472
1473 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1474
1475 match = sja1105_find_static_fdb_entry(priv, port, requested);
1476 if (match < 0) {
1477 /* Can't delete a missing entry. */
1478 if (!keep)
1479 return 0;
1480
1481 /* No match => new entry */
1482 rc = sja1105_table_resize(table, table->entry_count + 1);
1483 if (rc)
1484 return rc;
1485
1486 match = table->entry_count - 1;
1487 }
1488
1489 /* Assign pointer after the resize (it may be new memory) */
1490 l2_lookup = table->entries;
1491
1492 /* We have a match.
1493 * If the job was to add this FDB entry, it's already done (mostly
1494 * anyway, since the port forwarding mask may have changed, case in
1495 * which we update it).
1496 * Otherwise we have to delete it.
1497 */
1498 if (keep) {
1499 l2_lookup[match] = *requested;
1500 return 0;
1501 }
1502
1503 /* To remove, the strategy is to overwrite the element with
1504 * the last one, and then reduce the array size by 1
1505 */
1506 l2_lookup[match] = l2_lookup[table->entry_count - 1];
1507 return sja1105_table_resize(table, table->entry_count - 1);
1508}
1509
1510/* First-generation switches have a 4-way set associative TCAM that
1511 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1512 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1513 * For the placement of a newly learnt FDB entry, the switch selects the bin
1514 * based on a hash function, and the way within that bin incrementally.
1515 */
1516static int sja1105et_fdb_index(int bin, int way)
1517{
1518 return bin * SJA1105ET_FDB_BIN_SIZE + way;
1519}
1520
1521static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1522 const u8 *addr, u16 vid,
1523 struct sja1105_l2_lookup_entry *match,
1524 int *last_unused)
1525{
1526 int way;
1527
1528 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1529 struct sja1105_l2_lookup_entry l2_lookup = {0};
1530 int index = sja1105et_fdb_index(bin, way);
1531
1532 /* Skip unused entries, optionally marking them
1533 * into the return value
1534 */
1535 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1536 index, &l2_lookup)) {
1537 if (last_unused)
1538 *last_unused = way;
1539 continue;
1540 }
1541
1542 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1543 l2_lookup.vlanid == vid) {
1544 if (match)
1545 *match = l2_lookup;
1546 return way;
1547 }
1548 }
1549 /* Return an invalid entry index if not found */
1550 return -1;
1551}
1552
1553int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1554 const unsigned char *addr, u16 vid)
1555{
1556 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1557 struct sja1105_private *priv = ds->priv;
1558 struct device *dev = ds->dev;
1559 int last_unused = -1;
1560 int start, end, i;
1561 int bin, way, rc;
1562
1563 bin = sja1105et_fdb_hash(priv, addr, vid);
1564
1565 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1566 &l2_lookup, &last_unused);
1567 if (way >= 0) {
1568 /* We have an FDB entry. Is our port in the destination
1569 * mask? If yes, we need to do nothing. If not, we need
1570 * to rewrite the entry by adding this port to it.
1571 */
1572 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1573 return 0;
1574 l2_lookup.destports |= BIT(port);
1575 } else {
1576 int index = sja1105et_fdb_index(bin, way);
1577
1578 /* We don't have an FDB entry. We construct a new one and
1579 * try to find a place for it within the FDB table.
1580 */
1581 l2_lookup.macaddr = ether_addr_to_u64(addr);
1582 l2_lookup.destports = BIT(port);
1583 l2_lookup.vlanid = vid;
1584
1585 if (last_unused >= 0) {
1586 way = last_unused;
1587 } else {
1588 /* Bin is full, need to evict somebody.
1589 * Choose victim at random. If you get these messages
1590 * often, you may need to consider changing the
1591 * distribution function:
1592 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1593 */
1594 get_random_bytes(&way, sizeof(u8));
1595 way %= SJA1105ET_FDB_BIN_SIZE;
1596 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1597 bin, addr, way);
1598 /* Evict entry */
1599 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1600 index, NULL, false);
1601 }
1602 }
1603 l2_lookup.lockeds = true;
1604 l2_lookup.index = sja1105et_fdb_index(bin, way);
1605
1606 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1607 l2_lookup.index, &l2_lookup,
1608 true);
1609 if (rc < 0)
1610 return rc;
1611
1612 /* Invalidate a dynamically learned entry if that exists */
1613 start = sja1105et_fdb_index(bin, 0);
1614 end = sja1105et_fdb_index(bin, way);
1615
1616 for (i = start; i < end; i++) {
1617 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1618 i, &tmp);
1619 if (rc == -ENOENT)
1620 continue;
1621 if (rc)
1622 return rc;
1623
1624 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1625 continue;
1626
1627 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1628 i, NULL, false);
1629 if (rc)
1630 return rc;
1631
1632 break;
1633 }
1634
1635 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1636}
1637
1638int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1639 const unsigned char *addr, u16 vid)
1640{
1641 struct sja1105_l2_lookup_entry l2_lookup = {0};
1642 struct sja1105_private *priv = ds->priv;
1643 int index, bin, way, rc;
1644 bool keep;
1645
1646 bin = sja1105et_fdb_hash(priv, addr, vid);
1647 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1648 &l2_lookup, NULL);
1649 if (way < 0)
1650 return 0;
1651 index = sja1105et_fdb_index(bin, way);
1652
1653 /* We have an FDB entry. Is our port in the destination mask? If yes,
1654 * we need to remove it. If the resulting port mask becomes empty, we
1655 * need to completely evict the FDB entry.
1656 * Otherwise we just write it back.
1657 */
1658 l2_lookup.destports &= ~BIT(port);
1659
1660 if (l2_lookup.destports)
1661 keep = true;
1662 else
1663 keep = false;
1664
1665 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1666 index, &l2_lookup, keep);
1667 if (rc < 0)
1668 return rc;
1669
1670 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1671}
1672
1673int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1674 const unsigned char *addr, u16 vid)
1675{
1676 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1677 struct sja1105_private *priv = ds->priv;
1678 int rc, i;
1679
1680 /* Search for an existing entry in the FDB table */
1681 l2_lookup.macaddr = ether_addr_to_u64(addr);
1682 l2_lookup.vlanid = vid;
1683 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1684 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1685 l2_lookup.destports = BIT(port);
1686
1687 tmp = l2_lookup;
1688
1689 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1690 SJA1105_SEARCH, &tmp);
1691 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1692 /* Found a static entry and this port is already in the entry's
1693 * port mask => job done
1694 */
1695 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1696 return 0;
1697
1698 l2_lookup = tmp;
1699
1700 /* l2_lookup.index is populated by the switch in case it
1701 * found something.
1702 */
1703 l2_lookup.destports |= BIT(port);
1704 goto skip_finding_an_index;
1705 }
1706
1707 /* Not found, so try to find an unused spot in the FDB.
1708 * This is slightly inefficient because the strategy is knock-knock at
1709 * every possible position from 0 to 1023.
1710 */
1711 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1712 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1713 i, NULL);
1714 if (rc < 0)
1715 break;
1716 }
1717 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1718 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1719 return -EINVAL;
1720 }
1721 l2_lookup.index = i;
1722
1723skip_finding_an_index:
1724 l2_lookup.lockeds = true;
1725
1726 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1727 l2_lookup.index, &l2_lookup,
1728 true);
1729 if (rc < 0)
1730 return rc;
1731
1732 /* The switch learns dynamic entries and looks up the FDB left to
1733 * right. It is possible that our addition was concurrent with the
1734 * dynamic learning of the same address, so now that the static entry
1735 * has been installed, we are certain that address learning for this
1736 * particular address has been turned off, so the dynamic entry either
1737 * is in the FDB at an index smaller than the static one, or isn't (it
1738 * can also be at a larger index, but in that case it is inactive
1739 * because the static FDB entry will match first, and the dynamic one
1740 * will eventually age out). Search for a dynamically learned address
1741 * prior to our static one and invalidate it.
1742 */
1743 tmp = l2_lookup;
1744
1745 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1746 SJA1105_SEARCH, &tmp);
1747 if (rc < 0) {
1748 dev_err(ds->dev,
1749 "port %d failed to read back entry for %pM vid %d: %pe\n",
1750 port, addr, vid, ERR_PTR(rc));
1751 return rc;
1752 }
1753
1754 if (tmp.index < l2_lookup.index) {
1755 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1756 tmp.index, NULL, false);
1757 if (rc < 0)
1758 return rc;
1759 }
1760
1761 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1762}
1763
1764int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1765 const unsigned char *addr, u16 vid)
1766{
1767 struct sja1105_l2_lookup_entry l2_lookup = {0};
1768 struct sja1105_private *priv = ds->priv;
1769 bool keep;
1770 int rc;
1771
1772 l2_lookup.macaddr = ether_addr_to_u64(addr);
1773 l2_lookup.vlanid = vid;
1774 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1775 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1776 l2_lookup.destports = BIT(port);
1777
1778 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1779 SJA1105_SEARCH, &l2_lookup);
1780 if (rc < 0)
1781 return 0;
1782
1783 l2_lookup.destports &= ~BIT(port);
1784
1785 /* Decide whether we remove just this port from the FDB entry,
1786 * or if we remove it completely.
1787 */
1788 if (l2_lookup.destports)
1789 keep = true;
1790 else
1791 keep = false;
1792
1793 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1794 l2_lookup.index, &l2_lookup, keep);
1795 if (rc < 0)
1796 return rc;
1797
1798 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1799}
1800
1801static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1802 const unsigned char *addr, u16 vid,
1803 struct dsa_db db)
1804{
1805 struct sja1105_private *priv = ds->priv;
1806 int rc;
1807
1808 if (!vid) {
1809 switch (db.type) {
1810 case DSA_DB_PORT:
1811 vid = dsa_tag_8021q_standalone_vid(db.dp);
1812 break;
1813 case DSA_DB_BRIDGE:
1814 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1815 break;
1816 default:
1817 return -EOPNOTSUPP;
1818 }
1819 }
1820
1821 mutex_lock(&priv->fdb_lock);
1822 rc = priv->info->fdb_add_cmd(ds, port, addr, vid);
1823 mutex_unlock(&priv->fdb_lock);
1824
1825 return rc;
1826}
1827
1828static int __sja1105_fdb_del(struct dsa_switch *ds, int port,
1829 const unsigned char *addr, u16 vid,
1830 struct dsa_db db)
1831{
1832 struct sja1105_private *priv = ds->priv;
1833
1834 if (!vid) {
1835 switch (db.type) {
1836 case DSA_DB_PORT:
1837 vid = dsa_tag_8021q_standalone_vid(db.dp);
1838 break;
1839 case DSA_DB_BRIDGE:
1840 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1841 break;
1842 default:
1843 return -EOPNOTSUPP;
1844 }
1845 }
1846
1847 return priv->info->fdb_del_cmd(ds, port, addr, vid);
1848}
1849
1850static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1851 const unsigned char *addr, u16 vid,
1852 struct dsa_db db)
1853{
1854 struct sja1105_private *priv = ds->priv;
1855 int rc;
1856
1857 mutex_lock(&priv->fdb_lock);
1858 rc = __sja1105_fdb_del(ds, port, addr, vid, db);
1859 mutex_unlock(&priv->fdb_lock);
1860
1861 return rc;
1862}
1863
1864static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1865 dsa_fdb_dump_cb_t *cb, void *data)
1866{
1867 struct sja1105_private *priv = ds->priv;
1868 struct device *dev = ds->dev;
1869 int i;
1870
1871 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1872 struct sja1105_l2_lookup_entry l2_lookup = {0};
1873 u8 macaddr[ETH_ALEN];
1874 int rc;
1875
1876 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1877 i, &l2_lookup);
1878 /* No fdb entry at i, not an issue */
1879 if (rc == -ENOENT)
1880 continue;
1881 if (rc) {
1882 dev_err(dev, "Failed to dump FDB: %d\n", rc);
1883 return rc;
1884 }
1885
1886 /* FDB dump callback is per port. This means we have to
1887 * disregard a valid entry if it's not for this port, even if
1888 * only to revisit it later. This is inefficient because the
1889 * 1024-sized FDB table needs to be traversed 4 times through
1890 * SPI during a 'bridge fdb show' command.
1891 */
1892 if (!(l2_lookup.destports & BIT(port)))
1893 continue;
1894
1895 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1896
1897 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show"
1898 * only wants to see unicast
1899 */
1900 if (is_multicast_ether_addr(macaddr))
1901 continue;
1902
1903 /* We need to hide the dsa_8021q VLANs from the user. */
1904 if (vid_is_dsa_8021q(l2_lookup.vlanid))
1905 l2_lookup.vlanid = 0;
1906 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1907 if (rc)
1908 return rc;
1909 }
1910 return 0;
1911}
1912
1913static void sja1105_fast_age(struct dsa_switch *ds, int port)
1914{
1915 struct dsa_port *dp = dsa_to_port(ds, port);
1916 struct sja1105_private *priv = ds->priv;
1917 struct dsa_db db = {
1918 .type = DSA_DB_BRIDGE,
1919 .bridge = {
1920 .dev = dsa_port_bridge_dev_get(dp),
1921 .num = dsa_port_bridge_num_get(dp),
1922 },
1923 };
1924 int i;
1925
1926 mutex_lock(&priv->fdb_lock);
1927
1928 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1929 struct sja1105_l2_lookup_entry l2_lookup = {0};
1930 u8 macaddr[ETH_ALEN];
1931 int rc;
1932
1933 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1934 i, &l2_lookup);
1935 /* No fdb entry at i, not an issue */
1936 if (rc == -ENOENT)
1937 continue;
1938 if (rc) {
1939 dev_err(ds->dev, "Failed to read FDB: %pe\n",
1940 ERR_PTR(rc));
1941 break;
1942 }
1943
1944 if (!(l2_lookup.destports & BIT(port)))
1945 continue;
1946
1947 /* Don't delete static FDB entries */
1948 if (l2_lookup.lockeds)
1949 continue;
1950
1951 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1952
1953 rc = __sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db);
1954 if (rc) {
1955 dev_err(ds->dev,
1956 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1957 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1958 break;
1959 }
1960 }
1961
1962 mutex_unlock(&priv->fdb_lock);
1963}
1964
1965static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1966 const struct switchdev_obj_port_mdb *mdb,
1967 struct dsa_db db)
1968{
1969 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db);
1970}
1971
1972static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1973 const struct switchdev_obj_port_mdb *mdb,
1974 struct dsa_db db)
1975{
1976 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db);
1977}
1978
1979/* Common function for unicast and broadcast flood configuration.
1980 * Flooding is configured between each {ingress, egress} port pair, and since
1981 * the bridge's semantics are those of "egress flooding", it means we must
1982 * enable flooding towards this port from all ingress ports that are in the
1983 * same forwarding domain.
1984 */
1985static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1986{
1987 struct sja1105_l2_forwarding_entry *l2_fwd;
1988 struct dsa_switch *ds = priv->ds;
1989 int from, to, rc;
1990
1991 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1992
1993 for (from = 0; from < ds->num_ports; from++) {
1994 u64 fl_domain = 0, bc_domain = 0;
1995
1996 for (to = 0; to < priv->ds->num_ports; to++) {
1997 if (!sja1105_can_forward(l2_fwd, from, to))
1998 continue;
1999
2000 if (priv->ucast_egress_floods & BIT(to))
2001 fl_domain |= BIT(to);
2002 if (priv->bcast_egress_floods & BIT(to))
2003 bc_domain |= BIT(to);
2004 }
2005
2006 /* Nothing changed, nothing to do */
2007 if (l2_fwd[from].fl_domain == fl_domain &&
2008 l2_fwd[from].bc_domain == bc_domain)
2009 continue;
2010
2011 l2_fwd[from].fl_domain = fl_domain;
2012 l2_fwd[from].bc_domain = bc_domain;
2013
2014 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2015 from, &l2_fwd[from], true);
2016 if (rc < 0)
2017 return rc;
2018 }
2019
2020 return 0;
2021}
2022
2023static int sja1105_bridge_member(struct dsa_switch *ds, int port,
2024 struct dsa_bridge bridge, bool member)
2025{
2026 struct sja1105_l2_forwarding_entry *l2_fwd;
2027 struct sja1105_private *priv = ds->priv;
2028 int i, rc;
2029
2030 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
2031
2032 for (i = 0; i < ds->num_ports; i++) {
2033 /* Add this port to the forwarding matrix of the
2034 * other ports in the same bridge, and viceversa.
2035 */
2036 if (!dsa_is_user_port(ds, i))
2037 continue;
2038 /* For the ports already under the bridge, only one thing needs
2039 * to be done, and that is to add this port to their
2040 * reachability domain. So we can perform the SPI write for
2041 * them immediately. However, for this port itself (the one
2042 * that is new to the bridge), we need to add all other ports
2043 * to its reachability domain. So we do that incrementally in
2044 * this loop, and perform the SPI write only at the end, once
2045 * the domain contains all other bridge ports.
2046 */
2047 if (i == port)
2048 continue;
2049 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2050 continue;
2051 sja1105_port_allow_traffic(l2_fwd, i, port, member);
2052 sja1105_port_allow_traffic(l2_fwd, port, i, member);
2053
2054 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2055 i, &l2_fwd[i], true);
2056 if (rc < 0)
2057 return rc;
2058 }
2059
2060 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2061 port, &l2_fwd[port], true);
2062 if (rc)
2063 return rc;
2064
2065 rc = sja1105_commit_pvid(ds, port);
2066 if (rc)
2067 return rc;
2068
2069 return sja1105_manage_flood_domains(priv);
2070}
2071
2072static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2073 u8 state)
2074{
2075 struct dsa_port *dp = dsa_to_port(ds, port);
2076 struct sja1105_private *priv = ds->priv;
2077 struct sja1105_mac_config_entry *mac;
2078
2079 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2080
2081 switch (state) {
2082 case BR_STATE_DISABLED:
2083 case BR_STATE_BLOCKING:
2084 /* From UM10944 description of DRPDTAG (why put this there?):
2085 * "Management traffic flows to the port regardless of the state
2086 * of the INGRESS flag". So BPDUs are still be allowed to pass.
2087 * At the moment no difference between DISABLED and BLOCKING.
2088 */
2089 mac[port].ingress = false;
2090 mac[port].egress = false;
2091 mac[port].dyn_learn = false;
2092 break;
2093 case BR_STATE_LISTENING:
2094 mac[port].ingress = true;
2095 mac[port].egress = false;
2096 mac[port].dyn_learn = false;
2097 break;
2098 case BR_STATE_LEARNING:
2099 mac[port].ingress = true;
2100 mac[port].egress = false;
2101 mac[port].dyn_learn = dp->learning;
2102 break;
2103 case BR_STATE_FORWARDING:
2104 mac[port].ingress = true;
2105 mac[port].egress = true;
2106 mac[port].dyn_learn = dp->learning;
2107 break;
2108 default:
2109 dev_err(ds->dev, "invalid STP state: %d\n", state);
2110 return;
2111 }
2112
2113 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2114 &mac[port], true);
2115}
2116
2117static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2118 struct dsa_bridge bridge,
2119 bool *tx_fwd_offload,
2120 struct netlink_ext_ack *extack)
2121{
2122 int rc;
2123
2124 rc = sja1105_bridge_member(ds, port, bridge, true);
2125 if (rc)
2126 return rc;
2127
2128 rc = dsa_tag_8021q_bridge_join(ds, port, bridge, tx_fwd_offload,
2129 extack);
2130 if (rc) {
2131 sja1105_bridge_member(ds, port, bridge, false);
2132 return rc;
2133 }
2134
2135 return 0;
2136}
2137
2138static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2139 struct dsa_bridge bridge)
2140{
2141 dsa_tag_8021q_bridge_leave(ds, port, bridge);
2142 sja1105_bridge_member(ds, port, bridge, false);
2143}
2144
2145/* Port 0 (the uC port) does not have CBS shapers */
2146#define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio))
2147
2148static int sja1105_find_cbs_shaper(struct sja1105_private *priv,
2149 int port, int prio)
2150{
2151 int i;
2152
2153 if (priv->info->fixed_cbs_mapping) {
2154 i = SJA1110_FIXED_CBS(port, prio);
2155 if (i >= 0 && i < priv->info->num_cbs_shapers)
2156 return i;
2157
2158 return -1;
2159 }
2160
2161 for (i = 0; i < priv->info->num_cbs_shapers; i++)
2162 if (priv->cbs[i].port == port && priv->cbs[i].prio == prio)
2163 return i;
2164
2165 return -1;
2166}
2167
2168static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2169{
2170 int i;
2171
2172 if (priv->info->fixed_cbs_mapping)
2173 return -1;
2174
2175 for (i = 0; i < priv->info->num_cbs_shapers; i++)
2176 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2177 return i;
2178
2179 return -1;
2180}
2181
2182static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2183 int prio)
2184{
2185 int i;
2186
2187 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2188 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2189
2190 if (cbs->port == port && cbs->prio == prio) {
2191 memset(cbs, 0, sizeof(*cbs));
2192 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2193 i, cbs, true);
2194 }
2195 }
2196
2197 return 0;
2198}
2199
2200static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2201 struct tc_cbs_qopt_offload *offload)
2202{
2203 struct sja1105_private *priv = ds->priv;
2204 struct sja1105_cbs_entry *cbs;
2205 s64 port_transmit_rate_kbps;
2206 int index;
2207
2208 if (!offload->enable)
2209 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2210
2211 /* The user may be replacing an existing shaper */
2212 index = sja1105_find_cbs_shaper(priv, port, offload->queue);
2213 if (index < 0) {
2214 /* That isn't the case - see if we can allocate a new one */
2215 index = sja1105_find_unused_cbs_shaper(priv);
2216 if (index < 0)
2217 return -ENOSPC;
2218 }
2219
2220 cbs = &priv->cbs[index];
2221 cbs->port = port;
2222 cbs->prio = offload->queue;
2223 /* locredit and sendslope are negative by definition. In hardware,
2224 * positive values must be provided, and the negative sign is implicit.
2225 */
2226 cbs->credit_hi = offload->hicredit;
2227 cbs->credit_lo = abs(offload->locredit);
2228 /* User space is in kbits/sec, while the hardware in bytes/sec times
2229 * link speed. Since the given offload->sendslope is good only for the
2230 * current link speed anyway, and user space is likely to reprogram it
2231 * when that changes, don't even bother to track the port's link speed,
2232 * but deduce the port transmit rate from idleslope - sendslope.
2233 */
2234 port_transmit_rate_kbps = offload->idleslope - offload->sendslope;
2235 cbs->idle_slope = div_s64(offload->idleslope * BYTES_PER_KBIT,
2236 port_transmit_rate_kbps);
2237 cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT),
2238 port_transmit_rate_kbps);
2239 /* Convert the negative values from 64-bit 2's complement
2240 * to 32-bit 2's complement (for the case of 0x80000000 whose
2241 * negative is still negative).
2242 */
2243 cbs->credit_lo &= GENMASK_ULL(31, 0);
2244 cbs->send_slope &= GENMASK_ULL(31, 0);
2245
2246 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2247 true);
2248}
2249
2250static int sja1105_reload_cbs(struct sja1105_private *priv)
2251{
2252 int rc = 0, i;
2253
2254 /* The credit based shapers are only allocated if
2255 * CONFIG_NET_SCH_CBS is enabled.
2256 */
2257 if (!priv->cbs)
2258 return 0;
2259
2260 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2261 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2262
2263 if (!cbs->idle_slope && !cbs->send_slope)
2264 continue;
2265
2266 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2267 true);
2268 if (rc)
2269 break;
2270 }
2271
2272 return rc;
2273}
2274
2275static const char * const sja1105_reset_reasons[] = {
2276 [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2277 [SJA1105_AGEING_TIME] = "Ageing time",
2278 [SJA1105_SCHEDULING] = "Time-aware scheduling",
2279 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2280 [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2281};
2282
2283/* For situations where we need to change a setting at runtime that is only
2284 * available through the static configuration, resetting the switch in order
2285 * to upload the new static config is unavoidable. Back up the settings we
2286 * modify at runtime (currently only MAC) and restore them after uploading,
2287 * such that this operation is relatively seamless.
2288 */
2289int sja1105_static_config_reload(struct sja1105_private *priv,
2290 enum sja1105_reset_reason reason)
2291{
2292 struct ptp_system_timestamp ptp_sts_before;
2293 struct ptp_system_timestamp ptp_sts_after;
2294 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2295 u64 mac_speed[SJA1105_MAX_NUM_PORTS];
2296 struct sja1105_mac_config_entry *mac;
2297 struct dsa_switch *ds = priv->ds;
2298 s64 t1, t2, t3, t4;
2299 s64 t12, t34;
2300 int rc, i;
2301 s64 now;
2302
2303 mutex_lock(&priv->fdb_lock);
2304 mutex_lock(&priv->mgmt_lock);
2305
2306 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2307
2308 /* Back up the dynamic link speed changed by sja1105_set_port_speed()
2309 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2310 * switch wants to see in the static config in order to allow us to
2311 * change it through the dynamic interface later.
2312 */
2313 for (i = 0; i < ds->num_ports; i++) {
2314 mac_speed[i] = mac[i].speed;
2315 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2316
2317 if (priv->pcs[i])
2318 bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i,
2319 MDIO_MMD_VEND2, MDIO_CTRL1);
2320 }
2321
2322 /* No PTP operations can run right now */
2323 mutex_lock(&priv->ptp_data.lock);
2324
2325 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2326 if (rc < 0) {
2327 mutex_unlock(&priv->ptp_data.lock);
2328 goto out;
2329 }
2330
2331 /* Reset switch and send updated static configuration */
2332 rc = sja1105_static_config_upload(priv);
2333 if (rc < 0) {
2334 mutex_unlock(&priv->ptp_data.lock);
2335 goto out;
2336 }
2337
2338 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2339 if (rc < 0) {
2340 mutex_unlock(&priv->ptp_data.lock);
2341 goto out;
2342 }
2343
2344 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2345 t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2346 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2347 t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2348 /* Mid point, corresponds to pre-reset PTPCLKVAL */
2349 t12 = t1 + (t2 - t1) / 2;
2350 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2351 t34 = t3 + (t4 - t3) / 2;
2352 /* Advance PTPCLKVAL by the time it took since its readout */
2353 now += (t34 - t12);
2354
2355 __sja1105_ptp_adjtime(ds, now);
2356
2357 mutex_unlock(&priv->ptp_data.lock);
2358
2359 dev_info(priv->ds->dev,
2360 "Reset switch and programmed static config. Reason: %s\n",
2361 sja1105_reset_reasons[reason]);
2362
2363 /* Configure the CGU (PLLs) for MII and RMII PHYs.
2364 * For these interfaces there is no dynamic configuration
2365 * needed, since PLLs have same settings at all speeds.
2366 */
2367 if (priv->info->clocking_setup) {
2368 rc = priv->info->clocking_setup(priv);
2369 if (rc < 0)
2370 goto out;
2371 }
2372
2373 for (i = 0; i < ds->num_ports; i++) {
2374 struct phylink_pcs *pcs = priv->pcs[i];
2375 unsigned int neg_mode;
2376
2377 mac[i].speed = mac_speed[i];
2378 rc = sja1105_set_port_config(priv, i);
2379 if (rc < 0)
2380 goto out;
2381
2382 if (!pcs)
2383 continue;
2384
2385 if (bmcr[i] & BMCR_ANENABLE)
2386 neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
2387 else
2388 neg_mode = PHYLINK_PCS_NEG_OUTBAND;
2389
2390 rc = pcs->ops->pcs_config(pcs, neg_mode, priv->phy_mode[i],
2391 NULL, true);
2392 if (rc < 0)
2393 goto out;
2394
2395 if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) {
2396 int speed = SPEED_UNKNOWN;
2397
2398 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2399 speed = SPEED_2500;
2400 else if (bmcr[i] & BMCR_SPEED1000)
2401 speed = SPEED_1000;
2402 else if (bmcr[i] & BMCR_SPEED100)
2403 speed = SPEED_100;
2404 else
2405 speed = SPEED_10;
2406
2407 pcs->ops->pcs_link_up(pcs, neg_mode, priv->phy_mode[i],
2408 speed, DUPLEX_FULL);
2409 }
2410 }
2411
2412 rc = sja1105_reload_cbs(priv);
2413 if (rc < 0)
2414 goto out;
2415out:
2416 mutex_unlock(&priv->mgmt_lock);
2417 mutex_unlock(&priv->fdb_lock);
2418
2419 return rc;
2420}
2421
2422static enum dsa_tag_protocol
2423sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2424 enum dsa_tag_protocol mp)
2425{
2426 struct sja1105_private *priv = ds->priv;
2427
2428 return priv->info->tag_proto;
2429}
2430
2431/* The TPID setting belongs to the General Parameters table,
2432 * which can only be partially reconfigured at runtime (and not the TPID).
2433 * So a switch reset is required.
2434 */
2435int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2436 struct netlink_ext_ack *extack)
2437{
2438 struct sja1105_general_params_entry *general_params;
2439 struct sja1105_private *priv = ds->priv;
2440 struct sja1105_table *table;
2441 struct sja1105_rule *rule;
2442 u16 tpid, tpid2;
2443 int rc;
2444
2445 list_for_each_entry(rule, &priv->flow_block.rules, list) {
2446 if (rule->type == SJA1105_RULE_VL) {
2447 NL_SET_ERR_MSG_MOD(extack,
2448 "Cannot change VLAN filtering with active VL rules");
2449 return -EBUSY;
2450 }
2451 }
2452
2453 if (enabled) {
2454 /* Enable VLAN filtering. */
2455 tpid = ETH_P_8021Q;
2456 tpid2 = ETH_P_8021AD;
2457 } else {
2458 /* Disable VLAN filtering. */
2459 tpid = ETH_P_SJA1105;
2460 tpid2 = ETH_P_SJA1105;
2461 }
2462
2463 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2464 general_params = table->entries;
2465 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2466 general_params->tpid = tpid;
2467 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2468 general_params->tpid2 = tpid2;
2469
2470 for (port = 0; port < ds->num_ports; port++) {
2471 if (dsa_is_unused_port(ds, port))
2472 continue;
2473
2474 rc = sja1105_commit_pvid(ds, port);
2475 if (rc)
2476 return rc;
2477 }
2478
2479 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2480 if (rc)
2481 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2482
2483 return rc;
2484}
2485
2486static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2487 u16 flags, bool allowed_ingress)
2488{
2489 struct sja1105_vlan_lookup_entry *vlan;
2490 struct sja1105_table *table;
2491 int match, rc;
2492
2493 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2494
2495 match = sja1105_is_vlan_configured(priv, vid);
2496 if (match < 0) {
2497 rc = sja1105_table_resize(table, table->entry_count + 1);
2498 if (rc)
2499 return rc;
2500 match = table->entry_count - 1;
2501 }
2502
2503 /* Assign pointer after the resize (it's new memory) */
2504 vlan = table->entries;
2505
2506 vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2507 vlan[match].vlanid = vid;
2508 vlan[match].vlan_bc |= BIT(port);
2509
2510 if (allowed_ingress)
2511 vlan[match].vmemb_port |= BIT(port);
2512 else
2513 vlan[match].vmemb_port &= ~BIT(port);
2514
2515 if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2516 vlan[match].tag_port &= ~BIT(port);
2517 else
2518 vlan[match].tag_port |= BIT(port);
2519
2520 return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2521 &vlan[match], true);
2522}
2523
2524static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2525{
2526 struct sja1105_vlan_lookup_entry *vlan;
2527 struct sja1105_table *table;
2528 bool keep = true;
2529 int match, rc;
2530
2531 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2532
2533 match = sja1105_is_vlan_configured(priv, vid);
2534 /* Can't delete a missing entry. */
2535 if (match < 0)
2536 return 0;
2537
2538 /* Assign pointer after the resize (it's new memory) */
2539 vlan = table->entries;
2540
2541 vlan[match].vlanid = vid;
2542 vlan[match].vlan_bc &= ~BIT(port);
2543 vlan[match].vmemb_port &= ~BIT(port);
2544 /* Also unset tag_port, just so we don't have a confusing bitmap
2545 * (no practical purpose).
2546 */
2547 vlan[match].tag_port &= ~BIT(port);
2548
2549 /* If there's no port left as member of this VLAN,
2550 * it's time for it to go.
2551 */
2552 if (!vlan[match].vmemb_port)
2553 keep = false;
2554
2555 rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2556 &vlan[match], keep);
2557 if (rc < 0)
2558 return rc;
2559
2560 if (!keep)
2561 return sja1105_table_delete_entry(table, match);
2562
2563 return 0;
2564}
2565
2566static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2567 const struct switchdev_obj_port_vlan *vlan,
2568 struct netlink_ext_ack *extack)
2569{
2570 struct sja1105_private *priv = ds->priv;
2571 u16 flags = vlan->flags;
2572 int rc;
2573
2574 /* Be sure to deny alterations to the configuration done by tag_8021q.
2575 */
2576 if (vid_is_dsa_8021q(vlan->vid)) {
2577 NL_SET_ERR_MSG_MOD(extack,
2578 "Range 3072-4095 reserved for dsa_8021q operation");
2579 return -EBUSY;
2580 }
2581
2582 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2583 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2584 flags = 0;
2585
2586 rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2587 if (rc)
2588 return rc;
2589
2590 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2591 priv->bridge_pvid[port] = vlan->vid;
2592
2593 return sja1105_commit_pvid(ds, port);
2594}
2595
2596static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2597 const struct switchdev_obj_port_vlan *vlan)
2598{
2599 struct sja1105_private *priv = ds->priv;
2600 int rc;
2601
2602 rc = sja1105_vlan_del(priv, port, vlan->vid);
2603 if (rc)
2604 return rc;
2605
2606 /* In case the pvid was deleted, make sure that untagged packets will
2607 * be dropped.
2608 */
2609 return sja1105_commit_pvid(ds, port);
2610}
2611
2612static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2613 u16 flags)
2614{
2615 struct sja1105_private *priv = ds->priv;
2616 bool allowed_ingress = true;
2617 int rc;
2618
2619 /* Prevent attackers from trying to inject a DSA tag from
2620 * the outside world.
2621 */
2622 if (dsa_is_user_port(ds, port))
2623 allowed_ingress = false;
2624
2625 rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2626 if (rc)
2627 return rc;
2628
2629 if (flags & BRIDGE_VLAN_INFO_PVID)
2630 priv->tag_8021q_pvid[port] = vid;
2631
2632 return sja1105_commit_pvid(ds, port);
2633}
2634
2635static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2636{
2637 struct sja1105_private *priv = ds->priv;
2638
2639 return sja1105_vlan_del(priv, port, vid);
2640}
2641
2642static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2643 struct netdev_notifier_changeupper_info *info)
2644{
2645 struct netlink_ext_ack *extack = info->info.extack;
2646 struct net_device *upper = info->upper_dev;
2647 struct dsa_switch_tree *dst = ds->dst;
2648 struct dsa_port *dp;
2649
2650 if (is_vlan_dev(upper)) {
2651 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2652 return -EBUSY;
2653 }
2654
2655 if (netif_is_bridge_master(upper)) {
2656 list_for_each_entry(dp, &dst->ports, list) {
2657 struct net_device *br = dsa_port_bridge_dev_get(dp);
2658
2659 if (br && br != upper && br_vlan_enabled(br)) {
2660 NL_SET_ERR_MSG_MOD(extack,
2661 "Only one VLAN-aware bridge is supported");
2662 return -EBUSY;
2663 }
2664 }
2665 }
2666
2667 return 0;
2668}
2669
2670static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2671 struct sk_buff *skb, bool takets)
2672{
2673 struct sja1105_mgmt_entry mgmt_route = {0};
2674 struct sja1105_private *priv = ds->priv;
2675 struct ethhdr *hdr;
2676 int timeout = 10;
2677 int rc;
2678
2679 hdr = eth_hdr(skb);
2680
2681 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2682 mgmt_route.destports = BIT(port);
2683 mgmt_route.enfport = 1;
2684 mgmt_route.tsreg = 0;
2685 mgmt_route.takets = takets;
2686
2687 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2688 slot, &mgmt_route, true);
2689 if (rc < 0) {
2690 kfree_skb(skb);
2691 return rc;
2692 }
2693
2694 /* Transfer skb to the host port. */
2695 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->user);
2696
2697 /* Wait until the switch has processed the frame */
2698 do {
2699 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2700 slot, &mgmt_route);
2701 if (rc < 0) {
2702 dev_err_ratelimited(priv->ds->dev,
2703 "failed to poll for mgmt route\n");
2704 continue;
2705 }
2706
2707 /* UM10944: The ENFPORT flag of the respective entry is
2708 * cleared when a match is found. The host can use this
2709 * flag as an acknowledgment.
2710 */
2711 cpu_relax();
2712 } while (mgmt_route.enfport && --timeout);
2713
2714 if (!timeout) {
2715 /* Clean up the management route so that a follow-up
2716 * frame may not match on it by mistake.
2717 * This is only hardware supported on P/Q/R/S - on E/T it is
2718 * a no-op and we are silently discarding the -EOPNOTSUPP.
2719 */
2720 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2721 slot, &mgmt_route, false);
2722 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2723 }
2724
2725 return NETDEV_TX_OK;
2726}
2727
2728#define work_to_xmit_work(w) \
2729 container_of((w), struct sja1105_deferred_xmit_work, work)
2730
2731/* Deferred work is unfortunately necessary because setting up the management
2732 * route cannot be done from atomit context (SPI transfer takes a sleepable
2733 * lock on the bus)
2734 */
2735static void sja1105_port_deferred_xmit(struct kthread_work *work)
2736{
2737 struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2738 struct sk_buff *clone, *skb = xmit_work->skb;
2739 struct dsa_switch *ds = xmit_work->dp->ds;
2740 struct sja1105_private *priv = ds->priv;
2741 int port = xmit_work->dp->index;
2742
2743 clone = SJA1105_SKB_CB(skb)->clone;
2744
2745 mutex_lock(&priv->mgmt_lock);
2746
2747 sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2748
2749 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2750 if (clone)
2751 sja1105_ptp_txtstamp_skb(ds, port, clone);
2752
2753 mutex_unlock(&priv->mgmt_lock);
2754
2755 kfree(xmit_work);
2756}
2757
2758static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2759 enum dsa_tag_protocol proto)
2760{
2761 struct sja1105_private *priv = ds->priv;
2762 struct sja1105_tagger_data *tagger_data;
2763
2764 if (proto != priv->info->tag_proto)
2765 return -EPROTONOSUPPORT;
2766
2767 tagger_data = sja1105_tagger_data(ds);
2768 tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2769 tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2770
2771 return 0;
2772}
2773
2774/* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2775 * which cannot be reconfigured at runtime. So a switch reset is required.
2776 */
2777static int sja1105_set_ageing_time(struct dsa_switch *ds,
2778 unsigned int ageing_time)
2779{
2780 struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2781 struct sja1105_private *priv = ds->priv;
2782 struct sja1105_table *table;
2783 unsigned int maxage;
2784
2785 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2786 l2_lookup_params = table->entries;
2787
2788 maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2789
2790 if (l2_lookup_params->maxage == maxage)
2791 return 0;
2792
2793 l2_lookup_params->maxage = maxage;
2794
2795 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2796}
2797
2798static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2799{
2800 struct sja1105_l2_policing_entry *policing;
2801 struct sja1105_private *priv = ds->priv;
2802
2803 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2804
2805 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2806 new_mtu += VLAN_HLEN;
2807
2808 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2809
2810 if (policing[port].maxlen == new_mtu)
2811 return 0;
2812
2813 policing[port].maxlen = new_mtu;
2814
2815 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2816}
2817
2818static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2819{
2820 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2821}
2822
2823static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2824 enum tc_setup_type type,
2825 void *type_data)
2826{
2827 switch (type) {
2828 case TC_SETUP_QDISC_TAPRIO:
2829 return sja1105_setup_tc_taprio(ds, port, type_data);
2830 case TC_SETUP_QDISC_CBS:
2831 return sja1105_setup_tc_cbs(ds, port, type_data);
2832 default:
2833 return -EOPNOTSUPP;
2834 }
2835}
2836
2837/* We have a single mirror (@to) port, but can configure ingress and egress
2838 * mirroring on all other (@from) ports.
2839 * We need to allow mirroring rules only as long as the @to port is always the
2840 * same, and we need to unset the @to port from mirr_port only when there is no
2841 * mirroring rule that references it.
2842 */
2843static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2844 bool ingress, bool enabled)
2845{
2846 struct sja1105_general_params_entry *general_params;
2847 struct sja1105_mac_config_entry *mac;
2848 struct dsa_switch *ds = priv->ds;
2849 struct sja1105_table *table;
2850 bool already_enabled;
2851 u64 new_mirr_port;
2852 int rc;
2853
2854 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2855 general_params = table->entries;
2856
2857 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2858
2859 already_enabled = (general_params->mirr_port != ds->num_ports);
2860 if (already_enabled && enabled && general_params->mirr_port != to) {
2861 dev_err(priv->ds->dev,
2862 "Delete mirroring rules towards port %llu first\n",
2863 general_params->mirr_port);
2864 return -EBUSY;
2865 }
2866
2867 new_mirr_port = to;
2868 if (!enabled) {
2869 bool keep = false;
2870 int port;
2871
2872 /* Anybody still referencing mirr_port? */
2873 for (port = 0; port < ds->num_ports; port++) {
2874 if (mac[port].ing_mirr || mac[port].egr_mirr) {
2875 keep = true;
2876 break;
2877 }
2878 }
2879 /* Unset already_enabled for next time */
2880 if (!keep)
2881 new_mirr_port = ds->num_ports;
2882 }
2883 if (new_mirr_port != general_params->mirr_port) {
2884 general_params->mirr_port = new_mirr_port;
2885
2886 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2887 0, general_params, true);
2888 if (rc < 0)
2889 return rc;
2890 }
2891
2892 if (ingress)
2893 mac[from].ing_mirr = enabled;
2894 else
2895 mac[from].egr_mirr = enabled;
2896
2897 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2898 &mac[from], true);
2899}
2900
2901static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2902 struct dsa_mall_mirror_tc_entry *mirror,
2903 bool ingress, struct netlink_ext_ack *extack)
2904{
2905 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2906 ingress, true);
2907}
2908
2909static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2910 struct dsa_mall_mirror_tc_entry *mirror)
2911{
2912 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2913 mirror->ingress, false);
2914}
2915
2916static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2917 struct dsa_mall_policer_tc_entry *policer)
2918{
2919 struct sja1105_l2_policing_entry *policing;
2920 struct sja1105_private *priv = ds->priv;
2921
2922 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2923
2924 /* In hardware, every 8 microseconds the credit level is incremented by
2925 * the value of RATE bytes divided by 64, up to a maximum of SMAX
2926 * bytes.
2927 */
2928 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2929 1000000);
2930 policing[port].smax = policer->burst;
2931
2932 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2933}
2934
2935static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2936{
2937 struct sja1105_l2_policing_entry *policing;
2938 struct sja1105_private *priv = ds->priv;
2939
2940 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2941
2942 policing[port].rate = SJA1105_RATE_MBPS(1000);
2943 policing[port].smax = 65535;
2944
2945 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2946}
2947
2948static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2949 bool enabled)
2950{
2951 struct sja1105_mac_config_entry *mac;
2952
2953 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2954
2955 mac[port].dyn_learn = enabled;
2956
2957 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2958 &mac[port], true);
2959}
2960
2961static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2962 struct switchdev_brport_flags flags)
2963{
2964 if (flags.mask & BR_FLOOD) {
2965 if (flags.val & BR_FLOOD)
2966 priv->ucast_egress_floods |= BIT(to);
2967 else
2968 priv->ucast_egress_floods &= ~BIT(to);
2969 }
2970
2971 if (flags.mask & BR_BCAST_FLOOD) {
2972 if (flags.val & BR_BCAST_FLOOD)
2973 priv->bcast_egress_floods |= BIT(to);
2974 else
2975 priv->bcast_egress_floods &= ~BIT(to);
2976 }
2977
2978 return sja1105_manage_flood_domains(priv);
2979}
2980
2981static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2982 struct switchdev_brport_flags flags,
2983 struct netlink_ext_ack *extack)
2984{
2985 struct sja1105_l2_lookup_entry *l2_lookup;
2986 struct sja1105_table *table;
2987 int match, rc;
2988
2989 mutex_lock(&priv->fdb_lock);
2990
2991 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2992 l2_lookup = table->entries;
2993
2994 for (match = 0; match < table->entry_count; match++)
2995 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2996 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2997 break;
2998
2999 if (match == table->entry_count) {
3000 NL_SET_ERR_MSG_MOD(extack,
3001 "Could not find FDB entry for unknown multicast");
3002 rc = -ENOSPC;
3003 goto out;
3004 }
3005
3006 if (flags.val & BR_MCAST_FLOOD)
3007 l2_lookup[match].destports |= BIT(to);
3008 else
3009 l2_lookup[match].destports &= ~BIT(to);
3010
3011 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
3012 l2_lookup[match].index,
3013 &l2_lookup[match], true);
3014out:
3015 mutex_unlock(&priv->fdb_lock);
3016
3017 return rc;
3018}
3019
3020static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3021 struct switchdev_brport_flags flags,
3022 struct netlink_ext_ack *extack)
3023{
3024 struct sja1105_private *priv = ds->priv;
3025
3026 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
3027 BR_BCAST_FLOOD))
3028 return -EINVAL;
3029
3030 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
3031 !priv->info->can_limit_mcast_flood) {
3032 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
3033 bool unicast = !!(flags.val & BR_FLOOD);
3034
3035 if (unicast != multicast) {
3036 NL_SET_ERR_MSG_MOD(extack,
3037 "This chip cannot configure multicast flooding independently of unicast");
3038 return -EINVAL;
3039 }
3040 }
3041
3042 return 0;
3043}
3044
3045static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
3046 struct switchdev_brport_flags flags,
3047 struct netlink_ext_ack *extack)
3048{
3049 struct sja1105_private *priv = ds->priv;
3050 int rc;
3051
3052 if (flags.mask & BR_LEARNING) {
3053 bool learn_ena = !!(flags.val & BR_LEARNING);
3054
3055 rc = sja1105_port_set_learning(priv, port, learn_ena);
3056 if (rc)
3057 return rc;
3058 }
3059
3060 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
3061 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
3062 if (rc)
3063 return rc;
3064 }
3065
3066 /* For chips that can't offload BR_MCAST_FLOOD independently, there
3067 * is nothing to do here, we ensured the configuration is in sync by
3068 * offloading BR_FLOOD.
3069 */
3070 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3071 rc = sja1105_port_mcast_flood(priv, port, flags,
3072 extack);
3073 if (rc)
3074 return rc;
3075 }
3076
3077 return 0;
3078}
3079
3080/* The programming model for the SJA1105 switch is "all-at-once" via static
3081 * configuration tables. Some of these can be dynamically modified at runtime,
3082 * but not the xMII mode parameters table.
3083 * Furthermode, some PHYs may not have crystals for generating their clocks
3084 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3085 * ref_clk pin. So port clocking needs to be initialized early, before
3086 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3087 * Setting correct PHY link speed does not matter now.
3088 * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY
3089 * bindings are not yet parsed by DSA core. We need to parse early so that we
3090 * can populate the xMII mode parameters table.
3091 */
3092static int sja1105_setup(struct dsa_switch *ds)
3093{
3094 struct sja1105_private *priv = ds->priv;
3095 int rc;
3096
3097 if (priv->info->disable_microcontroller) {
3098 rc = priv->info->disable_microcontroller(priv);
3099 if (rc < 0) {
3100 dev_err(ds->dev,
3101 "Failed to disable microcontroller: %pe\n",
3102 ERR_PTR(rc));
3103 return rc;
3104 }
3105 }
3106
3107 /* Create and send configuration down to device */
3108 rc = sja1105_static_config_load(priv);
3109 if (rc < 0) {
3110 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3111 return rc;
3112 }
3113
3114 /* Configure the CGU (PHY link modes and speeds) */
3115 if (priv->info->clocking_setup) {
3116 rc = priv->info->clocking_setup(priv);
3117 if (rc < 0) {
3118 dev_err(ds->dev,
3119 "Failed to configure MII clocking: %pe\n",
3120 ERR_PTR(rc));
3121 goto out_static_config_free;
3122 }
3123 }
3124
3125 sja1105_tas_setup(ds);
3126 sja1105_flower_setup(ds);
3127
3128 rc = sja1105_ptp_clock_register(ds);
3129 if (rc < 0) {
3130 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3131 goto out_flower_teardown;
3132 }
3133
3134 rc = sja1105_mdiobus_register(ds);
3135 if (rc < 0) {
3136 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3137 ERR_PTR(rc));
3138 goto out_ptp_clock_unregister;
3139 }
3140
3141 rc = sja1105_devlink_setup(ds);
3142 if (rc < 0)
3143 goto out_mdiobus_unregister;
3144
3145 rtnl_lock();
3146 rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3147 rtnl_unlock();
3148 if (rc)
3149 goto out_devlink_teardown;
3150
3151 /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3152 * The only thing we can do to disable it is lie about what the 802.1Q
3153 * EtherType is.
3154 * So it will still try to apply VLAN filtering, but all ingress
3155 * traffic (except frames received with EtherType of ETH_P_SJA1105)
3156 * will be internally tagged with a distorted VLAN header where the
3157 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3158 */
3159 ds->vlan_filtering_is_global = true;
3160 ds->fdb_isolation = true;
3161 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES;
3162
3163 /* Advertise the 8 egress queues */
3164 ds->num_tx_queues = SJA1105_NUM_TC;
3165
3166 ds->mtu_enforcement_ingress = true;
3167 ds->assisted_learning_on_cpu_port = true;
3168
3169 return 0;
3170
3171out_devlink_teardown:
3172 sja1105_devlink_teardown(ds);
3173out_mdiobus_unregister:
3174 sja1105_mdiobus_unregister(ds);
3175out_ptp_clock_unregister:
3176 sja1105_ptp_clock_unregister(ds);
3177out_flower_teardown:
3178 sja1105_flower_teardown(ds);
3179 sja1105_tas_teardown(ds);
3180out_static_config_free:
3181 sja1105_static_config_free(&priv->static_config);
3182
3183 return rc;
3184}
3185
3186static void sja1105_teardown(struct dsa_switch *ds)
3187{
3188 struct sja1105_private *priv = ds->priv;
3189
3190 rtnl_lock();
3191 dsa_tag_8021q_unregister(ds);
3192 rtnl_unlock();
3193
3194 sja1105_devlink_teardown(ds);
3195 sja1105_mdiobus_unregister(ds);
3196 sja1105_ptp_clock_unregister(ds);
3197 sja1105_flower_teardown(ds);
3198 sja1105_tas_teardown(ds);
3199 sja1105_static_config_free(&priv->static_config);
3200}
3201
3202static const struct phylink_mac_ops sja1105_phylink_mac_ops = {
3203 .mac_select_pcs = sja1105_mac_select_pcs,
3204 .mac_config = sja1105_mac_config,
3205 .mac_link_up = sja1105_mac_link_up,
3206 .mac_link_down = sja1105_mac_link_down,
3207};
3208
3209static const struct dsa_switch_ops sja1105_switch_ops = {
3210 .get_tag_protocol = sja1105_get_tag_protocol,
3211 .connect_tag_protocol = sja1105_connect_tag_protocol,
3212 .setup = sja1105_setup,
3213 .teardown = sja1105_teardown,
3214 .set_ageing_time = sja1105_set_ageing_time,
3215 .port_change_mtu = sja1105_change_mtu,
3216 .port_max_mtu = sja1105_get_max_mtu,
3217 .phylink_get_caps = sja1105_phylink_get_caps,
3218 .get_strings = sja1105_get_strings,
3219 .get_ethtool_stats = sja1105_get_ethtool_stats,
3220 .get_sset_count = sja1105_get_sset_count,
3221 .get_ts_info = sja1105_get_ts_info,
3222 .port_fdb_dump = sja1105_fdb_dump,
3223 .port_fdb_add = sja1105_fdb_add,
3224 .port_fdb_del = sja1105_fdb_del,
3225 .port_fast_age = sja1105_fast_age,
3226 .port_bridge_join = sja1105_bridge_join,
3227 .port_bridge_leave = sja1105_bridge_leave,
3228 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags,
3229 .port_bridge_flags = sja1105_port_bridge_flags,
3230 .port_stp_state_set = sja1105_bridge_stp_state_set,
3231 .port_vlan_filtering = sja1105_vlan_filtering,
3232 .port_vlan_add = sja1105_bridge_vlan_add,
3233 .port_vlan_del = sja1105_bridge_vlan_del,
3234 .port_mdb_add = sja1105_mdb_add,
3235 .port_mdb_del = sja1105_mdb_del,
3236 .port_hwtstamp_get = sja1105_hwtstamp_get,
3237 .port_hwtstamp_set = sja1105_hwtstamp_set,
3238 .port_rxtstamp = sja1105_port_rxtstamp,
3239 .port_txtstamp = sja1105_port_txtstamp,
3240 .port_setup_tc = sja1105_port_setup_tc,
3241 .port_mirror_add = sja1105_mirror_add,
3242 .port_mirror_del = sja1105_mirror_del,
3243 .port_policer_add = sja1105_port_policer_add,
3244 .port_policer_del = sja1105_port_policer_del,
3245 .cls_flower_add = sja1105_cls_flower_add,
3246 .cls_flower_del = sja1105_cls_flower_del,
3247 .cls_flower_stats = sja1105_cls_flower_stats,
3248 .devlink_info_get = sja1105_devlink_info_get,
3249 .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add,
3250 .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del,
3251 .port_prechangeupper = sja1105_prechangeupper,
3252};
3253
3254static const struct of_device_id sja1105_dt_ids[];
3255
3256static int sja1105_check_device_id(struct sja1105_private *priv)
3257{
3258 const struct sja1105_regs *regs = priv->info->regs;
3259 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3260 struct device *dev = &priv->spidev->dev;
3261 const struct of_device_id *match;
3262 u32 device_id;
3263 u64 part_no;
3264 int rc;
3265
3266 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3267 NULL);
3268 if (rc < 0)
3269 return rc;
3270
3271 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3272 SJA1105_SIZE_DEVICE_ID);
3273 if (rc < 0)
3274 return rc;
3275
3276 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3277
3278 for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3279 const struct sja1105_info *info = match->data;
3280
3281 /* Is what's been probed in our match table at all? */
3282 if (info->device_id != device_id || info->part_no != part_no)
3283 continue;
3284
3285 /* But is it what's in the device tree? */
3286 if (priv->info->device_id != device_id ||
3287 priv->info->part_no != part_no) {
3288 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3289 priv->info->name, info->name);
3290 /* It isn't. No problem, pick that up. */
3291 priv->info = info;
3292 }
3293
3294 return 0;
3295 }
3296
3297 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3298 device_id, part_no);
3299
3300 return -ENODEV;
3301}
3302
3303static int sja1105_probe(struct spi_device *spi)
3304{
3305 struct device *dev = &spi->dev;
3306 struct sja1105_private *priv;
3307 size_t max_xfer, max_msg;
3308 struct dsa_switch *ds;
3309 int rc;
3310
3311 if (!dev->of_node) {
3312 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3313 return -EINVAL;
3314 }
3315
3316 rc = sja1105_hw_reset(dev, 1, 1);
3317 if (rc)
3318 return rc;
3319
3320 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3321 if (!priv)
3322 return -ENOMEM;
3323
3324 /* Populate our driver private structure (priv) based on
3325 * the device tree node that was probed (spi)
3326 */
3327 priv->spidev = spi;
3328 spi_set_drvdata(spi, priv);
3329
3330 /* Configure the SPI bus */
3331 spi->bits_per_word = 8;
3332 rc = spi_setup(spi);
3333 if (rc < 0) {
3334 dev_err(dev, "Could not init SPI\n");
3335 return rc;
3336 }
3337
3338 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3339 * a small one for the message header and another one for the current
3340 * chunk of the packed buffer.
3341 * Check that the restrictions imposed by the SPI controller are
3342 * respected: the chunk buffer is smaller than the max transfer size,
3343 * and the total length of the chunk plus its message header is smaller
3344 * than the max message size.
3345 * We do that during probe time since the maximum transfer size is a
3346 * runtime invariant.
3347 */
3348 max_xfer = spi_max_transfer_size(spi);
3349 max_msg = spi_max_message_size(spi);
3350
3351 /* We need to send at least one 64-bit word of SPI payload per message
3352 * in order to be able to make useful progress.
3353 */
3354 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3355 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3356 return -EINVAL;
3357 }
3358
3359 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3360 if (priv->max_xfer_len > max_xfer)
3361 priv->max_xfer_len = max_xfer;
3362 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3363 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3364
3365 priv->info = of_device_get_match_data(dev);
3366
3367 /* Detect hardware device */
3368 rc = sja1105_check_device_id(priv);
3369 if (rc < 0) {
3370 dev_err(dev, "Device ID check failed: %d\n", rc);
3371 return rc;
3372 }
3373
3374 dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3375
3376 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3377 if (!ds)
3378 return -ENOMEM;
3379
3380 ds->dev = dev;
3381 ds->num_ports = priv->info->num_ports;
3382 ds->ops = &sja1105_switch_ops;
3383 ds->phylink_mac_ops = &sja1105_phylink_mac_ops;
3384 ds->priv = priv;
3385 priv->ds = ds;
3386
3387 mutex_init(&priv->ptp_data.lock);
3388 mutex_init(&priv->dynamic_config_lock);
3389 mutex_init(&priv->mgmt_lock);
3390 mutex_init(&priv->fdb_lock);
3391 spin_lock_init(&priv->ts_id_lock);
3392
3393 rc = sja1105_parse_dt(priv);
3394 if (rc < 0) {
3395 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3396 return rc;
3397 }
3398
3399 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3400 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3401 sizeof(struct sja1105_cbs_entry),
3402 GFP_KERNEL);
3403 if (!priv->cbs)
3404 return -ENOMEM;
3405 }
3406
3407 return dsa_register_switch(priv->ds);
3408}
3409
3410static void sja1105_remove(struct spi_device *spi)
3411{
3412 struct sja1105_private *priv = spi_get_drvdata(spi);
3413
3414 if (!priv)
3415 return;
3416
3417 dsa_unregister_switch(priv->ds);
3418}
3419
3420static void sja1105_shutdown(struct spi_device *spi)
3421{
3422 struct sja1105_private *priv = spi_get_drvdata(spi);
3423
3424 if (!priv)
3425 return;
3426
3427 dsa_switch_shutdown(priv->ds);
3428
3429 spi_set_drvdata(spi, NULL);
3430}
3431
3432static const struct of_device_id sja1105_dt_ids[] = {
3433 { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3434 { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3435 { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3436 { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3437 { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3438 { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3439 { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3440 { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3441 { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3442 { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3443 { /* sentinel */ },
3444};
3445MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3446
3447static const struct spi_device_id sja1105_spi_ids[] = {
3448 { "sja1105e" },
3449 { "sja1105t" },
3450 { "sja1105p" },
3451 { "sja1105q" },
3452 { "sja1105r" },
3453 { "sja1105s" },
3454 { "sja1110a" },
3455 { "sja1110b" },
3456 { "sja1110c" },
3457 { "sja1110d" },
3458 { },
3459};
3460MODULE_DEVICE_TABLE(spi, sja1105_spi_ids);
3461
3462static struct spi_driver sja1105_driver = {
3463 .driver = {
3464 .name = "sja1105",
3465 .of_match_table = of_match_ptr(sja1105_dt_ids),
3466 },
3467 .id_table = sja1105_spi_ids,
3468 .probe = sja1105_probe,
3469 .remove = sja1105_remove,
3470 .shutdown = sja1105_shutdown,
3471};
3472
3473module_spi_driver(sja1105_driver);
3474
3475MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3476MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3477MODULE_DESCRIPTION("SJA1105 Driver");
3478MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
4 */
5
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <linux/delay.h>
9#include <linux/module.h>
10#include <linux/printk.h>
11#include <linux/spi/spi.h>
12#include <linux/errno.h>
13#include <linux/gpio/consumer.h>
14#include <linux/phylink.h>
15#include <linux/of.h>
16#include <linux/of_net.h>
17#include <linux/of_mdio.h>
18#include <linux/of_device.h>
19#include <linux/pcs/pcs-xpcs.h>
20#include <linux/netdev_features.h>
21#include <linux/netdevice.h>
22#include <linux/if_bridge.h>
23#include <linux/if_ether.h>
24#include <linux/dsa/8021q.h>
25#include "sja1105.h"
26#include "sja1105_tas.h"
27
28#define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
29#define SJA1105_DEFAULT_VLAN (VLAN_N_VID - 1)
30
31static const struct dsa_switch_ops sja1105_switch_ops;
32
33static void sja1105_hw_reset(struct gpio_desc *gpio, unsigned int pulse_len,
34 unsigned int startup_delay)
35{
36 gpiod_set_value_cansleep(gpio, 1);
37 /* Wait for minimum reset pulse length */
38 msleep(pulse_len);
39 gpiod_set_value_cansleep(gpio, 0);
40 /* Wait until chip is ready after reset */
41 msleep(startup_delay);
42}
43
44static void
45sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
46 int from, int to, bool allow)
47{
48 if (allow)
49 l2_fwd[from].reach_port |= BIT(to);
50 else
51 l2_fwd[from].reach_port &= ~BIT(to);
52}
53
54static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
55 int from, int to)
56{
57 return !!(l2_fwd[from].reach_port & BIT(to));
58}
59
60static int sja1105_init_mac_settings(struct sja1105_private *priv)
61{
62 struct sja1105_mac_config_entry default_mac = {
63 /* Enable all 8 priority queues on egress.
64 * Every queue i holds top[i] - base[i] frames.
65 * Sum of top[i] - base[i] is 511 (max hardware limit).
66 */
67 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
68 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
69 .enabled = {true, true, true, true, true, true, true, true},
70 /* Keep standard IFG of 12 bytes on egress. */
71 .ifg = 0,
72 /* Always put the MAC speed in automatic mode, where it can be
73 * adjusted at runtime by PHYLINK.
74 */
75 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
76 /* No static correction for 1-step 1588 events */
77 .tp_delin = 0,
78 .tp_delout = 0,
79 /* Disable aging for critical TTEthernet traffic */
80 .maxage = 0xFF,
81 /* Internal VLAN (pvid) to apply to untagged ingress */
82 .vlanprio = 0,
83 .vlanid = 1,
84 .ing_mirr = false,
85 .egr_mirr = false,
86 /* Don't drop traffic with other EtherType than ETH_P_IP */
87 .drpnona664 = false,
88 /* Don't drop double-tagged traffic */
89 .drpdtag = false,
90 /* Don't drop untagged traffic */
91 .drpuntag = false,
92 /* Don't retag 802.1p (VID 0) traffic with the pvid */
93 .retag = false,
94 /* Disable learning and I/O on user ports by default -
95 * STP will enable it.
96 */
97 .dyn_learn = false,
98 .egress = false,
99 .ingress = false,
100 };
101 struct sja1105_mac_config_entry *mac;
102 struct dsa_switch *ds = priv->ds;
103 struct sja1105_table *table;
104 int i;
105
106 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
107
108 /* Discard previous MAC Configuration Table */
109 if (table->entry_count) {
110 kfree(table->entries);
111 table->entry_count = 0;
112 }
113
114 table->entries = kcalloc(table->ops->max_entry_count,
115 table->ops->unpacked_entry_size, GFP_KERNEL);
116 if (!table->entries)
117 return -ENOMEM;
118
119 table->entry_count = table->ops->max_entry_count;
120
121 mac = table->entries;
122
123 for (i = 0; i < ds->num_ports; i++) {
124 mac[i] = default_mac;
125
126 /* Let sja1105_bridge_stp_state_set() keep address learning
127 * enabled for the CPU port.
128 */
129 if (dsa_is_cpu_port(ds, i))
130 priv->learn_ena |= BIT(i);
131 }
132
133 return 0;
134}
135
136static int sja1105_init_mii_settings(struct sja1105_private *priv)
137{
138 struct device *dev = &priv->spidev->dev;
139 struct sja1105_xmii_params_entry *mii;
140 struct dsa_switch *ds = priv->ds;
141 struct sja1105_table *table;
142 int i;
143
144 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
145
146 /* Discard previous xMII Mode Parameters Table */
147 if (table->entry_count) {
148 kfree(table->entries);
149 table->entry_count = 0;
150 }
151
152 table->entries = kcalloc(table->ops->max_entry_count,
153 table->ops->unpacked_entry_size, GFP_KERNEL);
154 if (!table->entries)
155 return -ENOMEM;
156
157 /* Override table based on PHYLINK DT bindings */
158 table->entry_count = table->ops->max_entry_count;
159
160 mii = table->entries;
161
162 for (i = 0; i < ds->num_ports; i++) {
163 sja1105_mii_role_t role = XMII_MAC;
164
165 if (dsa_is_unused_port(priv->ds, i))
166 continue;
167
168 switch (priv->phy_mode[i]) {
169 case PHY_INTERFACE_MODE_INTERNAL:
170 if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
171 goto unsupported;
172
173 mii->xmii_mode[i] = XMII_MODE_MII;
174 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
175 mii->special[i] = true;
176
177 break;
178 case PHY_INTERFACE_MODE_REVMII:
179 role = XMII_PHY;
180 fallthrough;
181 case PHY_INTERFACE_MODE_MII:
182 if (!priv->info->supports_mii[i])
183 goto unsupported;
184
185 mii->xmii_mode[i] = XMII_MODE_MII;
186 break;
187 case PHY_INTERFACE_MODE_REVRMII:
188 role = XMII_PHY;
189 fallthrough;
190 case PHY_INTERFACE_MODE_RMII:
191 if (!priv->info->supports_rmii[i])
192 goto unsupported;
193
194 mii->xmii_mode[i] = XMII_MODE_RMII;
195 break;
196 case PHY_INTERFACE_MODE_RGMII:
197 case PHY_INTERFACE_MODE_RGMII_ID:
198 case PHY_INTERFACE_MODE_RGMII_RXID:
199 case PHY_INTERFACE_MODE_RGMII_TXID:
200 if (!priv->info->supports_rgmii[i])
201 goto unsupported;
202
203 mii->xmii_mode[i] = XMII_MODE_RGMII;
204 break;
205 case PHY_INTERFACE_MODE_SGMII:
206 if (!priv->info->supports_sgmii[i])
207 goto unsupported;
208
209 mii->xmii_mode[i] = XMII_MODE_SGMII;
210 mii->special[i] = true;
211 break;
212 case PHY_INTERFACE_MODE_2500BASEX:
213 if (!priv->info->supports_2500basex[i])
214 goto unsupported;
215
216 mii->xmii_mode[i] = XMII_MODE_SGMII;
217 mii->special[i] = true;
218 break;
219unsupported:
220 default:
221 dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
222 phy_modes(priv->phy_mode[i]), i);
223 return -EINVAL;
224 }
225
226 mii->phy_mac[i] = role;
227 }
228 return 0;
229}
230
231static int sja1105_init_static_fdb(struct sja1105_private *priv)
232{
233 struct sja1105_l2_lookup_entry *l2_lookup;
234 struct sja1105_table *table;
235 int port;
236
237 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
238
239 /* We only populate the FDB table through dynamic L2 Address Lookup
240 * entries, except for a special entry at the end which is a catch-all
241 * for unknown multicast and will be used to control flooding domain.
242 */
243 if (table->entry_count) {
244 kfree(table->entries);
245 table->entry_count = 0;
246 }
247
248 if (!priv->info->can_limit_mcast_flood)
249 return 0;
250
251 table->entries = kcalloc(1, table->ops->unpacked_entry_size,
252 GFP_KERNEL);
253 if (!table->entries)
254 return -ENOMEM;
255
256 table->entry_count = 1;
257 l2_lookup = table->entries;
258
259 /* All L2 multicast addresses have an odd first octet */
260 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
261 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
262 l2_lookup[0].lockeds = true;
263 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
264
265 /* Flood multicast to every port by default */
266 for (port = 0; port < priv->ds->num_ports; port++)
267 if (!dsa_is_unused_port(priv->ds, port))
268 l2_lookup[0].destports |= BIT(port);
269
270 return 0;
271}
272
273static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
274{
275 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
276 /* Learned FDB entries are forgotten after 300 seconds */
277 .maxage = SJA1105_AGEING_TIME_MS(300000),
278 /* All entries within a FDB bin are available for learning */
279 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
280 /* And the P/Q/R/S equivalent setting: */
281 .start_dynspc = 0,
282 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
283 .poly = 0x97,
284 /* This selects between Independent VLAN Learning (IVL) and
285 * Shared VLAN Learning (SVL)
286 */
287 .shared_learn = true,
288 /* Don't discard management traffic based on ENFPORT -
289 * we don't perform SMAC port enforcement anyway, so
290 * what we are setting here doesn't matter.
291 */
292 .no_enf_hostprt = false,
293 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
294 * Maybe correlate with no_linklocal_learn from bridge driver?
295 */
296 .no_mgmt_learn = true,
297 /* P/Q/R/S only */
298 .use_static = true,
299 /* Dynamically learned FDB entries can overwrite other (older)
300 * dynamic FDB entries
301 */
302 .owr_dyn = true,
303 .drpnolearn = true,
304 };
305 struct dsa_switch *ds = priv->ds;
306 int port, num_used_ports = 0;
307 struct sja1105_table *table;
308 u64 max_fdb_entries;
309
310 for (port = 0; port < ds->num_ports; port++)
311 if (!dsa_is_unused_port(ds, port))
312 num_used_ports++;
313
314 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
315
316 for (port = 0; port < ds->num_ports; port++) {
317 if (dsa_is_unused_port(ds, port))
318 continue;
319
320 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
321 }
322
323 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
324
325 if (table->entry_count) {
326 kfree(table->entries);
327 table->entry_count = 0;
328 }
329
330 table->entries = kcalloc(table->ops->max_entry_count,
331 table->ops->unpacked_entry_size, GFP_KERNEL);
332 if (!table->entries)
333 return -ENOMEM;
334
335 table->entry_count = table->ops->max_entry_count;
336
337 /* This table only has a single entry */
338 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
339 default_l2_lookup_params;
340
341 return 0;
342}
343
344/* Set up a default VLAN for untagged traffic injected from the CPU
345 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
346 * All DT-defined ports are members of this VLAN, and there are no
347 * restrictions on forwarding (since the CPU selects the destination).
348 * Frames from this VLAN will always be transmitted as untagged, and
349 * neither the bridge nor the 8021q module cannot create this VLAN ID.
350 */
351static int sja1105_init_static_vlan(struct sja1105_private *priv)
352{
353 struct sja1105_table *table;
354 struct sja1105_vlan_lookup_entry pvid = {
355 .type_entry = SJA1110_VLAN_D_TAG,
356 .ving_mirr = 0,
357 .vegr_mirr = 0,
358 .vmemb_port = 0,
359 .vlan_bc = 0,
360 .tag_port = 0,
361 .vlanid = SJA1105_DEFAULT_VLAN,
362 };
363 struct dsa_switch *ds = priv->ds;
364 int port;
365
366 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
367
368 if (table->entry_count) {
369 kfree(table->entries);
370 table->entry_count = 0;
371 }
372
373 table->entries = kzalloc(table->ops->unpacked_entry_size,
374 GFP_KERNEL);
375 if (!table->entries)
376 return -ENOMEM;
377
378 table->entry_count = 1;
379
380 for (port = 0; port < ds->num_ports; port++) {
381 struct sja1105_bridge_vlan *v;
382
383 if (dsa_is_unused_port(ds, port))
384 continue;
385
386 pvid.vmemb_port |= BIT(port);
387 pvid.vlan_bc |= BIT(port);
388 pvid.tag_port &= ~BIT(port);
389
390 v = kzalloc(sizeof(*v), GFP_KERNEL);
391 if (!v)
392 return -ENOMEM;
393
394 v->port = port;
395 v->vid = SJA1105_DEFAULT_VLAN;
396 v->untagged = true;
397 if (dsa_is_cpu_port(ds, port))
398 v->pvid = true;
399 list_add(&v->list, &priv->dsa_8021q_vlans);
400
401 v = kmemdup(v, sizeof(*v), GFP_KERNEL);
402 if (!v)
403 return -ENOMEM;
404
405 list_add(&v->list, &priv->bridge_vlans);
406 }
407
408 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
409 return 0;
410}
411
412static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
413{
414 struct sja1105_l2_forwarding_entry *l2fwd;
415 struct dsa_switch *ds = priv->ds;
416 struct sja1105_table *table;
417 int i, j;
418
419 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
420
421 if (table->entry_count) {
422 kfree(table->entries);
423 table->entry_count = 0;
424 }
425
426 table->entries = kcalloc(table->ops->max_entry_count,
427 table->ops->unpacked_entry_size, GFP_KERNEL);
428 if (!table->entries)
429 return -ENOMEM;
430
431 table->entry_count = table->ops->max_entry_count;
432
433 l2fwd = table->entries;
434
435 /* First 5 entries define the forwarding rules */
436 for (i = 0; i < ds->num_ports; i++) {
437 unsigned int upstream = dsa_upstream_port(priv->ds, i);
438
439 if (dsa_is_unused_port(ds, i))
440 continue;
441
442 for (j = 0; j < SJA1105_NUM_TC; j++)
443 l2fwd[i].vlan_pmap[j] = j;
444
445 /* All ports start up with egress flooding enabled,
446 * including the CPU port.
447 */
448 priv->ucast_egress_floods |= BIT(i);
449 priv->bcast_egress_floods |= BIT(i);
450
451 if (i == upstream)
452 continue;
453
454 sja1105_port_allow_traffic(l2fwd, i, upstream, true);
455 sja1105_port_allow_traffic(l2fwd, upstream, i, true);
456
457 l2fwd[i].bc_domain = BIT(upstream);
458 l2fwd[i].fl_domain = BIT(upstream);
459
460 l2fwd[upstream].bc_domain |= BIT(i);
461 l2fwd[upstream].fl_domain |= BIT(i);
462 }
463
464 /* Next 8 entries define VLAN PCP mapping from ingress to egress.
465 * Create a one-to-one mapping.
466 */
467 for (i = 0; i < SJA1105_NUM_TC; i++) {
468 for (j = 0; j < ds->num_ports; j++) {
469 if (dsa_is_unused_port(ds, j))
470 continue;
471
472 l2fwd[ds->num_ports + i].vlan_pmap[j] = i;
473 }
474
475 l2fwd[ds->num_ports + i].type_egrpcp2outputq = true;
476 }
477
478 return 0;
479}
480
481static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
482{
483 struct sja1110_pcp_remapping_entry *pcp_remap;
484 struct dsa_switch *ds = priv->ds;
485 struct sja1105_table *table;
486 int port, tc;
487
488 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
489
490 /* Nothing to do for SJA1105 */
491 if (!table->ops->max_entry_count)
492 return 0;
493
494 if (table->entry_count) {
495 kfree(table->entries);
496 table->entry_count = 0;
497 }
498
499 table->entries = kcalloc(table->ops->max_entry_count,
500 table->ops->unpacked_entry_size, GFP_KERNEL);
501 if (!table->entries)
502 return -ENOMEM;
503
504 table->entry_count = table->ops->max_entry_count;
505
506 pcp_remap = table->entries;
507
508 /* Repeat the configuration done for vlan_pmap */
509 for (port = 0; port < ds->num_ports; port++) {
510 if (dsa_is_unused_port(ds, port))
511 continue;
512
513 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
514 pcp_remap[port].egrpcp[tc] = tc;
515 }
516
517 return 0;
518}
519
520static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
521{
522 struct sja1105_l2_forwarding_params_entry *l2fwd_params;
523 struct sja1105_table *table;
524
525 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
526
527 if (table->entry_count) {
528 kfree(table->entries);
529 table->entry_count = 0;
530 }
531
532 table->entries = kcalloc(table->ops->max_entry_count,
533 table->ops->unpacked_entry_size, GFP_KERNEL);
534 if (!table->entries)
535 return -ENOMEM;
536
537 table->entry_count = table->ops->max_entry_count;
538
539 /* This table only has a single entry */
540 l2fwd_params = table->entries;
541
542 /* Disallow dynamic reconfiguration of vlan_pmap */
543 l2fwd_params->max_dynp = 0;
544 /* Use a single memory partition for all ingress queues */
545 l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
546
547 return 0;
548}
549
550void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
551{
552 struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
553 struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
554 int max_mem = priv->info->max_frame_mem;
555 struct sja1105_table *table;
556
557 /* VLAN retagging is implemented using a loopback port that consumes
558 * frame buffers. That leaves less for us.
559 */
560 if (priv->vlan_state == SJA1105_VLAN_BEST_EFFORT)
561 max_mem -= SJA1105_FRAME_MEMORY_RETAGGING_OVERHEAD;
562
563 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
564 l2_fwd_params = table->entries;
565 l2_fwd_params->part_spc[0] = max_mem;
566
567 /* If we have any critical-traffic virtual links, we need to reserve
568 * some frame buffer memory for them. At the moment, hardcode the value
569 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
570 * remaining for best-effort traffic. TODO: figure out a more flexible
571 * way to perform the frame buffer partitioning.
572 */
573 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
574 return;
575
576 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
577 vl_fwd_params = table->entries;
578
579 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
580 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
581}
582
583/* SJA1110 TDMACONFIGIDX values:
584 *
585 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports
586 * -----+----------------+---------------+---------------+---------------
587 * 0 | 0, [5:10] | [1:2] | [3:4] | retag
588 * 1 |0, [5:10], retag| [1:2] | [3:4] | -
589 * 2 | 0, [5:10] | [1:3], retag | 4 | -
590 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -
591 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -
592 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -
593 * 14 | 0, [5:10] | [1:4], retag | - | -
594 * 15 | [5:10] | [0:4], retag | - | -
595 */
596static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
597{
598 struct sja1105_general_params_entry *general_params;
599 struct sja1105_table *table;
600 bool port_1_is_base_tx;
601 bool port_3_is_2500;
602 bool port_4_is_2500;
603 u64 tdmaconfigidx;
604
605 if (priv->info->device_id != SJA1110_DEVICE_ID)
606 return;
607
608 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
609 general_params = table->entries;
610
611 /* All the settings below are "as opposed to SGMII", which is the
612 * other pinmuxing option.
613 */
614 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
615 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
616 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
617
618 if (port_1_is_base_tx)
619 /* Retagging port will operate at 1 Gbps */
620 tdmaconfigidx = 5;
621 else if (port_3_is_2500 && port_4_is_2500)
622 /* Retagging port will operate at 100 Mbps */
623 tdmaconfigidx = 1;
624 else if (port_3_is_2500)
625 /* Retagging port will operate at 1 Gbps */
626 tdmaconfigidx = 3;
627 else if (port_4_is_2500)
628 /* Retagging port will operate at 1 Gbps */
629 tdmaconfigidx = 2;
630 else
631 /* Retagging port will operate at 1 Gbps */
632 tdmaconfigidx = 14;
633
634 general_params->tdmaconfigidx = tdmaconfigidx;
635}
636
637static int sja1105_init_general_params(struct sja1105_private *priv)
638{
639 struct sja1105_general_params_entry default_general_params = {
640 /* Allow dynamic changing of the mirror port */
641 .mirr_ptacu = true,
642 .switchid = priv->ds->index,
643 /* Priority queue for link-local management frames
644 * (both ingress to and egress from CPU - PTP, STP etc)
645 */
646 .hostprio = 7,
647 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
648 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK,
649 .incl_srcpt1 = false,
650 .send_meta1 = false,
651 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
652 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK,
653 .incl_srcpt0 = false,
654 .send_meta0 = false,
655 /* The destination for traffic matching mac_fltres1 and
656 * mac_fltres0 on all ports except host_port. Such traffic
657 * receieved on host_port itself would be dropped, except
658 * by installing a temporary 'management route'
659 */
660 .host_port = priv->ds->num_ports,
661 /* Default to an invalid value */
662 .mirr_port = priv->ds->num_ports,
663 /* No TTEthernet */
664 .vllupformat = SJA1105_VL_FORMAT_PSFP,
665 .vlmarker = 0,
666 .vlmask = 0,
667 /* Only update correctionField for 1-step PTP (L2 transport) */
668 .ignore2stf = 0,
669 /* Forcefully disable VLAN filtering by telling
670 * the switch that VLAN has a different EtherType.
671 */
672 .tpid = ETH_P_SJA1105,
673 .tpid2 = ETH_P_SJA1105,
674 /* Enable the TTEthernet engine on SJA1110 */
675 .tte_en = true,
676 /* Set up the EtherType for control packets on SJA1110 */
677 .header_type = ETH_P_SJA1110,
678 };
679 struct sja1105_general_params_entry *general_params;
680 struct dsa_switch *ds = priv->ds;
681 struct sja1105_table *table;
682 int port;
683
684 for (port = 0; port < ds->num_ports; port++) {
685 if (dsa_is_cpu_port(ds, port)) {
686 default_general_params.host_port = port;
687 break;
688 }
689 }
690
691 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
692
693 if (table->entry_count) {
694 kfree(table->entries);
695 table->entry_count = 0;
696 }
697
698 table->entries = kcalloc(table->ops->max_entry_count,
699 table->ops->unpacked_entry_size, GFP_KERNEL);
700 if (!table->entries)
701 return -ENOMEM;
702
703 table->entry_count = table->ops->max_entry_count;
704
705 general_params = table->entries;
706
707 /* This table only has a single entry */
708 general_params[0] = default_general_params;
709
710 sja1110_select_tdmaconfigidx(priv);
711
712 /* Link-local traffic received on casc_port will be forwarded
713 * to host_port without embedding the source port and device ID
714 * info in the destination MAC address, and no RX timestamps will be
715 * taken either (presumably because it is a cascaded port and a
716 * downstream SJA switch already did that).
717 * To disable the feature, we need to do different things depending on
718 * switch generation. On SJA1105 we need to set an invalid port, while
719 * on SJA1110 which support multiple cascaded ports, this field is a
720 * bitmask so it must be left zero.
721 */
722 if (!priv->info->multiple_cascade_ports)
723 general_params->casc_port = ds->num_ports;
724
725 return 0;
726}
727
728static int sja1105_init_avb_params(struct sja1105_private *priv)
729{
730 struct sja1105_avb_params_entry *avb;
731 struct sja1105_table *table;
732
733 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
734
735 /* Discard previous AVB Parameters Table */
736 if (table->entry_count) {
737 kfree(table->entries);
738 table->entry_count = 0;
739 }
740
741 table->entries = kcalloc(table->ops->max_entry_count,
742 table->ops->unpacked_entry_size, GFP_KERNEL);
743 if (!table->entries)
744 return -ENOMEM;
745
746 table->entry_count = table->ops->max_entry_count;
747
748 avb = table->entries;
749
750 /* Configure the MAC addresses for meta frames */
751 avb->destmeta = SJA1105_META_DMAC;
752 avb->srcmeta = SJA1105_META_SMAC;
753 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
754 * default. This is because there might be boards with a hardware
755 * layout where enabling the pin as output might cause an electrical
756 * clash. On E/T the pin is always an output, which the board designers
757 * probably already knew, so even if there are going to be electrical
758 * issues, there's nothing we can do.
759 */
760 avb->cas_master = false;
761
762 return 0;
763}
764
765/* The L2 policing table is 2-stage. The table is looked up for each frame
766 * according to the ingress port, whether it was broadcast or not, and the
767 * classified traffic class (given by VLAN PCP). This portion of the lookup is
768 * fixed, and gives access to the SHARINDX, an indirection register pointing
769 * within the policing table itself, which is used to resolve the policer that
770 * will be used for this frame.
771 *
772 * Stage 1 Stage 2
773 * +------------+--------+ +---------------------------------+
774 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |
775 * +------------+--------+ +---------------------------------+
776 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |
777 * +------------+--------+ +---------------------------------+
778 * ... | Policer 2: Rate, Burst, MTU |
779 * +------------+--------+ +---------------------------------+
780 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |
781 * +------------+--------+ +---------------------------------+
782 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |
783 * +------------+--------+ +---------------------------------+
784 * ... | Policer 5: Rate, Burst, MTU |
785 * +------------+--------+ +---------------------------------+
786 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |
787 * +------------+--------+ +---------------------------------+
788 * ... | Policer 7: Rate, Burst, MTU |
789 * +------------+--------+ +---------------------------------+
790 * |Port 4 TC 7 |SHARINDX| ...
791 * +------------+--------+
792 * |Port 0 BCAST|SHARINDX| ...
793 * +------------+--------+
794 * |Port 1 BCAST|SHARINDX| ...
795 * +------------+--------+
796 * ... ...
797 * +------------+--------+ +---------------------------------+
798 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |
799 * +------------+--------+ +---------------------------------+
800 *
801 * In this driver, we shall use policers 0-4 as statically alocated port
802 * (matchall) policers. So we need to make the SHARINDX for all lookups
803 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
804 * lookup) equal.
805 * The remaining policers (40) shall be dynamically allocated for flower
806 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
807 */
808#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
809
810static int sja1105_init_l2_policing(struct sja1105_private *priv)
811{
812 struct sja1105_l2_policing_entry *policing;
813 struct dsa_switch *ds = priv->ds;
814 struct sja1105_table *table;
815 int port, tc;
816
817 table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
818
819 /* Discard previous L2 Policing Table */
820 if (table->entry_count) {
821 kfree(table->entries);
822 table->entry_count = 0;
823 }
824
825 table->entries = kcalloc(table->ops->max_entry_count,
826 table->ops->unpacked_entry_size, GFP_KERNEL);
827 if (!table->entries)
828 return -ENOMEM;
829
830 table->entry_count = table->ops->max_entry_count;
831
832 policing = table->entries;
833
834 /* Setup shared indices for the matchall policers */
835 for (port = 0; port < ds->num_ports; port++) {
836 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
837 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
838
839 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
840 policing[port * SJA1105_NUM_TC + tc].sharindx = port;
841
842 policing[bcast].sharindx = port;
843 /* Only SJA1110 has multicast policers */
844 if (mcast <= table->ops->max_entry_count)
845 policing[mcast].sharindx = port;
846 }
847
848 /* Setup the matchall policer parameters */
849 for (port = 0; port < ds->num_ports; port++) {
850 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
851
852 if (dsa_is_cpu_port(priv->ds, port))
853 mtu += VLAN_HLEN;
854
855 policing[port].smax = 65535; /* Burst size in bytes */
856 policing[port].rate = SJA1105_RATE_MBPS(1000);
857 policing[port].maxlen = mtu;
858 policing[port].partition = 0;
859 }
860
861 return 0;
862}
863
864static int sja1105_static_config_load(struct sja1105_private *priv)
865{
866 int rc;
867
868 sja1105_static_config_free(&priv->static_config);
869 rc = sja1105_static_config_init(&priv->static_config,
870 priv->info->static_ops,
871 priv->info->device_id);
872 if (rc)
873 return rc;
874
875 /* Build static configuration */
876 rc = sja1105_init_mac_settings(priv);
877 if (rc < 0)
878 return rc;
879 rc = sja1105_init_mii_settings(priv);
880 if (rc < 0)
881 return rc;
882 rc = sja1105_init_static_fdb(priv);
883 if (rc < 0)
884 return rc;
885 rc = sja1105_init_static_vlan(priv);
886 if (rc < 0)
887 return rc;
888 rc = sja1105_init_l2_lookup_params(priv);
889 if (rc < 0)
890 return rc;
891 rc = sja1105_init_l2_forwarding(priv);
892 if (rc < 0)
893 return rc;
894 rc = sja1105_init_l2_forwarding_params(priv);
895 if (rc < 0)
896 return rc;
897 rc = sja1105_init_l2_policing(priv);
898 if (rc < 0)
899 return rc;
900 rc = sja1105_init_general_params(priv);
901 if (rc < 0)
902 return rc;
903 rc = sja1105_init_avb_params(priv);
904 if (rc < 0)
905 return rc;
906 rc = sja1110_init_pcp_remapping(priv);
907 if (rc < 0)
908 return rc;
909
910 /* Send initial configuration to hardware via SPI */
911 return sja1105_static_config_upload(priv);
912}
913
914static int sja1105_parse_rgmii_delays(struct sja1105_private *priv)
915{
916 struct dsa_switch *ds = priv->ds;
917 int port;
918
919 for (port = 0; port < ds->num_ports; port++) {
920 if (!priv->fixed_link[port])
921 continue;
922
923 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_RXID ||
924 priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID)
925 priv->rgmii_rx_delay[port] = true;
926
927 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_TXID ||
928 priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID)
929 priv->rgmii_tx_delay[port] = true;
930
931 if ((priv->rgmii_rx_delay[port] || priv->rgmii_tx_delay[port]) &&
932 !priv->info->setup_rgmii_delay)
933 return -EINVAL;
934 }
935 return 0;
936}
937
938static int sja1105_parse_ports_node(struct sja1105_private *priv,
939 struct device_node *ports_node)
940{
941 struct device *dev = &priv->spidev->dev;
942 struct device_node *child;
943
944 for_each_available_child_of_node(ports_node, child) {
945 struct device_node *phy_node;
946 phy_interface_t phy_mode;
947 u32 index;
948 int err;
949
950 /* Get switch port number from DT */
951 if (of_property_read_u32(child, "reg", &index) < 0) {
952 dev_err(dev, "Port number not defined in device tree "
953 "(property \"reg\")\n");
954 of_node_put(child);
955 return -ENODEV;
956 }
957
958 /* Get PHY mode from DT */
959 err = of_get_phy_mode(child, &phy_mode);
960 if (err) {
961 dev_err(dev, "Failed to read phy-mode or "
962 "phy-interface-type property for port %d\n",
963 index);
964 of_node_put(child);
965 return -ENODEV;
966 }
967
968 phy_node = of_parse_phandle(child, "phy-handle", 0);
969 if (!phy_node) {
970 if (!of_phy_is_fixed_link(child)) {
971 dev_err(dev, "phy-handle or fixed-link "
972 "properties missing!\n");
973 of_node_put(child);
974 return -ENODEV;
975 }
976 /* phy-handle is missing, but fixed-link isn't.
977 * So it's a fixed link. Default to PHY role.
978 */
979 priv->fixed_link[index] = true;
980 } else {
981 of_node_put(phy_node);
982 }
983
984 priv->phy_mode[index] = phy_mode;
985 }
986
987 return 0;
988}
989
990static int sja1105_parse_dt(struct sja1105_private *priv)
991{
992 struct device *dev = &priv->spidev->dev;
993 struct device_node *switch_node = dev->of_node;
994 struct device_node *ports_node;
995 int rc;
996
997 ports_node = of_get_child_by_name(switch_node, "ports");
998 if (!ports_node)
999 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1000 if (!ports_node) {
1001 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1002 return -ENODEV;
1003 }
1004
1005 rc = sja1105_parse_ports_node(priv, ports_node);
1006 of_node_put(ports_node);
1007
1008 return rc;
1009}
1010
1011/* Convert link speed from SJA1105 to ethtool encoding */
1012static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1013 u64 speed)
1014{
1015 if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1016 return SPEED_10;
1017 if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1018 return SPEED_100;
1019 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1020 return SPEED_1000;
1021 if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1022 return SPEED_2500;
1023 return SPEED_UNKNOWN;
1024}
1025
1026/* Set link speed in the MAC configuration for a specific port. */
1027static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1028 int speed_mbps)
1029{
1030 struct sja1105_mac_config_entry *mac;
1031 struct device *dev = priv->ds->dev;
1032 u64 speed;
1033 int rc;
1034
1035 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1036 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1037 * We have to *know* what the MAC looks like. For the sake of keeping
1038 * the code common, we'll use the static configuration tables as a
1039 * reasonable approximation for both E/T and P/Q/R/S.
1040 */
1041 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1042
1043 switch (speed_mbps) {
1044 case SPEED_UNKNOWN:
1045 /* PHYLINK called sja1105_mac_config() to inform us about
1046 * the state->interface, but AN has not completed and the
1047 * speed is not yet valid. UM10944.pdf says that setting
1048 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1049 * ok for power consumption in case AN will never complete -
1050 * otherwise PHYLINK should come back with a new update.
1051 */
1052 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1053 break;
1054 case SPEED_10:
1055 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1056 break;
1057 case SPEED_100:
1058 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1059 break;
1060 case SPEED_1000:
1061 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1062 break;
1063 case SPEED_2500:
1064 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1065 break;
1066 default:
1067 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1068 return -EINVAL;
1069 }
1070
1071 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1072 * table, since this will be used for the clocking setup, and we no
1073 * longer need to store it in the static config (already told hardware
1074 * we want auto during upload phase).
1075 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1076 * we need to configure the PCS only (if even that).
1077 */
1078 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1079 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1080 else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1081 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1082 else
1083 mac[port].speed = speed;
1084
1085 /* Write to the dynamic reconfiguration tables */
1086 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1087 &mac[port], true);
1088 if (rc < 0) {
1089 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1090 return rc;
1091 }
1092
1093 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1094 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1095 * RMII no change of the clock setup is required. Actually, changing
1096 * the clock setup does interrupt the clock signal for a certain time
1097 * which causes trouble for all PHYs relying on this signal.
1098 */
1099 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1100 return 0;
1101
1102 return sja1105_clocking_setup_port(priv, port);
1103}
1104
1105/* The SJA1105 MAC programming model is through the static config (the xMII
1106 * Mode table cannot be dynamically reconfigured), and we have to program
1107 * that early (earlier than PHYLINK calls us, anyway).
1108 * So just error out in case the connected PHY attempts to change the initial
1109 * system interface MII protocol from what is defined in the DT, at least for
1110 * now.
1111 */
1112static bool sja1105_phy_mode_mismatch(struct sja1105_private *priv, int port,
1113 phy_interface_t interface)
1114{
1115 return priv->phy_mode[port] != interface;
1116}
1117
1118static void sja1105_mac_config(struct dsa_switch *ds, int port,
1119 unsigned int mode,
1120 const struct phylink_link_state *state)
1121{
1122 struct dsa_port *dp = dsa_to_port(ds, port);
1123 struct sja1105_private *priv = ds->priv;
1124 struct dw_xpcs *xpcs;
1125
1126 if (sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1127 dev_err(ds->dev, "Changing PHY mode to %s not supported!\n",
1128 phy_modes(state->interface));
1129 return;
1130 }
1131
1132 xpcs = priv->xpcs[port];
1133
1134 if (xpcs)
1135 phylink_set_pcs(dp->pl, &xpcs->pcs);
1136}
1137
1138static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1139 unsigned int mode,
1140 phy_interface_t interface)
1141{
1142 sja1105_inhibit_tx(ds->priv, BIT(port), true);
1143}
1144
1145static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1146 unsigned int mode,
1147 phy_interface_t interface,
1148 struct phy_device *phydev,
1149 int speed, int duplex,
1150 bool tx_pause, bool rx_pause)
1151{
1152 struct sja1105_private *priv = ds->priv;
1153
1154 sja1105_adjust_port_config(priv, port, speed);
1155
1156 sja1105_inhibit_tx(priv, BIT(port), false);
1157}
1158
1159static void sja1105_phylink_validate(struct dsa_switch *ds, int port,
1160 unsigned long *supported,
1161 struct phylink_link_state *state)
1162{
1163 /* Construct a new mask which exhaustively contains all link features
1164 * supported by the MAC, and then apply that (logical AND) to what will
1165 * be sent to the PHY for "marketing".
1166 */
1167 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1168 struct sja1105_private *priv = ds->priv;
1169 struct sja1105_xmii_params_entry *mii;
1170
1171 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1172
1173 /* include/linux/phylink.h says:
1174 * When @state->interface is %PHY_INTERFACE_MODE_NA, phylink
1175 * expects the MAC driver to return all supported link modes.
1176 */
1177 if (state->interface != PHY_INTERFACE_MODE_NA &&
1178 sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1179 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1180 return;
1181 }
1182
1183 /* The MAC does not support pause frames, and also doesn't
1184 * support half-duplex traffic modes.
1185 */
1186 phylink_set(mask, Autoneg);
1187 phylink_set(mask, MII);
1188 phylink_set(mask, 10baseT_Full);
1189 phylink_set(mask, 100baseT_Full);
1190 phylink_set(mask, 100baseT1_Full);
1191 if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1192 mii->xmii_mode[port] == XMII_MODE_SGMII)
1193 phylink_set(mask, 1000baseT_Full);
1194 if (priv->info->supports_2500basex[port]) {
1195 phylink_set(mask, 2500baseT_Full);
1196 phylink_set(mask, 2500baseX_Full);
1197 }
1198
1199 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
1200 bitmap_and(state->advertising, state->advertising, mask,
1201 __ETHTOOL_LINK_MODE_MASK_NBITS);
1202}
1203
1204static int
1205sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1206 const struct sja1105_l2_lookup_entry *requested)
1207{
1208 struct sja1105_l2_lookup_entry *l2_lookup;
1209 struct sja1105_table *table;
1210 int i;
1211
1212 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1213 l2_lookup = table->entries;
1214
1215 for (i = 0; i < table->entry_count; i++)
1216 if (l2_lookup[i].macaddr == requested->macaddr &&
1217 l2_lookup[i].vlanid == requested->vlanid &&
1218 l2_lookup[i].destports & BIT(port))
1219 return i;
1220
1221 return -1;
1222}
1223
1224/* We want FDB entries added statically through the bridge command to persist
1225 * across switch resets, which are a common thing during normal SJA1105
1226 * operation. So we have to back them up in the static configuration tables
1227 * and hence apply them on next static config upload... yay!
1228 */
1229static int
1230sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1231 const struct sja1105_l2_lookup_entry *requested,
1232 bool keep)
1233{
1234 struct sja1105_l2_lookup_entry *l2_lookup;
1235 struct sja1105_table *table;
1236 int rc, match;
1237
1238 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1239
1240 match = sja1105_find_static_fdb_entry(priv, port, requested);
1241 if (match < 0) {
1242 /* Can't delete a missing entry. */
1243 if (!keep)
1244 return 0;
1245
1246 /* No match => new entry */
1247 rc = sja1105_table_resize(table, table->entry_count + 1);
1248 if (rc)
1249 return rc;
1250
1251 match = table->entry_count - 1;
1252 }
1253
1254 /* Assign pointer after the resize (it may be new memory) */
1255 l2_lookup = table->entries;
1256
1257 /* We have a match.
1258 * If the job was to add this FDB entry, it's already done (mostly
1259 * anyway, since the port forwarding mask may have changed, case in
1260 * which we update it).
1261 * Otherwise we have to delete it.
1262 */
1263 if (keep) {
1264 l2_lookup[match] = *requested;
1265 return 0;
1266 }
1267
1268 /* To remove, the strategy is to overwrite the element with
1269 * the last one, and then reduce the array size by 1
1270 */
1271 l2_lookup[match] = l2_lookup[table->entry_count - 1];
1272 return sja1105_table_resize(table, table->entry_count - 1);
1273}
1274
1275/* First-generation switches have a 4-way set associative TCAM that
1276 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1277 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1278 * For the placement of a newly learnt FDB entry, the switch selects the bin
1279 * based on a hash function, and the way within that bin incrementally.
1280 */
1281static int sja1105et_fdb_index(int bin, int way)
1282{
1283 return bin * SJA1105ET_FDB_BIN_SIZE + way;
1284}
1285
1286static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1287 const u8 *addr, u16 vid,
1288 struct sja1105_l2_lookup_entry *match,
1289 int *last_unused)
1290{
1291 int way;
1292
1293 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1294 struct sja1105_l2_lookup_entry l2_lookup = {0};
1295 int index = sja1105et_fdb_index(bin, way);
1296
1297 /* Skip unused entries, optionally marking them
1298 * into the return value
1299 */
1300 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1301 index, &l2_lookup)) {
1302 if (last_unused)
1303 *last_unused = way;
1304 continue;
1305 }
1306
1307 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1308 l2_lookup.vlanid == vid) {
1309 if (match)
1310 *match = l2_lookup;
1311 return way;
1312 }
1313 }
1314 /* Return an invalid entry index if not found */
1315 return -1;
1316}
1317
1318int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1319 const unsigned char *addr, u16 vid)
1320{
1321 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1322 struct sja1105_private *priv = ds->priv;
1323 struct device *dev = ds->dev;
1324 int last_unused = -1;
1325 int start, end, i;
1326 int bin, way, rc;
1327
1328 bin = sja1105et_fdb_hash(priv, addr, vid);
1329
1330 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1331 &l2_lookup, &last_unused);
1332 if (way >= 0) {
1333 /* We have an FDB entry. Is our port in the destination
1334 * mask? If yes, we need to do nothing. If not, we need
1335 * to rewrite the entry by adding this port to it.
1336 */
1337 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1338 return 0;
1339 l2_lookup.destports |= BIT(port);
1340 } else {
1341 int index = sja1105et_fdb_index(bin, way);
1342
1343 /* We don't have an FDB entry. We construct a new one and
1344 * try to find a place for it within the FDB table.
1345 */
1346 l2_lookup.macaddr = ether_addr_to_u64(addr);
1347 l2_lookup.destports = BIT(port);
1348 l2_lookup.vlanid = vid;
1349
1350 if (last_unused >= 0) {
1351 way = last_unused;
1352 } else {
1353 /* Bin is full, need to evict somebody.
1354 * Choose victim at random. If you get these messages
1355 * often, you may need to consider changing the
1356 * distribution function:
1357 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1358 */
1359 get_random_bytes(&way, sizeof(u8));
1360 way %= SJA1105ET_FDB_BIN_SIZE;
1361 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1362 bin, addr, way);
1363 /* Evict entry */
1364 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1365 index, NULL, false);
1366 }
1367 }
1368 l2_lookup.lockeds = true;
1369 l2_lookup.index = sja1105et_fdb_index(bin, way);
1370
1371 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1372 l2_lookup.index, &l2_lookup,
1373 true);
1374 if (rc < 0)
1375 return rc;
1376
1377 /* Invalidate a dynamically learned entry if that exists */
1378 start = sja1105et_fdb_index(bin, 0);
1379 end = sja1105et_fdb_index(bin, way);
1380
1381 for (i = start; i < end; i++) {
1382 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1383 i, &tmp);
1384 if (rc == -ENOENT)
1385 continue;
1386 if (rc)
1387 return rc;
1388
1389 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1390 continue;
1391
1392 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1393 i, NULL, false);
1394 if (rc)
1395 return rc;
1396
1397 break;
1398 }
1399
1400 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1401}
1402
1403int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1404 const unsigned char *addr, u16 vid)
1405{
1406 struct sja1105_l2_lookup_entry l2_lookup = {0};
1407 struct sja1105_private *priv = ds->priv;
1408 int index, bin, way, rc;
1409 bool keep;
1410
1411 bin = sja1105et_fdb_hash(priv, addr, vid);
1412 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1413 &l2_lookup, NULL);
1414 if (way < 0)
1415 return 0;
1416 index = sja1105et_fdb_index(bin, way);
1417
1418 /* We have an FDB entry. Is our port in the destination mask? If yes,
1419 * we need to remove it. If the resulting port mask becomes empty, we
1420 * need to completely evict the FDB entry.
1421 * Otherwise we just write it back.
1422 */
1423 l2_lookup.destports &= ~BIT(port);
1424
1425 if (l2_lookup.destports)
1426 keep = true;
1427 else
1428 keep = false;
1429
1430 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1431 index, &l2_lookup, keep);
1432 if (rc < 0)
1433 return rc;
1434
1435 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1436}
1437
1438int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1439 const unsigned char *addr, u16 vid)
1440{
1441 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1442 struct sja1105_private *priv = ds->priv;
1443 int rc, i;
1444
1445 /* Search for an existing entry in the FDB table */
1446 l2_lookup.macaddr = ether_addr_to_u64(addr);
1447 l2_lookup.vlanid = vid;
1448 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1449 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1450 l2_lookup.destports = BIT(port);
1451
1452 tmp = l2_lookup;
1453
1454 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1455 SJA1105_SEARCH, &tmp);
1456 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1457 /* Found a static entry and this port is already in the entry's
1458 * port mask => job done
1459 */
1460 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1461 return 0;
1462
1463 l2_lookup = tmp;
1464
1465 /* l2_lookup.index is populated by the switch in case it
1466 * found something.
1467 */
1468 l2_lookup.destports |= BIT(port);
1469 goto skip_finding_an_index;
1470 }
1471
1472 /* Not found, so try to find an unused spot in the FDB.
1473 * This is slightly inefficient because the strategy is knock-knock at
1474 * every possible position from 0 to 1023.
1475 */
1476 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1477 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1478 i, NULL);
1479 if (rc < 0)
1480 break;
1481 }
1482 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1483 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1484 return -EINVAL;
1485 }
1486 l2_lookup.index = i;
1487
1488skip_finding_an_index:
1489 l2_lookup.lockeds = true;
1490
1491 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1492 l2_lookup.index, &l2_lookup,
1493 true);
1494 if (rc < 0)
1495 return rc;
1496
1497 /* The switch learns dynamic entries and looks up the FDB left to
1498 * right. It is possible that our addition was concurrent with the
1499 * dynamic learning of the same address, so now that the static entry
1500 * has been installed, we are certain that address learning for this
1501 * particular address has been turned off, so the dynamic entry either
1502 * is in the FDB at an index smaller than the static one, or isn't (it
1503 * can also be at a larger index, but in that case it is inactive
1504 * because the static FDB entry will match first, and the dynamic one
1505 * will eventually age out). Search for a dynamically learned address
1506 * prior to our static one and invalidate it.
1507 */
1508 tmp = l2_lookup;
1509
1510 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1511 SJA1105_SEARCH, &tmp);
1512 if (rc < 0) {
1513 dev_err(ds->dev,
1514 "port %d failed to read back entry for %pM vid %d: %pe\n",
1515 port, addr, vid, ERR_PTR(rc));
1516 return rc;
1517 }
1518
1519 if (tmp.index < l2_lookup.index) {
1520 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1521 tmp.index, NULL, false);
1522 if (rc < 0)
1523 return rc;
1524 }
1525
1526 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1527}
1528
1529int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1530 const unsigned char *addr, u16 vid)
1531{
1532 struct sja1105_l2_lookup_entry l2_lookup = {0};
1533 struct sja1105_private *priv = ds->priv;
1534 bool keep;
1535 int rc;
1536
1537 l2_lookup.macaddr = ether_addr_to_u64(addr);
1538 l2_lookup.vlanid = vid;
1539 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1540 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1541 l2_lookup.destports = BIT(port);
1542
1543 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1544 SJA1105_SEARCH, &l2_lookup);
1545 if (rc < 0)
1546 return 0;
1547
1548 l2_lookup.destports &= ~BIT(port);
1549
1550 /* Decide whether we remove just this port from the FDB entry,
1551 * or if we remove it completely.
1552 */
1553 if (l2_lookup.destports)
1554 keep = true;
1555 else
1556 keep = false;
1557
1558 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1559 l2_lookup.index, &l2_lookup, keep);
1560 if (rc < 0)
1561 return rc;
1562
1563 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1564}
1565
1566static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1567 const unsigned char *addr, u16 vid)
1568{
1569 struct sja1105_private *priv = ds->priv;
1570
1571 /* dsa_8021q is in effect when the bridge's vlan_filtering isn't,
1572 * so the switch still does some VLAN processing internally.
1573 * But Shared VLAN Learning (SVL) is also active, and it will take
1574 * care of autonomous forwarding between the unique pvid's of each
1575 * port. Here we just make sure that users can't add duplicate FDB
1576 * entries when in this mode - the actual VID doesn't matter except
1577 * for what gets printed in 'bridge fdb show'. In the case of zero,
1578 * no VID gets printed at all.
1579 */
1580 if (priv->vlan_state != SJA1105_VLAN_FILTERING_FULL)
1581 vid = 0;
1582
1583 return priv->info->fdb_add_cmd(ds, port, addr, vid);
1584}
1585
1586static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1587 const unsigned char *addr, u16 vid)
1588{
1589 struct sja1105_private *priv = ds->priv;
1590
1591 if (priv->vlan_state != SJA1105_VLAN_FILTERING_FULL)
1592 vid = 0;
1593
1594 return priv->info->fdb_del_cmd(ds, port, addr, vid);
1595}
1596
1597static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1598 dsa_fdb_dump_cb_t *cb, void *data)
1599{
1600 struct sja1105_private *priv = ds->priv;
1601 struct device *dev = ds->dev;
1602 int i;
1603
1604 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1605 struct sja1105_l2_lookup_entry l2_lookup = {0};
1606 u8 macaddr[ETH_ALEN];
1607 int rc;
1608
1609 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1610 i, &l2_lookup);
1611 /* No fdb entry at i, not an issue */
1612 if (rc == -ENOENT)
1613 continue;
1614 if (rc) {
1615 dev_err(dev, "Failed to dump FDB: %d\n", rc);
1616 return rc;
1617 }
1618
1619 /* FDB dump callback is per port. This means we have to
1620 * disregard a valid entry if it's not for this port, even if
1621 * only to revisit it later. This is inefficient because the
1622 * 1024-sized FDB table needs to be traversed 4 times through
1623 * SPI during a 'bridge fdb show' command.
1624 */
1625 if (!(l2_lookup.destports & BIT(port)))
1626 continue;
1627
1628 /* We need to hide the FDB entry for unknown multicast */
1629 if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST &&
1630 l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
1631 continue;
1632
1633 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1634
1635 /* We need to hide the dsa_8021q VLANs from the user. */
1636 if (priv->vlan_state == SJA1105_VLAN_UNAWARE)
1637 l2_lookup.vlanid = 0;
1638 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1639 if (rc)
1640 return rc;
1641 }
1642 return 0;
1643}
1644
1645static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1646 const struct switchdev_obj_port_mdb *mdb)
1647{
1648 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid);
1649}
1650
1651static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1652 const struct switchdev_obj_port_mdb *mdb)
1653{
1654 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid);
1655}
1656
1657/* Common function for unicast and broadcast flood configuration.
1658 * Flooding is configured between each {ingress, egress} port pair, and since
1659 * the bridge's semantics are those of "egress flooding", it means we must
1660 * enable flooding towards this port from all ingress ports that are in the
1661 * same forwarding domain.
1662 */
1663static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1664{
1665 struct sja1105_l2_forwarding_entry *l2_fwd;
1666 struct dsa_switch *ds = priv->ds;
1667 int from, to, rc;
1668
1669 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1670
1671 for (from = 0; from < ds->num_ports; from++) {
1672 u64 fl_domain = 0, bc_domain = 0;
1673
1674 for (to = 0; to < priv->ds->num_ports; to++) {
1675 if (!sja1105_can_forward(l2_fwd, from, to))
1676 continue;
1677
1678 if (priv->ucast_egress_floods & BIT(to))
1679 fl_domain |= BIT(to);
1680 if (priv->bcast_egress_floods & BIT(to))
1681 bc_domain |= BIT(to);
1682 }
1683
1684 /* Nothing changed, nothing to do */
1685 if (l2_fwd[from].fl_domain == fl_domain &&
1686 l2_fwd[from].bc_domain == bc_domain)
1687 continue;
1688
1689 l2_fwd[from].fl_domain = fl_domain;
1690 l2_fwd[from].bc_domain = bc_domain;
1691
1692 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1693 from, &l2_fwd[from], true);
1694 if (rc < 0)
1695 return rc;
1696 }
1697
1698 return 0;
1699}
1700
1701static int sja1105_bridge_member(struct dsa_switch *ds, int port,
1702 struct net_device *br, bool member)
1703{
1704 struct sja1105_l2_forwarding_entry *l2_fwd;
1705 struct sja1105_private *priv = ds->priv;
1706 int i, rc;
1707
1708 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1709
1710 for (i = 0; i < ds->num_ports; i++) {
1711 /* Add this port to the forwarding matrix of the
1712 * other ports in the same bridge, and viceversa.
1713 */
1714 if (!dsa_is_user_port(ds, i))
1715 continue;
1716 /* For the ports already under the bridge, only one thing needs
1717 * to be done, and that is to add this port to their
1718 * reachability domain. So we can perform the SPI write for
1719 * them immediately. However, for this port itself (the one
1720 * that is new to the bridge), we need to add all other ports
1721 * to its reachability domain. So we do that incrementally in
1722 * this loop, and perform the SPI write only at the end, once
1723 * the domain contains all other bridge ports.
1724 */
1725 if (i == port)
1726 continue;
1727 if (dsa_to_port(ds, i)->bridge_dev != br)
1728 continue;
1729 sja1105_port_allow_traffic(l2_fwd, i, port, member);
1730 sja1105_port_allow_traffic(l2_fwd, port, i, member);
1731
1732 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1733 i, &l2_fwd[i], true);
1734 if (rc < 0)
1735 return rc;
1736 }
1737
1738 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1739 port, &l2_fwd[port], true);
1740 if (rc)
1741 return rc;
1742
1743 return sja1105_manage_flood_domains(priv);
1744}
1745
1746static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
1747 u8 state)
1748{
1749 struct sja1105_private *priv = ds->priv;
1750 struct sja1105_mac_config_entry *mac;
1751
1752 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1753
1754 switch (state) {
1755 case BR_STATE_DISABLED:
1756 case BR_STATE_BLOCKING:
1757 /* From UM10944 description of DRPDTAG (why put this there?):
1758 * "Management traffic flows to the port regardless of the state
1759 * of the INGRESS flag". So BPDUs are still be allowed to pass.
1760 * At the moment no difference between DISABLED and BLOCKING.
1761 */
1762 mac[port].ingress = false;
1763 mac[port].egress = false;
1764 mac[port].dyn_learn = false;
1765 break;
1766 case BR_STATE_LISTENING:
1767 mac[port].ingress = true;
1768 mac[port].egress = false;
1769 mac[port].dyn_learn = false;
1770 break;
1771 case BR_STATE_LEARNING:
1772 mac[port].ingress = true;
1773 mac[port].egress = false;
1774 mac[port].dyn_learn = !!(priv->learn_ena & BIT(port));
1775 break;
1776 case BR_STATE_FORWARDING:
1777 mac[port].ingress = true;
1778 mac[port].egress = true;
1779 mac[port].dyn_learn = !!(priv->learn_ena & BIT(port));
1780 break;
1781 default:
1782 dev_err(ds->dev, "invalid STP state: %d\n", state);
1783 return;
1784 }
1785
1786 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1787 &mac[port], true);
1788}
1789
1790static int sja1105_bridge_join(struct dsa_switch *ds, int port,
1791 struct net_device *br)
1792{
1793 return sja1105_bridge_member(ds, port, br, true);
1794}
1795
1796static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
1797 struct net_device *br)
1798{
1799 sja1105_bridge_member(ds, port, br, false);
1800}
1801
1802#define BYTES_PER_KBIT (1000LL / 8)
1803
1804static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
1805{
1806 int i;
1807
1808 for (i = 0; i < priv->info->num_cbs_shapers; i++)
1809 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
1810 return i;
1811
1812 return -1;
1813}
1814
1815static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
1816 int prio)
1817{
1818 int i;
1819
1820 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
1821 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
1822
1823 if (cbs->port == port && cbs->prio == prio) {
1824 memset(cbs, 0, sizeof(*cbs));
1825 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
1826 i, cbs, true);
1827 }
1828 }
1829
1830 return 0;
1831}
1832
1833static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
1834 struct tc_cbs_qopt_offload *offload)
1835{
1836 struct sja1105_private *priv = ds->priv;
1837 struct sja1105_cbs_entry *cbs;
1838 int index;
1839
1840 if (!offload->enable)
1841 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
1842
1843 index = sja1105_find_unused_cbs_shaper(priv);
1844 if (index < 0)
1845 return -ENOSPC;
1846
1847 cbs = &priv->cbs[index];
1848 cbs->port = port;
1849 cbs->prio = offload->queue;
1850 /* locredit and sendslope are negative by definition. In hardware,
1851 * positive values must be provided, and the negative sign is implicit.
1852 */
1853 cbs->credit_hi = offload->hicredit;
1854 cbs->credit_lo = abs(offload->locredit);
1855 /* User space is in kbits/sec, hardware in bytes/sec */
1856 cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT;
1857 cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT);
1858 /* Convert the negative values from 64-bit 2's complement
1859 * to 32-bit 2's complement (for the case of 0x80000000 whose
1860 * negative is still negative).
1861 */
1862 cbs->credit_lo &= GENMASK_ULL(31, 0);
1863 cbs->send_slope &= GENMASK_ULL(31, 0);
1864
1865 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
1866 true);
1867}
1868
1869static int sja1105_reload_cbs(struct sja1105_private *priv)
1870{
1871 int rc = 0, i;
1872
1873 /* The credit based shapers are only allocated if
1874 * CONFIG_NET_SCH_CBS is enabled.
1875 */
1876 if (!priv->cbs)
1877 return 0;
1878
1879 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
1880 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
1881
1882 if (!cbs->idle_slope && !cbs->send_slope)
1883 continue;
1884
1885 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
1886 true);
1887 if (rc)
1888 break;
1889 }
1890
1891 return rc;
1892}
1893
1894static const char * const sja1105_reset_reasons[] = {
1895 [SJA1105_VLAN_FILTERING] = "VLAN filtering",
1896 [SJA1105_RX_HWTSTAMPING] = "RX timestamping",
1897 [SJA1105_AGEING_TIME] = "Ageing time",
1898 [SJA1105_SCHEDULING] = "Time-aware scheduling",
1899 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
1900 [SJA1105_VIRTUAL_LINKS] = "Virtual links",
1901};
1902
1903/* For situations where we need to change a setting at runtime that is only
1904 * available through the static configuration, resetting the switch in order
1905 * to upload the new static config is unavoidable. Back up the settings we
1906 * modify at runtime (currently only MAC) and restore them after uploading,
1907 * such that this operation is relatively seamless.
1908 */
1909int sja1105_static_config_reload(struct sja1105_private *priv,
1910 enum sja1105_reset_reason reason)
1911{
1912 struct ptp_system_timestamp ptp_sts_before;
1913 struct ptp_system_timestamp ptp_sts_after;
1914 int speed_mbps[SJA1105_MAX_NUM_PORTS];
1915 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
1916 struct sja1105_mac_config_entry *mac;
1917 struct dsa_switch *ds = priv->ds;
1918 s64 t1, t2, t3, t4;
1919 s64 t12, t34;
1920 int rc, i;
1921 s64 now;
1922
1923 mutex_lock(&priv->mgmt_lock);
1924
1925 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1926
1927 /* Back up the dynamic link speed changed by sja1105_adjust_port_config
1928 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
1929 * switch wants to see in the static config in order to allow us to
1930 * change it through the dynamic interface later.
1931 */
1932 for (i = 0; i < ds->num_ports; i++) {
1933 u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1);
1934
1935 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
1936 mac[i].speed);
1937 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1938
1939 if (priv->xpcs[i])
1940 bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr);
1941 }
1942
1943 /* No PTP operations can run right now */
1944 mutex_lock(&priv->ptp_data.lock);
1945
1946 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
1947 if (rc < 0) {
1948 mutex_unlock(&priv->ptp_data.lock);
1949 goto out;
1950 }
1951
1952 /* Reset switch and send updated static configuration */
1953 rc = sja1105_static_config_upload(priv);
1954 if (rc < 0) {
1955 mutex_unlock(&priv->ptp_data.lock);
1956 goto out;
1957 }
1958
1959 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
1960 if (rc < 0) {
1961 mutex_unlock(&priv->ptp_data.lock);
1962 goto out;
1963 }
1964
1965 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
1966 t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
1967 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
1968 t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
1969 /* Mid point, corresponds to pre-reset PTPCLKVAL */
1970 t12 = t1 + (t2 - t1) / 2;
1971 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
1972 t34 = t3 + (t4 - t3) / 2;
1973 /* Advance PTPCLKVAL by the time it took since its readout */
1974 now += (t34 - t12);
1975
1976 __sja1105_ptp_adjtime(ds, now);
1977
1978 mutex_unlock(&priv->ptp_data.lock);
1979
1980 dev_info(priv->ds->dev,
1981 "Reset switch and programmed static config. Reason: %s\n",
1982 sja1105_reset_reasons[reason]);
1983
1984 /* Configure the CGU (PLLs) for MII and RMII PHYs.
1985 * For these interfaces there is no dynamic configuration
1986 * needed, since PLLs have same settings at all speeds.
1987 */
1988 if (priv->info->clocking_setup) {
1989 rc = priv->info->clocking_setup(priv);
1990 if (rc < 0)
1991 goto out;
1992 }
1993
1994 for (i = 0; i < ds->num_ports; i++) {
1995 struct dw_xpcs *xpcs = priv->xpcs[i];
1996 unsigned int mode;
1997
1998 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
1999 if (rc < 0)
2000 goto out;
2001
2002 if (!xpcs)
2003 continue;
2004
2005 if (bmcr[i] & BMCR_ANENABLE)
2006 mode = MLO_AN_INBAND;
2007 else if (priv->fixed_link[i])
2008 mode = MLO_AN_FIXED;
2009 else
2010 mode = MLO_AN_PHY;
2011
2012 rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
2013 if (rc < 0)
2014 goto out;
2015
2016 if (!phylink_autoneg_inband(mode)) {
2017 int speed = SPEED_UNKNOWN;
2018
2019 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2020 speed = SPEED_2500;
2021 else if (bmcr[i] & BMCR_SPEED1000)
2022 speed = SPEED_1000;
2023 else if (bmcr[i] & BMCR_SPEED100)
2024 speed = SPEED_100;
2025 else
2026 speed = SPEED_10;
2027
2028 xpcs_link_up(&xpcs->pcs, mode, priv->phy_mode[i],
2029 speed, DUPLEX_FULL);
2030 }
2031 }
2032
2033 rc = sja1105_reload_cbs(priv);
2034 if (rc < 0)
2035 goto out;
2036out:
2037 mutex_unlock(&priv->mgmt_lock);
2038
2039 return rc;
2040}
2041
2042static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
2043{
2044 struct sja1105_mac_config_entry *mac;
2045
2046 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2047
2048 mac[port].vlanid = pvid;
2049
2050 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2051 &mac[port], true);
2052}
2053
2054static int sja1105_crosschip_bridge_join(struct dsa_switch *ds,
2055 int tree_index, int sw_index,
2056 int other_port, struct net_device *br)
2057{
2058 struct dsa_switch *other_ds = dsa_switch_find(tree_index, sw_index);
2059 struct sja1105_private *other_priv = other_ds->priv;
2060 struct sja1105_private *priv = ds->priv;
2061 int port, rc;
2062
2063 if (other_ds->ops != &sja1105_switch_ops)
2064 return 0;
2065
2066 for (port = 0; port < ds->num_ports; port++) {
2067 if (!dsa_is_user_port(ds, port))
2068 continue;
2069 if (dsa_to_port(ds, port)->bridge_dev != br)
2070 continue;
2071
2072 rc = dsa_8021q_crosschip_bridge_join(priv->dsa_8021q_ctx,
2073 port,
2074 other_priv->dsa_8021q_ctx,
2075 other_port);
2076 if (rc)
2077 return rc;
2078
2079 rc = dsa_8021q_crosschip_bridge_join(other_priv->dsa_8021q_ctx,
2080 other_port,
2081 priv->dsa_8021q_ctx,
2082 port);
2083 if (rc)
2084 return rc;
2085 }
2086
2087 return 0;
2088}
2089
2090static void sja1105_crosschip_bridge_leave(struct dsa_switch *ds,
2091 int tree_index, int sw_index,
2092 int other_port,
2093 struct net_device *br)
2094{
2095 struct dsa_switch *other_ds = dsa_switch_find(tree_index, sw_index);
2096 struct sja1105_private *other_priv = other_ds->priv;
2097 struct sja1105_private *priv = ds->priv;
2098 int port;
2099
2100 if (other_ds->ops != &sja1105_switch_ops)
2101 return;
2102
2103 for (port = 0; port < ds->num_ports; port++) {
2104 if (!dsa_is_user_port(ds, port))
2105 continue;
2106 if (dsa_to_port(ds, port)->bridge_dev != br)
2107 continue;
2108
2109 dsa_8021q_crosschip_bridge_leave(priv->dsa_8021q_ctx, port,
2110 other_priv->dsa_8021q_ctx,
2111 other_port);
2112
2113 dsa_8021q_crosschip_bridge_leave(other_priv->dsa_8021q_ctx,
2114 other_port,
2115 priv->dsa_8021q_ctx, port);
2116 }
2117}
2118
2119static int sja1105_setup_8021q_tagging(struct dsa_switch *ds, bool enabled)
2120{
2121 struct sja1105_private *priv = ds->priv;
2122 int rc;
2123
2124 rc = dsa_8021q_setup(priv->dsa_8021q_ctx, enabled);
2125 if (rc)
2126 return rc;
2127
2128 dev_info(ds->dev, "%s switch tagging\n",
2129 enabled ? "Enabled" : "Disabled");
2130 return 0;
2131}
2132
2133static enum dsa_tag_protocol
2134sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2135 enum dsa_tag_protocol mp)
2136{
2137 struct sja1105_private *priv = ds->priv;
2138
2139 return priv->info->tag_proto;
2140}
2141
2142static int sja1105_find_free_subvlan(u16 *subvlan_map, bool pvid)
2143{
2144 int subvlan;
2145
2146 if (pvid)
2147 return 0;
2148
2149 for (subvlan = 1; subvlan < DSA_8021Q_N_SUBVLAN; subvlan++)
2150 if (subvlan_map[subvlan] == VLAN_N_VID)
2151 return subvlan;
2152
2153 return -1;
2154}
2155
2156static int sja1105_find_subvlan(u16 *subvlan_map, u16 vid)
2157{
2158 int subvlan;
2159
2160 for (subvlan = 0; subvlan < DSA_8021Q_N_SUBVLAN; subvlan++)
2161 if (subvlan_map[subvlan] == vid)
2162 return subvlan;
2163
2164 return -1;
2165}
2166
2167static int sja1105_find_committed_subvlan(struct sja1105_private *priv,
2168 int port, u16 vid)
2169{
2170 struct sja1105_port *sp = &priv->ports[port];
2171
2172 return sja1105_find_subvlan(sp->subvlan_map, vid);
2173}
2174
2175static void sja1105_init_subvlan_map(u16 *subvlan_map)
2176{
2177 int subvlan;
2178
2179 for (subvlan = 0; subvlan < DSA_8021Q_N_SUBVLAN; subvlan++)
2180 subvlan_map[subvlan] = VLAN_N_VID;
2181}
2182
2183static void sja1105_commit_subvlan_map(struct sja1105_private *priv, int port,
2184 u16 *subvlan_map)
2185{
2186 struct sja1105_port *sp = &priv->ports[port];
2187 int subvlan;
2188
2189 for (subvlan = 0; subvlan < DSA_8021Q_N_SUBVLAN; subvlan++)
2190 sp->subvlan_map[subvlan] = subvlan_map[subvlan];
2191}
2192
2193static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
2194{
2195 struct sja1105_vlan_lookup_entry *vlan;
2196 int count, i;
2197
2198 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
2199 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
2200
2201 for (i = 0; i < count; i++)
2202 if (vlan[i].vlanid == vid)
2203 return i;
2204
2205 /* Return an invalid entry index if not found */
2206 return -1;
2207}
2208
2209static int
2210sja1105_find_retagging_entry(struct sja1105_retagging_entry *retagging,
2211 int count, int from_port, u16 from_vid,
2212 u16 to_vid)
2213{
2214 int i;
2215
2216 for (i = 0; i < count; i++)
2217 if (retagging[i].ing_port == BIT(from_port) &&
2218 retagging[i].vlan_ing == from_vid &&
2219 retagging[i].vlan_egr == to_vid)
2220 return i;
2221
2222 /* Return an invalid entry index if not found */
2223 return -1;
2224}
2225
2226static int sja1105_commit_vlans(struct sja1105_private *priv,
2227 struct sja1105_vlan_lookup_entry *new_vlan,
2228 struct sja1105_retagging_entry *new_retagging,
2229 int num_retagging)
2230{
2231 struct sja1105_retagging_entry *retagging;
2232 struct sja1105_vlan_lookup_entry *vlan;
2233 struct sja1105_table *table;
2234 int num_vlans = 0;
2235 int rc, i, k = 0;
2236
2237 /* VLAN table */
2238 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2239 vlan = table->entries;
2240
2241 for (i = 0; i < VLAN_N_VID; i++) {
2242 int match = sja1105_is_vlan_configured(priv, i);
2243
2244 if (new_vlan[i].vlanid != VLAN_N_VID)
2245 num_vlans++;
2246
2247 if (new_vlan[i].vlanid == VLAN_N_VID && match >= 0) {
2248 /* Was there before, no longer is. Delete */
2249 dev_dbg(priv->ds->dev, "Deleting VLAN %d\n", i);
2250 rc = sja1105_dynamic_config_write(priv,
2251 BLK_IDX_VLAN_LOOKUP,
2252 i, &vlan[match], false);
2253 if (rc < 0)
2254 return rc;
2255 } else if (new_vlan[i].vlanid != VLAN_N_VID) {
2256 /* Nothing changed, don't do anything */
2257 if (match >= 0 &&
2258 vlan[match].vlanid == new_vlan[i].vlanid &&
2259 vlan[match].tag_port == new_vlan[i].tag_port &&
2260 vlan[match].vlan_bc == new_vlan[i].vlan_bc &&
2261 vlan[match].vmemb_port == new_vlan[i].vmemb_port)
2262 continue;
2263 /* Update entry */
2264 dev_dbg(priv->ds->dev, "Updating VLAN %d\n", i);
2265 rc = sja1105_dynamic_config_write(priv,
2266 BLK_IDX_VLAN_LOOKUP,
2267 i, &new_vlan[i],
2268 true);
2269 if (rc < 0)
2270 return rc;
2271 }
2272 }
2273
2274 if (table->entry_count)
2275 kfree(table->entries);
2276
2277 table->entries = kcalloc(num_vlans, table->ops->unpacked_entry_size,
2278 GFP_KERNEL);
2279 if (!table->entries)
2280 return -ENOMEM;
2281
2282 table->entry_count = num_vlans;
2283 vlan = table->entries;
2284
2285 for (i = 0; i < VLAN_N_VID; i++) {
2286 if (new_vlan[i].vlanid == VLAN_N_VID)
2287 continue;
2288 vlan[k++] = new_vlan[i];
2289 }
2290
2291 /* VLAN Retagging Table */
2292 table = &priv->static_config.tables[BLK_IDX_RETAGGING];
2293 retagging = table->entries;
2294
2295 for (i = 0; i < table->entry_count; i++) {
2296 rc = sja1105_dynamic_config_write(priv, BLK_IDX_RETAGGING,
2297 i, &retagging[i], false);
2298 if (rc)
2299 return rc;
2300 }
2301
2302 if (table->entry_count)
2303 kfree(table->entries);
2304
2305 table->entries = kcalloc(num_retagging, table->ops->unpacked_entry_size,
2306 GFP_KERNEL);
2307 if (!table->entries)
2308 return -ENOMEM;
2309
2310 table->entry_count = num_retagging;
2311 retagging = table->entries;
2312
2313 for (i = 0; i < num_retagging; i++) {
2314 retagging[i] = new_retagging[i];
2315
2316 /* Update entry */
2317 rc = sja1105_dynamic_config_write(priv, BLK_IDX_RETAGGING,
2318 i, &retagging[i], true);
2319 if (rc < 0)
2320 return rc;
2321 }
2322
2323 return 0;
2324}
2325
2326struct sja1105_crosschip_vlan {
2327 struct list_head list;
2328 u16 vid;
2329 bool untagged;
2330 int port;
2331 int other_port;
2332 struct dsa_8021q_context *other_ctx;
2333};
2334
2335struct sja1105_crosschip_switch {
2336 struct list_head list;
2337 struct dsa_8021q_context *other_ctx;
2338};
2339
2340static int sja1105_commit_pvid(struct sja1105_private *priv)
2341{
2342 struct sja1105_bridge_vlan *v;
2343 struct list_head *vlan_list;
2344 int rc = 0;
2345
2346 if (priv->vlan_state == SJA1105_VLAN_FILTERING_FULL)
2347 vlan_list = &priv->bridge_vlans;
2348 else
2349 vlan_list = &priv->dsa_8021q_vlans;
2350
2351 list_for_each_entry(v, vlan_list, list) {
2352 if (v->pvid) {
2353 rc = sja1105_pvid_apply(priv, v->port, v->vid);
2354 if (rc)
2355 break;
2356 }
2357 }
2358
2359 return rc;
2360}
2361
2362static int
2363sja1105_build_bridge_vlans(struct sja1105_private *priv,
2364 struct sja1105_vlan_lookup_entry *new_vlan)
2365{
2366 struct sja1105_bridge_vlan *v;
2367
2368 if (priv->vlan_state == SJA1105_VLAN_UNAWARE)
2369 return 0;
2370
2371 list_for_each_entry(v, &priv->bridge_vlans, list) {
2372 int match = v->vid;
2373
2374 new_vlan[match].vlanid = v->vid;
2375 new_vlan[match].vmemb_port |= BIT(v->port);
2376 new_vlan[match].vlan_bc |= BIT(v->port);
2377 if (!v->untagged)
2378 new_vlan[match].tag_port |= BIT(v->port);
2379 new_vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2380 }
2381
2382 return 0;
2383}
2384
2385static int
2386sja1105_build_dsa_8021q_vlans(struct sja1105_private *priv,
2387 struct sja1105_vlan_lookup_entry *new_vlan)
2388{
2389 struct sja1105_bridge_vlan *v;
2390
2391 if (priv->vlan_state == SJA1105_VLAN_FILTERING_FULL)
2392 return 0;
2393
2394 list_for_each_entry(v, &priv->dsa_8021q_vlans, list) {
2395 int match = v->vid;
2396
2397 new_vlan[match].vlanid = v->vid;
2398 new_vlan[match].vmemb_port |= BIT(v->port);
2399 new_vlan[match].vlan_bc |= BIT(v->port);
2400 if (!v->untagged)
2401 new_vlan[match].tag_port |= BIT(v->port);
2402 new_vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2403 }
2404
2405 return 0;
2406}
2407
2408static int sja1105_build_subvlans(struct sja1105_private *priv,
2409 u16 subvlan_map[][DSA_8021Q_N_SUBVLAN],
2410 struct sja1105_vlan_lookup_entry *new_vlan,
2411 struct sja1105_retagging_entry *new_retagging,
2412 int *num_retagging)
2413{
2414 struct sja1105_bridge_vlan *v;
2415 int k = *num_retagging;
2416
2417 if (priv->vlan_state != SJA1105_VLAN_BEST_EFFORT)
2418 return 0;
2419
2420 list_for_each_entry(v, &priv->bridge_vlans, list) {
2421 int upstream = dsa_upstream_port(priv->ds, v->port);
2422 int match, subvlan;
2423 u16 rx_vid;
2424
2425 /* Only sub-VLANs on user ports need to be applied.
2426 * Bridge VLANs also include VLANs added automatically
2427 * by DSA on the CPU port.
2428 */
2429 if (!dsa_is_user_port(priv->ds, v->port))
2430 continue;
2431
2432 subvlan = sja1105_find_subvlan(subvlan_map[v->port],
2433 v->vid);
2434 if (subvlan < 0) {
2435 subvlan = sja1105_find_free_subvlan(subvlan_map[v->port],
2436 v->pvid);
2437 if (subvlan < 0) {
2438 dev_err(priv->ds->dev, "No more free subvlans\n");
2439 return -ENOSPC;
2440 }
2441 }
2442
2443 rx_vid = dsa_8021q_rx_vid_subvlan(priv->ds, v->port, subvlan);
2444
2445 /* @v->vid on @v->port needs to be retagged to @rx_vid
2446 * on @upstream. Assume @v->vid on @v->port and on
2447 * @upstream was already configured by the previous
2448 * iteration over bridge_vlans.
2449 */
2450 match = rx_vid;
2451 new_vlan[match].vlanid = rx_vid;
2452 new_vlan[match].vmemb_port |= BIT(v->port);
2453 new_vlan[match].vmemb_port |= BIT(upstream);
2454 new_vlan[match].vlan_bc |= BIT(v->port);
2455 new_vlan[match].vlan_bc |= BIT(upstream);
2456 /* The "untagged" flag is set the same as for the
2457 * original VLAN
2458 */
2459 if (!v->untagged)
2460 new_vlan[match].tag_port |= BIT(v->port);
2461 /* But it's always tagged towards the CPU */
2462 new_vlan[match].tag_port |= BIT(upstream);
2463 new_vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2464
2465 /* The Retagging Table generates packet *clones* with
2466 * the new VLAN. This is a very odd hardware quirk
2467 * which we need to suppress by dropping the original
2468 * packet.
2469 * Deny egress of the original VLAN towards the CPU
2470 * port. This will force the switch to drop it, and
2471 * we'll see only the retagged packets.
2472 */
2473 match = v->vid;
2474 new_vlan[match].vlan_bc &= ~BIT(upstream);
2475
2476 /* And the retagging itself */
2477 new_retagging[k].vlan_ing = v->vid;
2478 new_retagging[k].vlan_egr = rx_vid;
2479 new_retagging[k].ing_port = BIT(v->port);
2480 new_retagging[k].egr_port = BIT(upstream);
2481 if (k++ == SJA1105_MAX_RETAGGING_COUNT) {
2482 dev_err(priv->ds->dev, "No more retagging rules\n");
2483 return -ENOSPC;
2484 }
2485
2486 subvlan_map[v->port][subvlan] = v->vid;
2487 }
2488
2489 *num_retagging = k;
2490
2491 return 0;
2492}
2493
2494/* Sadly, in crosschip scenarios where the CPU port is also the link to another
2495 * switch, we should retag backwards (the dsa_8021q vid to the original vid) on
2496 * the CPU port of neighbour switches.
2497 */
2498static int
2499sja1105_build_crosschip_subvlans(struct sja1105_private *priv,
2500 struct sja1105_vlan_lookup_entry *new_vlan,
2501 struct sja1105_retagging_entry *new_retagging,
2502 int *num_retagging)
2503{
2504 struct sja1105_crosschip_vlan *tmp, *pos;
2505 struct dsa_8021q_crosschip_link *c;
2506 struct sja1105_bridge_vlan *v, *w;
2507 struct list_head crosschip_vlans;
2508 int k = *num_retagging;
2509 int rc = 0;
2510
2511 if (priv->vlan_state != SJA1105_VLAN_BEST_EFFORT)
2512 return 0;
2513
2514 INIT_LIST_HEAD(&crosschip_vlans);
2515
2516 list_for_each_entry(c, &priv->dsa_8021q_ctx->crosschip_links, list) {
2517 struct sja1105_private *other_priv = c->other_ctx->ds->priv;
2518
2519 if (other_priv->vlan_state == SJA1105_VLAN_FILTERING_FULL)
2520 continue;
2521
2522 /* Crosschip links are also added to the CPU ports.
2523 * Ignore those.
2524 */
2525 if (!dsa_is_user_port(priv->ds, c->port))
2526 continue;
2527 if (!dsa_is_user_port(c->other_ctx->ds, c->other_port))
2528 continue;
2529
2530 /* Search for VLANs on the remote port */
2531 list_for_each_entry(v, &other_priv->bridge_vlans, list) {
2532 bool already_added = false;
2533 bool we_have_it = false;
2534
2535 if (v->port != c->other_port)
2536 continue;
2537
2538 /* If @v is a pvid on @other_ds, it does not need
2539 * re-retagging, because its SVL field is 0 and we
2540 * already allow that, via the dsa_8021q crosschip
2541 * links.
2542 */
2543 if (v->pvid)
2544 continue;
2545
2546 /* Search for the VLAN on our local port */
2547 list_for_each_entry(w, &priv->bridge_vlans, list) {
2548 if (w->port == c->port && w->vid == v->vid) {
2549 we_have_it = true;
2550 break;
2551 }
2552 }
2553
2554 if (!we_have_it)
2555 continue;
2556
2557 list_for_each_entry(tmp, &crosschip_vlans, list) {
2558 if (tmp->vid == v->vid &&
2559 tmp->untagged == v->untagged &&
2560 tmp->port == c->port &&
2561 tmp->other_port == v->port &&
2562 tmp->other_ctx == c->other_ctx) {
2563 already_added = true;
2564 break;
2565 }
2566 }
2567
2568 if (already_added)
2569 continue;
2570
2571 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
2572 if (!tmp) {
2573 dev_err(priv->ds->dev, "Failed to allocate memory\n");
2574 rc = -ENOMEM;
2575 goto out;
2576 }
2577 tmp->vid = v->vid;
2578 tmp->port = c->port;
2579 tmp->other_port = v->port;
2580 tmp->other_ctx = c->other_ctx;
2581 tmp->untagged = v->untagged;
2582 list_add(&tmp->list, &crosschip_vlans);
2583 }
2584 }
2585
2586 list_for_each_entry(tmp, &crosschip_vlans, list) {
2587 struct sja1105_private *other_priv = tmp->other_ctx->ds->priv;
2588 int upstream = dsa_upstream_port(priv->ds, tmp->port);
2589 int match, subvlan;
2590 u16 rx_vid;
2591
2592 subvlan = sja1105_find_committed_subvlan(other_priv,
2593 tmp->other_port,
2594 tmp->vid);
2595 /* If this happens, it's a bug. The neighbour switch does not
2596 * have a subvlan for tmp->vid on tmp->other_port, but it
2597 * should, since we already checked for its vlan_state.
2598 */
2599 if (WARN_ON(subvlan < 0)) {
2600 rc = -EINVAL;
2601 goto out;
2602 }
2603
2604 rx_vid = dsa_8021q_rx_vid_subvlan(tmp->other_ctx->ds,
2605 tmp->other_port,
2606 subvlan);
2607
2608 /* The @rx_vid retagged from @tmp->vid on
2609 * {@tmp->other_ds, @tmp->other_port} needs to be
2610 * re-retagged to @tmp->vid on the way back to us.
2611 *
2612 * Assume the original @tmp->vid is already configured
2613 * on this local switch, otherwise we wouldn't be
2614 * retagging its subvlan on the other switch in the
2615 * first place. We just need to add a reverse retagging
2616 * rule for @rx_vid and install @rx_vid on our ports.
2617 */
2618 match = rx_vid;
2619 new_vlan[match].vlanid = rx_vid;
2620 new_vlan[match].vmemb_port |= BIT(tmp->port);
2621 new_vlan[match].vmemb_port |= BIT(upstream);
2622 /* The "untagged" flag is set the same as for the
2623 * original VLAN. And towards the CPU, it doesn't
2624 * really matter, because @rx_vid will only receive
2625 * traffic on that port. For consistency with other dsa_8021q
2626 * VLANs, we'll keep the CPU port tagged.
2627 */
2628 if (!tmp->untagged)
2629 new_vlan[match].tag_port |= BIT(tmp->port);
2630 new_vlan[match].tag_port |= BIT(upstream);
2631 new_vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2632 /* Deny egress of @rx_vid towards our front-panel port.
2633 * This will force the switch to drop it, and we'll see
2634 * only the re-retagged packets (having the original,
2635 * pre-initial-retagging, VLAN @tmp->vid).
2636 */
2637 new_vlan[match].vlan_bc &= ~BIT(tmp->port);
2638
2639 /* On reverse retagging, the same ingress VLAN goes to multiple
2640 * ports. So we have an opportunity to create composite rules
2641 * to not waste the limited space in the retagging table.
2642 */
2643 k = sja1105_find_retagging_entry(new_retagging, *num_retagging,
2644 upstream, rx_vid, tmp->vid);
2645 if (k < 0) {
2646 if (*num_retagging == SJA1105_MAX_RETAGGING_COUNT) {
2647 dev_err(priv->ds->dev, "No more retagging rules\n");
2648 rc = -ENOSPC;
2649 goto out;
2650 }
2651 k = (*num_retagging)++;
2652 }
2653 /* And the retagging itself */
2654 new_retagging[k].vlan_ing = rx_vid;
2655 new_retagging[k].vlan_egr = tmp->vid;
2656 new_retagging[k].ing_port = BIT(upstream);
2657 new_retagging[k].egr_port |= BIT(tmp->port);
2658 }
2659
2660out:
2661 list_for_each_entry_safe(tmp, pos, &crosschip_vlans, list) {
2662 list_del(&tmp->list);
2663 kfree(tmp);
2664 }
2665
2666 return rc;
2667}
2668
2669static int sja1105_build_vlan_table(struct sja1105_private *priv, bool notify);
2670
2671static int sja1105_notify_crosschip_switches(struct sja1105_private *priv)
2672{
2673 struct sja1105_crosschip_switch *s, *pos;
2674 struct list_head crosschip_switches;
2675 struct dsa_8021q_crosschip_link *c;
2676 int rc = 0;
2677
2678 INIT_LIST_HEAD(&crosschip_switches);
2679
2680 list_for_each_entry(c, &priv->dsa_8021q_ctx->crosschip_links, list) {
2681 bool already_added = false;
2682
2683 list_for_each_entry(s, &crosschip_switches, list) {
2684 if (s->other_ctx == c->other_ctx) {
2685 already_added = true;
2686 break;
2687 }
2688 }
2689
2690 if (already_added)
2691 continue;
2692
2693 s = kzalloc(sizeof(*s), GFP_KERNEL);
2694 if (!s) {
2695 dev_err(priv->ds->dev, "Failed to allocate memory\n");
2696 rc = -ENOMEM;
2697 goto out;
2698 }
2699 s->other_ctx = c->other_ctx;
2700 list_add(&s->list, &crosschip_switches);
2701 }
2702
2703 list_for_each_entry(s, &crosschip_switches, list) {
2704 struct sja1105_private *other_priv = s->other_ctx->ds->priv;
2705
2706 rc = sja1105_build_vlan_table(other_priv, false);
2707 if (rc)
2708 goto out;
2709 }
2710
2711out:
2712 list_for_each_entry_safe(s, pos, &crosschip_switches, list) {
2713 list_del(&s->list);
2714 kfree(s);
2715 }
2716
2717 return rc;
2718}
2719
2720static int sja1105_build_vlan_table(struct sja1105_private *priv, bool notify)
2721{
2722 u16 subvlan_map[SJA1105_MAX_NUM_PORTS][DSA_8021Q_N_SUBVLAN];
2723 struct sja1105_retagging_entry *new_retagging;
2724 struct sja1105_vlan_lookup_entry *new_vlan;
2725 struct sja1105_table *table;
2726 int i, num_retagging = 0;
2727 int rc;
2728
2729 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2730 new_vlan = kcalloc(VLAN_N_VID,
2731 table->ops->unpacked_entry_size, GFP_KERNEL);
2732 if (!new_vlan)
2733 return -ENOMEM;
2734
2735 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2736 new_retagging = kcalloc(SJA1105_MAX_RETAGGING_COUNT,
2737 table->ops->unpacked_entry_size, GFP_KERNEL);
2738 if (!new_retagging) {
2739 kfree(new_vlan);
2740 return -ENOMEM;
2741 }
2742
2743 for (i = 0; i < VLAN_N_VID; i++)
2744 new_vlan[i].vlanid = VLAN_N_VID;
2745
2746 for (i = 0; i < SJA1105_MAX_RETAGGING_COUNT; i++)
2747 new_retagging[i].vlan_ing = VLAN_N_VID;
2748
2749 for (i = 0; i < priv->ds->num_ports; i++)
2750 sja1105_init_subvlan_map(subvlan_map[i]);
2751
2752 /* Bridge VLANs */
2753 rc = sja1105_build_bridge_vlans(priv, new_vlan);
2754 if (rc)
2755 goto out;
2756
2757 /* VLANs necessary for dsa_8021q operation, given to us by tag_8021q.c:
2758 * - RX VLANs
2759 * - TX VLANs
2760 * - Crosschip links
2761 */
2762 rc = sja1105_build_dsa_8021q_vlans(priv, new_vlan);
2763 if (rc)
2764 goto out;
2765
2766 /* Private VLANs necessary for dsa_8021q operation, which we need to
2767 * determine on our own:
2768 * - Sub-VLANs
2769 * - Sub-VLANs of crosschip switches
2770 */
2771 rc = sja1105_build_subvlans(priv, subvlan_map, new_vlan, new_retagging,
2772 &num_retagging);
2773 if (rc)
2774 goto out;
2775
2776 rc = sja1105_build_crosschip_subvlans(priv, new_vlan, new_retagging,
2777 &num_retagging);
2778 if (rc)
2779 goto out;
2780
2781 rc = sja1105_commit_vlans(priv, new_vlan, new_retagging, num_retagging);
2782 if (rc)
2783 goto out;
2784
2785 rc = sja1105_commit_pvid(priv);
2786 if (rc)
2787 goto out;
2788
2789 for (i = 0; i < priv->ds->num_ports; i++)
2790 sja1105_commit_subvlan_map(priv, i, subvlan_map[i]);
2791
2792 if (notify) {
2793 rc = sja1105_notify_crosschip_switches(priv);
2794 if (rc)
2795 goto out;
2796 }
2797
2798out:
2799 kfree(new_vlan);
2800 kfree(new_retagging);
2801
2802 return rc;
2803}
2804
2805/* The TPID setting belongs to the General Parameters table,
2806 * which can only be partially reconfigured at runtime (and not the TPID).
2807 * So a switch reset is required.
2808 */
2809int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2810 struct netlink_ext_ack *extack)
2811{
2812 struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2813 struct sja1105_general_params_entry *general_params;
2814 struct sja1105_private *priv = ds->priv;
2815 enum sja1105_vlan_state state;
2816 struct sja1105_table *table;
2817 struct sja1105_rule *rule;
2818 bool want_tagging;
2819 u16 tpid, tpid2;
2820 int rc;
2821
2822 list_for_each_entry(rule, &priv->flow_block.rules, list) {
2823 if (rule->type == SJA1105_RULE_VL) {
2824 NL_SET_ERR_MSG_MOD(extack,
2825 "Cannot change VLAN filtering with active VL rules");
2826 return -EBUSY;
2827 }
2828 }
2829
2830 if (enabled) {
2831 /* Enable VLAN filtering. */
2832 tpid = ETH_P_8021Q;
2833 tpid2 = ETH_P_8021AD;
2834 } else {
2835 /* Disable VLAN filtering. */
2836 tpid = ETH_P_SJA1105;
2837 tpid2 = ETH_P_SJA1105;
2838 }
2839
2840 for (port = 0; port < ds->num_ports; port++) {
2841 struct sja1105_port *sp = &priv->ports[port];
2842
2843 if (enabled)
2844 sp->xmit_tpid = priv->info->qinq_tpid;
2845 else
2846 sp->xmit_tpid = ETH_P_SJA1105;
2847 }
2848
2849 if (!enabled)
2850 state = SJA1105_VLAN_UNAWARE;
2851 else if (priv->best_effort_vlan_filtering)
2852 state = SJA1105_VLAN_BEST_EFFORT;
2853 else
2854 state = SJA1105_VLAN_FILTERING_FULL;
2855
2856 if (priv->vlan_state == state)
2857 return 0;
2858
2859 priv->vlan_state = state;
2860 want_tagging = (state == SJA1105_VLAN_UNAWARE ||
2861 state == SJA1105_VLAN_BEST_EFFORT);
2862
2863 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2864 general_params = table->entries;
2865 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2866 general_params->tpid = tpid;
2867 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2868 general_params->tpid2 = tpid2;
2869 /* When VLAN filtering is on, we need to at least be able to
2870 * decode management traffic through the "backup plan".
2871 */
2872 general_params->incl_srcpt1 = enabled;
2873 general_params->incl_srcpt0 = enabled;
2874
2875 want_tagging = priv->best_effort_vlan_filtering || !enabled;
2876
2877 /* VLAN filtering => independent VLAN learning.
2878 * No VLAN filtering (or best effort) => shared VLAN learning.
2879 *
2880 * In shared VLAN learning mode, untagged traffic still gets
2881 * pvid-tagged, and the FDB table gets populated with entries
2882 * containing the "real" (pvid or from VLAN tag) VLAN ID.
2883 * However the switch performs a masked L2 lookup in the FDB,
2884 * effectively only looking up a frame's DMAC (and not VID) for the
2885 * forwarding decision.
2886 *
2887 * This is extremely convenient for us, because in modes with
2888 * vlan_filtering=0, dsa_8021q actually installs unique pvid's into
2889 * each front panel port. This is good for identification but breaks
2890 * learning badly - the VID of the learnt FDB entry is unique, aka
2891 * no frames coming from any other port are going to have it. So
2892 * for forwarding purposes, this is as though learning was broken
2893 * (all frames get flooded).
2894 */
2895 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2896 l2_lookup_params = table->entries;
2897 l2_lookup_params->shared_learn = want_tagging;
2898
2899 sja1105_frame_memory_partitioning(priv);
2900
2901 rc = sja1105_build_vlan_table(priv, false);
2902 if (rc)
2903 return rc;
2904
2905 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2906 if (rc)
2907 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2908
2909 /* Switch port identification based on 802.1Q is only passable
2910 * if we are not under a vlan_filtering bridge. So make sure
2911 * the two configurations are mutually exclusive (of course, the
2912 * user may know better, i.e. best_effort_vlan_filtering).
2913 */
2914 return sja1105_setup_8021q_tagging(ds, want_tagging);
2915}
2916
2917/* Returns number of VLANs added (0 or 1) on success,
2918 * or a negative error code.
2919 */
2920static int sja1105_vlan_add_one(struct dsa_switch *ds, int port, u16 vid,
2921 u16 flags, struct list_head *vlan_list)
2922{
2923 bool untagged = flags & BRIDGE_VLAN_INFO_UNTAGGED;
2924 bool pvid = flags & BRIDGE_VLAN_INFO_PVID;
2925 struct sja1105_bridge_vlan *v;
2926
2927 list_for_each_entry(v, vlan_list, list) {
2928 if (v->port == port && v->vid == vid) {
2929 /* Already added */
2930 if (v->untagged == untagged && v->pvid == pvid)
2931 /* Nothing changed */
2932 return 0;
2933
2934 /* It's the same VLAN, but some of the flags changed
2935 * and the user did not bother to delete it first.
2936 * Update it and trigger sja1105_build_vlan_table.
2937 */
2938 v->untagged = untagged;
2939 v->pvid = pvid;
2940 return 1;
2941 }
2942 }
2943
2944 v = kzalloc(sizeof(*v), GFP_KERNEL);
2945 if (!v) {
2946 dev_err(ds->dev, "Out of memory while storing VLAN\n");
2947 return -ENOMEM;
2948 }
2949
2950 v->port = port;
2951 v->vid = vid;
2952 v->untagged = untagged;
2953 v->pvid = pvid;
2954 list_add(&v->list, vlan_list);
2955
2956 return 1;
2957}
2958
2959/* Returns number of VLANs deleted (0 or 1) */
2960static int sja1105_vlan_del_one(struct dsa_switch *ds, int port, u16 vid,
2961 struct list_head *vlan_list)
2962{
2963 struct sja1105_bridge_vlan *v, *n;
2964
2965 list_for_each_entry_safe(v, n, vlan_list, list) {
2966 if (v->port == port && v->vid == vid) {
2967 list_del(&v->list);
2968 kfree(v);
2969 return 1;
2970 }
2971 }
2972
2973 return 0;
2974}
2975
2976static int sja1105_vlan_add(struct dsa_switch *ds, int port,
2977 const struct switchdev_obj_port_vlan *vlan,
2978 struct netlink_ext_ack *extack)
2979{
2980 struct sja1105_private *priv = ds->priv;
2981 bool vlan_table_changed = false;
2982 int rc;
2983
2984 /* If the user wants best-effort VLAN filtering (aka vlan_filtering
2985 * bridge plus tagging), be sure to at least deny alterations to the
2986 * configuration done by dsa_8021q.
2987 */
2988 if (priv->vlan_state != SJA1105_VLAN_FILTERING_FULL &&
2989 vid_is_dsa_8021q(vlan->vid)) {
2990 NL_SET_ERR_MSG_MOD(extack,
2991 "Range 1024-3071 reserved for dsa_8021q operation");
2992 return -EBUSY;
2993 }
2994
2995 rc = sja1105_vlan_add_one(ds, port, vlan->vid, vlan->flags,
2996 &priv->bridge_vlans);
2997 if (rc < 0)
2998 return rc;
2999 if (rc > 0)
3000 vlan_table_changed = true;
3001
3002 if (!vlan_table_changed)
3003 return 0;
3004
3005 return sja1105_build_vlan_table(priv, true);
3006}
3007
3008static int sja1105_vlan_del(struct dsa_switch *ds, int port,
3009 const struct switchdev_obj_port_vlan *vlan)
3010{
3011 struct sja1105_private *priv = ds->priv;
3012 bool vlan_table_changed = false;
3013 int rc;
3014
3015 rc = sja1105_vlan_del_one(ds, port, vlan->vid, &priv->bridge_vlans);
3016 if (rc > 0)
3017 vlan_table_changed = true;
3018
3019 if (!vlan_table_changed)
3020 return 0;
3021
3022 return sja1105_build_vlan_table(priv, true);
3023}
3024
3025static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
3026 u16 flags)
3027{
3028 struct sja1105_private *priv = ds->priv;
3029 int rc;
3030
3031 rc = sja1105_vlan_add_one(ds, port, vid, flags, &priv->dsa_8021q_vlans);
3032 if (rc <= 0)
3033 return rc;
3034
3035 return sja1105_build_vlan_table(priv, true);
3036}
3037
3038static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
3039{
3040 struct sja1105_private *priv = ds->priv;
3041 int rc;
3042
3043 rc = sja1105_vlan_del_one(ds, port, vid, &priv->dsa_8021q_vlans);
3044 if (!rc)
3045 return 0;
3046
3047 return sja1105_build_vlan_table(priv, true);
3048}
3049
3050static const struct dsa_8021q_ops sja1105_dsa_8021q_ops = {
3051 .vlan_add = sja1105_dsa_8021q_vlan_add,
3052 .vlan_del = sja1105_dsa_8021q_vlan_del,
3053};
3054
3055/* The programming model for the SJA1105 switch is "all-at-once" via static
3056 * configuration tables. Some of these can be dynamically modified at runtime,
3057 * but not the xMII mode parameters table.
3058 * Furthermode, some PHYs may not have crystals for generating their clocks
3059 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3060 * ref_clk pin. So port clocking needs to be initialized early, before
3061 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3062 * Setting correct PHY link speed does not matter now.
3063 * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3064 * bindings are not yet parsed by DSA core. We need to parse early so that we
3065 * can populate the xMII mode parameters table.
3066 */
3067static int sja1105_setup(struct dsa_switch *ds)
3068{
3069 struct sja1105_private *priv = ds->priv;
3070 int rc;
3071
3072 rc = sja1105_parse_dt(priv);
3073 if (rc < 0) {
3074 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3075 return rc;
3076 }
3077
3078 /* Error out early if internal delays are required through DT
3079 * and we can't apply them.
3080 */
3081 rc = sja1105_parse_rgmii_delays(priv);
3082 if (rc < 0) {
3083 dev_err(ds->dev, "RGMII delay not supported\n");
3084 return rc;
3085 }
3086
3087 rc = sja1105_ptp_clock_register(ds);
3088 if (rc < 0) {
3089 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3090 return rc;
3091 }
3092
3093 rc = sja1105_mdiobus_register(ds);
3094 if (rc < 0) {
3095 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3096 ERR_PTR(rc));
3097 goto out_ptp_clock_unregister;
3098 }
3099
3100 if (priv->info->disable_microcontroller) {
3101 rc = priv->info->disable_microcontroller(priv);
3102 if (rc < 0) {
3103 dev_err(ds->dev,
3104 "Failed to disable microcontroller: %pe\n",
3105 ERR_PTR(rc));
3106 goto out_mdiobus_unregister;
3107 }
3108 }
3109
3110 /* Create and send configuration down to device */
3111 rc = sja1105_static_config_load(priv);
3112 if (rc < 0) {
3113 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3114 goto out_mdiobus_unregister;
3115 }
3116
3117 /* Configure the CGU (PHY link modes and speeds) */
3118 if (priv->info->clocking_setup) {
3119 rc = priv->info->clocking_setup(priv);
3120 if (rc < 0) {
3121 dev_err(ds->dev,
3122 "Failed to configure MII clocking: %pe\n",
3123 ERR_PTR(rc));
3124 goto out_static_config_free;
3125 }
3126 }
3127
3128 /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3129 * The only thing we can do to disable it is lie about what the 802.1Q
3130 * EtherType is.
3131 * So it will still try to apply VLAN filtering, but all ingress
3132 * traffic (except frames received with EtherType of ETH_P_SJA1105)
3133 * will be internally tagged with a distorted VLAN header where the
3134 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3135 */
3136 ds->vlan_filtering_is_global = true;
3137
3138 /* Advertise the 8 egress queues */
3139 ds->num_tx_queues = SJA1105_NUM_TC;
3140
3141 ds->mtu_enforcement_ingress = true;
3142
3143 priv->best_effort_vlan_filtering = true;
3144
3145 rc = sja1105_devlink_setup(ds);
3146 if (rc < 0)
3147 goto out_static_config_free;
3148
3149 /* The DSA/switchdev model brings up switch ports in standalone mode by
3150 * default, and that means vlan_filtering is 0 since they're not under
3151 * a bridge, so it's safe to set up switch tagging at this time.
3152 */
3153 rtnl_lock();
3154 rc = sja1105_setup_8021q_tagging(ds, true);
3155 rtnl_unlock();
3156 if (rc)
3157 goto out_devlink_teardown;
3158
3159 return 0;
3160
3161out_devlink_teardown:
3162 sja1105_devlink_teardown(ds);
3163out_mdiobus_unregister:
3164 sja1105_mdiobus_unregister(ds);
3165out_ptp_clock_unregister:
3166 sja1105_ptp_clock_unregister(ds);
3167out_static_config_free:
3168 sja1105_static_config_free(&priv->static_config);
3169
3170 return rc;
3171}
3172
3173static void sja1105_teardown(struct dsa_switch *ds)
3174{
3175 struct sja1105_private *priv = ds->priv;
3176 struct sja1105_bridge_vlan *v, *n;
3177 int port;
3178
3179 for (port = 0; port < ds->num_ports; port++) {
3180 struct sja1105_port *sp = &priv->ports[port];
3181
3182 if (!dsa_is_user_port(ds, port))
3183 continue;
3184
3185 if (sp->xmit_worker)
3186 kthread_destroy_worker(sp->xmit_worker);
3187 }
3188
3189 sja1105_devlink_teardown(ds);
3190 sja1105_mdiobus_unregister(ds);
3191 sja1105_flower_teardown(ds);
3192 sja1105_tas_teardown(ds);
3193 sja1105_ptp_clock_unregister(ds);
3194 sja1105_static_config_free(&priv->static_config);
3195
3196 list_for_each_entry_safe(v, n, &priv->dsa_8021q_vlans, list) {
3197 list_del(&v->list);
3198 kfree(v);
3199 }
3200
3201 list_for_each_entry_safe(v, n, &priv->bridge_vlans, list) {
3202 list_del(&v->list);
3203 kfree(v);
3204 }
3205}
3206
3207static void sja1105_port_disable(struct dsa_switch *ds, int port)
3208{
3209 struct sja1105_private *priv = ds->priv;
3210 struct sja1105_port *sp = &priv->ports[port];
3211
3212 if (!dsa_is_user_port(ds, port))
3213 return;
3214
3215 kthread_cancel_work_sync(&sp->xmit_work);
3216 skb_queue_purge(&sp->xmit_queue);
3217}
3218
3219static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
3220 struct sk_buff *skb, bool takets)
3221{
3222 struct sja1105_mgmt_entry mgmt_route = {0};
3223 struct sja1105_private *priv = ds->priv;
3224 struct ethhdr *hdr;
3225 int timeout = 10;
3226 int rc;
3227
3228 hdr = eth_hdr(skb);
3229
3230 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
3231 mgmt_route.destports = BIT(port);
3232 mgmt_route.enfport = 1;
3233 mgmt_route.tsreg = 0;
3234 mgmt_route.takets = takets;
3235
3236 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
3237 slot, &mgmt_route, true);
3238 if (rc < 0) {
3239 kfree_skb(skb);
3240 return rc;
3241 }
3242
3243 /* Transfer skb to the host port. */
3244 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave);
3245
3246 /* Wait until the switch has processed the frame */
3247 do {
3248 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
3249 slot, &mgmt_route);
3250 if (rc < 0) {
3251 dev_err_ratelimited(priv->ds->dev,
3252 "failed to poll for mgmt route\n");
3253 continue;
3254 }
3255
3256 /* UM10944: The ENFPORT flag of the respective entry is
3257 * cleared when a match is found. The host can use this
3258 * flag as an acknowledgment.
3259 */
3260 cpu_relax();
3261 } while (mgmt_route.enfport && --timeout);
3262
3263 if (!timeout) {
3264 /* Clean up the management route so that a follow-up
3265 * frame may not match on it by mistake.
3266 * This is only hardware supported on P/Q/R/S - on E/T it is
3267 * a no-op and we are silently discarding the -EOPNOTSUPP.
3268 */
3269 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
3270 slot, &mgmt_route, false);
3271 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
3272 }
3273
3274 return NETDEV_TX_OK;
3275}
3276
3277#define work_to_port(work) \
3278 container_of((work), struct sja1105_port, xmit_work)
3279#define tagger_to_sja1105(t) \
3280 container_of((t), struct sja1105_private, tagger_data)
3281
3282/* Deferred work is unfortunately necessary because setting up the management
3283 * route cannot be done from atomit context (SPI transfer takes a sleepable
3284 * lock on the bus)
3285 */
3286static void sja1105_port_deferred_xmit(struct kthread_work *work)
3287{
3288 struct sja1105_port *sp = work_to_port(work);
3289 struct sja1105_tagger_data *tagger_data = sp->data;
3290 struct sja1105_private *priv = tagger_to_sja1105(tagger_data);
3291 int port = sp - priv->ports;
3292 struct sk_buff *skb;
3293
3294 while ((skb = skb_dequeue(&sp->xmit_queue)) != NULL) {
3295 struct sk_buff *clone = SJA1105_SKB_CB(skb)->clone;
3296
3297 mutex_lock(&priv->mgmt_lock);
3298
3299 sja1105_mgmt_xmit(priv->ds, port, 0, skb, !!clone);
3300
3301 /* The clone, if there, was made by dsa_skb_tx_timestamp */
3302 if (clone)
3303 sja1105_ptp_txtstamp_skb(priv->ds, port, clone);
3304
3305 mutex_unlock(&priv->mgmt_lock);
3306 }
3307}
3308
3309/* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
3310 * which cannot be reconfigured at runtime. So a switch reset is required.
3311 */
3312static int sja1105_set_ageing_time(struct dsa_switch *ds,
3313 unsigned int ageing_time)
3314{
3315 struct sja1105_l2_lookup_params_entry *l2_lookup_params;
3316 struct sja1105_private *priv = ds->priv;
3317 struct sja1105_table *table;
3318 unsigned int maxage;
3319
3320 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
3321 l2_lookup_params = table->entries;
3322
3323 maxage = SJA1105_AGEING_TIME_MS(ageing_time);
3324
3325 if (l2_lookup_params->maxage == maxage)
3326 return 0;
3327
3328 l2_lookup_params->maxage = maxage;
3329
3330 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
3331}
3332
3333static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3334{
3335 struct sja1105_l2_policing_entry *policing;
3336 struct sja1105_private *priv = ds->priv;
3337
3338 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
3339
3340 if (dsa_is_cpu_port(ds, port))
3341 new_mtu += VLAN_HLEN;
3342
3343 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
3344
3345 if (policing[port].maxlen == new_mtu)
3346 return 0;
3347
3348 policing[port].maxlen = new_mtu;
3349
3350 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
3351}
3352
3353static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
3354{
3355 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
3356}
3357
3358static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
3359 enum tc_setup_type type,
3360 void *type_data)
3361{
3362 switch (type) {
3363 case TC_SETUP_QDISC_TAPRIO:
3364 return sja1105_setup_tc_taprio(ds, port, type_data);
3365 case TC_SETUP_QDISC_CBS:
3366 return sja1105_setup_tc_cbs(ds, port, type_data);
3367 default:
3368 return -EOPNOTSUPP;
3369 }
3370}
3371
3372/* We have a single mirror (@to) port, but can configure ingress and egress
3373 * mirroring on all other (@from) ports.
3374 * We need to allow mirroring rules only as long as the @to port is always the
3375 * same, and we need to unset the @to port from mirr_port only when there is no
3376 * mirroring rule that references it.
3377 */
3378static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
3379 bool ingress, bool enabled)
3380{
3381 struct sja1105_general_params_entry *general_params;
3382 struct sja1105_mac_config_entry *mac;
3383 struct dsa_switch *ds = priv->ds;
3384 struct sja1105_table *table;
3385 bool already_enabled;
3386 u64 new_mirr_port;
3387 int rc;
3388
3389 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
3390 general_params = table->entries;
3391
3392 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
3393
3394 already_enabled = (general_params->mirr_port != ds->num_ports);
3395 if (already_enabled && enabled && general_params->mirr_port != to) {
3396 dev_err(priv->ds->dev,
3397 "Delete mirroring rules towards port %llu first\n",
3398 general_params->mirr_port);
3399 return -EBUSY;
3400 }
3401
3402 new_mirr_port = to;
3403 if (!enabled) {
3404 bool keep = false;
3405 int port;
3406
3407 /* Anybody still referencing mirr_port? */
3408 for (port = 0; port < ds->num_ports; port++) {
3409 if (mac[port].ing_mirr || mac[port].egr_mirr) {
3410 keep = true;
3411 break;
3412 }
3413 }
3414 /* Unset already_enabled for next time */
3415 if (!keep)
3416 new_mirr_port = ds->num_ports;
3417 }
3418 if (new_mirr_port != general_params->mirr_port) {
3419 general_params->mirr_port = new_mirr_port;
3420
3421 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
3422 0, general_params, true);
3423 if (rc < 0)
3424 return rc;
3425 }
3426
3427 if (ingress)
3428 mac[from].ing_mirr = enabled;
3429 else
3430 mac[from].egr_mirr = enabled;
3431
3432 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
3433 &mac[from], true);
3434}
3435
3436static int sja1105_mirror_add(struct dsa_switch *ds, int port,
3437 struct dsa_mall_mirror_tc_entry *mirror,
3438 bool ingress)
3439{
3440 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
3441 ingress, true);
3442}
3443
3444static void sja1105_mirror_del(struct dsa_switch *ds, int port,
3445 struct dsa_mall_mirror_tc_entry *mirror)
3446{
3447 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
3448 mirror->ingress, false);
3449}
3450
3451static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
3452 struct dsa_mall_policer_tc_entry *policer)
3453{
3454 struct sja1105_l2_policing_entry *policing;
3455 struct sja1105_private *priv = ds->priv;
3456
3457 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
3458
3459 /* In hardware, every 8 microseconds the credit level is incremented by
3460 * the value of RATE bytes divided by 64, up to a maximum of SMAX
3461 * bytes.
3462 */
3463 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
3464 1000000);
3465 policing[port].smax = policer->burst;
3466
3467 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
3468}
3469
3470static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
3471{
3472 struct sja1105_l2_policing_entry *policing;
3473 struct sja1105_private *priv = ds->priv;
3474
3475 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
3476
3477 policing[port].rate = SJA1105_RATE_MBPS(1000);
3478 policing[port].smax = 65535;
3479
3480 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
3481}
3482
3483static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
3484 bool enabled)
3485{
3486 struct sja1105_mac_config_entry *mac;
3487 int rc;
3488
3489 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
3490
3491 mac[port].dyn_learn = enabled;
3492
3493 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
3494 &mac[port], true);
3495 if (rc)
3496 return rc;
3497
3498 if (enabled)
3499 priv->learn_ena |= BIT(port);
3500 else
3501 priv->learn_ena &= ~BIT(port);
3502
3503 return 0;
3504}
3505
3506static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
3507 struct switchdev_brport_flags flags)
3508{
3509 if (flags.mask & BR_FLOOD) {
3510 if (flags.val & BR_FLOOD)
3511 priv->ucast_egress_floods |= BIT(to);
3512 else
3513 priv->ucast_egress_floods &= ~BIT(to);
3514 }
3515
3516 if (flags.mask & BR_BCAST_FLOOD) {
3517 if (flags.val & BR_BCAST_FLOOD)
3518 priv->bcast_egress_floods |= BIT(to);
3519 else
3520 priv->bcast_egress_floods &= ~BIT(to);
3521 }
3522
3523 return sja1105_manage_flood_domains(priv);
3524}
3525
3526static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
3527 struct switchdev_brport_flags flags,
3528 struct netlink_ext_ack *extack)
3529{
3530 struct sja1105_l2_lookup_entry *l2_lookup;
3531 struct sja1105_table *table;
3532 int match;
3533
3534 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
3535 l2_lookup = table->entries;
3536
3537 for (match = 0; match < table->entry_count; match++)
3538 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
3539 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
3540 break;
3541
3542 if (match == table->entry_count) {
3543 NL_SET_ERR_MSG_MOD(extack,
3544 "Could not find FDB entry for unknown multicast");
3545 return -ENOSPC;
3546 }
3547
3548 if (flags.val & BR_MCAST_FLOOD)
3549 l2_lookup[match].destports |= BIT(to);
3550 else
3551 l2_lookup[match].destports &= ~BIT(to);
3552
3553 return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
3554 l2_lookup[match].index,
3555 &l2_lookup[match],
3556 true);
3557}
3558
3559static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3560 struct switchdev_brport_flags flags,
3561 struct netlink_ext_ack *extack)
3562{
3563 struct sja1105_private *priv = ds->priv;
3564
3565 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
3566 BR_BCAST_FLOOD))
3567 return -EINVAL;
3568
3569 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
3570 !priv->info->can_limit_mcast_flood) {
3571 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
3572 bool unicast = !!(flags.val & BR_FLOOD);
3573
3574 if (unicast != multicast) {
3575 NL_SET_ERR_MSG_MOD(extack,
3576 "This chip cannot configure multicast flooding independently of unicast");
3577 return -EINVAL;
3578 }
3579 }
3580
3581 return 0;
3582}
3583
3584static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
3585 struct switchdev_brport_flags flags,
3586 struct netlink_ext_ack *extack)
3587{
3588 struct sja1105_private *priv = ds->priv;
3589 int rc;
3590
3591 if (flags.mask & BR_LEARNING) {
3592 bool learn_ena = !!(flags.val & BR_LEARNING);
3593
3594 rc = sja1105_port_set_learning(priv, port, learn_ena);
3595 if (rc)
3596 return rc;
3597 }
3598
3599 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
3600 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
3601 if (rc)
3602 return rc;
3603 }
3604
3605 /* For chips that can't offload BR_MCAST_FLOOD independently, there
3606 * is nothing to do here, we ensured the configuration is in sync by
3607 * offloading BR_FLOOD.
3608 */
3609 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3610 rc = sja1105_port_mcast_flood(priv, port, flags,
3611 extack);
3612 if (rc)
3613 return rc;
3614 }
3615
3616 return 0;
3617}
3618
3619static const struct dsa_switch_ops sja1105_switch_ops = {
3620 .get_tag_protocol = sja1105_get_tag_protocol,
3621 .setup = sja1105_setup,
3622 .teardown = sja1105_teardown,
3623 .set_ageing_time = sja1105_set_ageing_time,
3624 .port_change_mtu = sja1105_change_mtu,
3625 .port_max_mtu = sja1105_get_max_mtu,
3626 .phylink_validate = sja1105_phylink_validate,
3627 .phylink_mac_config = sja1105_mac_config,
3628 .phylink_mac_link_up = sja1105_mac_link_up,
3629 .phylink_mac_link_down = sja1105_mac_link_down,
3630 .get_strings = sja1105_get_strings,
3631 .get_ethtool_stats = sja1105_get_ethtool_stats,
3632 .get_sset_count = sja1105_get_sset_count,
3633 .get_ts_info = sja1105_get_ts_info,
3634 .port_disable = sja1105_port_disable,
3635 .port_fdb_dump = sja1105_fdb_dump,
3636 .port_fdb_add = sja1105_fdb_add,
3637 .port_fdb_del = sja1105_fdb_del,
3638 .port_bridge_join = sja1105_bridge_join,
3639 .port_bridge_leave = sja1105_bridge_leave,
3640 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags,
3641 .port_bridge_flags = sja1105_port_bridge_flags,
3642 .port_stp_state_set = sja1105_bridge_stp_state_set,
3643 .port_vlan_filtering = sja1105_vlan_filtering,
3644 .port_vlan_add = sja1105_vlan_add,
3645 .port_vlan_del = sja1105_vlan_del,
3646 .port_mdb_add = sja1105_mdb_add,
3647 .port_mdb_del = sja1105_mdb_del,
3648 .port_hwtstamp_get = sja1105_hwtstamp_get,
3649 .port_hwtstamp_set = sja1105_hwtstamp_set,
3650 .port_rxtstamp = sja1105_port_rxtstamp,
3651 .port_txtstamp = sja1105_port_txtstamp,
3652 .port_setup_tc = sja1105_port_setup_tc,
3653 .port_mirror_add = sja1105_mirror_add,
3654 .port_mirror_del = sja1105_mirror_del,
3655 .port_policer_add = sja1105_port_policer_add,
3656 .port_policer_del = sja1105_port_policer_del,
3657 .cls_flower_add = sja1105_cls_flower_add,
3658 .cls_flower_del = sja1105_cls_flower_del,
3659 .cls_flower_stats = sja1105_cls_flower_stats,
3660 .crosschip_bridge_join = sja1105_crosschip_bridge_join,
3661 .crosschip_bridge_leave = sja1105_crosschip_bridge_leave,
3662 .devlink_param_get = sja1105_devlink_param_get,
3663 .devlink_param_set = sja1105_devlink_param_set,
3664 .devlink_info_get = sja1105_devlink_info_get,
3665};
3666
3667static const struct of_device_id sja1105_dt_ids[];
3668
3669static int sja1105_check_device_id(struct sja1105_private *priv)
3670{
3671 const struct sja1105_regs *regs = priv->info->regs;
3672 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3673 struct device *dev = &priv->spidev->dev;
3674 const struct of_device_id *match;
3675 u32 device_id;
3676 u64 part_no;
3677 int rc;
3678
3679 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3680 NULL);
3681 if (rc < 0)
3682 return rc;
3683
3684 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3685 SJA1105_SIZE_DEVICE_ID);
3686 if (rc < 0)
3687 return rc;
3688
3689 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3690
3691 for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3692 const struct sja1105_info *info = match->data;
3693
3694 /* Is what's been probed in our match table at all? */
3695 if (info->device_id != device_id || info->part_no != part_no)
3696 continue;
3697
3698 /* But is it what's in the device tree? */
3699 if (priv->info->device_id != device_id ||
3700 priv->info->part_no != part_no) {
3701 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3702 priv->info->name, info->name);
3703 /* It isn't. No problem, pick that up. */
3704 priv->info = info;
3705 }
3706
3707 return 0;
3708 }
3709
3710 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3711 device_id, part_no);
3712
3713 return -ENODEV;
3714}
3715
3716static int sja1105_probe(struct spi_device *spi)
3717{
3718 struct sja1105_tagger_data *tagger_data;
3719 struct device *dev = &spi->dev;
3720 struct sja1105_private *priv;
3721 size_t max_xfer, max_msg;
3722 struct dsa_switch *ds;
3723 int rc, port;
3724
3725 if (!dev->of_node) {
3726 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3727 return -EINVAL;
3728 }
3729
3730 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3731 if (!priv)
3732 return -ENOMEM;
3733
3734 /* Configure the optional reset pin and bring up switch */
3735 priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
3736 if (IS_ERR(priv->reset_gpio))
3737 dev_dbg(dev, "reset-gpios not defined, ignoring\n");
3738 else
3739 sja1105_hw_reset(priv->reset_gpio, 1, 1);
3740
3741 /* Populate our driver private structure (priv) based on
3742 * the device tree node that was probed (spi)
3743 */
3744 priv->spidev = spi;
3745 spi_set_drvdata(spi, priv);
3746
3747 /* Configure the SPI bus */
3748 spi->bits_per_word = 8;
3749 rc = spi_setup(spi);
3750 if (rc < 0) {
3751 dev_err(dev, "Could not init SPI\n");
3752 return rc;
3753 }
3754
3755 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3756 * a small one for the message header and another one for the current
3757 * chunk of the packed buffer.
3758 * Check that the restrictions imposed by the SPI controller are
3759 * respected: the chunk buffer is smaller than the max transfer size,
3760 * and the total length of the chunk plus its message header is smaller
3761 * than the max message size.
3762 * We do that during probe time since the maximum transfer size is a
3763 * runtime invariant.
3764 */
3765 max_xfer = spi_max_transfer_size(spi);
3766 max_msg = spi_max_message_size(spi);
3767
3768 /* We need to send at least one 64-bit word of SPI payload per message
3769 * in order to be able to make useful progress.
3770 */
3771 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3772 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3773 return -EINVAL;
3774 }
3775
3776 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3777 if (priv->max_xfer_len > max_xfer)
3778 priv->max_xfer_len = max_xfer;
3779 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3780 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3781
3782 priv->info = of_device_get_match_data(dev);
3783
3784 /* Detect hardware device */
3785 rc = sja1105_check_device_id(priv);
3786 if (rc < 0) {
3787 dev_err(dev, "Device ID check failed: %d\n", rc);
3788 return rc;
3789 }
3790
3791 dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3792
3793 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3794 if (!ds)
3795 return -ENOMEM;
3796
3797 ds->dev = dev;
3798 ds->num_ports = priv->info->num_ports;
3799 ds->ops = &sja1105_switch_ops;
3800 ds->priv = priv;
3801 priv->ds = ds;
3802
3803 tagger_data = &priv->tagger_data;
3804
3805 mutex_init(&priv->ptp_data.lock);
3806 mutex_init(&priv->mgmt_lock);
3807
3808 priv->dsa_8021q_ctx = devm_kzalloc(dev, sizeof(*priv->dsa_8021q_ctx),
3809 GFP_KERNEL);
3810 if (!priv->dsa_8021q_ctx)
3811 return -ENOMEM;
3812
3813 priv->dsa_8021q_ctx->ops = &sja1105_dsa_8021q_ops;
3814 priv->dsa_8021q_ctx->proto = htons(ETH_P_8021Q);
3815 priv->dsa_8021q_ctx->ds = ds;
3816
3817 INIT_LIST_HEAD(&priv->dsa_8021q_ctx->crosschip_links);
3818 INIT_LIST_HEAD(&priv->bridge_vlans);
3819 INIT_LIST_HEAD(&priv->dsa_8021q_vlans);
3820
3821 sja1105_tas_setup(ds);
3822 sja1105_flower_setup(ds);
3823
3824 rc = dsa_register_switch(priv->ds);
3825 if (rc)
3826 return rc;
3827
3828 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3829 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3830 sizeof(struct sja1105_cbs_entry),
3831 GFP_KERNEL);
3832 if (!priv->cbs) {
3833 rc = -ENOMEM;
3834 goto out_unregister_switch;
3835 }
3836 }
3837
3838 /* Connections between dsa_port and sja1105_port */
3839 for (port = 0; port < ds->num_ports; port++) {
3840 struct sja1105_port *sp = &priv->ports[port];
3841 struct dsa_port *dp = dsa_to_port(ds, port);
3842 struct net_device *slave;
3843 int subvlan;
3844
3845 if (!dsa_is_user_port(ds, port))
3846 continue;
3847
3848 dp->priv = sp;
3849 sp->dp = dp;
3850 sp->data = tagger_data;
3851 slave = dp->slave;
3852 kthread_init_work(&sp->xmit_work, sja1105_port_deferred_xmit);
3853 sp->xmit_worker = kthread_create_worker(0, "%s_xmit",
3854 slave->name);
3855 if (IS_ERR(sp->xmit_worker)) {
3856 rc = PTR_ERR(sp->xmit_worker);
3857 dev_err(ds->dev,
3858 "failed to create deferred xmit thread: %d\n",
3859 rc);
3860 goto out_destroy_workers;
3861 }
3862 skb_queue_head_init(&sp->xmit_queue);
3863 sp->xmit_tpid = ETH_P_SJA1105;
3864
3865 for (subvlan = 0; subvlan < DSA_8021Q_N_SUBVLAN; subvlan++)
3866 sp->subvlan_map[subvlan] = VLAN_N_VID;
3867 }
3868
3869 return 0;
3870
3871out_destroy_workers:
3872 while (port-- > 0) {
3873 struct sja1105_port *sp = &priv->ports[port];
3874
3875 if (!dsa_is_user_port(ds, port))
3876 continue;
3877
3878 kthread_destroy_worker(sp->xmit_worker);
3879 }
3880
3881out_unregister_switch:
3882 dsa_unregister_switch(ds);
3883
3884 return rc;
3885}
3886
3887static int sja1105_remove(struct spi_device *spi)
3888{
3889 struct sja1105_private *priv = spi_get_drvdata(spi);
3890
3891 dsa_unregister_switch(priv->ds);
3892 return 0;
3893}
3894
3895static const struct of_device_id sja1105_dt_ids[] = {
3896 { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3897 { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3898 { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3899 { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3900 { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3901 { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3902 { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3903 { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3904 { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3905 { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3906 { /* sentinel */ },
3907};
3908MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3909
3910static struct spi_driver sja1105_driver = {
3911 .driver = {
3912 .name = "sja1105",
3913 .owner = THIS_MODULE,
3914 .of_match_table = of_match_ptr(sja1105_dt_ids),
3915 },
3916 .probe = sja1105_probe,
3917 .remove = sja1105_remove,
3918};
3919
3920module_spi_driver(sja1105_driver);
3921
3922MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3923MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3924MODULE_DESCRIPTION("SJA1105 Driver");
3925MODULE_LICENSE("GPL v2");