1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Access SD/MMC cards through SPI master controllers
   4 *
   5 * (C) Copyright 2005, Intec Automation,
   6 *		Mike Lavender (mike@steroidmicros)
   7 * (C) Copyright 2006-2007, David Brownell
   8 * (C) Copyright 2007, Axis Communications,
   9 *		Hans-Peter Nilsson (hp@axis.com)
  10 * (C) Copyright 2007, ATRON electronic GmbH,
  11 *		Jan Nikitenko <jan.nikitenko@gmail.com>
  12 */
  13#include <linux/sched.h>
  14#include <linux/delay.h>
  15#include <linux/slab.h>
  16#include <linux/module.h>
  17#include <linux/bio.h>
 
  18#include <linux/crc7.h>
  19#include <linux/crc-itu-t.h>
  20#include <linux/scatterlist.h>
  21
  22#include <linux/mmc/host.h>
  23#include <linux/mmc/mmc.h>		/* for R1_SPI_* bit values */
  24#include <linux/mmc/slot-gpio.h>
  25
  26#include <linux/spi/spi.h>
  27#include <linux/spi/mmc_spi.h>
  28
  29#include <linux/unaligned.h>
  30
  31
  32/* NOTES:
  33 *
  34 * - For now, we won't try to interoperate with a real mmc/sd/sdio
  35 *   controller, although some of them do have hardware support for
  36 *   SPI protocol.  The main reason for such configs would be mmc-ish
  37 *   cards like DataFlash, which don't support that "native" protocol.
  38 *
  39 *   We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
  40 *   switch between driver stacks, and in any case if "native" mode
  41 *   is available, it will be faster and hence preferable.
  42 *
  43 * - MMC depends on a different chipselect management policy than the
  44 *   SPI interface currently supports for shared bus segments:  it needs
  45 *   to issue multiple spi_message requests with the chipselect active,
  46 *   using the results of one message to decide the next one to issue.
  47 *
  48 *   Pending updates to the programming interface, this driver expects
  49 *   that it not share the bus with other drivers (precluding conflicts).
  50 *
  51 * - We tell the controller to keep the chipselect active from the
  52 *   beginning of an mmc_host_ops.request until the end.  So beware
  53 *   of SPI controller drivers that mis-handle the cs_change flag!
  54 *
  55 *   However, many cards seem OK with chipselect flapping up/down
  56 *   during that time ... at least on unshared bus segments.
  57 */
  58
  59
  60/*
  61 * Local protocol constants, internal to data block protocols.
  62 */
  63
  64/* Response tokens used to ack each block written: */
  65#define SPI_MMC_RESPONSE_CODE(x)	((x) & 0x1f)
  66#define SPI_RESPONSE_ACCEPTED		((2 << 1)|1)
  67#define SPI_RESPONSE_CRC_ERR		((5 << 1)|1)
  68#define SPI_RESPONSE_WRITE_ERR		((6 << 1)|1)
  69
  70/* Read and write blocks start with these tokens and end with crc;
  71 * on error, read tokens act like a subset of R2_SPI_* values.
  72 */
  73#define SPI_TOKEN_SINGLE	0xfe	/* single block r/w, multiblock read */
  74#define SPI_TOKEN_MULTI_WRITE	0xfc	/* multiblock write */
  75#define SPI_TOKEN_STOP_TRAN	0xfd	/* terminate multiblock write */
  76
  77#define MMC_SPI_BLOCKSIZE	512
  78
  79#define MMC_SPI_R1B_TIMEOUT_MS	3000
  80#define MMC_SPI_INIT_TIMEOUT_MS	3000
  81
  82/* One of the critical speed parameters is the amount of data which may
  83 * be transferred in one command. If this value is too low, the SD card
  84 * controller has to do multiple partial block writes (argggh!). With
  85 * today (2008) SD cards there is little speed gain if we transfer more
  86 * than 64 KBytes at a time. So use this value until there is any indication
  87 * that we should do more here.
  88 */
  89#define MMC_SPI_BLOCKSATONCE	128
  90
  91/****************************************************************************/
  92
  93/*
  94 * Local Data Structures
  95 */
  96
  97/* "scratch" is per-{command,block} data exchanged with the card */
  98struct scratch {
  99	u8			status[29];
 100	u8			data_token;
 101	__be16			crc_val;
 102};
 103
 104struct mmc_spi_host {
 105	struct mmc_host		*mmc;
 106	struct spi_device	*spi;
 107
 108	unsigned char		power_mode;
 109	u16			powerup_msecs;
 110
 111	struct mmc_spi_platform_data	*pdata;
 112
 113	/* for bulk data transfers */
 114	struct spi_transfer	token, t, crc, early_status;
 115	struct spi_message	m;
 116
 117	/* for status readback */
 118	struct spi_transfer	status;
 119	struct spi_message	readback;
 120
 
 
 
 121	/* buffer used for commands and for message "overhead" */
 122	struct scratch		*data;
 
 123
 124	/* Specs say to write ones most of the time, even when the card
 125	 * has no need to read its input data; and many cards won't care.
 126	 * This is our source of those ones.
 127	 */
 128	void			*ones;
 
 129};
 130
 131
 132/****************************************************************************/
 133
 134/*
 135 * MMC-over-SPI protocol glue, used by the MMC stack interface
 136 */
 137
 138static inline int mmc_cs_off(struct mmc_spi_host *host)
 139{
 140	/* chipselect will always be inactive after setup() */
 141	return spi_setup(host->spi);
 142}
 143
 144static int mmc_spi_readbytes(struct mmc_spi_host *host, unsigned int len)
 
 145{
 
 
 146	if (len > sizeof(*host->data)) {
 147		WARN_ON(1);
 148		return -EIO;
 149	}
 150
 151	host->status.len = len;
 152
 153	return spi_sync_locked(host->spi, &host->readback);
 
 
 
 
 
 
 
 
 
 
 
 
 154}
 155
 156static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
 157			unsigned n, u8 byte)
 158{
 159	u8 *cp = host->data->status;
 160	unsigned long start = jiffies;
 161
 162	do {
 163		int		status;
 164		unsigned	i;
 165
 166		status = mmc_spi_readbytes(host, n);
 167		if (status < 0)
 168			return status;
 169
 170		for (i = 0; i < n; i++) {
 171			if (cp[i] != byte)
 172				return cp[i];
 173		}
 174
 175		/* If we need long timeouts, we may release the CPU */
 176		cond_resched();
 177	} while (time_is_after_jiffies(start + timeout));
 
 
 
 
 
 
 
 178	return -ETIMEDOUT;
 179}
 180
 181static inline int
 182mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
 183{
 184	return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
 185}
 186
 187static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
 188{
 189	return mmc_spi_skip(host, timeout, 1, 0xff);
 190}
 191
 192
 193/*
 194 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
 195 * hosts return!  The low byte holds R1_SPI bits.  The next byte may hold
 196 * R2_SPI bits ... for SEND_STATUS, or after data read errors.
 197 *
 198 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
 199 * newer cards R7 (IF_COND).
 200 */
 201
 202static char *maptype(struct mmc_command *cmd)
 203{
 204	switch (mmc_spi_resp_type(cmd)) {
 205	case MMC_RSP_SPI_R1:	return "R1";
 206	case MMC_RSP_SPI_R1B:	return "R1B";
 207	case MMC_RSP_SPI_R2:	return "R2/R5";
 208	case MMC_RSP_SPI_R3:	return "R3/R4/R7";
 209	default:		return "?";
 210	}
 211}
 212
 213/* return zero, else negative errno after setting cmd->error */
 214static int mmc_spi_response_get(struct mmc_spi_host *host,
 215		struct mmc_command *cmd, int cs_on)
 216{
 217	unsigned long timeout_ms;
 218	u8	*cp = host->data->status;
 219	u8	*end = cp + host->t.len;
 220	int	value = 0;
 221	int	bitshift;
 222	u8 	leftover = 0;
 223	unsigned short rotator;
 224	int 	i;
 
 
 
 
 225
 226	/* Except for data block reads, the whole response will already
 227	 * be stored in the scratch buffer.  It's somewhere after the
 228	 * command and the first byte we read after it.  We ignore that
 229	 * first byte.  After STOP_TRANSMISSION command it may include
 230	 * two data bits, but otherwise it's all ones.
 231	 */
 232	cp += 8;
 233	while (cp < end && *cp == 0xff)
 234		cp++;
 235
 236	/* Data block reads (R1 response types) may need more data... */
 237	if (cp == end) {
 238		cp = host->data->status;
 239		end = cp+1;
 240
 241		/* Card sends N(CR) (== 1..8) bytes of all-ones then one
 242		 * status byte ... and we already scanned 2 bytes.
 243		 *
 244		 * REVISIT block read paths use nasty byte-at-a-time I/O
 245		 * so it can always DMA directly into the target buffer.
 246		 * It'd probably be better to memcpy() the first chunk and
 247		 * avoid extra i/o calls...
 248		 *
 249		 * Note we check for more than 8 bytes, because in practice,
 250		 * some SD cards are slow...
 251		 */
 252		for (i = 2; i < 16; i++) {
 253			value = mmc_spi_readbytes(host, 1);
 254			if (value < 0)
 255				goto done;
 256			if (*cp != 0xff)
 257				goto checkstatus;
 258		}
 259		value = -ETIMEDOUT;
 260		goto done;
 261	}
 262
 263checkstatus:
 264	bitshift = 0;
 265	if (*cp & 0x80)	{
 266		/* Houston, we have an ugly card with a bit-shifted response */
 267		rotator = *cp++ << 8;
 268		/* read the next byte */
 269		if (cp == end) {
 270			value = mmc_spi_readbytes(host, 1);
 271			if (value < 0)
 272				goto done;
 273			cp = host->data->status;
 274			end = cp+1;
 275		}
 276		rotator |= *cp++;
 277		while (rotator & 0x8000) {
 278			bitshift++;
 279			rotator <<= 1;
 280		}
 281		cmd->resp[0] = rotator >> 8;
 282		leftover = rotator;
 283	} else {
 284		cmd->resp[0] = *cp++;
 285	}
 286	cmd->error = 0;
 287
 288	/* Status byte: the entire seven-bit R1 response.  */
 289	if (cmd->resp[0] != 0) {
 290		if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
 291				& cmd->resp[0])
 292			value = -EFAULT; /* Bad address */
 293		else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
 294			value = -ENOSYS; /* Function not implemented */
 295		else if (R1_SPI_COM_CRC & cmd->resp[0])
 296			value = -EILSEQ; /* Illegal byte sequence */
 297		else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
 298				& cmd->resp[0])
 299			value = -EIO;    /* I/O error */
 300		/* else R1_SPI_IDLE, "it's resetting" */
 301	}
 302
 303	switch (mmc_spi_resp_type(cmd)) {
 304
 305	/* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
 306	 * and less-common stuff like various erase operations.
 307	 */
 308	case MMC_RSP_SPI_R1B:
 309		/* maybe we read all the busy tokens already */
 310		while (cp < end && *cp == 0)
 311			cp++;
 312		if (cp == end) {
 313			timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
 314				MMC_SPI_R1B_TIMEOUT_MS;
 315			mmc_spi_wait_unbusy(host, msecs_to_jiffies(timeout_ms));
 316		}
 317		break;
 318
 319	/* SPI R2 == R1 + second status byte; SEND_STATUS
 320	 * SPI R5 == R1 + data byte; IO_RW_DIRECT
 321	 */
 322	case MMC_RSP_SPI_R2:
 323		/* read the next byte */
 324		if (cp == end) {
 325			value = mmc_spi_readbytes(host, 1);
 326			if (value < 0)
 327				goto done;
 328			cp = host->data->status;
 329			end = cp+1;
 330		}
 331		if (bitshift) {
 332			rotator = leftover << 8;
 333			rotator |= *cp << bitshift;
 334			cmd->resp[0] |= (rotator & 0xFF00);
 335		} else {
 336			cmd->resp[0] |= *cp << 8;
 337		}
 338		break;
 339
 340	/* SPI R3, R4, or R7 == R1 + 4 bytes */
 341	case MMC_RSP_SPI_R3:
 342		rotator = leftover << 8;
 343		cmd->resp[1] = 0;
 344		for (i = 0; i < 4; i++) {
 345			cmd->resp[1] <<= 8;
 346			/* read the next byte */
 347			if (cp == end) {
 348				value = mmc_spi_readbytes(host, 1);
 349				if (value < 0)
 350					goto done;
 351				cp = host->data->status;
 352				end = cp+1;
 353			}
 354			if (bitshift) {
 355				rotator |= *cp++ << bitshift;
 356				cmd->resp[1] |= (rotator >> 8);
 357				rotator <<= 8;
 358			} else {
 359				cmd->resp[1] |= *cp++;
 360			}
 361		}
 362		break;
 363
 364	/* SPI R1 == just one status byte */
 365	case MMC_RSP_SPI_R1:
 366		break;
 367
 368	default:
 369		dev_dbg(&host->spi->dev, "bad response type %04x\n",
 370			mmc_spi_resp_type(cmd));
 371		if (value >= 0)
 372			value = -EINVAL;
 373		goto done;
 374	}
 375
 376	if (value < 0)
 377		dev_dbg(&host->spi->dev,
 378			"  ... CMD%d response SPI_%s: resp %04x %08x\n",
 379			cmd->opcode, maptype(cmd), cmd->resp[0], cmd->resp[1]);
 380
 381	/* disable chipselect on errors and some success cases */
 382	if (value >= 0 && cs_on)
 383		return value;
 384done:
 385	if (value < 0)
 386		cmd->error = value;
 387	mmc_cs_off(host);
 388	return value;
 389}
 390
 391/* Issue command and read its response.
 392 * Returns zero on success, negative for error.
 393 *
 394 * On error, caller must cope with mmc core retry mechanism.  That
 395 * means immediate low-level resubmit, which affects the bus lock...
 396 */
 397static int
 398mmc_spi_command_send(struct mmc_spi_host *host,
 399		struct mmc_request *mrq,
 400		struct mmc_command *cmd, int cs_on)
 401{
 402	struct scratch		*data = host->data;
 403	u8			*cp = data->status;
 404	int			status;
 405	struct spi_transfer	*t;
 406
 407	/* We can handle most commands (except block reads) in one full
 408	 * duplex I/O operation before either starting the next transfer
 409	 * (data block or command) or else deselecting the card.
 410	 *
 411	 * First, write 7 bytes:
 412	 *  - an all-ones byte to ensure the card is ready
 413	 *  - opcode byte (plus start and transmission bits)
 414	 *  - four bytes of big-endian argument
 415	 *  - crc7 (plus end bit) ... always computed, it's cheap
 416	 *
 417	 * We init the whole buffer to all-ones, which is what we need
 418	 * to write while we're reading (later) response data.
 419	 */
 420	memset(cp, 0xff, sizeof(data->status));
 421
 422	cp[1] = 0x40 | cmd->opcode;
 423	put_unaligned_be32(cmd->arg, cp + 2);
 424	cp[6] = crc7_be(0, cp + 1, 5) | 0x01;
 425	cp += 7;
 426
 427	/* Then, read up to 13 bytes (while writing all-ones):
 428	 *  - N(CR) (== 1..8) bytes of all-ones
 429	 *  - status byte (for all response types)
 430	 *  - the rest of the response, either:
 431	 *      + nothing, for R1 or R1B responses
 432	 *	+ second status byte, for R2 responses
 433	 *	+ four data bytes, for R3 and R7 responses
 434	 *
 435	 * Finally, read some more bytes ... in the nice cases we know in
 436	 * advance how many, and reading 1 more is always OK:
 437	 *  - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
 438	 *  - N(RC) (== 1..N) bytes of all-ones, before next command
 439	 *  - N(WR) (== 1..N) bytes of all-ones, before data write
 440	 *
 441	 * So in those cases one full duplex I/O of at most 21 bytes will
 442	 * handle the whole command, leaving the card ready to receive a
 443	 * data block or new command.  We do that whenever we can, shaving
 444	 * CPU and IRQ costs (especially when using DMA or FIFOs).
 445	 *
 446	 * There are two other cases, where it's not generally practical
 447	 * to rely on a single I/O:
 448	 *
 449	 *  - R1B responses need at least N(EC) bytes of all-zeroes.
 450	 *
 451	 *    In this case we can *try* to fit it into one I/O, then
 452	 *    maybe read more data later.
 453	 *
 454	 *  - Data block reads are more troublesome, since a variable
 455	 *    number of padding bytes precede the token and data.
 456	 *      + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
 457	 *      + N(AC) (== 1..many) bytes of all-ones
 458	 *
 459	 *    In this case we currently only have minimal speedups here:
 460	 *    when N(CR) == 1 we can avoid I/O in response_get().
 461	 */
 462	if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
 463		cp += 2;	/* min(N(CR)) + status */
 464		/* R1 */
 465	} else {
 466		cp += 10;	/* max(N(CR)) + status + min(N(RC),N(WR)) */
 467		if (cmd->flags & MMC_RSP_SPI_S2)	/* R2/R5 */
 468			cp++;
 469		else if (cmd->flags & MMC_RSP_SPI_B4)	/* R3/R4/R7 */
 470			cp += 4;
 471		else if (cmd->flags & MMC_RSP_BUSY)	/* R1B */
 472			cp = data->status + sizeof(data->status);
 473		/* else:  R1 (most commands) */
 474	}
 475
 476	dev_dbg(&host->spi->dev, "  CMD%d, resp %s\n",
 477		cmd->opcode, maptype(cmd));
 478
 479	/* send command, leaving chipselect active */
 480	spi_message_init(&host->m);
 481
 482	t = &host->t;
 483	memset(t, 0, sizeof(*t));
 484	t->tx_buf = t->rx_buf = data->status;
 
 485	t->len = cp - data->status;
 486	t->cs_change = 1;
 487	spi_message_add_tail(t, &host->m);
 488
 
 
 
 
 
 
 489	status = spi_sync_locked(host->spi, &host->m);
 
 
 
 
 
 490	if (status < 0) {
 491		dev_dbg(&host->spi->dev, "  ... write returned %d\n", status);
 492		cmd->error = status;
 493		return status;
 494	}
 495
 496	/* after no-data commands and STOP_TRANSMISSION, chipselect off */
 497	return mmc_spi_response_get(host, cmd, cs_on);
 498}
 499
 500/* Build data message with up to four separate transfers.  For TX, we
 501 * start by writing the data token.  And in most cases, we finish with
 502 * a status transfer.
 503 *
 504 * We always provide TX data for data and CRC.  The MMC/SD protocol
 505 * requires us to write ones; but Linux defaults to writing zeroes;
 506 * so we explicitly initialize it to all ones on RX paths.
 
 
 
 507 */
 508static void
 509mmc_spi_setup_data_message(struct mmc_spi_host *host, bool multiple, bool write)
 
 
 
 510{
 511	struct spi_transfer	*t;
 512	struct scratch		*scratch = host->data;
 
 513
 514	spi_message_init(&host->m);
 
 
 515
 516	/* for reads, readblock() skips 0xff bytes before finding
 517	 * the token; for writes, this transfer issues that token.
 518	 */
 519	if (write) {
 520		t = &host->token;
 521		memset(t, 0, sizeof(*t));
 522		t->len = 1;
 523		if (multiple)
 524			scratch->data_token = SPI_TOKEN_MULTI_WRITE;
 525		else
 526			scratch->data_token = SPI_TOKEN_SINGLE;
 527		t->tx_buf = &scratch->data_token;
 
 
 528		spi_message_add_tail(t, &host->m);
 529	}
 530
 531	/* Body of transfer is buffer, then CRC ...
 532	 * either TX-only, or RX with TX-ones.
 533	 */
 534	t = &host->t;
 535	memset(t, 0, sizeof(*t));
 536	t->tx_buf = host->ones;
 
 537	/* length and actual buffer info are written later */
 538	spi_message_add_tail(t, &host->m);
 539
 540	t = &host->crc;
 541	memset(t, 0, sizeof(*t));
 542	t->len = 2;
 543	if (write) {
 544		/* the actual CRC may get written later */
 545		t->tx_buf = &scratch->crc_val;
 
 
 546	} else {
 547		t->tx_buf = host->ones;
 
 548		t->rx_buf = &scratch->crc_val;
 
 
 549	}
 550	spi_message_add_tail(t, &host->m);
 551
 552	/*
 553	 * A single block read is followed by N(EC) [0+] all-ones bytes
 554	 * before deselect ... don't bother.
 555	 *
 556	 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
 557	 * the next block is read, or a STOP_TRANSMISSION is issued.  We'll
 558	 * collect that single byte, so readblock() doesn't need to.
 559	 *
 560	 * For a write, the one-byte data response follows immediately, then
 561	 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
 562	 * Then single block reads may deselect, and multiblock ones issue
 563	 * the next token (next data block, or STOP_TRAN).  We can try to
 564	 * minimize I/O ops by using a single read to collect end-of-busy.
 565	 */
 566	if (multiple || write) {
 567		t = &host->early_status;
 568		memset(t, 0, sizeof(*t));
 569		t->len = write ? sizeof(scratch->status) : 1;
 570		t->tx_buf = host->ones;
 
 571		t->rx_buf = scratch->status;
 
 
 572		t->cs_change = 1;
 573		spi_message_add_tail(t, &host->m);
 574	}
 575}
 576
 577/*
 578 * Write one block:
 579 *  - caller handled preceding N(WR) [1+] all-ones bytes
 580 *  - data block
 581 *	+ token
 582 *	+ data bytes
 583 *	+ crc16
 584 *  - an all-ones byte ... card writes a data-response byte
 585 *  - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
 586 *
 587 * Return negative errno, else success.
 588 */
 589static int
 590mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
 591	unsigned long timeout)
 592{
 593	struct spi_device	*spi = host->spi;
 594	int			status, i;
 595	struct scratch		*scratch = host->data;
 596	u32			pattern;
 597
 598	if (host->mmc->use_spi_crc)
 599		scratch->crc_val = cpu_to_be16(crc_itu_t(0, t->tx_buf, t->len));
 
 
 
 
 600
 601	status = spi_sync_locked(spi, &host->m);
 
 602	if (status != 0) {
 603		dev_dbg(&spi->dev, "write error (%d)\n", status);
 604		return status;
 605	}
 606
 
 
 
 
 
 607	/*
 608	 * Get the transmission data-response reply.  It must follow
 609	 * immediately after the data block we transferred.  This reply
 610	 * doesn't necessarily tell whether the write operation succeeded;
 611	 * it just says if the transmission was ok and whether *earlier*
 612	 * writes succeeded; see the standard.
 613	 *
 614	 * In practice, there are (even modern SDHC-)cards which are late
 615	 * in sending the response, and miss the time frame by a few bits,
 616	 * so we have to cope with this situation and check the response
 617	 * bit-by-bit. Arggh!!!
 618	 */
 619	pattern = get_unaligned_be32(scratch->status);
 620
 621	/* First 3 bit of pattern are undefined */
 622	pattern |= 0xE0000000;
 623
 624	/* left-adjust to leading 0 bit */
 625	while (pattern & 0x80000000)
 626		pattern <<= 1;
 627	/* right-adjust for pattern matching. Code is in bit 4..0 now. */
 628	pattern >>= 27;
 629
 630	switch (pattern) {
 631	case SPI_RESPONSE_ACCEPTED:
 632		status = 0;
 633		break;
 634	case SPI_RESPONSE_CRC_ERR:
 635		/* host shall then issue MMC_STOP_TRANSMISSION */
 636		status = -EILSEQ;
 637		break;
 638	case SPI_RESPONSE_WRITE_ERR:
 639		/* host shall then issue MMC_STOP_TRANSMISSION,
 640		 * and should MMC_SEND_STATUS to sort it out
 641		 */
 642		status = -EIO;
 643		break;
 644	default:
 645		status = -EPROTO;
 646		break;
 647	}
 648	if (status != 0) {
 649		dev_dbg(&spi->dev, "write error %02x (%d)\n",
 650			scratch->status[0], status);
 651		return status;
 652	}
 653
 654	t->tx_buf += t->len;
 
 
 655
 656	/* Return when not busy.  If we didn't collect that status yet,
 657	 * we'll need some more I/O.
 658	 */
 659	for (i = 4; i < sizeof(scratch->status); i++) {
 660		/* card is non-busy if the most recent bit is 1 */
 661		if (scratch->status[i] & 0x01)
 662			return 0;
 663	}
 664	return mmc_spi_wait_unbusy(host, timeout);
 665}
 666
 667/*
 668 * Read one block:
 669 *  - skip leading all-ones bytes ... either
 670 *      + N(AC) [1..f(clock,CSD)] usually, else
 671 *      + N(CX) [0..8] when reading CSD or CID
 672 *  - data block
 673 *	+ token ... if error token, no data or crc
 674 *	+ data bytes
 675 *	+ crc16
 676 *
 677 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
 678 * before dropping chipselect.
 679 *
 680 * For multiblock reads, caller either reads the next block or issues a
 681 * STOP_TRANSMISSION command.
 682 */
 683static int
 684mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
 685	unsigned long timeout)
 686{
 687	struct spi_device	*spi = host->spi;
 688	int			status;
 689	struct scratch		*scratch = host->data;
 690	unsigned int 		bitshift;
 691	u8			leftover;
 692
 693	/* At least one SD card sends an all-zeroes byte when N(CX)
 694	 * applies, before the all-ones bytes ... just cope with that.
 695	 */
 696	status = mmc_spi_readbytes(host, 1);
 697	if (status < 0)
 698		return status;
 699	status = scratch->status[0];
 700	if (status == 0xff || status == 0)
 701		status = mmc_spi_readtoken(host, timeout);
 702
 703	if (status < 0) {
 704		dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
 705		return status;
 706	}
 707
 708	/* The token may be bit-shifted...
 709	 * the first 0-bit precedes the data stream.
 710	 */
 711	bitshift = 7;
 712	while (status & 0x80) {
 713		status <<= 1;
 714		bitshift--;
 715	}
 716	leftover = status << 1;
 717
 
 
 
 
 
 
 
 
 
 718	status = spi_sync_locked(spi, &host->m);
 719	if (status < 0) {
 720		dev_dbg(&spi->dev, "read error %d\n", status);
 721		return status;
 722	}
 723
 
 
 
 
 
 
 
 
 
 724	if (bitshift) {
 725		/* Walk through the data and the crc and do
 726		 * all the magic to get byte-aligned data.
 727		 */
 728		u8 *cp = t->rx_buf;
 729		unsigned int len;
 730		unsigned int bitright = 8 - bitshift;
 731		u8 temp;
 732		for (len = t->len; len; len--) {
 733			temp = *cp;
 734			*cp++ = leftover | (temp >> bitshift);
 735			leftover = temp << bitright;
 736		}
 737		cp = (u8 *) &scratch->crc_val;
 738		temp = *cp;
 739		*cp++ = leftover | (temp >> bitshift);
 740		leftover = temp << bitright;
 741		temp = *cp;
 742		*cp = leftover | (temp >> bitshift);
 743	}
 744
 745	if (host->mmc->use_spi_crc) {
 746		u16 crc = crc_itu_t(0, t->rx_buf, t->len);
 747
 748		be16_to_cpus(&scratch->crc_val);
 749		if (scratch->crc_val != crc) {
 750			dev_dbg(&spi->dev,
 751				"read - crc error: crc_val=0x%04x, computed=0x%04x len=%d\n",
 752				scratch->crc_val, crc, t->len);
 753			return -EILSEQ;
 754		}
 755	}
 756
 757	t->rx_buf += t->len;
 
 
 758
 759	return 0;
 760}
 761
 762/*
 763 * An MMC/SD data stage includes one or more blocks, optional CRCs,
 764 * and inline handshaking.  That handhaking makes it unlike most
 765 * other SPI protocol stacks.
 766 */
 767static void
 768mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
 769		struct mmc_data *data, u32 blk_size)
 770{
 771	struct spi_device	*spi = host->spi;
 
 772	struct spi_transfer	*t;
 
 773	struct scatterlist	*sg;
 774	unsigned		n_sg;
 775	bool			multiple = (data->blocks > 1);
 776	bool			write = (data->flags & MMC_DATA_WRITE);
 777	const char		*write_or_read = write ? "write" : "read";
 778	u32			clock_rate;
 779	unsigned long		timeout;
 780
 781	mmc_spi_setup_data_message(host, multiple, write);
 
 782	t = &host->t;
 783
 784	if (t->speed_hz)
 785		clock_rate = t->speed_hz;
 786	else
 787		clock_rate = spi->max_speed_hz;
 788
 789	timeout = data->timeout_ns / 1000 +
 790		  data->timeout_clks * 1000000 / clock_rate;
 791	timeout = usecs_to_jiffies((unsigned int)timeout) + 1;
 792
 793	/* Handle scatterlist segments one at a time, with synch for
 794	 * each 512-byte block
 795	 */
 796	for_each_sg(data->sg, sg, data->sg_len, n_sg) {
 797		int			status = 0;
 
 798		void			*kmap_addr;
 799		unsigned		length = sg->length;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 800
 801		/* allow pio too; we don't allow highmem */
 802		kmap_addr = kmap(sg_page(sg));
 803		if (write)
 804			t->tx_buf = kmap_addr + sg->offset;
 805		else
 806			t->rx_buf = kmap_addr + sg->offset;
 807
 808		/* transfer each block, and update request status */
 809		while (length) {
 810			t->len = min(length, blk_size);
 811
 812			dev_dbg(&spi->dev, "    %s block, %d bytes\n", write_or_read, t->len);
 
 
 813
 814			if (write)
 815				status = mmc_spi_writeblock(host, t, timeout);
 816			else
 817				status = mmc_spi_readblock(host, t, timeout);
 818			if (status < 0)
 819				break;
 820
 821			data->bytes_xfered += t->len;
 822			length -= t->len;
 823
 824			if (!multiple)
 825				break;
 826		}
 827
 828		/* discard mappings */
 829		if (write)
 830			/* nothing to do */;
 831		else
 832			flush_dcache_page(sg_page(sg));
 833		kunmap(sg_page(sg));
 
 
 834
 835		if (status < 0) {
 836			data->error = status;
 837			dev_dbg(&spi->dev, "%s status %d\n", write_or_read, status);
 
 
 838			break;
 839		}
 840	}
 841
 842	/* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
 843	 * can be issued before multiblock writes.  Unlike its more widely
 844	 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
 845	 * that can affect the STOP_TRAN logic.   Complete (and current)
 846	 * MMC specs should sort that out before Linux starts using CMD23.
 847	 */
 848	if (write && multiple) {
 849		struct scratch	*scratch = host->data;
 850		int		tmp;
 851		const unsigned	statlen = sizeof(scratch->status);
 852
 853		dev_dbg(&spi->dev, "    STOP_TRAN\n");
 854
 855		/* Tweak the per-block message we set up earlier by morphing
 856		 * it to hold single buffer with the token followed by some
 857		 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
 858		 * "not busy any longer" status, and leave chip selected.
 859		 */
 860		INIT_LIST_HEAD(&host->m.transfers);
 861		list_add(&host->early_status.transfer_list,
 862				&host->m.transfers);
 863
 864		memset(scratch->status, 0xff, statlen);
 865		scratch->status[0] = SPI_TOKEN_STOP_TRAN;
 866
 867		host->early_status.tx_buf = host->early_status.rx_buf;
 
 868		host->early_status.len = statlen;
 869
 
 
 
 
 
 870		tmp = spi_sync_locked(spi, &host->m);
 
 
 
 
 
 
 871		if (tmp < 0) {
 872			if (!data->error)
 873				data->error = tmp;
 874			return;
 875		}
 876
 877		/* Ideally we collected "not busy" status with one I/O,
 878		 * avoiding wasteful byte-at-a-time scanning... but more
 879		 * I/O is often needed.
 880		 */
 881		for (tmp = 2; tmp < statlen; tmp++) {
 882			if (scratch->status[tmp] != 0)
 883				return;
 884		}
 885		tmp = mmc_spi_wait_unbusy(host, timeout);
 886		if (tmp < 0 && !data->error)
 887			data->error = tmp;
 888	}
 889}
 890
 891/****************************************************************************/
 892
 893/*
 894 * MMC driver implementation -- the interface to the MMC stack
 895 */
 896
 897static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
 898{
 899	struct mmc_spi_host	*host = mmc_priv(mmc);
 900	int			status = -EINVAL;
 901	int			crc_retry = 5;
 902	struct mmc_command	stop;
 903
 904#ifdef DEBUG
 905	/* MMC core and layered drivers *MUST* issue SPI-aware commands */
 906	{
 907		struct mmc_command	*cmd;
 908		int			invalid = 0;
 909
 910		cmd = mrq->cmd;
 911		if (!mmc_spi_resp_type(cmd)) {
 912			dev_dbg(&host->spi->dev, "bogus command\n");
 913			cmd->error = -EINVAL;
 914			invalid = 1;
 915		}
 916
 917		cmd = mrq->stop;
 918		if (cmd && !mmc_spi_resp_type(cmd)) {
 919			dev_dbg(&host->spi->dev, "bogus STOP command\n");
 920			cmd->error = -EINVAL;
 921			invalid = 1;
 922		}
 923
 924		if (invalid) {
 925			dump_stack();
 926			mmc_request_done(host->mmc, mrq);
 927			return;
 928		}
 929	}
 930#endif
 931
 932	/* request exclusive bus access */
 933	spi_bus_lock(host->spi->controller);
 934
 935crc_recover:
 936	/* issue command; then optionally data and stop */
 937	status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
 938	if (status == 0 && mrq->data) {
 939		mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
 940
 941		/*
 942		 * The SPI bus is not always reliable for large data transfers.
 943		 * If an occasional crc error is reported by the SD device with
 944		 * data read/write over SPI, it may be recovered by repeating
 945		 * the last SD command again. The retry count is set to 5 to
 946		 * ensure the driver passes stress tests.
 947		 */
 948		if (mrq->data->error == -EILSEQ && crc_retry) {
 949			stop.opcode = MMC_STOP_TRANSMISSION;
 950			stop.arg = 0;
 951			stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
 952			status = mmc_spi_command_send(host, mrq, &stop, 0);
 953			crc_retry--;
 954			mrq->data->error = 0;
 955			goto crc_recover;
 956		}
 957
 958		if (mrq->stop)
 959			status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
 960		else
 961			mmc_cs_off(host);
 962	}
 963
 964	/* release the bus */
 965	spi_bus_unlock(host->spi->controller);
 966
 967	mmc_request_done(host->mmc, mrq);
 968}
 969
 970/* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
 971 *
 972 * NOTE that here we can't know that the card has just been powered up;
 973 * not all MMC/SD sockets support power switching.
 974 *
 975 * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
 976 * this doesn't seem to do the right thing at all...
 977 */
 978static void mmc_spi_initsequence(struct mmc_spi_host *host)
 979{
 980	/* Try to be very sure any previous command has completed;
 981	 * wait till not-busy, skip debris from any old commands.
 982	 */
 983	mmc_spi_wait_unbusy(host, msecs_to_jiffies(MMC_SPI_INIT_TIMEOUT_MS));
 984	mmc_spi_readbytes(host, 10);
 985
 986	/*
 987	 * Do a burst with chipselect active-high.  We need to do this to
 988	 * meet the requirement of 74 clock cycles with both chipselect
 989	 * and CMD (MOSI) high before CMD0 ... after the card has been
 990	 * powered up to Vdd(min), and so is ready to take commands.
 991	 *
 992	 * Some cards are particularly needy of this (e.g. Viking "SD256")
 993	 * while most others don't seem to care.
 994	 *
 995	 * Note that this is one of the places MMC/SD plays games with the
 996	 * SPI protocol.  Another is that when chipselect is released while
 997	 * the card returns BUSY status, the clock must issue several cycles
 998	 * with chipselect high before the card will stop driving its output.
 999	 *
1000	 * SPI_CS_HIGH means "asserted" here. In some cases like when using
1001	 * GPIOs for chip select, SPI_CS_HIGH is set but this will be logically
1002	 * inverted by gpiolib, so if we want to ascertain to drive it high
1003	 * we should toggle the default with an XOR as we do here.
1004	 */
1005	host->spi->mode ^= SPI_CS_HIGH;
1006	if (spi_setup(host->spi) != 0) {
1007		/* Just warn; most cards work without it. */
1008		dev_warn(&host->spi->dev,
1009				"can't change chip-select polarity\n");
1010		host->spi->mode ^= SPI_CS_HIGH;
1011	} else {
1012		mmc_spi_readbytes(host, 18);
1013
1014		host->spi->mode ^= SPI_CS_HIGH;
1015		if (spi_setup(host->spi) != 0) {
1016			/* Wot, we can't get the same setup we had before? */
1017			dev_err(&host->spi->dev,
1018					"can't restore chip-select polarity\n");
1019		}
1020	}
1021}
1022
1023static char *mmc_powerstring(u8 power_mode)
1024{
1025	switch (power_mode) {
1026	case MMC_POWER_OFF: return "off";
1027	case MMC_POWER_UP:  return "up";
1028	case MMC_POWER_ON:  return "on";
1029	}
1030	return "?";
1031}
1032
1033static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1034{
1035	struct mmc_spi_host *host = mmc_priv(mmc);
1036
1037	if (host->power_mode != ios->power_mode) {
1038		int		canpower;
1039
1040		canpower = host->pdata && host->pdata->setpower;
1041
1042		dev_dbg(&host->spi->dev, "power %s (%d)%s\n",
1043				mmc_powerstring(ios->power_mode),
1044				ios->vdd,
1045				canpower ? ", can switch" : "");
1046
1047		/* switch power on/off if possible, accounting for
1048		 * max 250msec powerup time if needed.
1049		 */
1050		if (canpower) {
1051			switch (ios->power_mode) {
1052			case MMC_POWER_OFF:
1053			case MMC_POWER_UP:
1054				host->pdata->setpower(&host->spi->dev,
1055						ios->vdd);
1056				if (ios->power_mode == MMC_POWER_UP)
1057					msleep(host->powerup_msecs);
1058			}
1059		}
1060
1061		/* See 6.4.1 in the simplified SD card physical spec 2.0 */
1062		if (ios->power_mode == MMC_POWER_ON)
1063			mmc_spi_initsequence(host);
1064
1065		/* If powering down, ground all card inputs to avoid power
1066		 * delivery from data lines!  On a shared SPI bus, this
1067		 * will probably be temporary; 6.4.2 of the simplified SD
1068		 * spec says this must last at least 1msec.
1069		 *
1070		 *   - Clock low means CPOL 0, e.g. mode 0
1071		 *   - MOSI low comes from writing zero
1072		 *   - Chipselect is usually active low...
1073		 */
1074		if (canpower && ios->power_mode == MMC_POWER_OFF) {
1075			int mres;
1076			u8 nullbyte = 0;
1077
1078			host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1079			mres = spi_setup(host->spi);
1080			if (mres < 0)
1081				dev_dbg(&host->spi->dev,
1082					"switch to SPI mode 0 failed\n");
1083
1084			if (spi_write(host->spi, &nullbyte, 1) < 0)
1085				dev_dbg(&host->spi->dev,
1086					"put spi signals to low failed\n");
1087
1088			/*
1089			 * Now clock should be low due to spi mode 0;
1090			 * MOSI should be low because of written 0x00;
1091			 * chipselect should be low (it is active low)
1092			 * power supply is off, so now MMC is off too!
1093			 *
1094			 * FIXME no, chipselect can be high since the
1095			 * device is inactive and SPI_CS_HIGH is clear...
1096			 */
1097			msleep(10);
1098			if (mres == 0) {
1099				host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1100				mres = spi_setup(host->spi);
1101				if (mres < 0)
1102					dev_dbg(&host->spi->dev,
1103						"switch back to SPI mode 3 failed\n");
1104			}
1105		}
1106
1107		host->power_mode = ios->power_mode;
1108	}
1109
1110	if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1111		int		status;
1112
1113		host->spi->max_speed_hz = ios->clock;
1114		status = spi_setup(host->spi);
1115		dev_dbg(&host->spi->dev, "  clock to %d Hz, %d\n",
1116			host->spi->max_speed_hz, status);
1117	}
1118}
1119
1120static const struct mmc_host_ops mmc_spi_ops = {
1121	.request	= mmc_spi_request,
1122	.set_ios	= mmc_spi_set_ios,
1123	.get_ro		= mmc_gpio_get_ro,
1124	.get_cd		= mmc_gpio_get_cd,
1125};
1126
1127
1128/****************************************************************************/
1129
1130/*
1131 * SPI driver implementation
1132 */
1133
1134static irqreturn_t
1135mmc_spi_detect_irq(int irq, void *mmc)
1136{
1137	struct mmc_spi_host *host = mmc_priv(mmc);
1138	u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1139
1140	mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1141	return IRQ_HANDLED;
1142}
1143
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1144static int mmc_spi_probe(struct spi_device *spi)
1145{
1146	void			*ones;
1147	struct mmc_host		*mmc;
1148	struct mmc_spi_host	*host;
1149	int			status;
1150	bool			has_ro = false;
1151
1152	/* We rely on full duplex transfers, mostly to reduce
1153	 * per-transfer overheads (by making fewer transfers).
1154	 */
1155	if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX)
1156		return -EINVAL;
1157
1158	/* MMC and SD specs only seem to care that sampling is on the
1159	 * rising edge ... meaning SPI modes 0 or 3.  So either SPI mode
1160	 * should be legit.  We'll use mode 0 since the steady state is 0,
1161	 * which is appropriate for hotplugging, unless the platform data
1162	 * specify mode 3 (if hardware is not compatible to mode 0).
1163	 */
1164	if (spi->mode != SPI_MODE_3)
1165		spi->mode = SPI_MODE_0;
1166	spi->bits_per_word = 8;
1167
1168	status = spi_setup(spi);
1169	if (status < 0) {
1170		dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1171				spi->mode, spi->max_speed_hz / 1000,
1172				status);
1173		return status;
1174	}
1175
1176	/* We need a supply of ones to transmit.  This is the only time
1177	 * the CPU touches these, so cache coherency isn't a concern.
1178	 *
1179	 * NOTE if many systems use more than one MMC-over-SPI connector
1180	 * it'd save some memory to share this.  That's evidently rare.
1181	 */
1182	status = -ENOMEM;
1183	ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1184	if (!ones)
1185		goto nomem;
1186	memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1187
1188	mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1189	if (!mmc)
1190		goto nomem;
1191
1192	mmc->ops = &mmc_spi_ops;
1193	mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1194	mmc->max_segs = MMC_SPI_BLOCKSATONCE;
1195	mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1196	mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1197
1198	mmc->caps = MMC_CAP_SPI;
1199
1200	/* SPI doesn't need the lowspeed device identification thing for
1201	 * MMC or SD cards, since it never comes up in open drain mode.
1202	 * That's good; some SPI masters can't handle very low speeds!
1203	 *
1204	 * However, low speed SDIO cards need not handle over 400 KHz;
1205	 * that's the only reason not to use a few MHz for f_min (until
1206	 * the upper layer reads the target frequency from the CSD).
1207	 */
1208	if (spi->controller->min_speed_hz > 400000)
1209		dev_warn(&spi->dev,"Controller unable to reduce bus clock to 400 KHz\n");
1210
1211	mmc->f_min = max(spi->controller->min_speed_hz, 400000);
1212	mmc->f_max = spi->max_speed_hz;
1213
1214	host = mmc_priv(mmc);
1215	host->mmc = mmc;
1216	host->spi = spi;
1217
1218	host->ones = ones;
1219
1220	dev_set_drvdata(&spi->dev, mmc);
1221
1222	/* Platform data is used to hook up things like card sensing
1223	 * and power switching gpios.
1224	 */
1225	host->pdata = mmc_spi_get_pdata(spi);
1226	if (host->pdata)
1227		mmc->ocr_avail = host->pdata->ocr_mask;
1228	if (!mmc->ocr_avail) {
1229		dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1230		mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1231	}
1232	if (host->pdata && host->pdata->setpower) {
1233		host->powerup_msecs = host->pdata->powerup_msecs;
1234		if (!host->powerup_msecs || host->powerup_msecs > 250)
1235			host->powerup_msecs = 250;
1236	}
1237
1238	/* Preallocate buffers */
1239	host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1240	if (!host->data)
1241		goto fail_nobuf1;
1242
 
 
 
 
1243	/* setup message for status/busy readback */
1244	spi_message_init(&host->readback);
 
1245
1246	spi_message_add_tail(&host->status, &host->readback);
1247	host->status.tx_buf = host->ones;
 
1248	host->status.rx_buf = &host->data->status;
 
1249	host->status.cs_change = 1;
1250
1251	/* register card detect irq */
1252	if (host->pdata && host->pdata->init) {
1253		status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1254		if (status != 0)
1255			goto fail_glue_init;
1256	}
1257
1258	/* pass platform capabilities, if any */
1259	if (host->pdata) {
1260		mmc->caps |= host->pdata->caps;
1261		mmc->caps2 |= host->pdata->caps2;
1262	}
1263
1264	status = mmc_add_host(mmc);
1265	if (status != 0)
1266		goto fail_glue_init;
1267
1268	/*
1269	 * Index 0 is card detect
1270	 * Old boardfiles were specifying 1 ms as debounce
1271	 */
1272	status = mmc_gpiod_request_cd(mmc, NULL, 0, false, 1000);
1273	if (status == -EPROBE_DEFER)
1274		goto fail_gpiod_request;
1275	if (!status) {
1276		/*
1277		 * The platform has a CD GPIO signal that may support
1278		 * interrupts, so let mmc_gpiod_request_cd_irq() decide
1279		 * if polling is needed or not.
1280		 */
1281		mmc->caps &= ~MMC_CAP_NEEDS_POLL;
1282		mmc_gpiod_request_cd_irq(mmc);
1283	}
1284	mmc_detect_change(mmc, 0);
1285
1286	/* Index 1 is write protect/read only */
1287	status = mmc_gpiod_request_ro(mmc, NULL, 1, 0);
1288	if (status == -EPROBE_DEFER)
1289		goto fail_gpiod_request;
1290	if (!status)
1291		has_ro = true;
1292
1293	dev_info(&spi->dev, "SD/MMC host %s%s%s%s\n",
1294			dev_name(&mmc->class_dev),
 
1295			has_ro ? "" : ", no WP",
1296			(host->pdata && host->pdata->setpower)
1297				? "" : ", no poweroff",
1298			(mmc->caps & MMC_CAP_NEEDS_POLL)
1299				? ", cd polling" : "");
1300	return 0;
1301
1302fail_gpiod_request:
1303	mmc_remove_host(mmc);
1304fail_glue_init:
 
 
1305	kfree(host->data);
1306fail_nobuf1:
1307	mmc_spi_put_pdata(spi);
1308	mmc_free_host(mmc);
1309nomem:
1310	kfree(ones);
1311	return status;
1312}
1313
1314
1315static void mmc_spi_remove(struct spi_device *spi)
1316{
1317	struct mmc_host		*mmc = dev_get_drvdata(&spi->dev);
1318	struct mmc_spi_host	*host = mmc_priv(mmc);
1319
1320	/* prevent new mmc_detect_change() calls */
1321	if (host->pdata && host->pdata->exit)
1322		host->pdata->exit(&spi->dev, mmc);
1323
1324	mmc_remove_host(mmc);
1325
 
1326	kfree(host->data);
1327	kfree(host->ones);
1328
1329	spi->max_speed_hz = mmc->f_max;
1330	mmc_spi_put_pdata(spi);
1331	mmc_free_host(mmc);
 
1332}
1333
1334static const struct spi_device_id mmc_spi_dev_ids[] = {
1335	{ "mmc-spi-slot"},
1336	{ },
1337};
1338MODULE_DEVICE_TABLE(spi, mmc_spi_dev_ids);
1339
1340static const struct of_device_id mmc_spi_of_match_table[] = {
1341	{ .compatible = "mmc-spi-slot", },
1342	{},
1343};
1344MODULE_DEVICE_TABLE(of, mmc_spi_of_match_table);
1345
1346static struct spi_driver mmc_spi_driver = {
1347	.driver = {
1348		.name =		"mmc_spi",
1349		.of_match_table = mmc_spi_of_match_table,
1350	},
1351	.id_table =	mmc_spi_dev_ids,
1352	.probe =	mmc_spi_probe,
1353	.remove =	mmc_spi_remove,
1354};
1355
1356module_spi_driver(mmc_spi_driver);
1357
1358MODULE_AUTHOR("Mike Lavender, David Brownell, Hans-Peter Nilsson, Jan Nikitenko");
1359MODULE_DESCRIPTION("SPI SD/MMC host driver");
1360MODULE_LICENSE("GPL");
1361MODULE_ALIAS("spi:mmc_spi");