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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * A fairly generic DMA-API to IOMMU-API glue layer.
4 *
5 * Copyright (C) 2014-2015 ARM Ltd.
6 *
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
9 */
10
11#include <linux/acpi_iort.h>
12#include <linux/atomic.h>
13#include <linux/crash_dump.h>
14#include <linux/device.h>
15#include <linux/dma-direct.h>
16#include <linux/dma-map-ops.h>
17#include <linux/gfp.h>
18#include <linux/huge_mm.h>
19#include <linux/iommu.h>
20#include <linux/iommu-dma.h>
21#include <linux/iova.h>
22#include <linux/irq.h>
23#include <linux/list_sort.h>
24#include <linux/memremap.h>
25#include <linux/mm.h>
26#include <linux/mutex.h>
27#include <linux/of_iommu.h>
28#include <linux/pci.h>
29#include <linux/scatterlist.h>
30#include <linux/spinlock.h>
31#include <linux/swiotlb.h>
32#include <linux/vmalloc.h>
33#include <trace/events/swiotlb.h>
34
35#include "dma-iommu.h"
36#include "iommu-pages.h"
37
38struct iommu_dma_msi_page {
39 struct list_head list;
40 dma_addr_t iova;
41 phys_addr_t phys;
42};
43
44enum iommu_dma_cookie_type {
45 IOMMU_DMA_IOVA_COOKIE,
46 IOMMU_DMA_MSI_COOKIE,
47};
48
49enum iommu_dma_queue_type {
50 IOMMU_DMA_OPTS_PER_CPU_QUEUE,
51 IOMMU_DMA_OPTS_SINGLE_QUEUE,
52};
53
54struct iommu_dma_options {
55 enum iommu_dma_queue_type qt;
56 size_t fq_size;
57 unsigned int fq_timeout;
58};
59
60struct iommu_dma_cookie {
61 enum iommu_dma_cookie_type type;
62 union {
63 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
64 struct {
65 struct iova_domain iovad;
66 /* Flush queue */
67 union {
68 struct iova_fq *single_fq;
69 struct iova_fq __percpu *percpu_fq;
70 };
71 /* Number of TLB flushes that have been started */
72 atomic64_t fq_flush_start_cnt;
73 /* Number of TLB flushes that have been finished */
74 atomic64_t fq_flush_finish_cnt;
75 /* Timer to regularily empty the flush queues */
76 struct timer_list fq_timer;
77 /* 1 when timer is active, 0 when not */
78 atomic_t fq_timer_on;
79 };
80 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
81 dma_addr_t msi_iova;
82 };
83 struct list_head msi_page_list;
84
85 /* Domain for flush queue callback; NULL if flush queue not in use */
86 struct iommu_domain *fq_domain;
87 /* Options for dma-iommu use */
88 struct iommu_dma_options options;
89 struct mutex mutex;
90};
91
92static DEFINE_STATIC_KEY_FALSE(iommu_deferred_attach_enabled);
93bool iommu_dma_forcedac __read_mostly;
94
95static int __init iommu_dma_forcedac_setup(char *str)
96{
97 int ret = kstrtobool(str, &iommu_dma_forcedac);
98
99 if (!ret && iommu_dma_forcedac)
100 pr_info("Forcing DAC for PCI devices\n");
101 return ret;
102}
103early_param("iommu.forcedac", iommu_dma_forcedac_setup);
104
105/* Number of entries per flush queue */
106#define IOVA_DEFAULT_FQ_SIZE 256
107#define IOVA_SINGLE_FQ_SIZE 32768
108
109/* Timeout (in ms) after which entries are flushed from the queue */
110#define IOVA_DEFAULT_FQ_TIMEOUT 10
111#define IOVA_SINGLE_FQ_TIMEOUT 1000
112
113/* Flush queue entry for deferred flushing */
114struct iova_fq_entry {
115 unsigned long iova_pfn;
116 unsigned long pages;
117 struct list_head freelist;
118 u64 counter; /* Flush counter when this entry was added */
119};
120
121/* Per-CPU flush queue structure */
122struct iova_fq {
123 spinlock_t lock;
124 unsigned int head, tail;
125 unsigned int mod_mask;
126 struct iova_fq_entry entries[];
127};
128
129#define fq_ring_for_each(i, fq) \
130 for ((i) = (fq)->head; (i) != (fq)->tail; (i) = ((i) + 1) & (fq)->mod_mask)
131
132static inline bool fq_full(struct iova_fq *fq)
133{
134 assert_spin_locked(&fq->lock);
135 return (((fq->tail + 1) & fq->mod_mask) == fq->head);
136}
137
138static inline unsigned int fq_ring_add(struct iova_fq *fq)
139{
140 unsigned int idx = fq->tail;
141
142 assert_spin_locked(&fq->lock);
143
144 fq->tail = (idx + 1) & fq->mod_mask;
145
146 return idx;
147}
148
149static void fq_ring_free_locked(struct iommu_dma_cookie *cookie, struct iova_fq *fq)
150{
151 u64 counter = atomic64_read(&cookie->fq_flush_finish_cnt);
152 unsigned int idx;
153
154 assert_spin_locked(&fq->lock);
155
156 fq_ring_for_each(idx, fq) {
157
158 if (fq->entries[idx].counter >= counter)
159 break;
160
161 iommu_put_pages_list(&fq->entries[idx].freelist);
162 free_iova_fast(&cookie->iovad,
163 fq->entries[idx].iova_pfn,
164 fq->entries[idx].pages);
165
166 fq->head = (fq->head + 1) & fq->mod_mask;
167 }
168}
169
170static void fq_ring_free(struct iommu_dma_cookie *cookie, struct iova_fq *fq)
171{
172 unsigned long flags;
173
174 spin_lock_irqsave(&fq->lock, flags);
175 fq_ring_free_locked(cookie, fq);
176 spin_unlock_irqrestore(&fq->lock, flags);
177}
178
179static void fq_flush_iotlb(struct iommu_dma_cookie *cookie)
180{
181 atomic64_inc(&cookie->fq_flush_start_cnt);
182 cookie->fq_domain->ops->flush_iotlb_all(cookie->fq_domain);
183 atomic64_inc(&cookie->fq_flush_finish_cnt);
184}
185
186static void fq_flush_timeout(struct timer_list *t)
187{
188 struct iommu_dma_cookie *cookie = from_timer(cookie, t, fq_timer);
189 int cpu;
190
191 atomic_set(&cookie->fq_timer_on, 0);
192 fq_flush_iotlb(cookie);
193
194 if (cookie->options.qt == IOMMU_DMA_OPTS_SINGLE_QUEUE) {
195 fq_ring_free(cookie, cookie->single_fq);
196 } else {
197 for_each_possible_cpu(cpu)
198 fq_ring_free(cookie, per_cpu_ptr(cookie->percpu_fq, cpu));
199 }
200}
201
202static void queue_iova(struct iommu_dma_cookie *cookie,
203 unsigned long pfn, unsigned long pages,
204 struct list_head *freelist)
205{
206 struct iova_fq *fq;
207 unsigned long flags;
208 unsigned int idx;
209
210 /*
211 * Order against the IOMMU driver's pagetable update from unmapping
212 * @pte, to guarantee that fq_flush_iotlb() observes that if called
213 * from a different CPU before we release the lock below. Full barrier
214 * so it also pairs with iommu_dma_init_fq() to avoid seeing partially
215 * written fq state here.
216 */
217 smp_mb();
218
219 if (cookie->options.qt == IOMMU_DMA_OPTS_SINGLE_QUEUE)
220 fq = cookie->single_fq;
221 else
222 fq = raw_cpu_ptr(cookie->percpu_fq);
223
224 spin_lock_irqsave(&fq->lock, flags);
225
226 /*
227 * First remove all entries from the flush queue that have already been
228 * flushed out on another CPU. This makes the fq_full() check below less
229 * likely to be true.
230 */
231 fq_ring_free_locked(cookie, fq);
232
233 if (fq_full(fq)) {
234 fq_flush_iotlb(cookie);
235 fq_ring_free_locked(cookie, fq);
236 }
237
238 idx = fq_ring_add(fq);
239
240 fq->entries[idx].iova_pfn = pfn;
241 fq->entries[idx].pages = pages;
242 fq->entries[idx].counter = atomic64_read(&cookie->fq_flush_start_cnt);
243 list_splice(freelist, &fq->entries[idx].freelist);
244
245 spin_unlock_irqrestore(&fq->lock, flags);
246
247 /* Avoid false sharing as much as possible. */
248 if (!atomic_read(&cookie->fq_timer_on) &&
249 !atomic_xchg(&cookie->fq_timer_on, 1))
250 mod_timer(&cookie->fq_timer,
251 jiffies + msecs_to_jiffies(cookie->options.fq_timeout));
252}
253
254static void iommu_dma_free_fq_single(struct iova_fq *fq)
255{
256 int idx;
257
258 fq_ring_for_each(idx, fq)
259 iommu_put_pages_list(&fq->entries[idx].freelist);
260 vfree(fq);
261}
262
263static void iommu_dma_free_fq_percpu(struct iova_fq __percpu *percpu_fq)
264{
265 int cpu, idx;
266
267 /* The IOVAs will be torn down separately, so just free our queued pages */
268 for_each_possible_cpu(cpu) {
269 struct iova_fq *fq = per_cpu_ptr(percpu_fq, cpu);
270
271 fq_ring_for_each(idx, fq)
272 iommu_put_pages_list(&fq->entries[idx].freelist);
273 }
274
275 free_percpu(percpu_fq);
276}
277
278static void iommu_dma_free_fq(struct iommu_dma_cookie *cookie)
279{
280 if (!cookie->fq_domain)
281 return;
282
283 del_timer_sync(&cookie->fq_timer);
284 if (cookie->options.qt == IOMMU_DMA_OPTS_SINGLE_QUEUE)
285 iommu_dma_free_fq_single(cookie->single_fq);
286 else
287 iommu_dma_free_fq_percpu(cookie->percpu_fq);
288}
289
290static void iommu_dma_init_one_fq(struct iova_fq *fq, size_t fq_size)
291{
292 int i;
293
294 fq->head = 0;
295 fq->tail = 0;
296 fq->mod_mask = fq_size - 1;
297
298 spin_lock_init(&fq->lock);
299
300 for (i = 0; i < fq_size; i++)
301 INIT_LIST_HEAD(&fq->entries[i].freelist);
302}
303
304static int iommu_dma_init_fq_single(struct iommu_dma_cookie *cookie)
305{
306 size_t fq_size = cookie->options.fq_size;
307 struct iova_fq *queue;
308
309 queue = vmalloc(struct_size(queue, entries, fq_size));
310 if (!queue)
311 return -ENOMEM;
312 iommu_dma_init_one_fq(queue, fq_size);
313 cookie->single_fq = queue;
314
315 return 0;
316}
317
318static int iommu_dma_init_fq_percpu(struct iommu_dma_cookie *cookie)
319{
320 size_t fq_size = cookie->options.fq_size;
321 struct iova_fq __percpu *queue;
322 int cpu;
323
324 queue = __alloc_percpu(struct_size(queue, entries, fq_size),
325 __alignof__(*queue));
326 if (!queue)
327 return -ENOMEM;
328
329 for_each_possible_cpu(cpu)
330 iommu_dma_init_one_fq(per_cpu_ptr(queue, cpu), fq_size);
331 cookie->percpu_fq = queue;
332 return 0;
333}
334
335/* sysfs updates are serialised by the mutex of the group owning @domain */
336int iommu_dma_init_fq(struct iommu_domain *domain)
337{
338 struct iommu_dma_cookie *cookie = domain->iova_cookie;
339 int rc;
340
341 if (cookie->fq_domain)
342 return 0;
343
344 atomic64_set(&cookie->fq_flush_start_cnt, 0);
345 atomic64_set(&cookie->fq_flush_finish_cnt, 0);
346
347 if (cookie->options.qt == IOMMU_DMA_OPTS_SINGLE_QUEUE)
348 rc = iommu_dma_init_fq_single(cookie);
349 else
350 rc = iommu_dma_init_fq_percpu(cookie);
351
352 if (rc) {
353 pr_warn("iova flush queue initialization failed\n");
354 return -ENOMEM;
355 }
356
357 timer_setup(&cookie->fq_timer, fq_flush_timeout, 0);
358 atomic_set(&cookie->fq_timer_on, 0);
359 /*
360 * Prevent incomplete fq state being observable. Pairs with path from
361 * __iommu_dma_unmap() through iommu_dma_free_iova() to queue_iova()
362 */
363 smp_wmb();
364 WRITE_ONCE(cookie->fq_domain, domain);
365 return 0;
366}
367
368static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
369{
370 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
371 return cookie->iovad.granule;
372 return PAGE_SIZE;
373}
374
375static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
376{
377 struct iommu_dma_cookie *cookie;
378
379 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
380 if (cookie) {
381 INIT_LIST_HEAD(&cookie->msi_page_list);
382 cookie->type = type;
383 }
384 return cookie;
385}
386
387/**
388 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
389 * @domain: IOMMU domain to prepare for DMA-API usage
390 */
391int iommu_get_dma_cookie(struct iommu_domain *domain)
392{
393 if (domain->iova_cookie)
394 return -EEXIST;
395
396 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
397 if (!domain->iova_cookie)
398 return -ENOMEM;
399
400 mutex_init(&domain->iova_cookie->mutex);
401 return 0;
402}
403
404/**
405 * iommu_get_msi_cookie - Acquire just MSI remapping resources
406 * @domain: IOMMU domain to prepare
407 * @base: Start address of IOVA region for MSI mappings
408 *
409 * Users who manage their own IOVA allocation and do not want DMA API support,
410 * but would still like to take advantage of automatic MSI remapping, can use
411 * this to initialise their own domain appropriately. Users should reserve a
412 * contiguous IOVA region, starting at @base, large enough to accommodate the
413 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
414 * used by the devices attached to @domain.
415 */
416int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
417{
418 struct iommu_dma_cookie *cookie;
419
420 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
421 return -EINVAL;
422
423 if (domain->iova_cookie)
424 return -EEXIST;
425
426 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
427 if (!cookie)
428 return -ENOMEM;
429
430 cookie->msi_iova = base;
431 domain->iova_cookie = cookie;
432 return 0;
433}
434EXPORT_SYMBOL(iommu_get_msi_cookie);
435
436/**
437 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
438 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
439 * iommu_get_msi_cookie()
440 */
441void iommu_put_dma_cookie(struct iommu_domain *domain)
442{
443 struct iommu_dma_cookie *cookie = domain->iova_cookie;
444 struct iommu_dma_msi_page *msi, *tmp;
445
446 if (!cookie)
447 return;
448
449 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule) {
450 iommu_dma_free_fq(cookie);
451 put_iova_domain(&cookie->iovad);
452 }
453
454 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
455 list_del(&msi->list);
456 kfree(msi);
457 }
458 kfree(cookie);
459 domain->iova_cookie = NULL;
460}
461
462/**
463 * iommu_dma_get_resv_regions - Reserved region driver helper
464 * @dev: Device from iommu_get_resv_regions()
465 * @list: Reserved region list from iommu_get_resv_regions()
466 *
467 * IOMMU drivers can use this to implement their .get_resv_regions callback
468 * for general non-IOMMU-specific reservations. Currently, this covers GICv3
469 * ITS region reservation on ACPI based ARM platforms that may require HW MSI
470 * reservation.
471 */
472void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
473{
474
475 if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode))
476 iort_iommu_get_resv_regions(dev, list);
477
478 if (dev->of_node)
479 of_iommu_get_resv_regions(dev, list);
480}
481EXPORT_SYMBOL(iommu_dma_get_resv_regions);
482
483static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
484 phys_addr_t start, phys_addr_t end)
485{
486 struct iova_domain *iovad = &cookie->iovad;
487 struct iommu_dma_msi_page *msi_page;
488 int i, num_pages;
489
490 start -= iova_offset(iovad, start);
491 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
492
493 for (i = 0; i < num_pages; i++) {
494 msi_page = kmalloc(sizeof(*msi_page), GFP_KERNEL);
495 if (!msi_page)
496 return -ENOMEM;
497
498 msi_page->phys = start;
499 msi_page->iova = start;
500 INIT_LIST_HEAD(&msi_page->list);
501 list_add(&msi_page->list, &cookie->msi_page_list);
502 start += iovad->granule;
503 }
504
505 return 0;
506}
507
508static int iommu_dma_ranges_sort(void *priv, const struct list_head *a,
509 const struct list_head *b)
510{
511 struct resource_entry *res_a = list_entry(a, typeof(*res_a), node);
512 struct resource_entry *res_b = list_entry(b, typeof(*res_b), node);
513
514 return res_a->res->start > res_b->res->start;
515}
516
517static int iova_reserve_pci_windows(struct pci_dev *dev,
518 struct iova_domain *iovad)
519{
520 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
521 struct resource_entry *window;
522 unsigned long lo, hi;
523 phys_addr_t start = 0, end;
524
525 resource_list_for_each_entry(window, &bridge->windows) {
526 if (resource_type(window->res) != IORESOURCE_MEM)
527 continue;
528
529 lo = iova_pfn(iovad, window->res->start - window->offset);
530 hi = iova_pfn(iovad, window->res->end - window->offset);
531 reserve_iova(iovad, lo, hi);
532 }
533
534 /* Get reserved DMA windows from host bridge */
535 list_sort(NULL, &bridge->dma_ranges, iommu_dma_ranges_sort);
536 resource_list_for_each_entry(window, &bridge->dma_ranges) {
537 end = window->res->start - window->offset;
538resv_iova:
539 if (end > start) {
540 lo = iova_pfn(iovad, start);
541 hi = iova_pfn(iovad, end);
542 reserve_iova(iovad, lo, hi);
543 } else if (end < start) {
544 /* DMA ranges should be non-overlapping */
545 dev_err(&dev->dev,
546 "Failed to reserve IOVA [%pa-%pa]\n",
547 &start, &end);
548 return -EINVAL;
549 }
550
551 start = window->res->end - window->offset + 1;
552 /* If window is last entry */
553 if (window->node.next == &bridge->dma_ranges &&
554 end != ~(phys_addr_t)0) {
555 end = ~(phys_addr_t)0;
556 goto resv_iova;
557 }
558 }
559
560 return 0;
561}
562
563static int iova_reserve_iommu_regions(struct device *dev,
564 struct iommu_domain *domain)
565{
566 struct iommu_dma_cookie *cookie = domain->iova_cookie;
567 struct iova_domain *iovad = &cookie->iovad;
568 struct iommu_resv_region *region;
569 LIST_HEAD(resv_regions);
570 int ret = 0;
571
572 if (dev_is_pci(dev)) {
573 ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad);
574 if (ret)
575 return ret;
576 }
577
578 iommu_get_resv_regions(dev, &resv_regions);
579 list_for_each_entry(region, &resv_regions, list) {
580 unsigned long lo, hi;
581
582 /* We ARE the software that manages these! */
583 if (region->type == IOMMU_RESV_SW_MSI)
584 continue;
585
586 lo = iova_pfn(iovad, region->start);
587 hi = iova_pfn(iovad, region->start + region->length - 1);
588 reserve_iova(iovad, lo, hi);
589
590 if (region->type == IOMMU_RESV_MSI)
591 ret = cookie_init_hw_msi_region(cookie, region->start,
592 region->start + region->length);
593 if (ret)
594 break;
595 }
596 iommu_put_resv_regions(dev, &resv_regions);
597
598 return ret;
599}
600
601static bool dev_is_untrusted(struct device *dev)
602{
603 return dev_is_pci(dev) && to_pci_dev(dev)->untrusted;
604}
605
606static bool dev_use_swiotlb(struct device *dev, size_t size,
607 enum dma_data_direction dir)
608{
609 return IS_ENABLED(CONFIG_SWIOTLB) &&
610 (dev_is_untrusted(dev) ||
611 dma_kmalloc_needs_bounce(dev, size, dir));
612}
613
614static bool dev_use_sg_swiotlb(struct device *dev, struct scatterlist *sg,
615 int nents, enum dma_data_direction dir)
616{
617 struct scatterlist *s;
618 int i;
619
620 if (!IS_ENABLED(CONFIG_SWIOTLB))
621 return false;
622
623 if (dev_is_untrusted(dev))
624 return true;
625
626 /*
627 * If kmalloc() buffers are not DMA-safe for this device and
628 * direction, check the individual lengths in the sg list. If any
629 * element is deemed unsafe, use the swiotlb for bouncing.
630 */
631 if (!dma_kmalloc_safe(dev, dir)) {
632 for_each_sg(sg, s, nents, i)
633 if (!dma_kmalloc_size_aligned(s->length))
634 return true;
635 }
636
637 return false;
638}
639
640/**
641 * iommu_dma_init_options - Initialize dma-iommu options
642 * @options: The options to be initialized
643 * @dev: Device the options are set for
644 *
645 * This allows tuning dma-iommu specific to device properties
646 */
647static void iommu_dma_init_options(struct iommu_dma_options *options,
648 struct device *dev)
649{
650 /* Shadowing IOTLB flushes do better with a single large queue */
651 if (dev->iommu->shadow_on_flush) {
652 options->qt = IOMMU_DMA_OPTS_SINGLE_QUEUE;
653 options->fq_timeout = IOVA_SINGLE_FQ_TIMEOUT;
654 options->fq_size = IOVA_SINGLE_FQ_SIZE;
655 } else {
656 options->qt = IOMMU_DMA_OPTS_PER_CPU_QUEUE;
657 options->fq_size = IOVA_DEFAULT_FQ_SIZE;
658 options->fq_timeout = IOVA_DEFAULT_FQ_TIMEOUT;
659 }
660}
661
662/**
663 * iommu_dma_init_domain - Initialise a DMA mapping domain
664 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
665 * @dev: Device the domain is being initialised for
666 *
667 * If the geometry and dma_range_map include address 0, we reserve that page
668 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
669 * any change which could make prior IOVAs invalid will fail.
670 */
671static int iommu_dma_init_domain(struct iommu_domain *domain, struct device *dev)
672{
673 struct iommu_dma_cookie *cookie = domain->iova_cookie;
674 const struct bus_dma_region *map = dev->dma_range_map;
675 unsigned long order, base_pfn;
676 struct iova_domain *iovad;
677 int ret;
678
679 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
680 return -EINVAL;
681
682 iovad = &cookie->iovad;
683
684 /* Use the smallest supported page size for IOVA granularity */
685 order = __ffs(domain->pgsize_bitmap);
686 base_pfn = 1;
687
688 /* Check the domain allows at least some access to the device... */
689 if (map) {
690 if (dma_range_map_min(map) > domain->geometry.aperture_end ||
691 dma_range_map_max(map) < domain->geometry.aperture_start) {
692 pr_warn("specified DMA range outside IOMMU capability\n");
693 return -EFAULT;
694 }
695 }
696 /* ...then finally give it a kicking to make sure it fits */
697 base_pfn = max_t(unsigned long, base_pfn,
698 domain->geometry.aperture_start >> order);
699
700 /* start_pfn is always nonzero for an already-initialised domain */
701 mutex_lock(&cookie->mutex);
702 if (iovad->start_pfn) {
703 if (1UL << order != iovad->granule ||
704 base_pfn != iovad->start_pfn) {
705 pr_warn("Incompatible range for DMA domain\n");
706 ret = -EFAULT;
707 goto done_unlock;
708 }
709
710 ret = 0;
711 goto done_unlock;
712 }
713
714 init_iova_domain(iovad, 1UL << order, base_pfn);
715 ret = iova_domain_init_rcaches(iovad);
716 if (ret)
717 goto done_unlock;
718
719 iommu_dma_init_options(&cookie->options, dev);
720
721 /* If the FQ fails we can simply fall back to strict mode */
722 if (domain->type == IOMMU_DOMAIN_DMA_FQ &&
723 (!device_iommu_capable(dev, IOMMU_CAP_DEFERRED_FLUSH) || iommu_dma_init_fq(domain)))
724 domain->type = IOMMU_DOMAIN_DMA;
725
726 ret = iova_reserve_iommu_regions(dev, domain);
727
728done_unlock:
729 mutex_unlock(&cookie->mutex);
730 return ret;
731}
732
733/**
734 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
735 * page flags.
736 * @dir: Direction of DMA transfer
737 * @coherent: Is the DMA master cache-coherent?
738 * @attrs: DMA attributes for the mapping
739 *
740 * Return: corresponding IOMMU API page protection flags
741 */
742static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
743 unsigned long attrs)
744{
745 int prot = coherent ? IOMMU_CACHE : 0;
746
747 if (attrs & DMA_ATTR_PRIVILEGED)
748 prot |= IOMMU_PRIV;
749
750 switch (dir) {
751 case DMA_BIDIRECTIONAL:
752 return prot | IOMMU_READ | IOMMU_WRITE;
753 case DMA_TO_DEVICE:
754 return prot | IOMMU_READ;
755 case DMA_FROM_DEVICE:
756 return prot | IOMMU_WRITE;
757 default:
758 return 0;
759 }
760}
761
762static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
763 size_t size, u64 dma_limit, struct device *dev)
764{
765 struct iommu_dma_cookie *cookie = domain->iova_cookie;
766 struct iova_domain *iovad = &cookie->iovad;
767 unsigned long shift, iova_len, iova;
768
769 if (cookie->type == IOMMU_DMA_MSI_COOKIE) {
770 cookie->msi_iova += size;
771 return cookie->msi_iova - size;
772 }
773
774 shift = iova_shift(iovad);
775 iova_len = size >> shift;
776
777 dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit);
778
779 if (domain->geometry.force_aperture)
780 dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end);
781
782 /*
783 * Try to use all the 32-bit PCI addresses first. The original SAC vs.
784 * DAC reasoning loses relevance with PCIe, but enough hardware and
785 * firmware bugs are still lurking out there that it's safest not to
786 * venture into the 64-bit space until necessary.
787 *
788 * If your device goes wrong after seeing the notice then likely either
789 * its driver is not setting DMA masks accurately, the hardware has
790 * some inherent bug in handling >32-bit addresses, or not all the
791 * expected address bits are wired up between the device and the IOMMU.
792 */
793 if (dma_limit > DMA_BIT_MASK(32) && dev->iommu->pci_32bit_workaround) {
794 iova = alloc_iova_fast(iovad, iova_len,
795 DMA_BIT_MASK(32) >> shift, false);
796 if (iova)
797 goto done;
798
799 dev->iommu->pci_32bit_workaround = false;
800 dev_notice(dev, "Using %d-bit DMA addresses\n", bits_per(dma_limit));
801 }
802
803 iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift, true);
804done:
805 return (dma_addr_t)iova << shift;
806}
807
808static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie,
809 dma_addr_t iova, size_t size, struct iommu_iotlb_gather *gather)
810{
811 struct iova_domain *iovad = &cookie->iovad;
812
813 /* The MSI case is only ever cleaning up its most recent allocation */
814 if (cookie->type == IOMMU_DMA_MSI_COOKIE)
815 cookie->msi_iova -= size;
816 else if (gather && gather->queued)
817 queue_iova(cookie, iova_pfn(iovad, iova),
818 size >> iova_shift(iovad),
819 &gather->freelist);
820 else
821 free_iova_fast(iovad, iova_pfn(iovad, iova),
822 size >> iova_shift(iovad));
823}
824
825static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr,
826 size_t size)
827{
828 struct iommu_domain *domain = iommu_get_dma_domain(dev);
829 struct iommu_dma_cookie *cookie = domain->iova_cookie;
830 struct iova_domain *iovad = &cookie->iovad;
831 size_t iova_off = iova_offset(iovad, dma_addr);
832 struct iommu_iotlb_gather iotlb_gather;
833 size_t unmapped;
834
835 dma_addr -= iova_off;
836 size = iova_align(iovad, size + iova_off);
837 iommu_iotlb_gather_init(&iotlb_gather);
838 iotlb_gather.queued = READ_ONCE(cookie->fq_domain);
839
840 unmapped = iommu_unmap_fast(domain, dma_addr, size, &iotlb_gather);
841 WARN_ON(unmapped != size);
842
843 if (!iotlb_gather.queued)
844 iommu_iotlb_sync(domain, &iotlb_gather);
845 iommu_dma_free_iova(cookie, dma_addr, size, &iotlb_gather);
846}
847
848static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
849 size_t size, int prot, u64 dma_mask)
850{
851 struct iommu_domain *domain = iommu_get_dma_domain(dev);
852 struct iommu_dma_cookie *cookie = domain->iova_cookie;
853 struct iova_domain *iovad = &cookie->iovad;
854 size_t iova_off = iova_offset(iovad, phys);
855 dma_addr_t iova;
856
857 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
858 iommu_deferred_attach(dev, domain))
859 return DMA_MAPPING_ERROR;
860
861 /* If anyone ever wants this we'd need support in the IOVA allocator */
862 if (dev_WARN_ONCE(dev, dma_get_min_align_mask(dev) > iova_mask(iovad),
863 "Unsupported alignment constraint\n"))
864 return DMA_MAPPING_ERROR;
865
866 size = iova_align(iovad, size + iova_off);
867
868 iova = iommu_dma_alloc_iova(domain, size, dma_mask, dev);
869 if (!iova)
870 return DMA_MAPPING_ERROR;
871
872 if (iommu_map(domain, iova, phys - iova_off, size, prot, GFP_ATOMIC)) {
873 iommu_dma_free_iova(cookie, iova, size, NULL);
874 return DMA_MAPPING_ERROR;
875 }
876 return iova + iova_off;
877}
878
879static void __iommu_dma_free_pages(struct page **pages, int count)
880{
881 while (count--)
882 __free_page(pages[count]);
883 kvfree(pages);
884}
885
886static struct page **__iommu_dma_alloc_pages(struct device *dev,
887 unsigned int count, unsigned long order_mask, gfp_t gfp)
888{
889 struct page **pages;
890 unsigned int i = 0, nid = dev_to_node(dev);
891
892 order_mask &= GENMASK(MAX_PAGE_ORDER, 0);
893 if (!order_mask)
894 return NULL;
895
896 pages = kvcalloc(count, sizeof(*pages), GFP_KERNEL);
897 if (!pages)
898 return NULL;
899
900 /* IOMMU can map any pages, so himem can also be used here */
901 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
902
903 while (count) {
904 struct page *page = NULL;
905 unsigned int order_size;
906
907 /*
908 * Higher-order allocations are a convenience rather
909 * than a necessity, hence using __GFP_NORETRY until
910 * falling back to minimum-order allocations.
911 */
912 for (order_mask &= GENMASK(__fls(count), 0);
913 order_mask; order_mask &= ~order_size) {
914 unsigned int order = __fls(order_mask);
915 gfp_t alloc_flags = gfp;
916
917 order_size = 1U << order;
918 if (order_mask > order_size)
919 alloc_flags |= __GFP_NORETRY;
920 page = alloc_pages_node(nid, alloc_flags, order);
921 if (!page)
922 continue;
923 if (order)
924 split_page(page, order);
925 break;
926 }
927 if (!page) {
928 __iommu_dma_free_pages(pages, i);
929 return NULL;
930 }
931 count -= order_size;
932 while (order_size--)
933 pages[i++] = page++;
934 }
935 return pages;
936}
937
938/*
939 * If size is less than PAGE_SIZE, then a full CPU page will be allocated,
940 * but an IOMMU which supports smaller pages might not map the whole thing.
941 */
942static struct page **__iommu_dma_alloc_noncontiguous(struct device *dev,
943 size_t size, struct sg_table *sgt, gfp_t gfp, unsigned long attrs)
944{
945 struct iommu_domain *domain = iommu_get_dma_domain(dev);
946 struct iommu_dma_cookie *cookie = domain->iova_cookie;
947 struct iova_domain *iovad = &cookie->iovad;
948 bool coherent = dev_is_dma_coherent(dev);
949 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
950 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
951 struct page **pages;
952 dma_addr_t iova;
953 ssize_t ret;
954
955 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
956 iommu_deferred_attach(dev, domain))
957 return NULL;
958
959 min_size = alloc_sizes & -alloc_sizes;
960 if (min_size < PAGE_SIZE) {
961 min_size = PAGE_SIZE;
962 alloc_sizes |= PAGE_SIZE;
963 } else {
964 size = ALIGN(size, min_size);
965 }
966 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
967 alloc_sizes = min_size;
968
969 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
970 pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT,
971 gfp);
972 if (!pages)
973 return NULL;
974
975 size = iova_align(iovad, size);
976 iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev);
977 if (!iova)
978 goto out_free_pages;
979
980 /*
981 * Remove the zone/policy flags from the GFP - these are applied to the
982 * __iommu_dma_alloc_pages() but are not used for the supporting
983 * internal allocations that follow.
984 */
985 gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM | __GFP_COMP);
986
987 if (sg_alloc_table_from_pages(sgt, pages, count, 0, size, gfp))
988 goto out_free_iova;
989
990 if (!(ioprot & IOMMU_CACHE)) {
991 struct scatterlist *sg;
992 int i;
993
994 for_each_sg(sgt->sgl, sg, sgt->orig_nents, i)
995 arch_dma_prep_coherent(sg_page(sg), sg->length);
996 }
997
998 ret = iommu_map_sg(domain, iova, sgt->sgl, sgt->orig_nents, ioprot,
999 gfp);
1000 if (ret < 0 || ret < size)
1001 goto out_free_sg;
1002
1003 sgt->sgl->dma_address = iova;
1004 sgt->sgl->dma_length = size;
1005 return pages;
1006
1007out_free_sg:
1008 sg_free_table(sgt);
1009out_free_iova:
1010 iommu_dma_free_iova(cookie, iova, size, NULL);
1011out_free_pages:
1012 __iommu_dma_free_pages(pages, count);
1013 return NULL;
1014}
1015
1016static void *iommu_dma_alloc_remap(struct device *dev, size_t size,
1017 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
1018{
1019 struct page **pages;
1020 struct sg_table sgt;
1021 void *vaddr;
1022 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
1023
1024 pages = __iommu_dma_alloc_noncontiguous(dev, size, &sgt, gfp, attrs);
1025 if (!pages)
1026 return NULL;
1027 *dma_handle = sgt.sgl->dma_address;
1028 sg_free_table(&sgt);
1029 vaddr = dma_common_pages_remap(pages, size, prot,
1030 __builtin_return_address(0));
1031 if (!vaddr)
1032 goto out_unmap;
1033 return vaddr;
1034
1035out_unmap:
1036 __iommu_dma_unmap(dev, *dma_handle, size);
1037 __iommu_dma_free_pages(pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
1038 return NULL;
1039}
1040
1041/*
1042 * This is the actual return value from the iommu_dma_alloc_noncontiguous.
1043 *
1044 * The users of the DMA API should only care about the sg_table, but to make
1045 * the DMA-API internal vmaping and freeing easier we stash away the page
1046 * array as well (except for the fallback case). This can go away any time,
1047 * e.g. when a vmap-variant that takes a scatterlist comes along.
1048 */
1049struct dma_sgt_handle {
1050 struct sg_table sgt;
1051 struct page **pages;
1052};
1053#define sgt_handle(sgt) \
1054 container_of((sgt), struct dma_sgt_handle, sgt)
1055
1056struct sg_table *iommu_dma_alloc_noncontiguous(struct device *dev, size_t size,
1057 enum dma_data_direction dir, gfp_t gfp, unsigned long attrs)
1058{
1059 struct dma_sgt_handle *sh;
1060
1061 sh = kmalloc(sizeof(*sh), gfp);
1062 if (!sh)
1063 return NULL;
1064
1065 sh->pages = __iommu_dma_alloc_noncontiguous(dev, size, &sh->sgt, gfp, attrs);
1066 if (!sh->pages) {
1067 kfree(sh);
1068 return NULL;
1069 }
1070 return &sh->sgt;
1071}
1072
1073void iommu_dma_free_noncontiguous(struct device *dev, size_t size,
1074 struct sg_table *sgt, enum dma_data_direction dir)
1075{
1076 struct dma_sgt_handle *sh = sgt_handle(sgt);
1077
1078 __iommu_dma_unmap(dev, sgt->sgl->dma_address, size);
1079 __iommu_dma_free_pages(sh->pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
1080 sg_free_table(&sh->sgt);
1081 kfree(sh);
1082}
1083
1084void *iommu_dma_vmap_noncontiguous(struct device *dev, size_t size,
1085 struct sg_table *sgt)
1086{
1087 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1088
1089 return vmap(sgt_handle(sgt)->pages, count, VM_MAP, PAGE_KERNEL);
1090}
1091
1092int iommu_dma_mmap_noncontiguous(struct device *dev, struct vm_area_struct *vma,
1093 size_t size, struct sg_table *sgt)
1094{
1095 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1096
1097 if (vma->vm_pgoff >= count || vma_pages(vma) > count - vma->vm_pgoff)
1098 return -ENXIO;
1099 return vm_map_pages(vma, sgt_handle(sgt)->pages, count);
1100}
1101
1102void iommu_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
1103 size_t size, enum dma_data_direction dir)
1104{
1105 phys_addr_t phys;
1106
1107 if (dev_is_dma_coherent(dev) && !dev_use_swiotlb(dev, size, dir))
1108 return;
1109
1110 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
1111 if (!dev_is_dma_coherent(dev))
1112 arch_sync_dma_for_cpu(phys, size, dir);
1113
1114 swiotlb_sync_single_for_cpu(dev, phys, size, dir);
1115}
1116
1117void iommu_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
1118 size_t size, enum dma_data_direction dir)
1119{
1120 phys_addr_t phys;
1121
1122 if (dev_is_dma_coherent(dev) && !dev_use_swiotlb(dev, size, dir))
1123 return;
1124
1125 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
1126 swiotlb_sync_single_for_device(dev, phys, size, dir);
1127
1128 if (!dev_is_dma_coherent(dev))
1129 arch_sync_dma_for_device(phys, size, dir);
1130}
1131
1132void iommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
1133 int nelems, enum dma_data_direction dir)
1134{
1135 struct scatterlist *sg;
1136 int i;
1137
1138 if (sg_dma_is_swiotlb(sgl))
1139 for_each_sg(sgl, sg, nelems, i)
1140 iommu_dma_sync_single_for_cpu(dev, sg_dma_address(sg),
1141 sg->length, dir);
1142 else if (!dev_is_dma_coherent(dev))
1143 for_each_sg(sgl, sg, nelems, i)
1144 arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir);
1145}
1146
1147void iommu_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
1148 int nelems, enum dma_data_direction dir)
1149{
1150 struct scatterlist *sg;
1151 int i;
1152
1153 if (sg_dma_is_swiotlb(sgl))
1154 for_each_sg(sgl, sg, nelems, i)
1155 iommu_dma_sync_single_for_device(dev,
1156 sg_dma_address(sg),
1157 sg->length, dir);
1158 else if (!dev_is_dma_coherent(dev))
1159 for_each_sg(sgl, sg, nelems, i)
1160 arch_sync_dma_for_device(sg_phys(sg), sg->length, dir);
1161}
1162
1163dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
1164 unsigned long offset, size_t size, enum dma_data_direction dir,
1165 unsigned long attrs)
1166{
1167 phys_addr_t phys = page_to_phys(page) + offset;
1168 bool coherent = dev_is_dma_coherent(dev);
1169 int prot = dma_info_to_prot(dir, coherent, attrs);
1170 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1171 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1172 struct iova_domain *iovad = &cookie->iovad;
1173 dma_addr_t iova, dma_mask = dma_get_mask(dev);
1174
1175 /*
1176 * If both the physical buffer start address and size are
1177 * page aligned, we don't need to use a bounce page.
1178 */
1179 if (dev_use_swiotlb(dev, size, dir) &&
1180 iova_offset(iovad, phys | size)) {
1181 if (!is_swiotlb_active(dev)) {
1182 dev_warn_once(dev, "DMA bounce buffers are inactive, unable to map unaligned transaction.\n");
1183 return DMA_MAPPING_ERROR;
1184 }
1185
1186 trace_swiotlb_bounced(dev, phys, size);
1187
1188 phys = swiotlb_tbl_map_single(dev, phys, size,
1189 iova_mask(iovad), dir, attrs);
1190
1191 if (phys == DMA_MAPPING_ERROR)
1192 return DMA_MAPPING_ERROR;
1193
1194 /*
1195 * Untrusted devices should not see padding areas with random
1196 * leftover kernel data, so zero the pre- and post-padding.
1197 * swiotlb_tbl_map_single() has initialized the bounce buffer
1198 * proper to the contents of the original memory buffer.
1199 */
1200 if (dev_is_untrusted(dev)) {
1201 size_t start, virt = (size_t)phys_to_virt(phys);
1202
1203 /* Pre-padding */
1204 start = iova_align_down(iovad, virt);
1205 memset((void *)start, 0, virt - start);
1206
1207 /* Post-padding */
1208 start = virt + size;
1209 memset((void *)start, 0,
1210 iova_align(iovad, start) - start);
1211 }
1212 }
1213
1214 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1215 arch_sync_dma_for_device(phys, size, dir);
1216
1217 iova = __iommu_dma_map(dev, phys, size, prot, dma_mask);
1218 if (iova == DMA_MAPPING_ERROR)
1219 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
1220 return iova;
1221}
1222
1223void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
1224 size_t size, enum dma_data_direction dir, unsigned long attrs)
1225{
1226 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1227 phys_addr_t phys;
1228
1229 phys = iommu_iova_to_phys(domain, dma_handle);
1230 if (WARN_ON(!phys))
1231 return;
1232
1233 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && !dev_is_dma_coherent(dev))
1234 arch_sync_dma_for_cpu(phys, size, dir);
1235
1236 __iommu_dma_unmap(dev, dma_handle, size);
1237
1238 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
1239}
1240
1241/*
1242 * Prepare a successfully-mapped scatterlist to give back to the caller.
1243 *
1244 * At this point the segments are already laid out by iommu_dma_map_sg() to
1245 * avoid individually crossing any boundaries, so we merely need to check a
1246 * segment's start address to avoid concatenating across one.
1247 */
1248static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
1249 dma_addr_t dma_addr)
1250{
1251 struct scatterlist *s, *cur = sg;
1252 unsigned long seg_mask = dma_get_seg_boundary(dev);
1253 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
1254 int i, count = 0;
1255
1256 for_each_sg(sg, s, nents, i) {
1257 /* Restore this segment's original unaligned fields first */
1258 dma_addr_t s_dma_addr = sg_dma_address(s);
1259 unsigned int s_iova_off = sg_dma_address(s);
1260 unsigned int s_length = sg_dma_len(s);
1261 unsigned int s_iova_len = s->length;
1262
1263 sg_dma_address(s) = DMA_MAPPING_ERROR;
1264 sg_dma_len(s) = 0;
1265
1266 if (sg_dma_is_bus_address(s)) {
1267 if (i > 0)
1268 cur = sg_next(cur);
1269
1270 sg_dma_unmark_bus_address(s);
1271 sg_dma_address(cur) = s_dma_addr;
1272 sg_dma_len(cur) = s_length;
1273 sg_dma_mark_bus_address(cur);
1274 count++;
1275 cur_len = 0;
1276 continue;
1277 }
1278
1279 s->offset += s_iova_off;
1280 s->length = s_length;
1281
1282 /*
1283 * Now fill in the real DMA data. If...
1284 * - there is a valid output segment to append to
1285 * - and this segment starts on an IOVA page boundary
1286 * - but doesn't fall at a segment boundary
1287 * - and wouldn't make the resulting output segment too long
1288 */
1289 if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
1290 (max_len - cur_len >= s_length)) {
1291 /* ...then concatenate it with the previous one */
1292 cur_len += s_length;
1293 } else {
1294 /* Otherwise start the next output segment */
1295 if (i > 0)
1296 cur = sg_next(cur);
1297 cur_len = s_length;
1298 count++;
1299
1300 sg_dma_address(cur) = dma_addr + s_iova_off;
1301 }
1302
1303 sg_dma_len(cur) = cur_len;
1304 dma_addr += s_iova_len;
1305
1306 if (s_length + s_iova_off < s_iova_len)
1307 cur_len = 0;
1308 }
1309 return count;
1310}
1311
1312/*
1313 * If mapping failed, then just restore the original list,
1314 * but making sure the DMA fields are invalidated.
1315 */
1316static void __invalidate_sg(struct scatterlist *sg, int nents)
1317{
1318 struct scatterlist *s;
1319 int i;
1320
1321 for_each_sg(sg, s, nents, i) {
1322 if (sg_dma_is_bus_address(s)) {
1323 sg_dma_unmark_bus_address(s);
1324 } else {
1325 if (sg_dma_address(s) != DMA_MAPPING_ERROR)
1326 s->offset += sg_dma_address(s);
1327 if (sg_dma_len(s))
1328 s->length = sg_dma_len(s);
1329 }
1330 sg_dma_address(s) = DMA_MAPPING_ERROR;
1331 sg_dma_len(s) = 0;
1332 }
1333}
1334
1335static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *sg,
1336 int nents, enum dma_data_direction dir, unsigned long attrs)
1337{
1338 struct scatterlist *s;
1339 int i;
1340
1341 for_each_sg(sg, s, nents, i)
1342 iommu_dma_unmap_page(dev, sg_dma_address(s),
1343 sg_dma_len(s), dir, attrs);
1344}
1345
1346static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg,
1347 int nents, enum dma_data_direction dir, unsigned long attrs)
1348{
1349 struct scatterlist *s;
1350 int i;
1351
1352 sg_dma_mark_swiotlb(sg);
1353
1354 for_each_sg(sg, s, nents, i) {
1355 sg_dma_address(s) = iommu_dma_map_page(dev, sg_page(s),
1356 s->offset, s->length, dir, attrs);
1357 if (sg_dma_address(s) == DMA_MAPPING_ERROR)
1358 goto out_unmap;
1359 sg_dma_len(s) = s->length;
1360 }
1361
1362 return nents;
1363
1364out_unmap:
1365 iommu_dma_unmap_sg_swiotlb(dev, sg, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
1366 return -EIO;
1367}
1368
1369/*
1370 * The DMA API client is passing in a scatterlist which could describe
1371 * any old buffer layout, but the IOMMU API requires everything to be
1372 * aligned to IOMMU pages. Hence the need for this complicated bit of
1373 * impedance-matching, to be able to hand off a suitably-aligned list,
1374 * but still preserve the original offsets and sizes for the caller.
1375 */
1376int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1377 enum dma_data_direction dir, unsigned long attrs)
1378{
1379 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1380 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1381 struct iova_domain *iovad = &cookie->iovad;
1382 struct scatterlist *s, *prev = NULL;
1383 int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs);
1384 struct pci_p2pdma_map_state p2pdma_state = {};
1385 enum pci_p2pdma_map_type map;
1386 dma_addr_t iova;
1387 size_t iova_len = 0;
1388 unsigned long mask = dma_get_seg_boundary(dev);
1389 ssize_t ret;
1390 int i;
1391
1392 if (static_branch_unlikely(&iommu_deferred_attach_enabled)) {
1393 ret = iommu_deferred_attach(dev, domain);
1394 if (ret)
1395 goto out;
1396 }
1397
1398 if (dev_use_sg_swiotlb(dev, sg, nents, dir))
1399 return iommu_dma_map_sg_swiotlb(dev, sg, nents, dir, attrs);
1400
1401 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1402 iommu_dma_sync_sg_for_device(dev, sg, nents, dir);
1403
1404 /*
1405 * Work out how much IOVA space we need, and align the segments to
1406 * IOVA granules for the IOMMU driver to handle. With some clever
1407 * trickery we can modify the list in-place, but reversibly, by
1408 * stashing the unaligned parts in the as-yet-unused DMA fields.
1409 */
1410 for_each_sg(sg, s, nents, i) {
1411 size_t s_iova_off = iova_offset(iovad, s->offset);
1412 size_t s_length = s->length;
1413 size_t pad_len = (mask - iova_len + 1) & mask;
1414
1415 if (is_pci_p2pdma_page(sg_page(s))) {
1416 map = pci_p2pdma_map_segment(&p2pdma_state, dev, s);
1417 switch (map) {
1418 case PCI_P2PDMA_MAP_BUS_ADDR:
1419 /*
1420 * iommu_map_sg() will skip this segment as
1421 * it is marked as a bus address,
1422 * __finalise_sg() will copy the dma address
1423 * into the output segment.
1424 */
1425 continue;
1426 case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
1427 /*
1428 * Mapping through host bridge should be
1429 * mapped with regular IOVAs, thus we
1430 * do nothing here and continue below.
1431 */
1432 break;
1433 default:
1434 ret = -EREMOTEIO;
1435 goto out_restore_sg;
1436 }
1437 }
1438
1439 sg_dma_address(s) = s_iova_off;
1440 sg_dma_len(s) = s_length;
1441 s->offset -= s_iova_off;
1442 s_length = iova_align(iovad, s_length + s_iova_off);
1443 s->length = s_length;
1444
1445 /*
1446 * Due to the alignment of our single IOVA allocation, we can
1447 * depend on these assumptions about the segment boundary mask:
1448 * - If mask size >= IOVA size, then the IOVA range cannot
1449 * possibly fall across a boundary, so we don't care.
1450 * - If mask size < IOVA size, then the IOVA range must start
1451 * exactly on a boundary, therefore we can lay things out
1452 * based purely on segment lengths without needing to know
1453 * the actual addresses beforehand.
1454 * - The mask must be a power of 2, so pad_len == 0 if
1455 * iova_len == 0, thus we cannot dereference prev the first
1456 * time through here (i.e. before it has a meaningful value).
1457 */
1458 if (pad_len && pad_len < s_length - 1) {
1459 prev->length += pad_len;
1460 iova_len += pad_len;
1461 }
1462
1463 iova_len += s_length;
1464 prev = s;
1465 }
1466
1467 if (!iova_len)
1468 return __finalise_sg(dev, sg, nents, 0);
1469
1470 iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev);
1471 if (!iova) {
1472 ret = -ENOMEM;
1473 goto out_restore_sg;
1474 }
1475
1476 /*
1477 * We'll leave any physical concatenation to the IOMMU driver's
1478 * implementation - it knows better than we do.
1479 */
1480 ret = iommu_map_sg(domain, iova, sg, nents, prot, GFP_ATOMIC);
1481 if (ret < 0 || ret < iova_len)
1482 goto out_free_iova;
1483
1484 return __finalise_sg(dev, sg, nents, iova);
1485
1486out_free_iova:
1487 iommu_dma_free_iova(cookie, iova, iova_len, NULL);
1488out_restore_sg:
1489 __invalidate_sg(sg, nents);
1490out:
1491 if (ret != -ENOMEM && ret != -EREMOTEIO)
1492 return -EINVAL;
1493 return ret;
1494}
1495
1496void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1497 enum dma_data_direction dir, unsigned long attrs)
1498{
1499 dma_addr_t end = 0, start;
1500 struct scatterlist *tmp;
1501 int i;
1502
1503 if (sg_dma_is_swiotlb(sg)) {
1504 iommu_dma_unmap_sg_swiotlb(dev, sg, nents, dir, attrs);
1505 return;
1506 }
1507
1508 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1509 iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir);
1510
1511 /*
1512 * The scatterlist segments are mapped into a single
1513 * contiguous IOVA allocation, the start and end points
1514 * just have to be determined.
1515 */
1516 for_each_sg(sg, tmp, nents, i) {
1517 if (sg_dma_is_bus_address(tmp)) {
1518 sg_dma_unmark_bus_address(tmp);
1519 continue;
1520 }
1521
1522 if (sg_dma_len(tmp) == 0)
1523 break;
1524
1525 start = sg_dma_address(tmp);
1526 break;
1527 }
1528
1529 nents -= i;
1530 for_each_sg(tmp, tmp, nents, i) {
1531 if (sg_dma_is_bus_address(tmp)) {
1532 sg_dma_unmark_bus_address(tmp);
1533 continue;
1534 }
1535
1536 if (sg_dma_len(tmp) == 0)
1537 break;
1538
1539 end = sg_dma_address(tmp) + sg_dma_len(tmp);
1540 }
1541
1542 if (end)
1543 __iommu_dma_unmap(dev, start, end - start);
1544}
1545
1546dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
1547 size_t size, enum dma_data_direction dir, unsigned long attrs)
1548{
1549 return __iommu_dma_map(dev, phys, size,
1550 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
1551 dma_get_mask(dev));
1552}
1553
1554void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
1555 size_t size, enum dma_data_direction dir, unsigned long attrs)
1556{
1557 __iommu_dma_unmap(dev, handle, size);
1558}
1559
1560static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
1561{
1562 size_t alloc_size = PAGE_ALIGN(size);
1563 int count = alloc_size >> PAGE_SHIFT;
1564 struct page *page = NULL, **pages = NULL;
1565
1566 /* Non-coherent atomic allocation? Easy */
1567 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1568 dma_free_from_pool(dev, cpu_addr, alloc_size))
1569 return;
1570
1571 if (is_vmalloc_addr(cpu_addr)) {
1572 /*
1573 * If it the address is remapped, then it's either non-coherent
1574 * or highmem CMA, or an iommu_dma_alloc_remap() construction.
1575 */
1576 pages = dma_common_find_pages(cpu_addr);
1577 if (!pages)
1578 page = vmalloc_to_page(cpu_addr);
1579 dma_common_free_remap(cpu_addr, alloc_size);
1580 } else {
1581 /* Lowmem means a coherent atomic or CMA allocation */
1582 page = virt_to_page(cpu_addr);
1583 }
1584
1585 if (pages)
1586 __iommu_dma_free_pages(pages, count);
1587 if (page)
1588 dma_free_contiguous(dev, page, alloc_size);
1589}
1590
1591void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
1592 dma_addr_t handle, unsigned long attrs)
1593{
1594 __iommu_dma_unmap(dev, handle, size);
1595 __iommu_dma_free(dev, size, cpu_addr);
1596}
1597
1598static void *iommu_dma_alloc_pages(struct device *dev, size_t size,
1599 struct page **pagep, gfp_t gfp, unsigned long attrs)
1600{
1601 bool coherent = dev_is_dma_coherent(dev);
1602 size_t alloc_size = PAGE_ALIGN(size);
1603 int node = dev_to_node(dev);
1604 struct page *page = NULL;
1605 void *cpu_addr;
1606
1607 page = dma_alloc_contiguous(dev, alloc_size, gfp);
1608 if (!page)
1609 page = alloc_pages_node(node, gfp, get_order(alloc_size));
1610 if (!page)
1611 return NULL;
1612
1613 if (!coherent || PageHighMem(page)) {
1614 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
1615
1616 cpu_addr = dma_common_contiguous_remap(page, alloc_size,
1617 prot, __builtin_return_address(0));
1618 if (!cpu_addr)
1619 goto out_free_pages;
1620
1621 if (!coherent)
1622 arch_dma_prep_coherent(page, size);
1623 } else {
1624 cpu_addr = page_address(page);
1625 }
1626
1627 *pagep = page;
1628 memset(cpu_addr, 0, alloc_size);
1629 return cpu_addr;
1630out_free_pages:
1631 dma_free_contiguous(dev, page, alloc_size);
1632 return NULL;
1633}
1634
1635void *iommu_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
1636 gfp_t gfp, unsigned long attrs)
1637{
1638 bool coherent = dev_is_dma_coherent(dev);
1639 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
1640 struct page *page = NULL;
1641 void *cpu_addr;
1642
1643 gfp |= __GFP_ZERO;
1644
1645 if (gfpflags_allow_blocking(gfp) &&
1646 !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) {
1647 return iommu_dma_alloc_remap(dev, size, handle, gfp, attrs);
1648 }
1649
1650 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1651 !gfpflags_allow_blocking(gfp) && !coherent)
1652 page = dma_alloc_from_pool(dev, PAGE_ALIGN(size), &cpu_addr,
1653 gfp, NULL);
1654 else
1655 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);
1656 if (!cpu_addr)
1657 return NULL;
1658
1659 *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot,
1660 dev->coherent_dma_mask);
1661 if (*handle == DMA_MAPPING_ERROR) {
1662 __iommu_dma_free(dev, size, cpu_addr);
1663 return NULL;
1664 }
1665
1666 return cpu_addr;
1667}
1668
1669int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
1670 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1671 unsigned long attrs)
1672{
1673 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1674 unsigned long pfn, off = vma->vm_pgoff;
1675 int ret;
1676
1677 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
1678
1679 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
1680 return ret;
1681
1682 if (off >= nr_pages || vma_pages(vma) > nr_pages - off)
1683 return -ENXIO;
1684
1685 if (is_vmalloc_addr(cpu_addr)) {
1686 struct page **pages = dma_common_find_pages(cpu_addr);
1687
1688 if (pages)
1689 return vm_map_pages(vma, pages, nr_pages);
1690 pfn = vmalloc_to_pfn(cpu_addr);
1691 } else {
1692 pfn = page_to_pfn(virt_to_page(cpu_addr));
1693 }
1694
1695 return remap_pfn_range(vma, vma->vm_start, pfn + off,
1696 vma->vm_end - vma->vm_start,
1697 vma->vm_page_prot);
1698}
1699
1700int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
1701 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1702 unsigned long attrs)
1703{
1704 struct page *page;
1705 int ret;
1706
1707 if (is_vmalloc_addr(cpu_addr)) {
1708 struct page **pages = dma_common_find_pages(cpu_addr);
1709
1710 if (pages) {
1711 return sg_alloc_table_from_pages(sgt, pages,
1712 PAGE_ALIGN(size) >> PAGE_SHIFT,
1713 0, size, GFP_KERNEL);
1714 }
1715
1716 page = vmalloc_to_page(cpu_addr);
1717 } else {
1718 page = virt_to_page(cpu_addr);
1719 }
1720
1721 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
1722 if (!ret)
1723 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
1724 return ret;
1725}
1726
1727unsigned long iommu_dma_get_merge_boundary(struct device *dev)
1728{
1729 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1730
1731 return (1UL << __ffs(domain->pgsize_bitmap)) - 1;
1732}
1733
1734size_t iommu_dma_opt_mapping_size(void)
1735{
1736 return iova_rcache_range();
1737}
1738
1739size_t iommu_dma_max_mapping_size(struct device *dev)
1740{
1741 if (dev_is_untrusted(dev))
1742 return swiotlb_max_mapping_size(dev);
1743
1744 return SIZE_MAX;
1745}
1746
1747void iommu_setup_dma_ops(struct device *dev)
1748{
1749 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1750
1751 if (dev_is_pci(dev))
1752 dev->iommu->pci_32bit_workaround = !iommu_dma_forcedac;
1753
1754 dev->dma_iommu = iommu_is_dma_domain(domain);
1755 if (dev->dma_iommu && iommu_dma_init_domain(domain, dev))
1756 goto out_err;
1757
1758 return;
1759out_err:
1760 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
1761 dev_name(dev));
1762 dev->dma_iommu = false;
1763}
1764
1765static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
1766 phys_addr_t msi_addr, struct iommu_domain *domain)
1767{
1768 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1769 struct iommu_dma_msi_page *msi_page;
1770 dma_addr_t iova;
1771 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1772 size_t size = cookie_msi_granule(cookie);
1773
1774 msi_addr &= ~(phys_addr_t)(size - 1);
1775 list_for_each_entry(msi_page, &cookie->msi_page_list, list)
1776 if (msi_page->phys == msi_addr)
1777 return msi_page;
1778
1779 msi_page = kzalloc(sizeof(*msi_page), GFP_KERNEL);
1780 if (!msi_page)
1781 return NULL;
1782
1783 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
1784 if (!iova)
1785 goto out_free_page;
1786
1787 if (iommu_map(domain, iova, msi_addr, size, prot, GFP_KERNEL))
1788 goto out_free_iova;
1789
1790 INIT_LIST_HEAD(&msi_page->list);
1791 msi_page->phys = msi_addr;
1792 msi_page->iova = iova;
1793 list_add(&msi_page->list, &cookie->msi_page_list);
1794 return msi_page;
1795
1796out_free_iova:
1797 iommu_dma_free_iova(cookie, iova, size, NULL);
1798out_free_page:
1799 kfree(msi_page);
1800 return NULL;
1801}
1802
1803/**
1804 * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain
1805 * @desc: MSI descriptor, will store the MSI page
1806 * @msi_addr: MSI target address to be mapped
1807 *
1808 * Return: 0 on success or negative error code if the mapping failed.
1809 */
1810int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
1811{
1812 struct device *dev = msi_desc_to_dev(desc);
1813 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1814 struct iommu_dma_msi_page *msi_page;
1815 static DEFINE_MUTEX(msi_prepare_lock); /* see below */
1816
1817 if (!domain || !domain->iova_cookie) {
1818 desc->iommu_cookie = NULL;
1819 return 0;
1820 }
1821
1822 /*
1823 * In fact the whole prepare operation should already be serialised by
1824 * irq_domain_mutex further up the callchain, but that's pretty subtle
1825 * on its own, so consider this locking as failsafe documentation...
1826 */
1827 mutex_lock(&msi_prepare_lock);
1828 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
1829 mutex_unlock(&msi_prepare_lock);
1830
1831 msi_desc_set_iommu_cookie(desc, msi_page);
1832
1833 if (!msi_page)
1834 return -ENOMEM;
1835 return 0;
1836}
1837
1838/**
1839 * iommu_dma_compose_msi_msg() - Apply translation to an MSI message
1840 * @desc: MSI descriptor prepared by iommu_dma_prepare_msi()
1841 * @msg: MSI message containing target physical address
1842 */
1843void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1844{
1845 struct device *dev = msi_desc_to_dev(desc);
1846 const struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1847 const struct iommu_dma_msi_page *msi_page;
1848
1849 msi_page = msi_desc_get_iommu_cookie(desc);
1850
1851 if (!domain || !domain->iova_cookie || WARN_ON(!msi_page))
1852 return;
1853
1854 msg->address_hi = upper_32_bits(msi_page->iova);
1855 msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1;
1856 msg->address_lo += lower_32_bits(msi_page->iova);
1857}
1858
1859static int iommu_dma_init(void)
1860{
1861 if (is_kdump_kernel())
1862 static_branch_enable(&iommu_deferred_attach_enabled);
1863
1864 return iova_cache_get();
1865}
1866arch_initcall(iommu_dma_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * A fairly generic DMA-API to IOMMU-API glue layer.
4 *
5 * Copyright (C) 2014-2015 ARM Ltd.
6 *
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
9 */
10
11#include <linux/acpi_iort.h>
12#include <linux/device.h>
13#include <linux/dma-map-ops.h>
14#include <linux/dma-iommu.h>
15#include <linux/gfp.h>
16#include <linux/huge_mm.h>
17#include <linux/iommu.h>
18#include <linux/iova.h>
19#include <linux/irq.h>
20#include <linux/mm.h>
21#include <linux/mutex.h>
22#include <linux/pci.h>
23#include <linux/swiotlb.h>
24#include <linux/scatterlist.h>
25#include <linux/vmalloc.h>
26#include <linux/crash_dump.h>
27#include <linux/dma-direct.h>
28
29struct iommu_dma_msi_page {
30 struct list_head list;
31 dma_addr_t iova;
32 phys_addr_t phys;
33};
34
35enum iommu_dma_cookie_type {
36 IOMMU_DMA_IOVA_COOKIE,
37 IOMMU_DMA_MSI_COOKIE,
38};
39
40struct iommu_dma_cookie {
41 enum iommu_dma_cookie_type type;
42 union {
43 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
44 struct iova_domain iovad;
45 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
46 dma_addr_t msi_iova;
47 };
48 struct list_head msi_page_list;
49
50 /* Domain for flush queue callback; NULL if flush queue not in use */
51 struct iommu_domain *fq_domain;
52};
53
54static DEFINE_STATIC_KEY_FALSE(iommu_deferred_attach_enabled);
55bool iommu_dma_forcedac __read_mostly;
56
57static int __init iommu_dma_forcedac_setup(char *str)
58{
59 int ret = kstrtobool(str, &iommu_dma_forcedac);
60
61 if (!ret && iommu_dma_forcedac)
62 pr_info("Forcing DAC for PCI devices\n");
63 return ret;
64}
65early_param("iommu.forcedac", iommu_dma_forcedac_setup);
66
67static void iommu_dma_entry_dtor(unsigned long data)
68{
69 struct page *freelist = (struct page *)data;
70
71 while (freelist) {
72 unsigned long p = (unsigned long)page_address(freelist);
73
74 freelist = freelist->freelist;
75 free_page(p);
76 }
77}
78
79static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
80{
81 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
82 return cookie->iovad.granule;
83 return PAGE_SIZE;
84}
85
86static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
87{
88 struct iommu_dma_cookie *cookie;
89
90 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
91 if (cookie) {
92 INIT_LIST_HEAD(&cookie->msi_page_list);
93 cookie->type = type;
94 }
95 return cookie;
96}
97
98/**
99 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
100 * @domain: IOMMU domain to prepare for DMA-API usage
101 *
102 * IOMMU drivers should normally call this from their domain_alloc
103 * callback when domain->type == IOMMU_DOMAIN_DMA.
104 */
105int iommu_get_dma_cookie(struct iommu_domain *domain)
106{
107 if (domain->iova_cookie)
108 return -EEXIST;
109
110 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
111 if (!domain->iova_cookie)
112 return -ENOMEM;
113
114 return 0;
115}
116EXPORT_SYMBOL(iommu_get_dma_cookie);
117
118/**
119 * iommu_get_msi_cookie - Acquire just MSI remapping resources
120 * @domain: IOMMU domain to prepare
121 * @base: Start address of IOVA region for MSI mappings
122 *
123 * Users who manage their own IOVA allocation and do not want DMA API support,
124 * but would still like to take advantage of automatic MSI remapping, can use
125 * this to initialise their own domain appropriately. Users should reserve a
126 * contiguous IOVA region, starting at @base, large enough to accommodate the
127 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
128 * used by the devices attached to @domain.
129 */
130int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
131{
132 struct iommu_dma_cookie *cookie;
133
134 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
135 return -EINVAL;
136
137 if (domain->iova_cookie)
138 return -EEXIST;
139
140 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
141 if (!cookie)
142 return -ENOMEM;
143
144 cookie->msi_iova = base;
145 domain->iova_cookie = cookie;
146 return 0;
147}
148EXPORT_SYMBOL(iommu_get_msi_cookie);
149
150/**
151 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
152 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
153 * iommu_get_msi_cookie()
154 *
155 * IOMMU drivers should normally call this from their domain_free callback.
156 */
157void iommu_put_dma_cookie(struct iommu_domain *domain)
158{
159 struct iommu_dma_cookie *cookie = domain->iova_cookie;
160 struct iommu_dma_msi_page *msi, *tmp;
161
162 if (!cookie)
163 return;
164
165 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
166 put_iova_domain(&cookie->iovad);
167
168 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
169 list_del(&msi->list);
170 kfree(msi);
171 }
172 kfree(cookie);
173 domain->iova_cookie = NULL;
174}
175EXPORT_SYMBOL(iommu_put_dma_cookie);
176
177/**
178 * iommu_dma_get_resv_regions - Reserved region driver helper
179 * @dev: Device from iommu_get_resv_regions()
180 * @list: Reserved region list from iommu_get_resv_regions()
181 *
182 * IOMMU drivers can use this to implement their .get_resv_regions callback
183 * for general non-IOMMU-specific reservations. Currently, this covers GICv3
184 * ITS region reservation on ACPI based ARM platforms that may require HW MSI
185 * reservation.
186 */
187void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
188{
189
190 if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode))
191 iort_iommu_msi_get_resv_regions(dev, list);
192
193}
194EXPORT_SYMBOL(iommu_dma_get_resv_regions);
195
196static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
197 phys_addr_t start, phys_addr_t end)
198{
199 struct iova_domain *iovad = &cookie->iovad;
200 struct iommu_dma_msi_page *msi_page;
201 int i, num_pages;
202
203 start -= iova_offset(iovad, start);
204 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
205
206 for (i = 0; i < num_pages; i++) {
207 msi_page = kmalloc(sizeof(*msi_page), GFP_KERNEL);
208 if (!msi_page)
209 return -ENOMEM;
210
211 msi_page->phys = start;
212 msi_page->iova = start;
213 INIT_LIST_HEAD(&msi_page->list);
214 list_add(&msi_page->list, &cookie->msi_page_list);
215 start += iovad->granule;
216 }
217
218 return 0;
219}
220
221static int iova_reserve_pci_windows(struct pci_dev *dev,
222 struct iova_domain *iovad)
223{
224 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
225 struct resource_entry *window;
226 unsigned long lo, hi;
227 phys_addr_t start = 0, end;
228
229 resource_list_for_each_entry(window, &bridge->windows) {
230 if (resource_type(window->res) != IORESOURCE_MEM)
231 continue;
232
233 lo = iova_pfn(iovad, window->res->start - window->offset);
234 hi = iova_pfn(iovad, window->res->end - window->offset);
235 reserve_iova(iovad, lo, hi);
236 }
237
238 /* Get reserved DMA windows from host bridge */
239 resource_list_for_each_entry(window, &bridge->dma_ranges) {
240 end = window->res->start - window->offset;
241resv_iova:
242 if (end > start) {
243 lo = iova_pfn(iovad, start);
244 hi = iova_pfn(iovad, end);
245 reserve_iova(iovad, lo, hi);
246 } else if (end < start) {
247 /* dma_ranges list should be sorted */
248 dev_err(&dev->dev,
249 "Failed to reserve IOVA [%pa-%pa]\n",
250 &start, &end);
251 return -EINVAL;
252 }
253
254 start = window->res->end - window->offset + 1;
255 /* If window is last entry */
256 if (window->node.next == &bridge->dma_ranges &&
257 end != ~(phys_addr_t)0) {
258 end = ~(phys_addr_t)0;
259 goto resv_iova;
260 }
261 }
262
263 return 0;
264}
265
266static int iova_reserve_iommu_regions(struct device *dev,
267 struct iommu_domain *domain)
268{
269 struct iommu_dma_cookie *cookie = domain->iova_cookie;
270 struct iova_domain *iovad = &cookie->iovad;
271 struct iommu_resv_region *region;
272 LIST_HEAD(resv_regions);
273 int ret = 0;
274
275 if (dev_is_pci(dev)) {
276 ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad);
277 if (ret)
278 return ret;
279 }
280
281 iommu_get_resv_regions(dev, &resv_regions);
282 list_for_each_entry(region, &resv_regions, list) {
283 unsigned long lo, hi;
284
285 /* We ARE the software that manages these! */
286 if (region->type == IOMMU_RESV_SW_MSI)
287 continue;
288
289 lo = iova_pfn(iovad, region->start);
290 hi = iova_pfn(iovad, region->start + region->length - 1);
291 reserve_iova(iovad, lo, hi);
292
293 if (region->type == IOMMU_RESV_MSI)
294 ret = cookie_init_hw_msi_region(cookie, region->start,
295 region->start + region->length);
296 if (ret)
297 break;
298 }
299 iommu_put_resv_regions(dev, &resv_regions);
300
301 return ret;
302}
303
304static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad)
305{
306 struct iommu_dma_cookie *cookie;
307 struct iommu_domain *domain;
308
309 cookie = container_of(iovad, struct iommu_dma_cookie, iovad);
310 domain = cookie->fq_domain;
311
312 domain->ops->flush_iotlb_all(domain);
313}
314
315static bool dev_is_untrusted(struct device *dev)
316{
317 return dev_is_pci(dev) && to_pci_dev(dev)->untrusted;
318}
319
320/**
321 * iommu_dma_init_domain - Initialise a DMA mapping domain
322 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
323 * @base: IOVA at which the mappable address space starts
324 * @limit: Last address of the IOVA space
325 * @dev: Device the domain is being initialised for
326 *
327 * @base and @limit + 1 should be exact multiples of IOMMU page granularity to
328 * avoid rounding surprises. If necessary, we reserve the page at address 0
329 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
330 * any change which could make prior IOVAs invalid will fail.
331 */
332static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
333 dma_addr_t limit, struct device *dev)
334{
335 struct iommu_dma_cookie *cookie = domain->iova_cookie;
336 unsigned long order, base_pfn;
337 struct iova_domain *iovad;
338
339 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
340 return -EINVAL;
341
342 iovad = &cookie->iovad;
343
344 /* Use the smallest supported page size for IOVA granularity */
345 order = __ffs(domain->pgsize_bitmap);
346 base_pfn = max_t(unsigned long, 1, base >> order);
347
348 /* Check the domain allows at least some access to the device... */
349 if (domain->geometry.force_aperture) {
350 if (base > domain->geometry.aperture_end ||
351 limit < domain->geometry.aperture_start) {
352 pr_warn("specified DMA range outside IOMMU capability\n");
353 return -EFAULT;
354 }
355 /* ...then finally give it a kicking to make sure it fits */
356 base_pfn = max_t(unsigned long, base_pfn,
357 domain->geometry.aperture_start >> order);
358 }
359
360 /* start_pfn is always nonzero for an already-initialised domain */
361 if (iovad->start_pfn) {
362 if (1UL << order != iovad->granule ||
363 base_pfn != iovad->start_pfn) {
364 pr_warn("Incompatible range for DMA domain\n");
365 return -EFAULT;
366 }
367
368 return 0;
369 }
370
371 init_iova_domain(iovad, 1UL << order, base_pfn);
372
373 if (!cookie->fq_domain && (!dev || !dev_is_untrusted(dev)) &&
374 domain->ops->flush_iotlb_all && !iommu_get_dma_strict(domain)) {
375 if (init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all,
376 iommu_dma_entry_dtor))
377 pr_warn("iova flush queue initialization failed\n");
378 else
379 cookie->fq_domain = domain;
380 }
381
382 if (!dev)
383 return 0;
384
385 return iova_reserve_iommu_regions(dev, domain);
386}
387
388/**
389 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
390 * page flags.
391 * @dir: Direction of DMA transfer
392 * @coherent: Is the DMA master cache-coherent?
393 * @attrs: DMA attributes for the mapping
394 *
395 * Return: corresponding IOMMU API page protection flags
396 */
397static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
398 unsigned long attrs)
399{
400 int prot = coherent ? IOMMU_CACHE : 0;
401
402 if (attrs & DMA_ATTR_PRIVILEGED)
403 prot |= IOMMU_PRIV;
404
405 switch (dir) {
406 case DMA_BIDIRECTIONAL:
407 return prot | IOMMU_READ | IOMMU_WRITE;
408 case DMA_TO_DEVICE:
409 return prot | IOMMU_READ;
410 case DMA_FROM_DEVICE:
411 return prot | IOMMU_WRITE;
412 default:
413 return 0;
414 }
415}
416
417static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
418 size_t size, u64 dma_limit, struct device *dev)
419{
420 struct iommu_dma_cookie *cookie = domain->iova_cookie;
421 struct iova_domain *iovad = &cookie->iovad;
422 unsigned long shift, iova_len, iova = 0;
423
424 if (cookie->type == IOMMU_DMA_MSI_COOKIE) {
425 cookie->msi_iova += size;
426 return cookie->msi_iova - size;
427 }
428
429 shift = iova_shift(iovad);
430 iova_len = size >> shift;
431 /*
432 * Freeing non-power-of-two-sized allocations back into the IOVA caches
433 * will come back to bite us badly, so we have to waste a bit of space
434 * rounding up anything cacheable to make sure that can't happen. The
435 * order of the unadjusted size will still match upon freeing.
436 */
437 if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1)))
438 iova_len = roundup_pow_of_two(iova_len);
439
440 dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit);
441
442 if (domain->geometry.force_aperture)
443 dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end);
444
445 /* Try to get PCI devices a SAC address */
446 if (dma_limit > DMA_BIT_MASK(32) && !iommu_dma_forcedac && dev_is_pci(dev))
447 iova = alloc_iova_fast(iovad, iova_len,
448 DMA_BIT_MASK(32) >> shift, false);
449
450 if (!iova)
451 iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift,
452 true);
453
454 return (dma_addr_t)iova << shift;
455}
456
457static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie,
458 dma_addr_t iova, size_t size, struct page *freelist)
459{
460 struct iova_domain *iovad = &cookie->iovad;
461
462 /* The MSI case is only ever cleaning up its most recent allocation */
463 if (cookie->type == IOMMU_DMA_MSI_COOKIE)
464 cookie->msi_iova -= size;
465 else if (cookie->fq_domain) /* non-strict mode */
466 queue_iova(iovad, iova_pfn(iovad, iova),
467 size >> iova_shift(iovad),
468 (unsigned long)freelist);
469 else
470 free_iova_fast(iovad, iova_pfn(iovad, iova),
471 size >> iova_shift(iovad));
472}
473
474static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr,
475 size_t size)
476{
477 struct iommu_domain *domain = iommu_get_dma_domain(dev);
478 struct iommu_dma_cookie *cookie = domain->iova_cookie;
479 struct iova_domain *iovad = &cookie->iovad;
480 size_t iova_off = iova_offset(iovad, dma_addr);
481 struct iommu_iotlb_gather iotlb_gather;
482 size_t unmapped;
483
484 dma_addr -= iova_off;
485 size = iova_align(iovad, size + iova_off);
486 iommu_iotlb_gather_init(&iotlb_gather);
487
488 unmapped = iommu_unmap_fast(domain, dma_addr, size, &iotlb_gather);
489 WARN_ON(unmapped != size);
490
491 if (!cookie->fq_domain)
492 iommu_iotlb_sync(domain, &iotlb_gather);
493 iommu_dma_free_iova(cookie, dma_addr, size, iotlb_gather.freelist);
494}
495
496static void __iommu_dma_unmap_swiotlb(struct device *dev, dma_addr_t dma_addr,
497 size_t size, enum dma_data_direction dir,
498 unsigned long attrs)
499{
500 struct iommu_domain *domain = iommu_get_dma_domain(dev);
501 phys_addr_t phys;
502
503 phys = iommu_iova_to_phys(domain, dma_addr);
504 if (WARN_ON(!phys))
505 return;
506
507 __iommu_dma_unmap(dev, dma_addr, size);
508
509 if (unlikely(is_swiotlb_buffer(phys)))
510 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
511}
512
513static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
514 size_t size, int prot, u64 dma_mask)
515{
516 struct iommu_domain *domain = iommu_get_dma_domain(dev);
517 struct iommu_dma_cookie *cookie = domain->iova_cookie;
518 struct iova_domain *iovad = &cookie->iovad;
519 size_t iova_off = iova_offset(iovad, phys);
520 dma_addr_t iova;
521
522 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
523 iommu_deferred_attach(dev, domain))
524 return DMA_MAPPING_ERROR;
525
526 size = iova_align(iovad, size + iova_off);
527
528 iova = iommu_dma_alloc_iova(domain, size, dma_mask, dev);
529 if (!iova)
530 return DMA_MAPPING_ERROR;
531
532 if (iommu_map_atomic(domain, iova, phys - iova_off, size, prot)) {
533 iommu_dma_free_iova(cookie, iova, size, NULL);
534 return DMA_MAPPING_ERROR;
535 }
536 return iova + iova_off;
537}
538
539static dma_addr_t __iommu_dma_map_swiotlb(struct device *dev, phys_addr_t phys,
540 size_t org_size, dma_addr_t dma_mask, bool coherent,
541 enum dma_data_direction dir, unsigned long attrs)
542{
543 int prot = dma_info_to_prot(dir, coherent, attrs);
544 struct iommu_domain *domain = iommu_get_dma_domain(dev);
545 struct iommu_dma_cookie *cookie = domain->iova_cookie;
546 struct iova_domain *iovad = &cookie->iovad;
547 size_t aligned_size = org_size;
548 void *padding_start;
549 size_t padding_size;
550 dma_addr_t iova;
551
552 /*
553 * If both the physical buffer start address and size are
554 * page aligned, we don't need to use a bounce page.
555 */
556 if (IS_ENABLED(CONFIG_SWIOTLB) && dev_is_untrusted(dev) &&
557 iova_offset(iovad, phys | org_size)) {
558 aligned_size = iova_align(iovad, org_size);
559 phys = swiotlb_tbl_map_single(dev, phys, org_size,
560 aligned_size, dir, attrs);
561
562 if (phys == DMA_MAPPING_ERROR)
563 return DMA_MAPPING_ERROR;
564
565 /* Cleanup the padding area. */
566 padding_start = phys_to_virt(phys);
567 padding_size = aligned_size;
568
569 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
570 (dir == DMA_TO_DEVICE ||
571 dir == DMA_BIDIRECTIONAL)) {
572 padding_start += org_size;
573 padding_size -= org_size;
574 }
575
576 memset(padding_start, 0, padding_size);
577 }
578
579 iova = __iommu_dma_map(dev, phys, aligned_size, prot, dma_mask);
580 if (iova == DMA_MAPPING_ERROR && is_swiotlb_buffer(phys))
581 swiotlb_tbl_unmap_single(dev, phys, org_size, dir, attrs);
582 return iova;
583}
584
585static void __iommu_dma_free_pages(struct page **pages, int count)
586{
587 while (count--)
588 __free_page(pages[count]);
589 kvfree(pages);
590}
591
592static struct page **__iommu_dma_alloc_pages(struct device *dev,
593 unsigned int count, unsigned long order_mask, gfp_t gfp)
594{
595 struct page **pages;
596 unsigned int i = 0, nid = dev_to_node(dev);
597
598 order_mask &= (2U << MAX_ORDER) - 1;
599 if (!order_mask)
600 return NULL;
601
602 pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL);
603 if (!pages)
604 return NULL;
605
606 /* IOMMU can map any pages, so himem can also be used here */
607 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
608
609 /* It makes no sense to muck about with huge pages */
610 gfp &= ~__GFP_COMP;
611
612 while (count) {
613 struct page *page = NULL;
614 unsigned int order_size;
615
616 /*
617 * Higher-order allocations are a convenience rather
618 * than a necessity, hence using __GFP_NORETRY until
619 * falling back to minimum-order allocations.
620 */
621 for (order_mask &= (2U << __fls(count)) - 1;
622 order_mask; order_mask &= ~order_size) {
623 unsigned int order = __fls(order_mask);
624 gfp_t alloc_flags = gfp;
625
626 order_size = 1U << order;
627 if (order_mask > order_size)
628 alloc_flags |= __GFP_NORETRY;
629 page = alloc_pages_node(nid, alloc_flags, order);
630 if (!page)
631 continue;
632 if (order)
633 split_page(page, order);
634 break;
635 }
636 if (!page) {
637 __iommu_dma_free_pages(pages, i);
638 return NULL;
639 }
640 count -= order_size;
641 while (order_size--)
642 pages[i++] = page++;
643 }
644 return pages;
645}
646
647/*
648 * If size is less than PAGE_SIZE, then a full CPU page will be allocated,
649 * but an IOMMU which supports smaller pages might not map the whole thing.
650 */
651static struct page **__iommu_dma_alloc_noncontiguous(struct device *dev,
652 size_t size, struct sg_table *sgt, gfp_t gfp, pgprot_t prot,
653 unsigned long attrs)
654{
655 struct iommu_domain *domain = iommu_get_dma_domain(dev);
656 struct iommu_dma_cookie *cookie = domain->iova_cookie;
657 struct iova_domain *iovad = &cookie->iovad;
658 bool coherent = dev_is_dma_coherent(dev);
659 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
660 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
661 struct page **pages;
662 dma_addr_t iova;
663
664 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
665 iommu_deferred_attach(dev, domain))
666 return NULL;
667
668 min_size = alloc_sizes & -alloc_sizes;
669 if (min_size < PAGE_SIZE) {
670 min_size = PAGE_SIZE;
671 alloc_sizes |= PAGE_SIZE;
672 } else {
673 size = ALIGN(size, min_size);
674 }
675 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
676 alloc_sizes = min_size;
677
678 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
679 pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT,
680 gfp);
681 if (!pages)
682 return NULL;
683
684 size = iova_align(iovad, size);
685 iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev);
686 if (!iova)
687 goto out_free_pages;
688
689 if (sg_alloc_table_from_pages(sgt, pages, count, 0, size, GFP_KERNEL))
690 goto out_free_iova;
691
692 if (!(ioprot & IOMMU_CACHE)) {
693 struct scatterlist *sg;
694 int i;
695
696 for_each_sg(sgt->sgl, sg, sgt->orig_nents, i)
697 arch_dma_prep_coherent(sg_page(sg), sg->length);
698 }
699
700 if (iommu_map_sg_atomic(domain, iova, sgt->sgl, sgt->orig_nents, ioprot)
701 < size)
702 goto out_free_sg;
703
704 sgt->sgl->dma_address = iova;
705 sgt->sgl->dma_length = size;
706 return pages;
707
708out_free_sg:
709 sg_free_table(sgt);
710out_free_iova:
711 iommu_dma_free_iova(cookie, iova, size, NULL);
712out_free_pages:
713 __iommu_dma_free_pages(pages, count);
714 return NULL;
715}
716
717static void *iommu_dma_alloc_remap(struct device *dev, size_t size,
718 dma_addr_t *dma_handle, gfp_t gfp, pgprot_t prot,
719 unsigned long attrs)
720{
721 struct page **pages;
722 struct sg_table sgt;
723 void *vaddr;
724
725 pages = __iommu_dma_alloc_noncontiguous(dev, size, &sgt, gfp, prot,
726 attrs);
727 if (!pages)
728 return NULL;
729 *dma_handle = sgt.sgl->dma_address;
730 sg_free_table(&sgt);
731 vaddr = dma_common_pages_remap(pages, size, prot,
732 __builtin_return_address(0));
733 if (!vaddr)
734 goto out_unmap;
735 return vaddr;
736
737out_unmap:
738 __iommu_dma_unmap(dev, *dma_handle, size);
739 __iommu_dma_free_pages(pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
740 return NULL;
741}
742
743#ifdef CONFIG_DMA_REMAP
744static struct sg_table *iommu_dma_alloc_noncontiguous(struct device *dev,
745 size_t size, enum dma_data_direction dir, gfp_t gfp,
746 unsigned long attrs)
747{
748 struct dma_sgt_handle *sh;
749
750 sh = kmalloc(sizeof(*sh), gfp);
751 if (!sh)
752 return NULL;
753
754 sh->pages = __iommu_dma_alloc_noncontiguous(dev, size, &sh->sgt, gfp,
755 PAGE_KERNEL, attrs);
756 if (!sh->pages) {
757 kfree(sh);
758 return NULL;
759 }
760 return &sh->sgt;
761}
762
763static void iommu_dma_free_noncontiguous(struct device *dev, size_t size,
764 struct sg_table *sgt, enum dma_data_direction dir)
765{
766 struct dma_sgt_handle *sh = sgt_handle(sgt);
767
768 __iommu_dma_unmap(dev, sgt->sgl->dma_address, size);
769 __iommu_dma_free_pages(sh->pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
770 sg_free_table(&sh->sgt);
771 kfree(sh);
772}
773#endif /* CONFIG_DMA_REMAP */
774
775static void iommu_dma_sync_single_for_cpu(struct device *dev,
776 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
777{
778 phys_addr_t phys;
779
780 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
781 return;
782
783 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
784 if (!dev_is_dma_coherent(dev))
785 arch_sync_dma_for_cpu(phys, size, dir);
786
787 if (is_swiotlb_buffer(phys))
788 swiotlb_sync_single_for_cpu(dev, phys, size, dir);
789}
790
791static void iommu_dma_sync_single_for_device(struct device *dev,
792 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
793{
794 phys_addr_t phys;
795
796 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
797 return;
798
799 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
800 if (is_swiotlb_buffer(phys))
801 swiotlb_sync_single_for_device(dev, phys, size, dir);
802
803 if (!dev_is_dma_coherent(dev))
804 arch_sync_dma_for_device(phys, size, dir);
805}
806
807static void iommu_dma_sync_sg_for_cpu(struct device *dev,
808 struct scatterlist *sgl, int nelems,
809 enum dma_data_direction dir)
810{
811 struct scatterlist *sg;
812 int i;
813
814 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
815 return;
816
817 for_each_sg(sgl, sg, nelems, i) {
818 if (!dev_is_dma_coherent(dev))
819 arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir);
820
821 if (is_swiotlb_buffer(sg_phys(sg)))
822 swiotlb_sync_single_for_cpu(dev, sg_phys(sg),
823 sg->length, dir);
824 }
825}
826
827static void iommu_dma_sync_sg_for_device(struct device *dev,
828 struct scatterlist *sgl, int nelems,
829 enum dma_data_direction dir)
830{
831 struct scatterlist *sg;
832 int i;
833
834 if (dev_is_dma_coherent(dev) && !dev_is_untrusted(dev))
835 return;
836
837 for_each_sg(sgl, sg, nelems, i) {
838 if (is_swiotlb_buffer(sg_phys(sg)))
839 swiotlb_sync_single_for_device(dev, sg_phys(sg),
840 sg->length, dir);
841
842 if (!dev_is_dma_coherent(dev))
843 arch_sync_dma_for_device(sg_phys(sg), sg->length, dir);
844 }
845}
846
847static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
848 unsigned long offset, size_t size, enum dma_data_direction dir,
849 unsigned long attrs)
850{
851 phys_addr_t phys = page_to_phys(page) + offset;
852 bool coherent = dev_is_dma_coherent(dev);
853 dma_addr_t dma_handle;
854
855 dma_handle = __iommu_dma_map_swiotlb(dev, phys, size, dma_get_mask(dev),
856 coherent, dir, attrs);
857 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
858 dma_handle != DMA_MAPPING_ERROR)
859 arch_sync_dma_for_device(phys, size, dir);
860 return dma_handle;
861}
862
863static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
864 size_t size, enum dma_data_direction dir, unsigned long attrs)
865{
866 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
867 iommu_dma_sync_single_for_cpu(dev, dma_handle, size, dir);
868 __iommu_dma_unmap_swiotlb(dev, dma_handle, size, dir, attrs);
869}
870
871/*
872 * Prepare a successfully-mapped scatterlist to give back to the caller.
873 *
874 * At this point the segments are already laid out by iommu_dma_map_sg() to
875 * avoid individually crossing any boundaries, so we merely need to check a
876 * segment's start address to avoid concatenating across one.
877 */
878static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
879 dma_addr_t dma_addr)
880{
881 struct scatterlist *s, *cur = sg;
882 unsigned long seg_mask = dma_get_seg_boundary(dev);
883 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
884 int i, count = 0;
885
886 for_each_sg(sg, s, nents, i) {
887 /* Restore this segment's original unaligned fields first */
888 unsigned int s_iova_off = sg_dma_address(s);
889 unsigned int s_length = sg_dma_len(s);
890 unsigned int s_iova_len = s->length;
891
892 s->offset += s_iova_off;
893 s->length = s_length;
894 sg_dma_address(s) = DMA_MAPPING_ERROR;
895 sg_dma_len(s) = 0;
896
897 /*
898 * Now fill in the real DMA data. If...
899 * - there is a valid output segment to append to
900 * - and this segment starts on an IOVA page boundary
901 * - but doesn't fall at a segment boundary
902 * - and wouldn't make the resulting output segment too long
903 */
904 if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
905 (max_len - cur_len >= s_length)) {
906 /* ...then concatenate it with the previous one */
907 cur_len += s_length;
908 } else {
909 /* Otherwise start the next output segment */
910 if (i > 0)
911 cur = sg_next(cur);
912 cur_len = s_length;
913 count++;
914
915 sg_dma_address(cur) = dma_addr + s_iova_off;
916 }
917
918 sg_dma_len(cur) = cur_len;
919 dma_addr += s_iova_len;
920
921 if (s_length + s_iova_off < s_iova_len)
922 cur_len = 0;
923 }
924 return count;
925}
926
927/*
928 * If mapping failed, then just restore the original list,
929 * but making sure the DMA fields are invalidated.
930 */
931static void __invalidate_sg(struct scatterlist *sg, int nents)
932{
933 struct scatterlist *s;
934 int i;
935
936 for_each_sg(sg, s, nents, i) {
937 if (sg_dma_address(s) != DMA_MAPPING_ERROR)
938 s->offset += sg_dma_address(s);
939 if (sg_dma_len(s))
940 s->length = sg_dma_len(s);
941 sg_dma_address(s) = DMA_MAPPING_ERROR;
942 sg_dma_len(s) = 0;
943 }
944}
945
946static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *sg,
947 int nents, enum dma_data_direction dir, unsigned long attrs)
948{
949 struct scatterlist *s;
950 int i;
951
952 for_each_sg(sg, s, nents, i)
953 __iommu_dma_unmap_swiotlb(dev, sg_dma_address(s),
954 sg_dma_len(s), dir, attrs);
955}
956
957static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg,
958 int nents, enum dma_data_direction dir, unsigned long attrs)
959{
960 struct scatterlist *s;
961 int i;
962
963 for_each_sg(sg, s, nents, i) {
964 sg_dma_address(s) = __iommu_dma_map_swiotlb(dev, sg_phys(s),
965 s->length, dma_get_mask(dev),
966 dev_is_dma_coherent(dev), dir, attrs);
967 if (sg_dma_address(s) == DMA_MAPPING_ERROR)
968 goto out_unmap;
969 sg_dma_len(s) = s->length;
970 }
971
972 return nents;
973
974out_unmap:
975 iommu_dma_unmap_sg_swiotlb(dev, sg, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
976 return 0;
977}
978
979/*
980 * The DMA API client is passing in a scatterlist which could describe
981 * any old buffer layout, but the IOMMU API requires everything to be
982 * aligned to IOMMU pages. Hence the need for this complicated bit of
983 * impedance-matching, to be able to hand off a suitably-aligned list,
984 * but still preserve the original offsets and sizes for the caller.
985 */
986static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg,
987 int nents, enum dma_data_direction dir, unsigned long attrs)
988{
989 struct iommu_domain *domain = iommu_get_dma_domain(dev);
990 struct iommu_dma_cookie *cookie = domain->iova_cookie;
991 struct iova_domain *iovad = &cookie->iovad;
992 struct scatterlist *s, *prev = NULL;
993 int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs);
994 dma_addr_t iova;
995 size_t iova_len = 0;
996 unsigned long mask = dma_get_seg_boundary(dev);
997 int i;
998
999 if (static_branch_unlikely(&iommu_deferred_attach_enabled) &&
1000 iommu_deferred_attach(dev, domain))
1001 return 0;
1002
1003 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1004 iommu_dma_sync_sg_for_device(dev, sg, nents, dir);
1005
1006 if (dev_is_untrusted(dev))
1007 return iommu_dma_map_sg_swiotlb(dev, sg, nents, dir, attrs);
1008
1009 /*
1010 * Work out how much IOVA space we need, and align the segments to
1011 * IOVA granules for the IOMMU driver to handle. With some clever
1012 * trickery we can modify the list in-place, but reversibly, by
1013 * stashing the unaligned parts in the as-yet-unused DMA fields.
1014 */
1015 for_each_sg(sg, s, nents, i) {
1016 size_t s_iova_off = iova_offset(iovad, s->offset);
1017 size_t s_length = s->length;
1018 size_t pad_len = (mask - iova_len + 1) & mask;
1019
1020 sg_dma_address(s) = s_iova_off;
1021 sg_dma_len(s) = s_length;
1022 s->offset -= s_iova_off;
1023 s_length = iova_align(iovad, s_length + s_iova_off);
1024 s->length = s_length;
1025
1026 /*
1027 * Due to the alignment of our single IOVA allocation, we can
1028 * depend on these assumptions about the segment boundary mask:
1029 * - If mask size >= IOVA size, then the IOVA range cannot
1030 * possibly fall across a boundary, so we don't care.
1031 * - If mask size < IOVA size, then the IOVA range must start
1032 * exactly on a boundary, therefore we can lay things out
1033 * based purely on segment lengths without needing to know
1034 * the actual addresses beforehand.
1035 * - The mask must be a power of 2, so pad_len == 0 if
1036 * iova_len == 0, thus we cannot dereference prev the first
1037 * time through here (i.e. before it has a meaningful value).
1038 */
1039 if (pad_len && pad_len < s_length - 1) {
1040 prev->length += pad_len;
1041 iova_len += pad_len;
1042 }
1043
1044 iova_len += s_length;
1045 prev = s;
1046 }
1047
1048 iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev);
1049 if (!iova)
1050 goto out_restore_sg;
1051
1052 /*
1053 * We'll leave any physical concatenation to the IOMMU driver's
1054 * implementation - it knows better than we do.
1055 */
1056 if (iommu_map_sg_atomic(domain, iova, sg, nents, prot) < iova_len)
1057 goto out_free_iova;
1058
1059 return __finalise_sg(dev, sg, nents, iova);
1060
1061out_free_iova:
1062 iommu_dma_free_iova(cookie, iova, iova_len, NULL);
1063out_restore_sg:
1064 __invalidate_sg(sg, nents);
1065 return 0;
1066}
1067
1068static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
1069 int nents, enum dma_data_direction dir, unsigned long attrs)
1070{
1071 dma_addr_t start, end;
1072 struct scatterlist *tmp;
1073 int i;
1074
1075 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1076 iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir);
1077
1078 if (dev_is_untrusted(dev)) {
1079 iommu_dma_unmap_sg_swiotlb(dev, sg, nents, dir, attrs);
1080 return;
1081 }
1082
1083 /*
1084 * The scatterlist segments are mapped into a single
1085 * contiguous IOVA allocation, so this is incredibly easy.
1086 */
1087 start = sg_dma_address(sg);
1088 for_each_sg(sg_next(sg), tmp, nents - 1, i) {
1089 if (sg_dma_len(tmp) == 0)
1090 break;
1091 sg = tmp;
1092 }
1093 end = sg_dma_address(sg) + sg_dma_len(sg);
1094 __iommu_dma_unmap(dev, start, end - start);
1095}
1096
1097static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
1098 size_t size, enum dma_data_direction dir, unsigned long attrs)
1099{
1100 return __iommu_dma_map(dev, phys, size,
1101 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
1102 dma_get_mask(dev));
1103}
1104
1105static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
1106 size_t size, enum dma_data_direction dir, unsigned long attrs)
1107{
1108 __iommu_dma_unmap(dev, handle, size);
1109}
1110
1111static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
1112{
1113 size_t alloc_size = PAGE_ALIGN(size);
1114 int count = alloc_size >> PAGE_SHIFT;
1115 struct page *page = NULL, **pages = NULL;
1116
1117 /* Non-coherent atomic allocation? Easy */
1118 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1119 dma_free_from_pool(dev, cpu_addr, alloc_size))
1120 return;
1121
1122 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1123 /*
1124 * If it the address is remapped, then it's either non-coherent
1125 * or highmem CMA, or an iommu_dma_alloc_remap() construction.
1126 */
1127 pages = dma_common_find_pages(cpu_addr);
1128 if (!pages)
1129 page = vmalloc_to_page(cpu_addr);
1130 dma_common_free_remap(cpu_addr, alloc_size);
1131 } else {
1132 /* Lowmem means a coherent atomic or CMA allocation */
1133 page = virt_to_page(cpu_addr);
1134 }
1135
1136 if (pages)
1137 __iommu_dma_free_pages(pages, count);
1138 if (page)
1139 dma_free_contiguous(dev, page, alloc_size);
1140}
1141
1142static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
1143 dma_addr_t handle, unsigned long attrs)
1144{
1145 __iommu_dma_unmap(dev, handle, size);
1146 __iommu_dma_free(dev, size, cpu_addr);
1147}
1148
1149static void *iommu_dma_alloc_pages(struct device *dev, size_t size,
1150 struct page **pagep, gfp_t gfp, unsigned long attrs)
1151{
1152 bool coherent = dev_is_dma_coherent(dev);
1153 size_t alloc_size = PAGE_ALIGN(size);
1154 int node = dev_to_node(dev);
1155 struct page *page = NULL;
1156 void *cpu_addr;
1157
1158 page = dma_alloc_contiguous(dev, alloc_size, gfp);
1159 if (!page)
1160 page = alloc_pages_node(node, gfp, get_order(alloc_size));
1161 if (!page)
1162 return NULL;
1163
1164 if (IS_ENABLED(CONFIG_DMA_REMAP) && (!coherent || PageHighMem(page))) {
1165 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
1166
1167 cpu_addr = dma_common_contiguous_remap(page, alloc_size,
1168 prot, __builtin_return_address(0));
1169 if (!cpu_addr)
1170 goto out_free_pages;
1171
1172 if (!coherent)
1173 arch_dma_prep_coherent(page, size);
1174 } else {
1175 cpu_addr = page_address(page);
1176 }
1177
1178 *pagep = page;
1179 memset(cpu_addr, 0, alloc_size);
1180 return cpu_addr;
1181out_free_pages:
1182 dma_free_contiguous(dev, page, alloc_size);
1183 return NULL;
1184}
1185
1186static void *iommu_dma_alloc(struct device *dev, size_t size,
1187 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1188{
1189 bool coherent = dev_is_dma_coherent(dev);
1190 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
1191 struct page *page = NULL;
1192 void *cpu_addr;
1193
1194 gfp |= __GFP_ZERO;
1195
1196 if (IS_ENABLED(CONFIG_DMA_REMAP) && gfpflags_allow_blocking(gfp) &&
1197 !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) {
1198 return iommu_dma_alloc_remap(dev, size, handle, gfp,
1199 dma_pgprot(dev, PAGE_KERNEL, attrs), attrs);
1200 }
1201
1202 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1203 !gfpflags_allow_blocking(gfp) && !coherent)
1204 page = dma_alloc_from_pool(dev, PAGE_ALIGN(size), &cpu_addr,
1205 gfp, NULL);
1206 else
1207 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);
1208 if (!cpu_addr)
1209 return NULL;
1210
1211 *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot,
1212 dev->coherent_dma_mask);
1213 if (*handle == DMA_MAPPING_ERROR) {
1214 __iommu_dma_free(dev, size, cpu_addr);
1215 return NULL;
1216 }
1217
1218 return cpu_addr;
1219}
1220
1221static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
1222 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1223 unsigned long attrs)
1224{
1225 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1226 unsigned long pfn, off = vma->vm_pgoff;
1227 int ret;
1228
1229 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
1230
1231 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
1232 return ret;
1233
1234 if (off >= nr_pages || vma_pages(vma) > nr_pages - off)
1235 return -ENXIO;
1236
1237 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1238 struct page **pages = dma_common_find_pages(cpu_addr);
1239
1240 if (pages)
1241 return vm_map_pages(vma, pages, nr_pages);
1242 pfn = vmalloc_to_pfn(cpu_addr);
1243 } else {
1244 pfn = page_to_pfn(virt_to_page(cpu_addr));
1245 }
1246
1247 return remap_pfn_range(vma, vma->vm_start, pfn + off,
1248 vma->vm_end - vma->vm_start,
1249 vma->vm_page_prot);
1250}
1251
1252static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
1253 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1254 unsigned long attrs)
1255{
1256 struct page *page;
1257 int ret;
1258
1259 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1260 struct page **pages = dma_common_find_pages(cpu_addr);
1261
1262 if (pages) {
1263 return sg_alloc_table_from_pages(sgt, pages,
1264 PAGE_ALIGN(size) >> PAGE_SHIFT,
1265 0, size, GFP_KERNEL);
1266 }
1267
1268 page = vmalloc_to_page(cpu_addr);
1269 } else {
1270 page = virt_to_page(cpu_addr);
1271 }
1272
1273 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
1274 if (!ret)
1275 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
1276 return ret;
1277}
1278
1279static unsigned long iommu_dma_get_merge_boundary(struct device *dev)
1280{
1281 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1282
1283 return (1UL << __ffs(domain->pgsize_bitmap)) - 1;
1284}
1285
1286static const struct dma_map_ops iommu_dma_ops = {
1287 .alloc = iommu_dma_alloc,
1288 .free = iommu_dma_free,
1289 .alloc_pages = dma_common_alloc_pages,
1290 .free_pages = dma_common_free_pages,
1291#ifdef CONFIG_DMA_REMAP
1292 .alloc_noncontiguous = iommu_dma_alloc_noncontiguous,
1293 .free_noncontiguous = iommu_dma_free_noncontiguous,
1294#endif
1295 .mmap = iommu_dma_mmap,
1296 .get_sgtable = iommu_dma_get_sgtable,
1297 .map_page = iommu_dma_map_page,
1298 .unmap_page = iommu_dma_unmap_page,
1299 .map_sg = iommu_dma_map_sg,
1300 .unmap_sg = iommu_dma_unmap_sg,
1301 .sync_single_for_cpu = iommu_dma_sync_single_for_cpu,
1302 .sync_single_for_device = iommu_dma_sync_single_for_device,
1303 .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu,
1304 .sync_sg_for_device = iommu_dma_sync_sg_for_device,
1305 .map_resource = iommu_dma_map_resource,
1306 .unmap_resource = iommu_dma_unmap_resource,
1307 .get_merge_boundary = iommu_dma_get_merge_boundary,
1308};
1309
1310/*
1311 * The IOMMU core code allocates the default DMA domain, which the underlying
1312 * IOMMU driver needs to support via the dma-iommu layer.
1313 */
1314void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit)
1315{
1316 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1317
1318 if (!domain)
1319 goto out_err;
1320
1321 /*
1322 * The IOMMU core code allocates the default DMA domain, which the
1323 * underlying IOMMU driver needs to support via the dma-iommu layer.
1324 */
1325 if (domain->type == IOMMU_DOMAIN_DMA) {
1326 if (iommu_dma_init_domain(domain, dma_base, dma_limit, dev))
1327 goto out_err;
1328 dev->dma_ops = &iommu_dma_ops;
1329 }
1330
1331 return;
1332out_err:
1333 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
1334 dev_name(dev));
1335}
1336EXPORT_SYMBOL_GPL(iommu_setup_dma_ops);
1337
1338static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
1339 phys_addr_t msi_addr, struct iommu_domain *domain)
1340{
1341 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1342 struct iommu_dma_msi_page *msi_page;
1343 dma_addr_t iova;
1344 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1345 size_t size = cookie_msi_granule(cookie);
1346
1347 msi_addr &= ~(phys_addr_t)(size - 1);
1348 list_for_each_entry(msi_page, &cookie->msi_page_list, list)
1349 if (msi_page->phys == msi_addr)
1350 return msi_page;
1351
1352 msi_page = kzalloc(sizeof(*msi_page), GFP_KERNEL);
1353 if (!msi_page)
1354 return NULL;
1355
1356 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
1357 if (!iova)
1358 goto out_free_page;
1359
1360 if (iommu_map(domain, iova, msi_addr, size, prot))
1361 goto out_free_iova;
1362
1363 INIT_LIST_HEAD(&msi_page->list);
1364 msi_page->phys = msi_addr;
1365 msi_page->iova = iova;
1366 list_add(&msi_page->list, &cookie->msi_page_list);
1367 return msi_page;
1368
1369out_free_iova:
1370 iommu_dma_free_iova(cookie, iova, size, NULL);
1371out_free_page:
1372 kfree(msi_page);
1373 return NULL;
1374}
1375
1376int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
1377{
1378 struct device *dev = msi_desc_to_dev(desc);
1379 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1380 struct iommu_dma_msi_page *msi_page;
1381 static DEFINE_MUTEX(msi_prepare_lock); /* see below */
1382
1383 if (!domain || !domain->iova_cookie) {
1384 desc->iommu_cookie = NULL;
1385 return 0;
1386 }
1387
1388 /*
1389 * In fact the whole prepare operation should already be serialised by
1390 * irq_domain_mutex further up the callchain, but that's pretty subtle
1391 * on its own, so consider this locking as failsafe documentation...
1392 */
1393 mutex_lock(&msi_prepare_lock);
1394 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
1395 mutex_unlock(&msi_prepare_lock);
1396
1397 msi_desc_set_iommu_cookie(desc, msi_page);
1398
1399 if (!msi_page)
1400 return -ENOMEM;
1401 return 0;
1402}
1403
1404void iommu_dma_compose_msi_msg(struct msi_desc *desc,
1405 struct msi_msg *msg)
1406{
1407 struct device *dev = msi_desc_to_dev(desc);
1408 const struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1409 const struct iommu_dma_msi_page *msi_page;
1410
1411 msi_page = msi_desc_get_iommu_cookie(desc);
1412
1413 if (!domain || !domain->iova_cookie || WARN_ON(!msi_page))
1414 return;
1415
1416 msg->address_hi = upper_32_bits(msi_page->iova);
1417 msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1;
1418 msg->address_lo += lower_32_bits(msi_page->iova);
1419}
1420
1421static int iommu_dma_init(void)
1422{
1423 if (is_kdump_kernel())
1424 static_branch_enable(&iommu_deferred_attach_enabled);
1425
1426 return iova_cache_get();
1427}
1428arch_initcall(iommu_dma_init);