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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/debugfs.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/regulator/consumer.h>
15#include <linux/reset.h>
16
17#include <soc/tegra/pmc.h>
18
19#include <drm/display/drm_dp_helper.h>
20#include <drm/display/drm_scdc_helper.h>
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_debugfs.h>
23#include <drm/drm_edid.h>
24#include <drm/drm_eld.h>
25#include <drm/drm_file.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_simple_kms_helper.h>
28
29#include "dc.h"
30#include "dp.h"
31#include "drm.h"
32#include "hda.h"
33#include "sor.h"
34#include "trace.h"
35
36#define SOR_REKEY 0x38
37
38struct tegra_sor_hdmi_settings {
39 unsigned long frequency;
40
41 u8 vcocap;
42 u8 filter;
43 u8 ichpmp;
44 u8 loadadj;
45 u8 tmds_termadj;
46 u8 tx_pu_value;
47 u8 bg_temp_coef;
48 u8 bg_vref_level;
49 u8 avdd10_level;
50 u8 avdd14_level;
51 u8 sparepll;
52
53 u8 drive_current[4];
54 u8 preemphasis[4];
55};
56
57#if 1
58static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
59 {
60 .frequency = 54000000,
61 .vcocap = 0x0,
62 .filter = 0x0,
63 .ichpmp = 0x1,
64 .loadadj = 0x3,
65 .tmds_termadj = 0x9,
66 .tx_pu_value = 0x10,
67 .bg_temp_coef = 0x3,
68 .bg_vref_level = 0x8,
69 .avdd10_level = 0x4,
70 .avdd14_level = 0x4,
71 .sparepll = 0x0,
72 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
73 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
74 }, {
75 .frequency = 75000000,
76 .vcocap = 0x3,
77 .filter = 0x0,
78 .ichpmp = 0x1,
79 .loadadj = 0x3,
80 .tmds_termadj = 0x9,
81 .tx_pu_value = 0x40,
82 .bg_temp_coef = 0x3,
83 .bg_vref_level = 0x8,
84 .avdd10_level = 0x4,
85 .avdd14_level = 0x4,
86 .sparepll = 0x0,
87 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
88 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
89 }, {
90 .frequency = 150000000,
91 .vcocap = 0x3,
92 .filter = 0x0,
93 .ichpmp = 0x1,
94 .loadadj = 0x3,
95 .tmds_termadj = 0x9,
96 .tx_pu_value = 0x66,
97 .bg_temp_coef = 0x3,
98 .bg_vref_level = 0x8,
99 .avdd10_level = 0x4,
100 .avdd14_level = 0x4,
101 .sparepll = 0x0,
102 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
103 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
104 }, {
105 .frequency = 300000000,
106 .vcocap = 0x3,
107 .filter = 0x0,
108 .ichpmp = 0x1,
109 .loadadj = 0x3,
110 .tmds_termadj = 0x9,
111 .tx_pu_value = 0x66,
112 .bg_temp_coef = 0x3,
113 .bg_vref_level = 0xa,
114 .avdd10_level = 0x4,
115 .avdd14_level = 0x4,
116 .sparepll = 0x0,
117 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
118 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
119 }, {
120 .frequency = 600000000,
121 .vcocap = 0x3,
122 .filter = 0x0,
123 .ichpmp = 0x1,
124 .loadadj = 0x3,
125 .tmds_termadj = 0x9,
126 .tx_pu_value = 0x66,
127 .bg_temp_coef = 0x3,
128 .bg_vref_level = 0x8,
129 .avdd10_level = 0x4,
130 .avdd14_level = 0x4,
131 .sparepll = 0x0,
132 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
133 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
134 },
135};
136#else
137static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
138 {
139 .frequency = 75000000,
140 .vcocap = 0x3,
141 .filter = 0x0,
142 .ichpmp = 0x1,
143 .loadadj = 0x3,
144 .tmds_termadj = 0x9,
145 .tx_pu_value = 0x40,
146 .bg_temp_coef = 0x3,
147 .bg_vref_level = 0x8,
148 .avdd10_level = 0x4,
149 .avdd14_level = 0x4,
150 .sparepll = 0x0,
151 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
152 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
153 }, {
154 .frequency = 150000000,
155 .vcocap = 0x3,
156 .filter = 0x0,
157 .ichpmp = 0x1,
158 .loadadj = 0x3,
159 .tmds_termadj = 0x9,
160 .tx_pu_value = 0x66,
161 .bg_temp_coef = 0x3,
162 .bg_vref_level = 0x8,
163 .avdd10_level = 0x4,
164 .avdd14_level = 0x4,
165 .sparepll = 0x0,
166 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
167 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
168 }, {
169 .frequency = 300000000,
170 .vcocap = 0x3,
171 .filter = 0x0,
172 .ichpmp = 0x6,
173 .loadadj = 0x3,
174 .tmds_termadj = 0x9,
175 .tx_pu_value = 0x66,
176 .bg_temp_coef = 0x3,
177 .bg_vref_level = 0xf,
178 .avdd10_level = 0x4,
179 .avdd14_level = 0x4,
180 .sparepll = 0x0,
181 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
182 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
183 }, {
184 .frequency = 600000000,
185 .vcocap = 0x3,
186 .filter = 0x0,
187 .ichpmp = 0xa,
188 .loadadj = 0x3,
189 .tmds_termadj = 0xb,
190 .tx_pu_value = 0x66,
191 .bg_temp_coef = 0x3,
192 .bg_vref_level = 0xe,
193 .avdd10_level = 0x4,
194 .avdd14_level = 0x4,
195 .sparepll = 0x0,
196 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
197 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
198 },
199};
200#endif
201
202static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
203 {
204 .frequency = 54000000,
205 .vcocap = 0,
206 .filter = 5,
207 .ichpmp = 5,
208 .loadadj = 3,
209 .tmds_termadj = 0xf,
210 .tx_pu_value = 0,
211 .bg_temp_coef = 3,
212 .bg_vref_level = 8,
213 .avdd10_level = 4,
214 .avdd14_level = 4,
215 .sparepll = 0x54,
216 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
217 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
218 }, {
219 .frequency = 75000000,
220 .vcocap = 1,
221 .filter = 5,
222 .ichpmp = 5,
223 .loadadj = 3,
224 .tmds_termadj = 0xf,
225 .tx_pu_value = 0,
226 .bg_temp_coef = 3,
227 .bg_vref_level = 8,
228 .avdd10_level = 4,
229 .avdd14_level = 4,
230 .sparepll = 0x44,
231 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
232 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
233 }, {
234 .frequency = 150000000,
235 .vcocap = 3,
236 .filter = 5,
237 .ichpmp = 5,
238 .loadadj = 3,
239 .tmds_termadj = 15,
240 .tx_pu_value = 0x66 /* 0 */,
241 .bg_temp_coef = 3,
242 .bg_vref_level = 8,
243 .avdd10_level = 4,
244 .avdd14_level = 4,
245 .sparepll = 0x00, /* 0x34 */
246 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
247 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
248 }, {
249 .frequency = 300000000,
250 .vcocap = 3,
251 .filter = 5,
252 .ichpmp = 5,
253 .loadadj = 3,
254 .tmds_termadj = 15,
255 .tx_pu_value = 64,
256 .bg_temp_coef = 3,
257 .bg_vref_level = 8,
258 .avdd10_level = 4,
259 .avdd14_level = 4,
260 .sparepll = 0x34,
261 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
262 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
263 }, {
264 .frequency = 600000000,
265 .vcocap = 3,
266 .filter = 5,
267 .ichpmp = 5,
268 .loadadj = 3,
269 .tmds_termadj = 12,
270 .tx_pu_value = 96,
271 .bg_temp_coef = 3,
272 .bg_vref_level = 8,
273 .avdd10_level = 4,
274 .avdd14_level = 4,
275 .sparepll = 0x34,
276 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
277 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
278 }
279};
280
281static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
282 {
283 .frequency = 54000000,
284 .vcocap = 0,
285 .filter = 5,
286 .ichpmp = 5,
287 .loadadj = 3,
288 .tmds_termadj = 0xf,
289 .tx_pu_value = 0,
290 .bg_temp_coef = 3,
291 .bg_vref_level = 8,
292 .avdd10_level = 4,
293 .avdd14_level = 4,
294 .sparepll = 0x54,
295 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
296 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
297 }, {
298 .frequency = 75000000,
299 .vcocap = 1,
300 .filter = 5,
301 .ichpmp = 5,
302 .loadadj = 3,
303 .tmds_termadj = 0xf,
304 .tx_pu_value = 0,
305 .bg_temp_coef = 3,
306 .bg_vref_level = 8,
307 .avdd10_level = 4,
308 .avdd14_level = 4,
309 .sparepll = 0x44,
310 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
311 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
312 }, {
313 .frequency = 150000000,
314 .vcocap = 3,
315 .filter = 5,
316 .ichpmp = 5,
317 .loadadj = 3,
318 .tmds_termadj = 15,
319 .tx_pu_value = 0x66 /* 0 */,
320 .bg_temp_coef = 3,
321 .bg_vref_level = 8,
322 .avdd10_level = 4,
323 .avdd14_level = 4,
324 .sparepll = 0x00, /* 0x34 */
325 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
326 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
327 }, {
328 .frequency = 300000000,
329 .vcocap = 3,
330 .filter = 5,
331 .ichpmp = 5,
332 .loadadj = 3,
333 .tmds_termadj = 15,
334 .tx_pu_value = 64,
335 .bg_temp_coef = 3,
336 .bg_vref_level = 8,
337 .avdd10_level = 4,
338 .avdd14_level = 4,
339 .sparepll = 0x34,
340 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
341 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
342 }, {
343 .frequency = 600000000,
344 .vcocap = 3,
345 .filter = 5,
346 .ichpmp = 5,
347 .loadadj = 3,
348 .tmds_termadj = 12,
349 .tx_pu_value = 96,
350 .bg_temp_coef = 3,
351 .bg_vref_level = 8,
352 .avdd10_level = 4,
353 .avdd14_level = 4,
354 .sparepll = 0x34,
355 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
356 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
357 }
358};
359
360struct tegra_sor_regs {
361 unsigned int head_state0;
362 unsigned int head_state1;
363 unsigned int head_state2;
364 unsigned int head_state3;
365 unsigned int head_state4;
366 unsigned int head_state5;
367 unsigned int pll0;
368 unsigned int pll1;
369 unsigned int pll2;
370 unsigned int pll3;
371 unsigned int dp_padctl0;
372 unsigned int dp_padctl2;
373};
374
375struct tegra_sor_soc {
376 bool supports_lvds;
377 bool supports_hdmi;
378 bool supports_dp;
379 bool supports_audio;
380 bool supports_hdcp;
381
382 const struct tegra_sor_regs *regs;
383 bool has_nvdisplay;
384
385 const struct tegra_sor_hdmi_settings *settings;
386 unsigned int num_settings;
387
388 const u8 *xbar_cfg;
389 const u8 *lane_map;
390
391 const u8 (*voltage_swing)[4][4];
392 const u8 (*pre_emphasis)[4][4];
393 const u8 (*post_cursor)[4][4];
394 const u8 (*tx_pu)[4][4];
395};
396
397struct tegra_sor;
398
399struct tegra_sor_ops {
400 const char *name;
401 int (*probe)(struct tegra_sor *sor);
402 void (*audio_enable)(struct tegra_sor *sor);
403 void (*audio_disable)(struct tegra_sor *sor);
404};
405
406struct tegra_sor {
407 struct host1x_client client;
408 struct tegra_output output;
409 struct device *dev;
410
411 const struct tegra_sor_soc *soc;
412 void __iomem *regs;
413 unsigned int index;
414 unsigned int irq;
415
416 struct reset_control *rst;
417 struct clk *clk_parent;
418 struct clk *clk_safe;
419 struct clk *clk_out;
420 struct clk *clk_pad;
421 struct clk *clk_dp;
422 struct clk *clk;
423
424 u8 xbar_cfg[5];
425
426 struct drm_dp_link link;
427 struct drm_dp_aux *aux;
428
429 struct drm_info_list *debugfs_files;
430
431 const struct tegra_sor_ops *ops;
432 enum tegra_io_pad pad;
433
434 /* for HDMI 2.0 */
435 struct tegra_sor_hdmi_settings *settings;
436 unsigned int num_settings;
437
438 struct regulator *avdd_io_supply;
439 struct regulator *vdd_pll_supply;
440 struct regulator *hdmi_supply;
441
442 struct delayed_work scdc;
443 bool scdc_enabled;
444
445 struct tegra_hda_format format;
446};
447
448struct tegra_sor_state {
449 struct drm_connector_state base;
450
451 unsigned int link_speed;
452 unsigned long pclk;
453 unsigned int bpc;
454};
455
456static inline struct tegra_sor_state *
457to_sor_state(struct drm_connector_state *state)
458{
459 return container_of(state, struct tegra_sor_state, base);
460}
461
462struct tegra_sor_config {
463 u32 bits_per_pixel;
464
465 u32 active_polarity;
466 u32 active_count;
467 u32 tu_size;
468 u32 active_frac;
469 u32 watermark;
470
471 u32 hblank_symbols;
472 u32 vblank_symbols;
473};
474
475static inline struct tegra_sor *
476host1x_client_to_sor(struct host1x_client *client)
477{
478 return container_of(client, struct tegra_sor, client);
479}
480
481static inline struct tegra_sor *to_sor(struct tegra_output *output)
482{
483 return container_of(output, struct tegra_sor, output);
484}
485
486static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
487{
488 u32 value = readl(sor->regs + (offset << 2));
489
490 trace_sor_readl(sor->dev, offset, value);
491
492 return value;
493}
494
495static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
496 unsigned int offset)
497{
498 trace_sor_writel(sor->dev, offset, value);
499 writel(value, sor->regs + (offset << 2));
500}
501
502static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
503{
504 int err;
505
506 clk_disable_unprepare(sor->clk);
507
508 err = clk_set_parent(sor->clk_out, parent);
509 if (err < 0)
510 return err;
511
512 err = clk_prepare_enable(sor->clk);
513 if (err < 0)
514 return err;
515
516 return 0;
517}
518
519struct tegra_clk_sor_pad {
520 struct clk_hw hw;
521 struct tegra_sor *sor;
522};
523
524static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
525{
526 return container_of(hw, struct tegra_clk_sor_pad, hw);
527}
528
529static const char * const tegra_clk_sor_pad_parents[2][2] = {
530 { "pll_d_out0", "pll_dp" },
531 { "pll_d2_out0", "pll_dp" },
532};
533
534/*
535 * Implementing ->set_parent() here isn't really required because the parent
536 * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
537 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
538 * Tegra186 and later SoC generations where the BPMP implements this clock
539 * and doesn't expose the mux via the common clock framework.
540 */
541
542static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
543{
544 struct tegra_clk_sor_pad *pad = to_pad(hw);
545 struct tegra_sor *sor = pad->sor;
546 u32 value;
547
548 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
549 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
550
551 switch (index) {
552 case 0:
553 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
554 break;
555
556 case 1:
557 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
558 break;
559 }
560
561 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
562
563 return 0;
564}
565
566static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
567{
568 struct tegra_clk_sor_pad *pad = to_pad(hw);
569 struct tegra_sor *sor = pad->sor;
570 u8 parent = U8_MAX;
571 u32 value;
572
573 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
574
575 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
576 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
577 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
578 parent = 0;
579 break;
580
581 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
582 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
583 parent = 1;
584 break;
585 }
586
587 return parent;
588}
589
590static const struct clk_ops tegra_clk_sor_pad_ops = {
591 .determine_rate = clk_hw_determine_rate_no_reparent,
592 .set_parent = tegra_clk_sor_pad_set_parent,
593 .get_parent = tegra_clk_sor_pad_get_parent,
594};
595
596static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
597 const char *name)
598{
599 struct tegra_clk_sor_pad *pad;
600 struct clk_init_data init;
601 struct clk *clk;
602
603 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
604 if (!pad)
605 return ERR_PTR(-ENOMEM);
606
607 pad->sor = sor;
608
609 init.name = name;
610 init.flags = 0;
611 init.parent_names = tegra_clk_sor_pad_parents[sor->index];
612 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
613 init.ops = &tegra_clk_sor_pad_ops;
614
615 pad->hw.init = &init;
616
617 clk = devm_clk_register(sor->dev, &pad->hw);
618
619 return clk;
620}
621
622static void tegra_sor_filter_rates(struct tegra_sor *sor)
623{
624 struct drm_dp_link *link = &sor->link;
625 unsigned int i;
626
627 /* Tegra only supports RBR, HBR and HBR2 */
628 for (i = 0; i < link->num_rates; i++) {
629 switch (link->rates[i]) {
630 case 1620000:
631 case 2700000:
632 case 5400000:
633 break;
634
635 default:
636 DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
637 link->rates[i]);
638 link->rates[i] = 0;
639 break;
640 }
641 }
642
643 drm_dp_link_update_rates(link);
644}
645
646static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
647{
648 unsigned long timeout;
649 u32 value;
650
651 /*
652 * Clear or set the PD_TXD bit corresponding to each lane, depending
653 * on whether it is used or not.
654 */
655 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
656
657 if (lanes <= 2)
658 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
660 else
661 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
662 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
663
664 if (lanes <= 1)
665 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
666 else
667 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
668
669 if (lanes == 0)
670 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
671 else
672 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
673
674 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
675
676 /* start lane sequencer */
677 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
678 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
679 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
680
681 timeout = jiffies + msecs_to_jiffies(250);
682
683 while (time_before(jiffies, timeout)) {
684 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
685 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
686 break;
687
688 usleep_range(250, 1000);
689 }
690
691 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
692 return -ETIMEDOUT;
693
694 return 0;
695}
696
697static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
698{
699 unsigned long timeout;
700 u32 value;
701
702 /* power down all lanes */
703 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
704 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
705 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
706 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
707
708 /* start lane sequencer */
709 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
710 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
711 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
712
713 timeout = jiffies + msecs_to_jiffies(250);
714
715 while (time_before(jiffies, timeout)) {
716 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
717 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
718 break;
719
720 usleep_range(25, 100);
721 }
722
723 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
724 return -ETIMEDOUT;
725
726 return 0;
727}
728
729static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
730{
731 u32 value;
732
733 /* pre-charge all used lanes */
734 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
735
736 if (lanes <= 2)
737 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
738 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
739 else
740 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
741 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
742
743 if (lanes <= 1)
744 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
745 else
746 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
747
748 if (lanes == 0)
749 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
750 else
751 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
752
753 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
754
755 usleep_range(15, 100);
756
757 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
758 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
759 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
760 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
761}
762
763static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
764{
765 u32 mask = 0x08, adj = 0, value;
766
767 /* enable pad calibration logic */
768 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
769 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
770 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
771
772 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
773 value |= SOR_PLL1_TMDS_TERM;
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
775
776 while (mask) {
777 adj |= mask;
778
779 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
780 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
781 value |= SOR_PLL1_TMDS_TERMADJ(adj);
782 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
783
784 usleep_range(100, 200);
785
786 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
787 if (value & SOR_PLL1_TERM_COMPOUT)
788 adj &= ~mask;
789
790 mask >>= 1;
791 }
792
793 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
794 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
795 value |= SOR_PLL1_TMDS_TERMADJ(adj);
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
797
798 /* disable pad calibration logic */
799 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
800 value |= SOR_DP_PADCTL_PAD_CAL_PD;
801 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
802}
803
804static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
805{
806 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
807 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
808 const struct tegra_sor_soc *soc = sor->soc;
809 u32 pattern = 0, tx_pu = 0, value;
810 unsigned int i;
811
812 for (value = 0, i = 0; i < link->lanes; i++) {
813 u8 vs = link->train.request.voltage_swing[i];
814 u8 pe = link->train.request.pre_emphasis[i];
815 u8 pc = link->train.request.post_cursor[i];
816 u8 shift = sor->soc->lane_map[i] << 3;
817
818 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
819 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
820 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
821
822 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
823 tx_pu = sor->soc->tx_pu[pc][vs][pe];
824
825 switch (link->train.pattern) {
826 case DP_TRAINING_PATTERN_DISABLE:
827 value = SOR_DP_TPG_SCRAMBLER_GALIOS |
828 SOR_DP_TPG_PATTERN_NONE;
829 break;
830
831 case DP_TRAINING_PATTERN_1:
832 value = SOR_DP_TPG_SCRAMBLER_NONE |
833 SOR_DP_TPG_PATTERN_TRAIN1;
834 break;
835
836 case DP_TRAINING_PATTERN_2:
837 value = SOR_DP_TPG_SCRAMBLER_NONE |
838 SOR_DP_TPG_PATTERN_TRAIN2;
839 break;
840
841 case DP_TRAINING_PATTERN_3:
842 value = SOR_DP_TPG_SCRAMBLER_NONE |
843 SOR_DP_TPG_PATTERN_TRAIN3;
844 break;
845
846 default:
847 return -EINVAL;
848 }
849
850 if (link->caps.channel_coding)
851 value |= SOR_DP_TPG_CHANNEL_CODING;
852
853 pattern = pattern << 8 | value;
854 }
855
856 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
857 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
858
859 if (link->caps.tps3_supported)
860 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
861
862 tegra_sor_writel(sor, pattern, SOR_DP_TPG);
863
864 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
865 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
866 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
867 value |= SOR_DP_PADCTL_TX_PU(tx_pu);
868 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
869
870 usleep_range(20, 100);
871
872 return 0;
873}
874
875static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
876{
877 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
878 unsigned int rate, lanes;
879 u32 value;
880 int err;
881
882 rate = drm_dp_link_rate_to_bw_code(link->rate);
883 lanes = link->lanes;
884
885 /* configure link speed and lane count */
886 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
887 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
888 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
889 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
890
891 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
892 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
893 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
894
895 if (link->caps.enhanced_framing)
896 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
897
898 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
899
900 usleep_range(400, 1000);
901
902 /* configure load pulse position adjustment */
903 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
904 value &= ~SOR_PLL1_LOADADJ_MASK;
905
906 switch (rate) {
907 case DP_LINK_BW_1_62:
908 value |= SOR_PLL1_LOADADJ(0x3);
909 break;
910
911 case DP_LINK_BW_2_7:
912 value |= SOR_PLL1_LOADADJ(0x4);
913 break;
914
915 case DP_LINK_BW_5_4:
916 value |= SOR_PLL1_LOADADJ(0x6);
917 break;
918 }
919
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
921
922 /* use alternate scrambler reset for eDP */
923 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
924
925 if (link->edp == 0)
926 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
927 else
928 value |= SOR_DP_SPARE_PANEL_INTERNAL;
929
930 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
931
932 err = tegra_sor_power_down_lanes(sor);
933 if (err < 0) {
934 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
935 return err;
936 }
937
938 /* power up and pre-charge lanes */
939 err = tegra_sor_power_up_lanes(sor, lanes);
940 if (err < 0) {
941 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
942 lanes, (lanes != 1) ? "s" : "", err);
943 return err;
944 }
945
946 tegra_sor_dp_precharge(sor, lanes);
947
948 return 0;
949}
950
951static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
952 .apply_training = tegra_sor_dp_link_apply_training,
953 .configure = tegra_sor_dp_link_configure,
954};
955
956static void tegra_sor_super_update(struct tegra_sor *sor)
957{
958 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
959 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
960 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
961}
962
963static void tegra_sor_update(struct tegra_sor *sor)
964{
965 tegra_sor_writel(sor, 0, SOR_STATE0);
966 tegra_sor_writel(sor, 1, SOR_STATE0);
967 tegra_sor_writel(sor, 0, SOR_STATE0);
968}
969
970static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
971{
972 u32 value;
973
974 value = tegra_sor_readl(sor, SOR_PWM_DIV);
975 value &= ~SOR_PWM_DIV_MASK;
976 value |= 0x400; /* period */
977 tegra_sor_writel(sor, value, SOR_PWM_DIV);
978
979 value = tegra_sor_readl(sor, SOR_PWM_CTL);
980 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
981 value |= 0x400; /* duty cycle */
982 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
983 value |= SOR_PWM_CTL_TRIGGER;
984 tegra_sor_writel(sor, value, SOR_PWM_CTL);
985
986 timeout = jiffies + msecs_to_jiffies(timeout);
987
988 while (time_before(jiffies, timeout)) {
989 value = tegra_sor_readl(sor, SOR_PWM_CTL);
990 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
991 return 0;
992
993 usleep_range(25, 100);
994 }
995
996 return -ETIMEDOUT;
997}
998
999static int tegra_sor_attach(struct tegra_sor *sor)
1000{
1001 unsigned long value, timeout;
1002
1003 /* wake up in normal mode */
1004 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1005 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1006 value |= SOR_SUPER_STATE_MODE_NORMAL;
1007 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1008 tegra_sor_super_update(sor);
1009
1010 /* attach */
1011 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1012 value |= SOR_SUPER_STATE_ATTACHED;
1013 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1014 tegra_sor_super_update(sor);
1015
1016 timeout = jiffies + msecs_to_jiffies(250);
1017
1018 while (time_before(jiffies, timeout)) {
1019 value = tegra_sor_readl(sor, SOR_TEST);
1020 if ((value & SOR_TEST_ATTACHED) != 0)
1021 return 0;
1022
1023 usleep_range(25, 100);
1024 }
1025
1026 return -ETIMEDOUT;
1027}
1028
1029static int tegra_sor_wakeup(struct tegra_sor *sor)
1030{
1031 unsigned long value, timeout;
1032
1033 timeout = jiffies + msecs_to_jiffies(250);
1034
1035 /* wait for head to wake up */
1036 while (time_before(jiffies, timeout)) {
1037 value = tegra_sor_readl(sor, SOR_TEST);
1038 value &= SOR_TEST_HEAD_MODE_MASK;
1039
1040 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1041 return 0;
1042
1043 usleep_range(25, 100);
1044 }
1045
1046 return -ETIMEDOUT;
1047}
1048
1049static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1050{
1051 u32 value;
1052
1053 value = tegra_sor_readl(sor, SOR_PWR);
1054 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1055 tegra_sor_writel(sor, value, SOR_PWR);
1056
1057 timeout = jiffies + msecs_to_jiffies(timeout);
1058
1059 while (time_before(jiffies, timeout)) {
1060 value = tegra_sor_readl(sor, SOR_PWR);
1061 if ((value & SOR_PWR_TRIGGER) == 0)
1062 return 0;
1063
1064 usleep_range(25, 100);
1065 }
1066
1067 return -ETIMEDOUT;
1068}
1069
1070struct tegra_sor_params {
1071 /* number of link clocks per line */
1072 unsigned int num_clocks;
1073 /* ratio between input and output */
1074 u64 ratio;
1075 /* precision factor */
1076 u64 precision;
1077
1078 unsigned int active_polarity;
1079 unsigned int active_count;
1080 unsigned int active_frac;
1081 unsigned int tu_size;
1082 unsigned int error;
1083};
1084
1085static int tegra_sor_compute_params(struct tegra_sor *sor,
1086 struct tegra_sor_params *params,
1087 unsigned int tu_size)
1088{
1089 u64 active_sym, active_count, frac, approx;
1090 u32 active_polarity, active_frac = 0;
1091 const u64 f = params->precision;
1092 s64 error;
1093
1094 active_sym = params->ratio * tu_size;
1095 active_count = div_u64(active_sym, f) * f;
1096 frac = active_sym - active_count;
1097
1098 /* fraction < 0.5 */
1099 if (frac >= (f / 2)) {
1100 active_polarity = 1;
1101 frac = f - frac;
1102 } else {
1103 active_polarity = 0;
1104 }
1105
1106 if (frac != 0) {
1107 frac = div_u64(f * f, frac); /* 1/fraction */
1108 if (frac <= (15 * f)) {
1109 active_frac = div_u64(frac, f);
1110
1111 /* round up */
1112 if (active_polarity)
1113 active_frac++;
1114 } else {
1115 active_frac = active_polarity ? 1 : 15;
1116 }
1117 }
1118
1119 if (active_frac == 1)
1120 active_polarity = 0;
1121
1122 if (active_polarity == 1) {
1123 if (active_frac) {
1124 approx = active_count + (active_frac * (f - 1)) * f;
1125 approx = div_u64(approx, active_frac * f);
1126 } else {
1127 approx = active_count + f;
1128 }
1129 } else {
1130 if (active_frac)
1131 approx = active_count + div_u64(f, active_frac);
1132 else
1133 approx = active_count;
1134 }
1135
1136 error = div_s64(active_sym - approx, tu_size);
1137 error *= params->num_clocks;
1138
1139 if (error <= 0 && abs(error) < params->error) {
1140 params->active_count = div_u64(active_count, f);
1141 params->active_polarity = active_polarity;
1142 params->active_frac = active_frac;
1143 params->error = abs(error);
1144 params->tu_size = tu_size;
1145
1146 if (error == 0)
1147 return true;
1148 }
1149
1150 return false;
1151}
1152
1153static int tegra_sor_compute_config(struct tegra_sor *sor,
1154 const struct drm_display_mode *mode,
1155 struct tegra_sor_config *config,
1156 struct drm_dp_link *link)
1157{
1158 const u64 f = 100000, link_rate = link->rate * 1000;
1159 const u64 pclk = (u64)mode->clock * 1000;
1160 u64 input, output, watermark, num;
1161 struct tegra_sor_params params;
1162 u32 num_syms_per_line;
1163 unsigned int i;
1164
1165 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1166 return -EINVAL;
1167
1168 input = pclk * config->bits_per_pixel;
1169 output = link_rate * 8 * link->lanes;
1170
1171 if (input >= output)
1172 return -ERANGE;
1173
1174 memset(¶ms, 0, sizeof(params));
1175 params.ratio = div64_u64(input * f, output);
1176 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1177 params.precision = f;
1178 params.error = 64 * f;
1179 params.tu_size = 64;
1180
1181 for (i = params.tu_size; i >= 32; i--)
1182 if (tegra_sor_compute_params(sor, ¶ms, i))
1183 break;
1184
1185 if (params.active_frac == 0) {
1186 config->active_polarity = 0;
1187 config->active_count = params.active_count;
1188
1189 if (!params.active_polarity)
1190 config->active_count--;
1191
1192 config->tu_size = params.tu_size;
1193 config->active_frac = 1;
1194 } else {
1195 config->active_polarity = params.active_polarity;
1196 config->active_count = params.active_count;
1197 config->active_frac = params.active_frac;
1198 config->tu_size = params.tu_size;
1199 }
1200
1201 dev_dbg(sor->dev,
1202 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1203 config->active_polarity, config->active_count,
1204 config->tu_size, config->active_frac);
1205
1206 watermark = params.ratio * config->tu_size * (f - params.ratio);
1207 watermark = div_u64(watermark, f);
1208
1209 watermark = div_u64(watermark + params.error, f);
1210 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1211 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1212 (link->lanes * 8);
1213
1214 if (config->watermark > 30) {
1215 config->watermark = 30;
1216 dev_err(sor->dev,
1217 "unable to compute TU size, forcing watermark to %u\n",
1218 config->watermark);
1219 } else if (config->watermark > num_syms_per_line) {
1220 config->watermark = num_syms_per_line;
1221 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1222 config->watermark);
1223 }
1224
1225 /* compute the number of symbols per horizontal blanking interval */
1226 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1227 config->hblank_symbols = div_u64(num, pclk);
1228
1229 if (link->caps.enhanced_framing)
1230 config->hblank_symbols -= 3;
1231
1232 config->hblank_symbols -= 12 / link->lanes;
1233
1234 /* compute the number of symbols per vertical blanking interval */
1235 num = (mode->hdisplay - 25) * link_rate;
1236 config->vblank_symbols = div_u64(num, pclk);
1237 config->vblank_symbols -= 36 / link->lanes + 4;
1238
1239 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1240 config->vblank_symbols);
1241
1242 return 0;
1243}
1244
1245static void tegra_sor_apply_config(struct tegra_sor *sor,
1246 const struct tegra_sor_config *config)
1247{
1248 u32 value;
1249
1250 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1251 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1252 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1253 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1254
1255 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1256 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1257 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1258
1259 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1261
1262 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1263 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1264
1265 if (config->active_polarity)
1266 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1267 else
1268 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1269
1270 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1271 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1272 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1273
1274 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1275 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1276 value |= config->hblank_symbols & 0xffff;
1277 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1278
1279 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1280 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1281 value |= config->vblank_symbols & 0xffff;
1282 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1283}
1284
1285static void tegra_sor_mode_set(struct tegra_sor *sor,
1286 const struct drm_display_mode *mode,
1287 struct tegra_sor_state *state)
1288{
1289 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1290 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1291 u32 value;
1292
1293 value = tegra_sor_readl(sor, SOR_STATE1);
1294 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1295 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1296 value &= ~SOR_STATE_ASY_OWNER_MASK;
1297
1298 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1299 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1300
1301 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1302 value &= ~SOR_STATE_ASY_HSYNCPOL;
1303
1304 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1305 value |= SOR_STATE_ASY_HSYNCPOL;
1306
1307 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1308 value &= ~SOR_STATE_ASY_VSYNCPOL;
1309
1310 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1311 value |= SOR_STATE_ASY_VSYNCPOL;
1312
1313 switch (state->bpc) {
1314 case 16:
1315 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1316 break;
1317
1318 case 12:
1319 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1320 break;
1321
1322 case 10:
1323 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1324 break;
1325
1326 case 8:
1327 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1328 break;
1329
1330 case 6:
1331 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1332 break;
1333
1334 default:
1335 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1336 break;
1337 }
1338
1339 tegra_sor_writel(sor, value, SOR_STATE1);
1340
1341 /*
1342 * TODO: The video timing programming below doesn't seem to match the
1343 * register definitions.
1344 */
1345
1346 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1347 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1348
1349 /* sync end = sync width - 1 */
1350 vse = mode->vsync_end - mode->vsync_start - 1;
1351 hse = mode->hsync_end - mode->hsync_start - 1;
1352
1353 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1354 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1355
1356 /* blank end = sync end + back porch */
1357 vbe = vse + (mode->vtotal - mode->vsync_end);
1358 hbe = hse + (mode->htotal - mode->hsync_end);
1359
1360 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1361 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1362
1363 /* blank start = blank end + active */
1364 vbs = vbe + mode->vdisplay;
1365 hbs = hbe + mode->hdisplay;
1366
1367 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1368 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1369
1370 /* XXX interlacing support */
1371 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1372}
1373
1374static int tegra_sor_detach(struct tegra_sor *sor)
1375{
1376 unsigned long value, timeout;
1377
1378 /* switch to safe mode */
1379 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1380 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1381 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1382 tegra_sor_super_update(sor);
1383
1384 timeout = jiffies + msecs_to_jiffies(250);
1385
1386 while (time_before(jiffies, timeout)) {
1387 value = tegra_sor_readl(sor, SOR_PWR);
1388 if (value & SOR_PWR_MODE_SAFE)
1389 break;
1390 }
1391
1392 if ((value & SOR_PWR_MODE_SAFE) == 0)
1393 return -ETIMEDOUT;
1394
1395 /* go to sleep */
1396 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1397 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1398 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1399 tegra_sor_super_update(sor);
1400
1401 /* detach */
1402 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1403 value &= ~SOR_SUPER_STATE_ATTACHED;
1404 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1405 tegra_sor_super_update(sor);
1406
1407 timeout = jiffies + msecs_to_jiffies(250);
1408
1409 while (time_before(jiffies, timeout)) {
1410 value = tegra_sor_readl(sor, SOR_TEST);
1411 if ((value & SOR_TEST_ATTACHED) == 0)
1412 break;
1413
1414 usleep_range(25, 100);
1415 }
1416
1417 if ((value & SOR_TEST_ATTACHED) != 0)
1418 return -ETIMEDOUT;
1419
1420 return 0;
1421}
1422
1423static int tegra_sor_power_down(struct tegra_sor *sor)
1424{
1425 unsigned long value, timeout;
1426 int err;
1427
1428 value = tegra_sor_readl(sor, SOR_PWR);
1429 value &= ~SOR_PWR_NORMAL_STATE_PU;
1430 value |= SOR_PWR_TRIGGER;
1431 tegra_sor_writel(sor, value, SOR_PWR);
1432
1433 timeout = jiffies + msecs_to_jiffies(250);
1434
1435 while (time_before(jiffies, timeout)) {
1436 value = tegra_sor_readl(sor, SOR_PWR);
1437 if ((value & SOR_PWR_TRIGGER) == 0)
1438 return 0;
1439
1440 usleep_range(25, 100);
1441 }
1442
1443 if ((value & SOR_PWR_TRIGGER) != 0)
1444 return -ETIMEDOUT;
1445
1446 /* switch to safe parent clock */
1447 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1448 if (err < 0) {
1449 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1450 return err;
1451 }
1452
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1454 value |= SOR_PLL2_PORT_POWERDOWN;
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1456
1457 usleep_range(20, 100);
1458
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1460 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1462
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1464 value |= SOR_PLL2_SEQ_PLLCAPPD;
1465 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1467
1468 usleep_range(20, 100);
1469
1470 return 0;
1471}
1472
1473static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1474{
1475 u32 value;
1476
1477 timeout = jiffies + msecs_to_jiffies(timeout);
1478
1479 while (time_before(jiffies, timeout)) {
1480 value = tegra_sor_readl(sor, SOR_CRCA);
1481 if (value & SOR_CRCA_VALID)
1482 return 0;
1483
1484 usleep_range(100, 200);
1485 }
1486
1487 return -ETIMEDOUT;
1488}
1489
1490static int tegra_sor_show_crc(struct seq_file *s, void *data)
1491{
1492 struct drm_info_node *node = s->private;
1493 struct tegra_sor *sor = node->info_ent->data;
1494 struct drm_crtc *crtc = sor->output.encoder.crtc;
1495 struct drm_device *drm = node->minor->dev;
1496 int err = 0;
1497 u32 value;
1498
1499 drm_modeset_lock_all(drm);
1500
1501 if (!crtc || !crtc->state->active) {
1502 err = -EBUSY;
1503 goto unlock;
1504 }
1505
1506 value = tegra_sor_readl(sor, SOR_STATE1);
1507 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1508 tegra_sor_writel(sor, value, SOR_STATE1);
1509
1510 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1511 value |= SOR_CRC_CNTRL_ENABLE;
1512 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1513
1514 value = tegra_sor_readl(sor, SOR_TEST);
1515 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1516 tegra_sor_writel(sor, value, SOR_TEST);
1517
1518 err = tegra_sor_crc_wait(sor, 100);
1519 if (err < 0)
1520 goto unlock;
1521
1522 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1523 value = tegra_sor_readl(sor, SOR_CRCB);
1524
1525 seq_printf(s, "%08x\n", value);
1526
1527unlock:
1528 drm_modeset_unlock_all(drm);
1529 return err;
1530}
1531
1532#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1533
1534static const struct debugfs_reg32 tegra_sor_regs[] = {
1535 DEBUGFS_REG32(SOR_CTXSW),
1536 DEBUGFS_REG32(SOR_SUPER_STATE0),
1537 DEBUGFS_REG32(SOR_SUPER_STATE1),
1538 DEBUGFS_REG32(SOR_STATE0),
1539 DEBUGFS_REG32(SOR_STATE1),
1540 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1541 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1542 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1543 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1544 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1545 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1546 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1547 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1548 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1549 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1550 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1551 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1552 DEBUGFS_REG32(SOR_CRC_CNTRL),
1553 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1554 DEBUGFS_REG32(SOR_CLK_CNTRL),
1555 DEBUGFS_REG32(SOR_CAP),
1556 DEBUGFS_REG32(SOR_PWR),
1557 DEBUGFS_REG32(SOR_TEST),
1558 DEBUGFS_REG32(SOR_PLL0),
1559 DEBUGFS_REG32(SOR_PLL1),
1560 DEBUGFS_REG32(SOR_PLL2),
1561 DEBUGFS_REG32(SOR_PLL3),
1562 DEBUGFS_REG32(SOR_CSTM),
1563 DEBUGFS_REG32(SOR_LVDS),
1564 DEBUGFS_REG32(SOR_CRCA),
1565 DEBUGFS_REG32(SOR_CRCB),
1566 DEBUGFS_REG32(SOR_BLANK),
1567 DEBUGFS_REG32(SOR_SEQ_CTL),
1568 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1569 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1570 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1571 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1572 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1573 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1574 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1575 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1576 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1577 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1578 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1579 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1580 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1581 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1582 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1583 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1584 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1585 DEBUGFS_REG32(SOR_PWM_DIV),
1586 DEBUGFS_REG32(SOR_PWM_CTL),
1587 DEBUGFS_REG32(SOR_VCRC_A0),
1588 DEBUGFS_REG32(SOR_VCRC_A1),
1589 DEBUGFS_REG32(SOR_VCRC_B0),
1590 DEBUGFS_REG32(SOR_VCRC_B1),
1591 DEBUGFS_REG32(SOR_CCRC_A0),
1592 DEBUGFS_REG32(SOR_CCRC_A1),
1593 DEBUGFS_REG32(SOR_CCRC_B0),
1594 DEBUGFS_REG32(SOR_CCRC_B1),
1595 DEBUGFS_REG32(SOR_EDATA_A0),
1596 DEBUGFS_REG32(SOR_EDATA_A1),
1597 DEBUGFS_REG32(SOR_EDATA_B0),
1598 DEBUGFS_REG32(SOR_EDATA_B1),
1599 DEBUGFS_REG32(SOR_COUNT_A0),
1600 DEBUGFS_REG32(SOR_COUNT_A1),
1601 DEBUGFS_REG32(SOR_COUNT_B0),
1602 DEBUGFS_REG32(SOR_COUNT_B1),
1603 DEBUGFS_REG32(SOR_DEBUG_A0),
1604 DEBUGFS_REG32(SOR_DEBUG_A1),
1605 DEBUGFS_REG32(SOR_DEBUG_B0),
1606 DEBUGFS_REG32(SOR_DEBUG_B1),
1607 DEBUGFS_REG32(SOR_TRIG),
1608 DEBUGFS_REG32(SOR_MSCHECK),
1609 DEBUGFS_REG32(SOR_XBAR_CTRL),
1610 DEBUGFS_REG32(SOR_XBAR_POL),
1611 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1612 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1613 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1614 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1615 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1616 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1617 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1618 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1619 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1620 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1621 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1622 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1623 DEBUGFS_REG32(SOR_DP_CONFIG0),
1624 DEBUGFS_REG32(SOR_DP_CONFIG1),
1625 DEBUGFS_REG32(SOR_DP_MN0),
1626 DEBUGFS_REG32(SOR_DP_MN1),
1627 DEBUGFS_REG32(SOR_DP_PADCTL0),
1628 DEBUGFS_REG32(SOR_DP_PADCTL1),
1629 DEBUGFS_REG32(SOR_DP_PADCTL2),
1630 DEBUGFS_REG32(SOR_DP_DEBUG0),
1631 DEBUGFS_REG32(SOR_DP_DEBUG1),
1632 DEBUGFS_REG32(SOR_DP_SPARE0),
1633 DEBUGFS_REG32(SOR_DP_SPARE1),
1634 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1635 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1636 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1637 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1638 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1639 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1640 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1641 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1642 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1643 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1644 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1645 DEBUGFS_REG32(SOR_DP_TPG),
1646 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1647 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1648 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1649 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1650};
1651
1652static int tegra_sor_show_regs(struct seq_file *s, void *data)
1653{
1654 struct drm_info_node *node = s->private;
1655 struct tegra_sor *sor = node->info_ent->data;
1656 struct drm_crtc *crtc = sor->output.encoder.crtc;
1657 struct drm_device *drm = node->minor->dev;
1658 unsigned int i;
1659 int err = 0;
1660
1661 drm_modeset_lock_all(drm);
1662
1663 if (!crtc || !crtc->state->active) {
1664 err = -EBUSY;
1665 goto unlock;
1666 }
1667
1668 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1669 unsigned int offset = tegra_sor_regs[i].offset;
1670
1671 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1672 offset, tegra_sor_readl(sor, offset));
1673 }
1674
1675unlock:
1676 drm_modeset_unlock_all(drm);
1677 return err;
1678}
1679
1680static const struct drm_info_list debugfs_files[] = {
1681 { "crc", tegra_sor_show_crc, 0, NULL },
1682 { "regs", tegra_sor_show_regs, 0, NULL },
1683};
1684
1685static int tegra_sor_late_register(struct drm_connector *connector)
1686{
1687 struct tegra_output *output = connector_to_output(connector);
1688 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1689 struct drm_minor *minor = connector->dev->primary;
1690 struct dentry *root = connector->debugfs_entry;
1691 struct tegra_sor *sor = to_sor(output);
1692
1693 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1694 GFP_KERNEL);
1695 if (!sor->debugfs_files)
1696 return -ENOMEM;
1697
1698 for (i = 0; i < count; i++)
1699 sor->debugfs_files[i].data = sor;
1700
1701 drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1702
1703 return 0;
1704}
1705
1706static void tegra_sor_early_unregister(struct drm_connector *connector)
1707{
1708 struct tegra_output *output = connector_to_output(connector);
1709 unsigned int count = ARRAY_SIZE(debugfs_files);
1710 struct tegra_sor *sor = to_sor(output);
1711
1712 drm_debugfs_remove_files(sor->debugfs_files, count,
1713 connector->debugfs_entry,
1714 connector->dev->primary);
1715 kfree(sor->debugfs_files);
1716 sor->debugfs_files = NULL;
1717}
1718
1719static void tegra_sor_connector_reset(struct drm_connector *connector)
1720{
1721 struct tegra_sor_state *state;
1722
1723 state = kzalloc(sizeof(*state), GFP_KERNEL);
1724 if (!state)
1725 return;
1726
1727 if (connector->state) {
1728 __drm_atomic_helper_connector_destroy_state(connector->state);
1729 kfree(connector->state);
1730 }
1731
1732 __drm_atomic_helper_connector_reset(connector, &state->base);
1733}
1734
1735static enum drm_connector_status
1736tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1737{
1738 struct tegra_output *output = connector_to_output(connector);
1739 struct tegra_sor *sor = to_sor(output);
1740
1741 if (sor->aux)
1742 return drm_dp_aux_detect(sor->aux);
1743
1744 return tegra_output_connector_detect(connector, force);
1745}
1746
1747static struct drm_connector_state *
1748tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1749{
1750 struct tegra_sor_state *state = to_sor_state(connector->state);
1751 struct tegra_sor_state *copy;
1752
1753 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1754 if (!copy)
1755 return NULL;
1756
1757 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1758
1759 return ©->base;
1760}
1761
1762static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1763 .reset = tegra_sor_connector_reset,
1764 .detect = tegra_sor_connector_detect,
1765 .fill_modes = drm_helper_probe_single_connector_modes,
1766 .destroy = tegra_output_connector_destroy,
1767 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1768 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1769 .late_register = tegra_sor_late_register,
1770 .early_unregister = tegra_sor_early_unregister,
1771};
1772
1773static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1774{
1775 struct tegra_output *output = connector_to_output(connector);
1776 struct tegra_sor *sor = to_sor(output);
1777 int err;
1778
1779 if (sor->aux)
1780 drm_dp_aux_enable(sor->aux);
1781
1782 err = tegra_output_connector_get_modes(connector);
1783
1784 if (sor->aux)
1785 drm_dp_aux_disable(sor->aux);
1786
1787 return err;
1788}
1789
1790static enum drm_mode_status
1791tegra_sor_connector_mode_valid(struct drm_connector *connector,
1792 struct drm_display_mode *mode)
1793{
1794 return MODE_OK;
1795}
1796
1797static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1798 .get_modes = tegra_sor_connector_get_modes,
1799 .mode_valid = tegra_sor_connector_mode_valid,
1800};
1801
1802static int
1803tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1804 struct drm_crtc_state *crtc_state,
1805 struct drm_connector_state *conn_state)
1806{
1807 struct tegra_output *output = encoder_to_output(encoder);
1808 struct tegra_sor_state *state = to_sor_state(conn_state);
1809 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1810 unsigned long pclk = crtc_state->mode.clock * 1000;
1811 struct tegra_sor *sor = to_sor(output);
1812 struct drm_display_info *info;
1813 int err;
1814
1815 info = &output->connector.display_info;
1816
1817 /*
1818 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1819 * the pixel clock must be corrected accordingly.
1820 */
1821 if (pclk >= 340000000) {
1822 state->link_speed = 20;
1823 state->pclk = pclk / 2;
1824 } else {
1825 state->link_speed = 10;
1826 state->pclk = pclk;
1827 }
1828
1829 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1830 pclk, 0);
1831 if (err < 0) {
1832 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1833 return err;
1834 }
1835
1836 switch (info->bpc) {
1837 case 8:
1838 case 6:
1839 state->bpc = info->bpc;
1840 break;
1841
1842 default:
1843 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1844 state->bpc = 8;
1845 break;
1846 }
1847
1848 return 0;
1849}
1850
1851static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1852{
1853 u32 value = 0;
1854 size_t i;
1855
1856 for (i = size; i > 0; i--)
1857 value = (value << 8) | ptr[i - 1];
1858
1859 return value;
1860}
1861
1862static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1863 const void *data, size_t size)
1864{
1865 const u8 *ptr = data;
1866 unsigned long offset;
1867 size_t i, j;
1868 u32 value;
1869
1870 switch (ptr[0]) {
1871 case HDMI_INFOFRAME_TYPE_AVI:
1872 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1873 break;
1874
1875 case HDMI_INFOFRAME_TYPE_AUDIO:
1876 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1877 break;
1878
1879 case HDMI_INFOFRAME_TYPE_VENDOR:
1880 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1881 break;
1882
1883 default:
1884 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1885 ptr[0]);
1886 return;
1887 }
1888
1889 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1890 INFOFRAME_HEADER_VERSION(ptr[1]) |
1891 INFOFRAME_HEADER_LEN(ptr[2]);
1892 tegra_sor_writel(sor, value, offset);
1893 offset++;
1894
1895 /*
1896 * Each subpack contains 7 bytes, divided into:
1897 * - subpack_low: bytes 0 - 3
1898 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1899 */
1900 for (i = 3, j = 0; i < size; i += 7, j += 8) {
1901 size_t rem = size - i, num = min_t(size_t, rem, 4);
1902
1903 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1904 tegra_sor_writel(sor, value, offset++);
1905
1906 num = min_t(size_t, rem - num, 3);
1907
1908 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1909 tegra_sor_writel(sor, value, offset++);
1910 }
1911}
1912
1913static int
1914tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1915 const struct drm_display_mode *mode)
1916{
1917 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1918 struct hdmi_avi_infoframe frame;
1919 u32 value;
1920 int err;
1921
1922 /* disable AVI infoframe */
1923 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1924 value &= ~INFOFRAME_CTRL_SINGLE;
1925 value &= ~INFOFRAME_CTRL_OTHER;
1926 value &= ~INFOFRAME_CTRL_ENABLE;
1927 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1928
1929 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1930 &sor->output.connector, mode);
1931 if (err < 0) {
1932 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1933 return err;
1934 }
1935
1936 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1937 if (err < 0) {
1938 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1939 return err;
1940 }
1941
1942 tegra_sor_hdmi_write_infopack(sor, buffer, err);
1943
1944 /* enable AVI infoframe */
1945 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1946 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1947 value |= INFOFRAME_CTRL_ENABLE;
1948 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1949
1950 return 0;
1951}
1952
1953static void tegra_sor_write_eld(struct tegra_sor *sor)
1954{
1955 size_t length = drm_eld_size(sor->output.connector.eld), i;
1956
1957 for (i = 0; i < length; i++)
1958 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1959 SOR_AUDIO_HDA_ELD_BUFWR);
1960
1961 /*
1962 * The HDA codec will always report an ELD buffer size of 96 bytes and
1963 * the HDA codec driver will check that each byte read from the buffer
1964 * is valid. Therefore every byte must be written, even if no 96 bytes
1965 * were parsed from EDID.
1966 */
1967 for (i = length; i < 96; i++)
1968 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1969}
1970
1971static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1972{
1973 u32 value;
1974
1975 /*
1976 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1977 * is used for interoperability between the HDA codec driver and the
1978 * HDMI/DP driver.
1979 */
1980 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1981 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1982 tegra_sor_writel(sor, value, SOR_INT_MASK);
1983
1984 tegra_sor_write_eld(sor);
1985
1986 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1987 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1988}
1989
1990static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1991{
1992 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1993 tegra_sor_writel(sor, 0, SOR_INT_MASK);
1994 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
1995}
1996
1997static void tegra_sor_audio_enable(struct tegra_sor *sor)
1998{
1999 u32 value;
2000
2001 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2002
2003 /* select HDA audio input */
2004 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2005 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2006
2007 /* inject null samples */
2008 if (sor->format.channels != 2)
2009 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2010 else
2011 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2012
2013 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2014
2015 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2016
2017 /* enable advertising HBR capability */
2018 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2019}
2020
2021static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2022{
2023 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2024 struct hdmi_audio_infoframe frame;
2025 u32 value;
2026 int err;
2027
2028 err = hdmi_audio_infoframe_init(&frame);
2029 if (err < 0) {
2030 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2031 return err;
2032 }
2033
2034 frame.channels = sor->format.channels;
2035
2036 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2037 if (err < 0) {
2038 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2039 return err;
2040 }
2041
2042 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2043
2044 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2045 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2046 value |= INFOFRAME_CTRL_ENABLE;
2047 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2048
2049 return 0;
2050}
2051
2052static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2053{
2054 u32 value;
2055
2056 tegra_sor_audio_enable(sor);
2057
2058 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2059
2060 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2061 SOR_HDMI_SPARE_CTS_RESET(1) |
2062 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2063 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2064
2065 /* enable HW CTS */
2066 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2068
2069 /* allow packet to be sent */
2070 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2071 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2072
2073 /* reset N counter and enable lookup */
2074 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2075 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2076
2077 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2078 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2079 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2080
2081 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2082 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2083
2084 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2085 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2086
2087 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2088 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2089
2090 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2092 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2093
2094 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2096 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2097
2098 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2099 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2100 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2101
2102 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2103 value &= ~SOR_HDMI_AUDIO_N_RESET;
2104 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2105
2106 tegra_sor_hdmi_enable_audio_infoframe(sor);
2107}
2108
2109static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2110{
2111 u32 value;
2112
2113 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2114 value &= ~INFOFRAME_CTRL_ENABLE;
2115 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2116}
2117
2118static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2119{
2120 tegra_sor_hdmi_disable_audio_infoframe(sor);
2121}
2122
2123static struct tegra_sor_hdmi_settings *
2124tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2125{
2126 unsigned int i;
2127
2128 for (i = 0; i < sor->num_settings; i++)
2129 if (frequency <= sor->settings[i].frequency)
2130 return &sor->settings[i];
2131
2132 return NULL;
2133}
2134
2135static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2136{
2137 u32 value;
2138
2139 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2140 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2141 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2142 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2143}
2144
2145static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2146{
2147 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false);
2148 drm_scdc_set_scrambling(&sor->output.connector, false);
2149
2150 tegra_sor_hdmi_disable_scrambling(sor);
2151}
2152
2153static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2154{
2155 if (sor->scdc_enabled) {
2156 cancel_delayed_work_sync(&sor->scdc);
2157 tegra_sor_hdmi_scdc_disable(sor);
2158 }
2159}
2160
2161static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2162{
2163 u32 value;
2164
2165 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2166 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2167 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2168 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2169}
2170
2171static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2172{
2173 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true);
2174 drm_scdc_set_scrambling(&sor->output.connector, true);
2175
2176 tegra_sor_hdmi_enable_scrambling(sor);
2177}
2178
2179static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2180{
2181 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2182
2183 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) {
2184 DRM_DEBUG_KMS("SCDC not scrambled\n");
2185 tegra_sor_hdmi_scdc_enable(sor);
2186 }
2187
2188 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2189}
2190
2191static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2192{
2193 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2194 struct drm_display_mode *mode;
2195
2196 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2197
2198 if (mode->clock >= 340000 && scdc->supported) {
2199 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2200 tegra_sor_hdmi_scdc_enable(sor);
2201 sor->scdc_enabled = true;
2202 }
2203}
2204
2205static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2206{
2207 struct tegra_output *output = encoder_to_output(encoder);
2208 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2209 struct tegra_sor *sor = to_sor(output);
2210 u32 value;
2211 int err;
2212
2213 tegra_sor_audio_unprepare(sor);
2214 tegra_sor_hdmi_scdc_stop(sor);
2215
2216 err = tegra_sor_detach(sor);
2217 if (err < 0)
2218 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2219
2220 tegra_sor_writel(sor, 0, SOR_STATE1);
2221 tegra_sor_update(sor);
2222
2223 /* disable display to SOR clock */
2224 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2225
2226 if (!sor->soc->has_nvdisplay)
2227 value &= ~SOR1_TIMING_CYA;
2228
2229 value &= ~SOR_ENABLE(sor->index);
2230
2231 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2232
2233 tegra_dc_commit(dc);
2234
2235 err = tegra_sor_power_down(sor);
2236 if (err < 0)
2237 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2238
2239 err = tegra_io_pad_power_disable(sor->pad);
2240 if (err < 0)
2241 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2242
2243 host1x_client_suspend(&sor->client);
2244}
2245
2246static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2247{
2248 struct tegra_output *output = encoder_to_output(encoder);
2249 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2250 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2251 struct tegra_sor_hdmi_settings *settings;
2252 struct tegra_sor *sor = to_sor(output);
2253 struct tegra_sor_state *state;
2254 struct drm_display_mode *mode;
2255 unsigned long rate, pclk;
2256 unsigned int div, i;
2257 u32 value;
2258 int err;
2259
2260 state = to_sor_state(output->connector.state);
2261 mode = &encoder->crtc->state->adjusted_mode;
2262 pclk = mode->clock * 1000;
2263
2264 err = host1x_client_resume(&sor->client);
2265 if (err < 0) {
2266 dev_err(sor->dev, "failed to resume: %d\n", err);
2267 return;
2268 }
2269
2270 /* switch to safe parent clock */
2271 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2272 if (err < 0) {
2273 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2274 return;
2275 }
2276
2277 div = clk_get_rate(sor->clk) / 1000000 * 4;
2278
2279 err = tegra_io_pad_power_enable(sor->pad);
2280 if (err < 0)
2281 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2282
2283 usleep_range(20, 100);
2284
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2286 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2288
2289 usleep_range(20, 100);
2290
2291 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2292 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2294
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2296 value &= ~SOR_PLL0_VCOPD;
2297 value &= ~SOR_PLL0_PWR;
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2299
2300 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2301 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2303
2304 usleep_range(200, 400);
2305
2306 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2307 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2308 value &= ~SOR_PLL2_PORT_POWERDOWN;
2309 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2310
2311 usleep_range(20, 100);
2312
2313 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2314 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2315 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2316 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2317
2318 while (true) {
2319 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2320 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2321 break;
2322
2323 usleep_range(250, 1000);
2324 }
2325
2326 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2327 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2328 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2329
2330 while (true) {
2331 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2332 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2333 break;
2334
2335 usleep_range(250, 1000);
2336 }
2337
2338 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2339 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2340 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2341
2342 if (mode->clock < 340000) {
2343 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2344 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2345 } else {
2346 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2347 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2348 }
2349
2350 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2351 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2352
2353 /* SOR pad PLL stabilization time */
2354 usleep_range(250, 1000);
2355
2356 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2357 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2358 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2359 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2360
2361 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2362 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2363 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2364 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2365 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2366 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2367
2368 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2369 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2370 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2371
2372 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2373 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2374 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2376
2377 if (!sor->soc->has_nvdisplay) {
2378 /* program the reference clock */
2379 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2380 tegra_sor_writel(sor, value, SOR_REFCLK);
2381 }
2382
2383 /* XXX not in TRM */
2384 for (value = 0, i = 0; i < 5; i++)
2385 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2386 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2387
2388 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2389 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2390
2391 /*
2392 * Switch the pad clock to the DP clock. Note that we cannot actually
2393 * do this because Tegra186 and later don't support clk_set_parent()
2394 * on the sorX_pad_clkout clocks. We already do the equivalent above
2395 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2396 */
2397#if 0
2398 err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2399 if (err < 0) {
2400 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2401 err);
2402 return;
2403 }
2404#endif
2405
2406 /* switch the SOR clock to the pad clock */
2407 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2408 if (err < 0) {
2409 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2410 err);
2411 return;
2412 }
2413
2414 /* switch the output clock to the parent pixel clock */
2415 err = clk_set_parent(sor->clk, sor->clk_parent);
2416 if (err < 0) {
2417 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2418 err);
2419 return;
2420 }
2421
2422 /* adjust clock rate for HDMI 2.0 modes */
2423 rate = clk_get_rate(sor->clk_parent);
2424
2425 if (mode->clock >= 340000)
2426 rate /= 2;
2427
2428 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2429
2430 clk_set_rate(sor->clk, rate);
2431
2432 if (!sor->soc->has_nvdisplay) {
2433 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2434
2435 /* XXX is this the proper check? */
2436 if (mode->clock < 75000)
2437 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2438
2439 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2440 }
2441
2442 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2443
2444 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2445 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2446 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2447
2448 if (!dc->soc->has_nvdisplay) {
2449 /* H_PULSE2 setup */
2450 pulse_start = h_ref_to_sync +
2451 (mode->hsync_end - mode->hsync_start) +
2452 (mode->htotal - mode->hsync_end) - 10;
2453
2454 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2455 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2456 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2457
2458 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2459 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2460
2461 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2462 value |= H_PULSE2_ENABLE;
2463 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2464 }
2465
2466 /* infoframe setup */
2467 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2468 if (err < 0)
2469 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2470
2471 /* XXX HDMI audio support not implemented yet */
2472 tegra_sor_hdmi_disable_audio_infoframe(sor);
2473
2474 /* use single TMDS protocol */
2475 value = tegra_sor_readl(sor, SOR_STATE1);
2476 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2477 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2478 tegra_sor_writel(sor, value, SOR_STATE1);
2479
2480 /* power up pad calibration */
2481 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2482 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2483 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2484
2485 /* production settings */
2486 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2487 if (!settings) {
2488 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2489 mode->clock * 1000);
2490 return;
2491 }
2492
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2494 value &= ~SOR_PLL0_ICHPMP_MASK;
2495 value &= ~SOR_PLL0_FILTER_MASK;
2496 value &= ~SOR_PLL0_VCOCAP_MASK;
2497 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2498 value |= SOR_PLL0_FILTER(settings->filter);
2499 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2501
2502 /* XXX not in TRM */
2503 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2504 value &= ~SOR_PLL1_LOADADJ_MASK;
2505 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2506 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2507 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2508 value |= SOR_PLL1_TMDS_TERM;
2509 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2510
2511 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2512 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2513 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2514 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2515 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2516 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2517 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2518 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2519 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2521
2522 value = settings->drive_current[3] << 24 |
2523 settings->drive_current[2] << 16 |
2524 settings->drive_current[1] << 8 |
2525 settings->drive_current[0] << 0;
2526 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2527
2528 value = settings->preemphasis[3] << 24 |
2529 settings->preemphasis[2] << 16 |
2530 settings->preemphasis[1] << 8 |
2531 settings->preemphasis[0] << 0;
2532 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2533
2534 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2535 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2536 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2537 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2538 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2539
2540 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2541 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2542 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2543 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2544
2545 /* power down pad calibration */
2546 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2547 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2549
2550 if (!dc->soc->has_nvdisplay) {
2551 /* miscellaneous display controller settings */
2552 value = VSYNC_H_POSITION(1);
2553 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2554 }
2555
2556 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2557 value &= ~DITHER_CONTROL_MASK;
2558 value &= ~BASE_COLOR_SIZE_MASK;
2559
2560 switch (state->bpc) {
2561 case 6:
2562 value |= BASE_COLOR_SIZE_666;
2563 break;
2564
2565 case 8:
2566 value |= BASE_COLOR_SIZE_888;
2567 break;
2568
2569 case 10:
2570 value |= BASE_COLOR_SIZE_101010;
2571 break;
2572
2573 case 12:
2574 value |= BASE_COLOR_SIZE_121212;
2575 break;
2576
2577 default:
2578 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2579 value |= BASE_COLOR_SIZE_888;
2580 break;
2581 }
2582
2583 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2584
2585 /* XXX set display head owner */
2586 value = tegra_sor_readl(sor, SOR_STATE1);
2587 value &= ~SOR_STATE_ASY_OWNER_MASK;
2588 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2589 tegra_sor_writel(sor, value, SOR_STATE1);
2590
2591 err = tegra_sor_power_up(sor, 250);
2592 if (err < 0)
2593 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2594
2595 /* configure dynamic range of output */
2596 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2597 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2598 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2599 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2600
2601 /* configure colorspace */
2602 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2603 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2604 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2605 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2606
2607 tegra_sor_mode_set(sor, mode, state);
2608
2609 tegra_sor_update(sor);
2610
2611 /* program preamble timing in SOR (XXX) */
2612 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2613 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2614 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2615
2616 err = tegra_sor_attach(sor);
2617 if (err < 0)
2618 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2619
2620 /* enable display to SOR clock and generate HDMI preamble */
2621 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2622
2623 if (!sor->soc->has_nvdisplay)
2624 value |= SOR1_TIMING_CYA;
2625
2626 value |= SOR_ENABLE(sor->index);
2627
2628 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2629
2630 if (dc->soc->has_nvdisplay) {
2631 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2632 value &= ~PROTOCOL_MASK;
2633 value |= PROTOCOL_SINGLE_TMDS_A;
2634 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2635 }
2636
2637 tegra_dc_commit(dc);
2638
2639 err = tegra_sor_wakeup(sor);
2640 if (err < 0)
2641 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2642
2643 tegra_sor_hdmi_scdc_start(sor);
2644 tegra_sor_audio_prepare(sor);
2645}
2646
2647static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2648 .disable = tegra_sor_hdmi_disable,
2649 .enable = tegra_sor_hdmi_enable,
2650 .atomic_check = tegra_sor_encoder_atomic_check,
2651};
2652
2653static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2654{
2655 struct tegra_output *output = encoder_to_output(encoder);
2656 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2657 struct tegra_sor *sor = to_sor(output);
2658 u32 value;
2659 int err;
2660
2661 if (output->panel)
2662 drm_panel_disable(output->panel);
2663
2664 /*
2665 * Do not attempt to power down a DP link if we're not connected since
2666 * the AUX transactions would just be timing out.
2667 */
2668 if (output->connector.status != connector_status_disconnected) {
2669 err = drm_dp_link_power_down(sor->aux, &sor->link);
2670 if (err < 0)
2671 dev_err(sor->dev, "failed to power down link: %d\n",
2672 err);
2673 }
2674
2675 err = tegra_sor_detach(sor);
2676 if (err < 0)
2677 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2678
2679 tegra_sor_writel(sor, 0, SOR_STATE1);
2680 tegra_sor_update(sor);
2681
2682 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2683 value &= ~SOR_ENABLE(sor->index);
2684 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2685 tegra_dc_commit(dc);
2686
2687 value = tegra_sor_readl(sor, SOR_STATE1);
2688 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2689 value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2690 value &= ~SOR_STATE_ASY_OWNER_MASK;
2691 tegra_sor_writel(sor, value, SOR_STATE1);
2692 tegra_sor_update(sor);
2693
2694 /* switch to safe parent clock */
2695 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2696 if (err < 0)
2697 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2698
2699 err = tegra_sor_power_down(sor);
2700 if (err < 0)
2701 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2702
2703 err = tegra_io_pad_power_disable(sor->pad);
2704 if (err < 0)
2705 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2706
2707 err = drm_dp_aux_disable(sor->aux);
2708 if (err < 0)
2709 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2710
2711 if (output->panel)
2712 drm_panel_unprepare(output->panel);
2713
2714 host1x_client_suspend(&sor->client);
2715}
2716
2717static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2718{
2719 struct tegra_output *output = encoder_to_output(encoder);
2720 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2721 struct tegra_sor *sor = to_sor(output);
2722 struct tegra_sor_config config;
2723 struct tegra_sor_state *state;
2724 struct drm_display_mode *mode;
2725 struct drm_display_info *info;
2726 unsigned int i;
2727 u32 value;
2728 int err;
2729
2730 state = to_sor_state(output->connector.state);
2731 mode = &encoder->crtc->state->adjusted_mode;
2732 info = &output->connector.display_info;
2733
2734 err = host1x_client_resume(&sor->client);
2735 if (err < 0) {
2736 dev_err(sor->dev, "failed to resume: %d\n", err);
2737 return;
2738 }
2739
2740 /* switch to safe parent clock */
2741 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2742 if (err < 0)
2743 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2744
2745 err = tegra_io_pad_power_enable(sor->pad);
2746 if (err < 0)
2747 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2748
2749 usleep_range(20, 100);
2750
2751 err = drm_dp_aux_enable(sor->aux);
2752 if (err < 0)
2753 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2754
2755 err = drm_dp_link_probe(sor->aux, &sor->link);
2756 if (err < 0)
2757 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2758
2759 tegra_sor_filter_rates(sor);
2760
2761 err = drm_dp_link_choose(&sor->link, mode, info);
2762 if (err < 0)
2763 dev_err(sor->dev, "failed to choose link: %d\n", err);
2764
2765 if (output->panel)
2766 drm_panel_prepare(output->panel);
2767
2768 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2769 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2770 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2771
2772 usleep_range(20, 40);
2773
2774 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2775 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2777
2778 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2779 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2781
2782 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2783 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2784 value |= SOR_PLL2_SEQ_PLLCAPPD;
2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2786
2787 usleep_range(200, 400);
2788
2789 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2790 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2791 value &= ~SOR_PLL2_PORT_POWERDOWN;
2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2793
2794 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2795 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2796
2797 if (output->panel)
2798 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2799 else
2800 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2801
2802 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2803
2804 usleep_range(200, 400);
2805
2806 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2807 /* XXX not in TRM */
2808 if (output->panel)
2809 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2810 else
2811 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2812
2813 value |= SOR_DP_SPARE_SEQ_ENABLE;
2814 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2815
2816 /* XXX not in TRM */
2817 tegra_sor_writel(sor, 0, SOR_LVDS);
2818
2819 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2820 value &= ~SOR_PLL0_ICHPMP_MASK;
2821 value &= ~SOR_PLL0_VCOCAP_MASK;
2822 value |= SOR_PLL0_ICHPMP(0x1);
2823 value |= SOR_PLL0_VCOCAP(0x3);
2824 value |= SOR_PLL0_RESISTOR_EXT;
2825 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2826
2827 /* XXX not in TRM */
2828 for (value = 0, i = 0; i < 5; i++)
2829 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2830 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2831
2832 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2833 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2834
2835 /*
2836 * Switch the pad clock to the DP clock. Note that we cannot actually
2837 * do this because Tegra186 and later don't support clk_set_parent()
2838 * on the sorX_pad_clkout clocks. We already do the equivalent above
2839 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2840 */
2841#if 0
2842 err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2843 if (err < 0) {
2844 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2845 err);
2846 return;
2847 }
2848#endif
2849
2850 /* switch the SOR clock to the pad clock */
2851 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2852 if (err < 0) {
2853 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2854 err);
2855 return;
2856 }
2857
2858 /* switch the output clock to the parent pixel clock */
2859 err = clk_set_parent(sor->clk, sor->clk_parent);
2860 if (err < 0) {
2861 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2862 err);
2863 return;
2864 }
2865
2866 /* use DP-A protocol */
2867 value = tegra_sor_readl(sor, SOR_STATE1);
2868 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2869 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2870 tegra_sor_writel(sor, value, SOR_STATE1);
2871
2872 /* enable port */
2873 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2874 value |= SOR_DP_LINKCTL_ENABLE;
2875 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2876
2877 tegra_sor_dp_term_calibrate(sor);
2878
2879 err = drm_dp_link_train(&sor->link);
2880 if (err < 0)
2881 dev_err(sor->dev, "link training failed: %d\n", err);
2882 else
2883 dev_dbg(sor->dev, "link training succeeded\n");
2884
2885 err = drm_dp_link_power_up(sor->aux, &sor->link);
2886 if (err < 0)
2887 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2888
2889 /* compute configuration */
2890 memset(&config, 0, sizeof(config));
2891 config.bits_per_pixel = state->bpc * 3;
2892
2893 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2894 if (err < 0)
2895 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2896
2897 tegra_sor_apply_config(sor, &config);
2898 tegra_sor_mode_set(sor, mode, state);
2899
2900 if (output->panel) {
2901 /* CSTM (LVDS, link A/B, upper) */
2902 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2903 SOR_CSTM_UPPER;
2904 tegra_sor_writel(sor, value, SOR_CSTM);
2905
2906 /* PWM setup */
2907 err = tegra_sor_setup_pwm(sor, 250);
2908 if (err < 0)
2909 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2910 }
2911
2912 tegra_sor_update(sor);
2913
2914 err = tegra_sor_power_up(sor, 250);
2915 if (err < 0)
2916 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2917
2918 /* attach and wake up */
2919 err = tegra_sor_attach(sor);
2920 if (err < 0)
2921 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2922
2923 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2924 value |= SOR_ENABLE(sor->index);
2925 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2926
2927 tegra_dc_commit(dc);
2928
2929 err = tegra_sor_wakeup(sor);
2930 if (err < 0)
2931 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2932
2933 if (output->panel)
2934 drm_panel_enable(output->panel);
2935}
2936
2937static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2938 .disable = tegra_sor_dp_disable,
2939 .enable = tegra_sor_dp_enable,
2940 .atomic_check = tegra_sor_encoder_atomic_check,
2941};
2942
2943static void tegra_sor_disable_regulator(void *data)
2944{
2945 struct regulator *reg = data;
2946
2947 regulator_disable(reg);
2948}
2949
2950static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
2951{
2952 int err;
2953
2954 err = regulator_enable(reg);
2955 if (err)
2956 return err;
2957
2958 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2959}
2960
2961static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2962{
2963 int err;
2964
2965 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2966 if (IS_ERR(sor->avdd_io_supply))
2967 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply),
2968 "cannot get AVDD I/O supply\n");
2969
2970 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
2971 if (err < 0) {
2972 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2973 err);
2974 return err;
2975 }
2976
2977 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2978 if (IS_ERR(sor->vdd_pll_supply))
2979 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply),
2980 "cannot get VDD PLL supply\n");
2981
2982 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
2983 if (err < 0) {
2984 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2985 err);
2986 return err;
2987 }
2988
2989 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2990 if (IS_ERR(sor->hdmi_supply))
2991 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply),
2992 "cannot get HDMI supply\n");
2993
2994 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
2995 if (err < 0) {
2996 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2997 return err;
2998 }
2999
3000 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3001
3002 return 0;
3003}
3004
3005static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3006 .name = "HDMI",
3007 .probe = tegra_sor_hdmi_probe,
3008 .audio_enable = tegra_sor_hdmi_audio_enable,
3009 .audio_disable = tegra_sor_hdmi_audio_disable,
3010};
3011
3012static int tegra_sor_dp_probe(struct tegra_sor *sor)
3013{
3014 int err;
3015
3016 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3017 if (IS_ERR(sor->avdd_io_supply))
3018 return PTR_ERR(sor->avdd_io_supply);
3019
3020 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
3021 if (err < 0)
3022 return err;
3023
3024 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3025 if (IS_ERR(sor->vdd_pll_supply))
3026 return PTR_ERR(sor->vdd_pll_supply);
3027
3028 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
3029 if (err < 0)
3030 return err;
3031
3032 return 0;
3033}
3034
3035static const struct tegra_sor_ops tegra_sor_dp_ops = {
3036 .name = "DP",
3037 .probe = tegra_sor_dp_probe,
3038};
3039
3040static int tegra_sor_init(struct host1x_client *client)
3041{
3042 struct drm_device *drm = dev_get_drvdata(client->host);
3043 const struct drm_encoder_helper_funcs *helpers = NULL;
3044 struct tegra_sor *sor = host1x_client_to_sor(client);
3045 int connector = DRM_MODE_CONNECTOR_Unknown;
3046 int encoder = DRM_MODE_ENCODER_NONE;
3047 int err;
3048
3049 if (!sor->aux) {
3050 if (sor->ops == &tegra_sor_hdmi_ops) {
3051 connector = DRM_MODE_CONNECTOR_HDMIA;
3052 encoder = DRM_MODE_ENCODER_TMDS;
3053 helpers = &tegra_sor_hdmi_helpers;
3054 } else if (sor->soc->supports_lvds) {
3055 connector = DRM_MODE_CONNECTOR_LVDS;
3056 encoder = DRM_MODE_ENCODER_LVDS;
3057 }
3058 } else {
3059 if (sor->output.panel) {
3060 connector = DRM_MODE_CONNECTOR_eDP;
3061 encoder = DRM_MODE_ENCODER_TMDS;
3062 helpers = &tegra_sor_dp_helpers;
3063 } else {
3064 connector = DRM_MODE_CONNECTOR_DisplayPort;
3065 encoder = DRM_MODE_ENCODER_TMDS;
3066 helpers = &tegra_sor_dp_helpers;
3067 }
3068
3069 sor->link.ops = &tegra_sor_dp_link_ops;
3070 sor->link.aux = sor->aux;
3071 }
3072
3073 sor->output.dev = sor->dev;
3074
3075 drm_connector_init_with_ddc(drm, &sor->output.connector,
3076 &tegra_sor_connector_funcs,
3077 connector,
3078 sor->output.ddc);
3079 drm_connector_helper_add(&sor->output.connector,
3080 &tegra_sor_connector_helper_funcs);
3081 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3082
3083 drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3084 drm_encoder_helper_add(&sor->output.encoder, helpers);
3085
3086 drm_connector_attach_encoder(&sor->output.connector,
3087 &sor->output.encoder);
3088 drm_connector_register(&sor->output.connector);
3089
3090 err = tegra_output_init(drm, &sor->output);
3091 if (err < 0) {
3092 dev_err(client->dev, "failed to initialize output: %d\n", err);
3093 return err;
3094 }
3095
3096 tegra_output_find_possible_crtcs(&sor->output, drm);
3097
3098 if (sor->aux) {
3099 err = drm_dp_aux_attach(sor->aux, &sor->output);
3100 if (err < 0) {
3101 dev_err(sor->dev, "failed to attach DP: %d\n", err);
3102 return err;
3103 }
3104 }
3105
3106 /*
3107 * XXX: Remove this reset once proper hand-over from firmware to
3108 * kernel is possible.
3109 */
3110 if (sor->rst) {
3111 err = pm_runtime_resume_and_get(sor->dev);
3112 if (err < 0) {
3113 dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3114 return err;
3115 }
3116
3117 err = reset_control_acquire(sor->rst);
3118 if (err < 0) {
3119 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3120 err);
3121 goto rpm_put;
3122 }
3123
3124 err = reset_control_assert(sor->rst);
3125 if (err < 0) {
3126 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3127 err);
3128 goto rpm_put;
3129 }
3130 }
3131
3132 err = clk_prepare_enable(sor->clk);
3133 if (err < 0) {
3134 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3135 goto rpm_put;
3136 }
3137
3138 usleep_range(1000, 3000);
3139
3140 if (sor->rst) {
3141 err = reset_control_deassert(sor->rst);
3142 if (err < 0) {
3143 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3144 err);
3145 clk_disable_unprepare(sor->clk);
3146 goto rpm_put;
3147 }
3148
3149 reset_control_release(sor->rst);
3150 pm_runtime_put(sor->dev);
3151 }
3152
3153 err = clk_prepare_enable(sor->clk_safe);
3154 if (err < 0) {
3155 clk_disable_unprepare(sor->clk);
3156 return err;
3157 }
3158
3159 err = clk_prepare_enable(sor->clk_dp);
3160 if (err < 0) {
3161 clk_disable_unprepare(sor->clk_safe);
3162 clk_disable_unprepare(sor->clk);
3163 return err;
3164 }
3165
3166 return 0;
3167
3168rpm_put:
3169 if (sor->rst)
3170 pm_runtime_put(sor->dev);
3171
3172 return err;
3173}
3174
3175static int tegra_sor_exit(struct host1x_client *client)
3176{
3177 struct tegra_sor *sor = host1x_client_to_sor(client);
3178 int err;
3179
3180 tegra_output_exit(&sor->output);
3181
3182 if (sor->aux) {
3183 err = drm_dp_aux_detach(sor->aux);
3184 if (err < 0) {
3185 dev_err(sor->dev, "failed to detach DP: %d\n", err);
3186 return err;
3187 }
3188 }
3189
3190 clk_disable_unprepare(sor->clk_safe);
3191 clk_disable_unprepare(sor->clk_dp);
3192 clk_disable_unprepare(sor->clk);
3193
3194 return 0;
3195}
3196
3197static int tegra_sor_runtime_suspend(struct host1x_client *client)
3198{
3199 struct tegra_sor *sor = host1x_client_to_sor(client);
3200 struct device *dev = client->dev;
3201 int err;
3202
3203 if (sor->rst) {
3204 err = reset_control_assert(sor->rst);
3205 if (err < 0) {
3206 dev_err(dev, "failed to assert reset: %d\n", err);
3207 return err;
3208 }
3209
3210 reset_control_release(sor->rst);
3211 }
3212
3213 usleep_range(1000, 2000);
3214
3215 clk_disable_unprepare(sor->clk);
3216 pm_runtime_put_sync(dev);
3217
3218 return 0;
3219}
3220
3221static int tegra_sor_runtime_resume(struct host1x_client *client)
3222{
3223 struct tegra_sor *sor = host1x_client_to_sor(client);
3224 struct device *dev = client->dev;
3225 int err;
3226
3227 err = pm_runtime_resume_and_get(dev);
3228 if (err < 0) {
3229 dev_err(dev, "failed to get runtime PM: %d\n", err);
3230 return err;
3231 }
3232
3233 err = clk_prepare_enable(sor->clk);
3234 if (err < 0) {
3235 dev_err(dev, "failed to enable clock: %d\n", err);
3236 goto put_rpm;
3237 }
3238
3239 usleep_range(1000, 2000);
3240
3241 if (sor->rst) {
3242 err = reset_control_acquire(sor->rst);
3243 if (err < 0) {
3244 dev_err(dev, "failed to acquire reset: %d\n", err);
3245 goto disable_clk;
3246 }
3247
3248 err = reset_control_deassert(sor->rst);
3249 if (err < 0) {
3250 dev_err(dev, "failed to deassert reset: %d\n", err);
3251 goto release_reset;
3252 }
3253 }
3254
3255 return 0;
3256
3257release_reset:
3258 reset_control_release(sor->rst);
3259disable_clk:
3260 clk_disable_unprepare(sor->clk);
3261put_rpm:
3262 pm_runtime_put_sync(dev);
3263 return err;
3264}
3265
3266static const struct host1x_client_ops sor_client_ops = {
3267 .init = tegra_sor_init,
3268 .exit = tegra_sor_exit,
3269 .suspend = tegra_sor_runtime_suspend,
3270 .resume = tegra_sor_runtime_resume,
3271};
3272
3273static const u8 tegra124_sor_xbar_cfg[5] = {
3274 0, 1, 2, 3, 4
3275};
3276
3277static const struct tegra_sor_regs tegra124_sor_regs = {
3278 .head_state0 = 0x05,
3279 .head_state1 = 0x07,
3280 .head_state2 = 0x09,
3281 .head_state3 = 0x0b,
3282 .head_state4 = 0x0d,
3283 .head_state5 = 0x0f,
3284 .pll0 = 0x17,
3285 .pll1 = 0x18,
3286 .pll2 = 0x19,
3287 .pll3 = 0x1a,
3288 .dp_padctl0 = 0x5c,
3289 .dp_padctl2 = 0x73,
3290};
3291
3292/* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3293static const u8 tegra124_sor_lane_map[4] = {
3294 2, 1, 0, 3,
3295};
3296
3297static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3298 {
3299 { 0x13, 0x19, 0x1e, 0x28 },
3300 { 0x1e, 0x25, 0x2d, },
3301 { 0x28, 0x32, },
3302 { 0x3c, },
3303 }, {
3304 { 0x12, 0x17, 0x1b, 0x25 },
3305 { 0x1c, 0x23, 0x2a, },
3306 { 0x25, 0x2f, },
3307 { 0x39, }
3308 }, {
3309 { 0x12, 0x16, 0x1a, 0x22 },
3310 { 0x1b, 0x20, 0x27, },
3311 { 0x24, 0x2d, },
3312 { 0x36, },
3313 }, {
3314 { 0x11, 0x14, 0x17, 0x1f },
3315 { 0x19, 0x1e, 0x24, },
3316 { 0x22, 0x2a, },
3317 { 0x32, },
3318 },
3319};
3320
3321static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3322 {
3323 { 0x00, 0x09, 0x13, 0x25 },
3324 { 0x00, 0x0f, 0x1e, },
3325 { 0x00, 0x14, },
3326 { 0x00, },
3327 }, {
3328 { 0x00, 0x0a, 0x14, 0x28 },
3329 { 0x00, 0x0f, 0x1e, },
3330 { 0x00, 0x14, },
3331 { 0x00 },
3332 }, {
3333 { 0x00, 0x0a, 0x14, 0x28 },
3334 { 0x00, 0x0f, 0x1e, },
3335 { 0x00, 0x14, },
3336 { 0x00, },
3337 }, {
3338 { 0x00, 0x0a, 0x14, 0x28 },
3339 { 0x00, 0x0f, 0x1e, },
3340 { 0x00, 0x14, },
3341 { 0x00, },
3342 },
3343};
3344
3345static const u8 tegra124_sor_post_cursor[4][4][4] = {
3346 {
3347 { 0x00, 0x00, 0x00, 0x00 },
3348 { 0x00, 0x00, 0x00, },
3349 { 0x00, 0x00, },
3350 { 0x00, },
3351 }, {
3352 { 0x02, 0x02, 0x04, 0x05 },
3353 { 0x02, 0x04, 0x05, },
3354 { 0x04, 0x05, },
3355 { 0x05, },
3356 }, {
3357 { 0x04, 0x05, 0x08, 0x0b },
3358 { 0x05, 0x09, 0x0b, },
3359 { 0x08, 0x0a, },
3360 { 0x0b, },
3361 }, {
3362 { 0x05, 0x09, 0x0b, 0x12 },
3363 { 0x09, 0x0d, 0x12, },
3364 { 0x0b, 0x0f, },
3365 { 0x12, },
3366 },
3367};
3368
3369static const u8 tegra124_sor_tx_pu[4][4][4] = {
3370 {
3371 { 0x20, 0x30, 0x40, 0x60 },
3372 { 0x30, 0x40, 0x60, },
3373 { 0x40, 0x60, },
3374 { 0x60, },
3375 }, {
3376 { 0x20, 0x20, 0x30, 0x50 },
3377 { 0x30, 0x40, 0x50, },
3378 { 0x40, 0x50, },
3379 { 0x60, },
3380 }, {
3381 { 0x20, 0x20, 0x30, 0x40, },
3382 { 0x30, 0x30, 0x40, },
3383 { 0x40, 0x50, },
3384 { 0x60, },
3385 }, {
3386 { 0x20, 0x20, 0x20, 0x40, },
3387 { 0x30, 0x30, 0x40, },
3388 { 0x40, 0x40, },
3389 { 0x60, },
3390 },
3391};
3392
3393static const struct tegra_sor_soc tegra124_sor = {
3394 .supports_lvds = true,
3395 .supports_hdmi = false,
3396 .supports_dp = true,
3397 .supports_audio = false,
3398 .supports_hdcp = false,
3399 .regs = &tegra124_sor_regs,
3400 .has_nvdisplay = false,
3401 .xbar_cfg = tegra124_sor_xbar_cfg,
3402 .lane_map = tegra124_sor_lane_map,
3403 .voltage_swing = tegra124_sor_voltage_swing,
3404 .pre_emphasis = tegra124_sor_pre_emphasis,
3405 .post_cursor = tegra124_sor_post_cursor,
3406 .tx_pu = tegra124_sor_tx_pu,
3407};
3408
3409static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3410 {
3411 { 0x00, 0x08, 0x12, 0x24 },
3412 { 0x01, 0x0e, 0x1d, },
3413 { 0x01, 0x13, },
3414 { 0x00, },
3415 }, {
3416 { 0x00, 0x08, 0x12, 0x24 },
3417 { 0x00, 0x0e, 0x1d, },
3418 { 0x00, 0x13, },
3419 { 0x00 },
3420 }, {
3421 { 0x00, 0x08, 0x12, 0x24 },
3422 { 0x00, 0x0e, 0x1d, },
3423 { 0x00, 0x13, },
3424 { 0x00, },
3425 }, {
3426 { 0x00, 0x08, 0x12, 0x24 },
3427 { 0x00, 0x0e, 0x1d, },
3428 { 0x00, 0x13, },
3429 { 0x00, },
3430 },
3431};
3432
3433static const struct tegra_sor_soc tegra132_sor = {
3434 .supports_lvds = true,
3435 .supports_hdmi = false,
3436 .supports_dp = true,
3437 .supports_audio = false,
3438 .supports_hdcp = false,
3439 .regs = &tegra124_sor_regs,
3440 .has_nvdisplay = false,
3441 .xbar_cfg = tegra124_sor_xbar_cfg,
3442 .lane_map = tegra124_sor_lane_map,
3443 .voltage_swing = tegra124_sor_voltage_swing,
3444 .pre_emphasis = tegra132_sor_pre_emphasis,
3445 .post_cursor = tegra124_sor_post_cursor,
3446 .tx_pu = tegra124_sor_tx_pu,
3447};
3448
3449static const struct tegra_sor_regs tegra210_sor_regs = {
3450 .head_state0 = 0x05,
3451 .head_state1 = 0x07,
3452 .head_state2 = 0x09,
3453 .head_state3 = 0x0b,
3454 .head_state4 = 0x0d,
3455 .head_state5 = 0x0f,
3456 .pll0 = 0x17,
3457 .pll1 = 0x18,
3458 .pll2 = 0x19,
3459 .pll3 = 0x1a,
3460 .dp_padctl0 = 0x5c,
3461 .dp_padctl2 = 0x73,
3462};
3463
3464static const u8 tegra210_sor_xbar_cfg[5] = {
3465 2, 1, 0, 3, 4
3466};
3467
3468static const u8 tegra210_sor_lane_map[4] = {
3469 0, 1, 2, 3,
3470};
3471
3472static const struct tegra_sor_soc tegra210_sor = {
3473 .supports_lvds = false,
3474 .supports_hdmi = false,
3475 .supports_dp = true,
3476 .supports_audio = false,
3477 .supports_hdcp = false,
3478
3479 .regs = &tegra210_sor_regs,
3480 .has_nvdisplay = false,
3481
3482 .xbar_cfg = tegra210_sor_xbar_cfg,
3483 .lane_map = tegra210_sor_lane_map,
3484 .voltage_swing = tegra124_sor_voltage_swing,
3485 .pre_emphasis = tegra124_sor_pre_emphasis,
3486 .post_cursor = tegra124_sor_post_cursor,
3487 .tx_pu = tegra124_sor_tx_pu,
3488};
3489
3490static const struct tegra_sor_soc tegra210_sor1 = {
3491 .supports_lvds = false,
3492 .supports_hdmi = true,
3493 .supports_dp = true,
3494 .supports_audio = true,
3495 .supports_hdcp = true,
3496
3497 .regs = &tegra210_sor_regs,
3498 .has_nvdisplay = false,
3499
3500 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3501 .settings = tegra210_sor_hdmi_defaults,
3502 .xbar_cfg = tegra210_sor_xbar_cfg,
3503 .lane_map = tegra210_sor_lane_map,
3504 .voltage_swing = tegra124_sor_voltage_swing,
3505 .pre_emphasis = tegra124_sor_pre_emphasis,
3506 .post_cursor = tegra124_sor_post_cursor,
3507 .tx_pu = tegra124_sor_tx_pu,
3508};
3509
3510static const struct tegra_sor_regs tegra186_sor_regs = {
3511 .head_state0 = 0x151,
3512 .head_state1 = 0x154,
3513 .head_state2 = 0x157,
3514 .head_state3 = 0x15a,
3515 .head_state4 = 0x15d,
3516 .head_state5 = 0x160,
3517 .pll0 = 0x163,
3518 .pll1 = 0x164,
3519 .pll2 = 0x165,
3520 .pll3 = 0x166,
3521 .dp_padctl0 = 0x168,
3522 .dp_padctl2 = 0x16a,
3523};
3524
3525static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3526 {
3527 { 0x13, 0x19, 0x1e, 0x28 },
3528 { 0x1e, 0x25, 0x2d, },
3529 { 0x28, 0x32, },
3530 { 0x39, },
3531 }, {
3532 { 0x12, 0x16, 0x1b, 0x25 },
3533 { 0x1c, 0x23, 0x2a, },
3534 { 0x25, 0x2f, },
3535 { 0x37, }
3536 }, {
3537 { 0x12, 0x16, 0x1a, 0x22 },
3538 { 0x1b, 0x20, 0x27, },
3539 { 0x24, 0x2d, },
3540 { 0x35, },
3541 }, {
3542 { 0x11, 0x14, 0x17, 0x1f },
3543 { 0x19, 0x1e, 0x24, },
3544 { 0x22, 0x2a, },
3545 { 0x32, },
3546 },
3547};
3548
3549static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3550 {
3551 { 0x00, 0x08, 0x12, 0x24 },
3552 { 0x01, 0x0e, 0x1d, },
3553 { 0x01, 0x13, },
3554 { 0x00, },
3555 }, {
3556 { 0x00, 0x08, 0x12, 0x24 },
3557 { 0x00, 0x0e, 0x1d, },
3558 { 0x00, 0x13, },
3559 { 0x00 },
3560 }, {
3561 { 0x00, 0x08, 0x14, 0x24 },
3562 { 0x00, 0x0e, 0x1d, },
3563 { 0x00, 0x13, },
3564 { 0x00, },
3565 }, {
3566 { 0x00, 0x08, 0x12, 0x24 },
3567 { 0x00, 0x0e, 0x1d, },
3568 { 0x00, 0x13, },
3569 { 0x00, },
3570 },
3571};
3572
3573static const struct tegra_sor_soc tegra186_sor = {
3574 .supports_lvds = false,
3575 .supports_hdmi = true,
3576 .supports_dp = true,
3577 .supports_audio = true,
3578 .supports_hdcp = true,
3579
3580 .regs = &tegra186_sor_regs,
3581 .has_nvdisplay = true,
3582
3583 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3584 .settings = tegra186_sor_hdmi_defaults,
3585 .xbar_cfg = tegra124_sor_xbar_cfg,
3586 .lane_map = tegra124_sor_lane_map,
3587 .voltage_swing = tegra186_sor_voltage_swing,
3588 .pre_emphasis = tegra186_sor_pre_emphasis,
3589 .post_cursor = tegra124_sor_post_cursor,
3590 .tx_pu = tegra124_sor_tx_pu,
3591};
3592
3593static const struct tegra_sor_regs tegra194_sor_regs = {
3594 .head_state0 = 0x151,
3595 .head_state1 = 0x155,
3596 .head_state2 = 0x159,
3597 .head_state3 = 0x15d,
3598 .head_state4 = 0x161,
3599 .head_state5 = 0x165,
3600 .pll0 = 0x169,
3601 .pll1 = 0x16a,
3602 .pll2 = 0x16b,
3603 .pll3 = 0x16c,
3604 .dp_padctl0 = 0x16e,
3605 .dp_padctl2 = 0x16f,
3606};
3607
3608static const struct tegra_sor_soc tegra194_sor = {
3609 .supports_lvds = false,
3610 .supports_hdmi = true,
3611 .supports_dp = true,
3612 .supports_audio = true,
3613 .supports_hdcp = true,
3614
3615 .regs = &tegra194_sor_regs,
3616 .has_nvdisplay = true,
3617
3618 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3619 .settings = tegra194_sor_hdmi_defaults,
3620
3621 .xbar_cfg = tegra210_sor_xbar_cfg,
3622 .lane_map = tegra124_sor_lane_map,
3623 .voltage_swing = tegra186_sor_voltage_swing,
3624 .pre_emphasis = tegra186_sor_pre_emphasis,
3625 .post_cursor = tegra124_sor_post_cursor,
3626 .tx_pu = tegra124_sor_tx_pu,
3627};
3628
3629static const struct of_device_id tegra_sor_of_match[] = {
3630 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3631 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3632 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3633 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3634 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3635 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3636 { },
3637};
3638MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3639
3640static int tegra_sor_parse_dt(struct tegra_sor *sor)
3641{
3642 struct device_node *np = sor->dev->of_node;
3643 u32 xbar_cfg[5];
3644 unsigned int i;
3645 u32 value;
3646 int err;
3647
3648 if (sor->soc->has_nvdisplay) {
3649 err = of_property_read_u32(np, "nvidia,interface", &value);
3650 if (err < 0)
3651 return err;
3652
3653 sor->index = value;
3654
3655 /*
3656 * override the default that we already set for Tegra210 and
3657 * earlier
3658 */
3659 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3660 } else {
3661 if (!sor->soc->supports_audio)
3662 sor->index = 0;
3663 else
3664 sor->index = 1;
3665 }
3666
3667 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3668 if (err < 0) {
3669 /* fall back to default per-SoC XBAR configuration */
3670 for (i = 0; i < 5; i++)
3671 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3672 } else {
3673 /* copy cells to SOR XBAR configuration */
3674 for (i = 0; i < 5; i++)
3675 sor->xbar_cfg[i] = xbar_cfg[i];
3676 }
3677
3678 return 0;
3679}
3680
3681static irqreturn_t tegra_sor_irq(int irq, void *data)
3682{
3683 struct tegra_sor *sor = data;
3684 u32 value;
3685
3686 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3687 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3688
3689 if (value & SOR_INT_CODEC_SCRATCH0) {
3690 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3691
3692 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3693 unsigned int format;
3694
3695 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3696
3697 tegra_hda_parse_format(format, &sor->format);
3698
3699 if (sor->ops->audio_enable)
3700 sor->ops->audio_enable(sor);
3701 } else {
3702 if (sor->ops->audio_disable)
3703 sor->ops->audio_disable(sor);
3704 }
3705 }
3706
3707 return IRQ_HANDLED;
3708}
3709
3710static int tegra_sor_probe(struct platform_device *pdev)
3711{
3712 struct device_node *np;
3713 struct tegra_sor *sor;
3714 int err;
3715
3716 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3717 if (!sor)
3718 return -ENOMEM;
3719
3720 sor->soc = of_device_get_match_data(&pdev->dev);
3721 sor->output.dev = sor->dev = &pdev->dev;
3722
3723 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3724 sor->soc->num_settings *
3725 sizeof(*sor->settings),
3726 GFP_KERNEL);
3727 if (!sor->settings)
3728 return -ENOMEM;
3729
3730 sor->num_settings = sor->soc->num_settings;
3731
3732 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3733 if (np) {
3734 sor->aux = drm_dp_aux_find_by_of_node(np);
3735 of_node_put(np);
3736
3737 if (!sor->aux)
3738 return -EPROBE_DEFER;
3739
3740 if (get_device(sor->aux->dev))
3741 sor->output.ddc = &sor->aux->ddc;
3742 }
3743
3744 if (!sor->aux) {
3745 if (sor->soc->supports_hdmi) {
3746 sor->ops = &tegra_sor_hdmi_ops;
3747 sor->pad = TEGRA_IO_PAD_HDMI;
3748 } else if (sor->soc->supports_lvds) {
3749 dev_err(&pdev->dev, "LVDS not supported yet\n");
3750 return -ENODEV;
3751 } else {
3752 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3753 return -ENODEV;
3754 }
3755 } else {
3756 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3757 /*
3758 * No need to keep this around since we only use it as a check
3759 * to see if a panel is connected (eDP) or not (DP).
3760 */
3761 of_node_put(np);
3762
3763 sor->ops = &tegra_sor_dp_ops;
3764 sor->pad = TEGRA_IO_PAD_LVDS;
3765 }
3766
3767 err = tegra_sor_parse_dt(sor);
3768 if (err < 0)
3769 goto put_aux;
3770
3771 err = tegra_output_probe(&sor->output);
3772 if (err < 0) {
3773 dev_err_probe(&pdev->dev, err, "failed to probe output\n");
3774 goto put_aux;
3775 }
3776
3777 if (sor->ops && sor->ops->probe) {
3778 err = sor->ops->probe(sor);
3779 if (err < 0) {
3780 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3781 sor->ops->name, err);
3782 goto remove;
3783 }
3784 }
3785
3786 sor->regs = devm_platform_ioremap_resource(pdev, 0);
3787 if (IS_ERR(sor->regs)) {
3788 err = PTR_ERR(sor->regs);
3789 goto remove;
3790 }
3791
3792 err = platform_get_irq(pdev, 0);
3793 if (err < 0)
3794 goto remove;
3795
3796 sor->irq = err;
3797
3798 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3799 dev_name(sor->dev), sor);
3800 if (err < 0) {
3801 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3802 goto remove;
3803 }
3804
3805 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3806 if (IS_ERR(sor->rst)) {
3807 err = PTR_ERR(sor->rst);
3808
3809 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3810 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3811 err);
3812 goto remove;
3813 }
3814
3815 /*
3816 * At this point, the reset control is most likely being used
3817 * by the generic power domain implementation. With any luck
3818 * the power domain will have taken care of resetting the SOR
3819 * and we don't have to do anything.
3820 */
3821 sor->rst = NULL;
3822 }
3823
3824 sor->clk = devm_clk_get(&pdev->dev, NULL);
3825 if (IS_ERR(sor->clk)) {
3826 err = PTR_ERR(sor->clk);
3827 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3828 goto remove;
3829 }
3830
3831 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3832 struct device_node *np = pdev->dev.of_node;
3833 const char *name;
3834
3835 /*
3836 * For backwards compatibility with Tegra210 device trees,
3837 * fall back to the old clock name "source" if the new "out"
3838 * clock is not available.
3839 */
3840 if (of_property_match_string(np, "clock-names", "out") < 0)
3841 name = "source";
3842 else
3843 name = "out";
3844
3845 sor->clk_out = devm_clk_get(&pdev->dev, name);
3846 if (IS_ERR(sor->clk_out)) {
3847 err = PTR_ERR(sor->clk_out);
3848 dev_err(sor->dev, "failed to get %s clock: %d\n",
3849 name, err);
3850 goto remove;
3851 }
3852 } else {
3853 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3854 sor->clk_out = sor->clk;
3855 }
3856
3857 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3858 if (IS_ERR(sor->clk_parent)) {
3859 err = PTR_ERR(sor->clk_parent);
3860 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3861 goto remove;
3862 }
3863
3864 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3865 if (IS_ERR(sor->clk_safe)) {
3866 err = PTR_ERR(sor->clk_safe);
3867 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3868 goto remove;
3869 }
3870
3871 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3872 if (IS_ERR(sor->clk_dp)) {
3873 err = PTR_ERR(sor->clk_dp);
3874 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3875 goto remove;
3876 }
3877
3878 /*
3879 * Starting with Tegra186, the BPMP provides an implementation for
3880 * the pad output clock, so we have to look it up from device tree.
3881 */
3882 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3883 if (IS_ERR(sor->clk_pad)) {
3884 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3885 err = PTR_ERR(sor->clk_pad);
3886 goto remove;
3887 }
3888
3889 /*
3890 * If the pad output clock is not available, then we assume
3891 * we're on Tegra210 or earlier and have to provide our own
3892 * implementation.
3893 */
3894 sor->clk_pad = NULL;
3895 }
3896
3897 /*
3898 * The bootloader may have set up the SOR such that it's module clock
3899 * is sourced by one of the display PLLs. However, that doesn't work
3900 * without properly having set up other bits of the SOR.
3901 */
3902 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3903 if (err < 0) {
3904 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3905 goto remove;
3906 }
3907
3908 platform_set_drvdata(pdev, sor);
3909 pm_runtime_enable(&pdev->dev);
3910
3911 host1x_client_init(&sor->client);
3912 sor->client.ops = &sor_client_ops;
3913 sor->client.dev = &pdev->dev;
3914
3915 /*
3916 * On Tegra210 and earlier, provide our own implementation for the
3917 * pad output clock.
3918 */
3919 if (!sor->clk_pad) {
3920 char *name;
3921
3922 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3923 sor->index);
3924 if (!name) {
3925 err = -ENOMEM;
3926 goto uninit;
3927 }
3928
3929 err = host1x_client_resume(&sor->client);
3930 if (err < 0) {
3931 dev_err(sor->dev, "failed to resume: %d\n", err);
3932 goto uninit;
3933 }
3934
3935 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3936 host1x_client_suspend(&sor->client);
3937 }
3938
3939 if (IS_ERR(sor->clk_pad)) {
3940 err = PTR_ERR(sor->clk_pad);
3941 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3942 err);
3943 goto uninit;
3944 }
3945
3946 err = __host1x_client_register(&sor->client);
3947 if (err < 0) {
3948 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3949 err);
3950 goto uninit;
3951 }
3952
3953 return 0;
3954
3955uninit:
3956 host1x_client_exit(&sor->client);
3957 pm_runtime_disable(&pdev->dev);
3958remove:
3959 if (sor->aux)
3960 sor->output.ddc = NULL;
3961
3962 tegra_output_remove(&sor->output);
3963put_aux:
3964 if (sor->aux)
3965 put_device(sor->aux->dev);
3966
3967 return err;
3968}
3969
3970static void tegra_sor_remove(struct platform_device *pdev)
3971{
3972 struct tegra_sor *sor = platform_get_drvdata(pdev);
3973
3974 host1x_client_unregister(&sor->client);
3975
3976 pm_runtime_disable(&pdev->dev);
3977
3978 if (sor->aux) {
3979 put_device(sor->aux->dev);
3980 sor->output.ddc = NULL;
3981 }
3982
3983 tegra_output_remove(&sor->output);
3984}
3985
3986static int __maybe_unused tegra_sor_suspend(struct device *dev)
3987{
3988 struct tegra_sor *sor = dev_get_drvdata(dev);
3989 int err;
3990
3991 err = tegra_output_suspend(&sor->output);
3992 if (err < 0) {
3993 dev_err(dev, "failed to suspend output: %d\n", err);
3994 return err;
3995 }
3996
3997 if (sor->hdmi_supply) {
3998 err = regulator_disable(sor->hdmi_supply);
3999 if (err < 0) {
4000 tegra_output_resume(&sor->output);
4001 return err;
4002 }
4003 }
4004
4005 return 0;
4006}
4007
4008static int __maybe_unused tegra_sor_resume(struct device *dev)
4009{
4010 struct tegra_sor *sor = dev_get_drvdata(dev);
4011 int err;
4012
4013 if (sor->hdmi_supply) {
4014 err = regulator_enable(sor->hdmi_supply);
4015 if (err < 0)
4016 return err;
4017 }
4018
4019 err = tegra_output_resume(&sor->output);
4020 if (err < 0) {
4021 dev_err(dev, "failed to resume output: %d\n", err);
4022
4023 if (sor->hdmi_supply)
4024 regulator_disable(sor->hdmi_supply);
4025
4026 return err;
4027 }
4028
4029 return 0;
4030}
4031
4032static const struct dev_pm_ops tegra_sor_pm_ops = {
4033 SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4034};
4035
4036struct platform_driver tegra_sor_driver = {
4037 .driver = {
4038 .name = "tegra-sor",
4039 .of_match_table = tegra_sor_of_match,
4040 .pm = &tegra_sor_pm_ops,
4041 },
4042 .probe = tegra_sor_probe,
4043 .remove = tegra_sor_remove,
4044};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/debugfs.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/regulator/consumer.h>
15#include <linux/reset.h>
16
17#include <soc/tegra/pmc.h>
18
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_debugfs.h>
21#include <drm/drm_dp_helper.h>
22#include <drm/drm_file.h>
23#include <drm/drm_panel.h>
24#include <drm/drm_scdc_helper.h>
25#include <drm/drm_simple_kms_helper.h>
26
27#include "dc.h"
28#include "dp.h"
29#include "drm.h"
30#include "hda.h"
31#include "sor.h"
32#include "trace.h"
33
34#define SOR_REKEY 0x38
35
36struct tegra_sor_hdmi_settings {
37 unsigned long frequency;
38
39 u8 vcocap;
40 u8 filter;
41 u8 ichpmp;
42 u8 loadadj;
43 u8 tmds_termadj;
44 u8 tx_pu_value;
45 u8 bg_temp_coef;
46 u8 bg_vref_level;
47 u8 avdd10_level;
48 u8 avdd14_level;
49 u8 sparepll;
50
51 u8 drive_current[4];
52 u8 preemphasis[4];
53};
54
55#if 1
56static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
57 {
58 .frequency = 54000000,
59 .vcocap = 0x0,
60 .filter = 0x0,
61 .ichpmp = 0x1,
62 .loadadj = 0x3,
63 .tmds_termadj = 0x9,
64 .tx_pu_value = 0x10,
65 .bg_temp_coef = 0x3,
66 .bg_vref_level = 0x8,
67 .avdd10_level = 0x4,
68 .avdd14_level = 0x4,
69 .sparepll = 0x0,
70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
72 }, {
73 .frequency = 75000000,
74 .vcocap = 0x3,
75 .filter = 0x0,
76 .ichpmp = 0x1,
77 .loadadj = 0x3,
78 .tmds_termadj = 0x9,
79 .tx_pu_value = 0x40,
80 .bg_temp_coef = 0x3,
81 .bg_vref_level = 0x8,
82 .avdd10_level = 0x4,
83 .avdd14_level = 0x4,
84 .sparepll = 0x0,
85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
87 }, {
88 .frequency = 150000000,
89 .vcocap = 0x3,
90 .filter = 0x0,
91 .ichpmp = 0x1,
92 .loadadj = 0x3,
93 .tmds_termadj = 0x9,
94 .tx_pu_value = 0x66,
95 .bg_temp_coef = 0x3,
96 .bg_vref_level = 0x8,
97 .avdd10_level = 0x4,
98 .avdd14_level = 0x4,
99 .sparepll = 0x0,
100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
102 }, {
103 .frequency = 300000000,
104 .vcocap = 0x3,
105 .filter = 0x0,
106 .ichpmp = 0x1,
107 .loadadj = 0x3,
108 .tmds_termadj = 0x9,
109 .tx_pu_value = 0x66,
110 .bg_temp_coef = 0x3,
111 .bg_vref_level = 0xa,
112 .avdd10_level = 0x4,
113 .avdd14_level = 0x4,
114 .sparepll = 0x0,
115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
117 }, {
118 .frequency = 600000000,
119 .vcocap = 0x3,
120 .filter = 0x0,
121 .ichpmp = 0x1,
122 .loadadj = 0x3,
123 .tmds_termadj = 0x9,
124 .tx_pu_value = 0x66,
125 .bg_temp_coef = 0x3,
126 .bg_vref_level = 0x8,
127 .avdd10_level = 0x4,
128 .avdd14_level = 0x4,
129 .sparepll = 0x0,
130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
132 },
133};
134#else
135static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
136 {
137 .frequency = 75000000,
138 .vcocap = 0x3,
139 .filter = 0x0,
140 .ichpmp = 0x1,
141 .loadadj = 0x3,
142 .tmds_termadj = 0x9,
143 .tx_pu_value = 0x40,
144 .bg_temp_coef = 0x3,
145 .bg_vref_level = 0x8,
146 .avdd10_level = 0x4,
147 .avdd14_level = 0x4,
148 .sparepll = 0x0,
149 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
151 }, {
152 .frequency = 150000000,
153 .vcocap = 0x3,
154 .filter = 0x0,
155 .ichpmp = 0x1,
156 .loadadj = 0x3,
157 .tmds_termadj = 0x9,
158 .tx_pu_value = 0x66,
159 .bg_temp_coef = 0x3,
160 .bg_vref_level = 0x8,
161 .avdd10_level = 0x4,
162 .avdd14_level = 0x4,
163 .sparepll = 0x0,
164 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
166 }, {
167 .frequency = 300000000,
168 .vcocap = 0x3,
169 .filter = 0x0,
170 .ichpmp = 0x6,
171 .loadadj = 0x3,
172 .tmds_termadj = 0x9,
173 .tx_pu_value = 0x66,
174 .bg_temp_coef = 0x3,
175 .bg_vref_level = 0xf,
176 .avdd10_level = 0x4,
177 .avdd14_level = 0x4,
178 .sparepll = 0x0,
179 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
181 }, {
182 .frequency = 600000000,
183 .vcocap = 0x3,
184 .filter = 0x0,
185 .ichpmp = 0xa,
186 .loadadj = 0x3,
187 .tmds_termadj = 0xb,
188 .tx_pu_value = 0x66,
189 .bg_temp_coef = 0x3,
190 .bg_vref_level = 0xe,
191 .avdd10_level = 0x4,
192 .avdd14_level = 0x4,
193 .sparepll = 0x0,
194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
196 },
197};
198#endif
199
200static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
201 {
202 .frequency = 54000000,
203 .vcocap = 0,
204 .filter = 5,
205 .ichpmp = 5,
206 .loadadj = 3,
207 .tmds_termadj = 0xf,
208 .tx_pu_value = 0,
209 .bg_temp_coef = 3,
210 .bg_vref_level = 8,
211 .avdd10_level = 4,
212 .avdd14_level = 4,
213 .sparepll = 0x54,
214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
216 }, {
217 .frequency = 75000000,
218 .vcocap = 1,
219 .filter = 5,
220 .ichpmp = 5,
221 .loadadj = 3,
222 .tmds_termadj = 0xf,
223 .tx_pu_value = 0,
224 .bg_temp_coef = 3,
225 .bg_vref_level = 8,
226 .avdd10_level = 4,
227 .avdd14_level = 4,
228 .sparepll = 0x44,
229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
231 }, {
232 .frequency = 150000000,
233 .vcocap = 3,
234 .filter = 5,
235 .ichpmp = 5,
236 .loadadj = 3,
237 .tmds_termadj = 15,
238 .tx_pu_value = 0x66 /* 0 */,
239 .bg_temp_coef = 3,
240 .bg_vref_level = 8,
241 .avdd10_level = 4,
242 .avdd14_level = 4,
243 .sparepll = 0x00, /* 0x34 */
244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
246 }, {
247 .frequency = 300000000,
248 .vcocap = 3,
249 .filter = 5,
250 .ichpmp = 5,
251 .loadadj = 3,
252 .tmds_termadj = 15,
253 .tx_pu_value = 64,
254 .bg_temp_coef = 3,
255 .bg_vref_level = 8,
256 .avdd10_level = 4,
257 .avdd14_level = 4,
258 .sparepll = 0x34,
259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
261 }, {
262 .frequency = 600000000,
263 .vcocap = 3,
264 .filter = 5,
265 .ichpmp = 5,
266 .loadadj = 3,
267 .tmds_termadj = 12,
268 .tx_pu_value = 96,
269 .bg_temp_coef = 3,
270 .bg_vref_level = 8,
271 .avdd10_level = 4,
272 .avdd14_level = 4,
273 .sparepll = 0x34,
274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
276 }
277};
278
279static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
280 {
281 .frequency = 54000000,
282 .vcocap = 0,
283 .filter = 5,
284 .ichpmp = 5,
285 .loadadj = 3,
286 .tmds_termadj = 0xf,
287 .tx_pu_value = 0,
288 .bg_temp_coef = 3,
289 .bg_vref_level = 8,
290 .avdd10_level = 4,
291 .avdd14_level = 4,
292 .sparepll = 0x54,
293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
295 }, {
296 .frequency = 75000000,
297 .vcocap = 1,
298 .filter = 5,
299 .ichpmp = 5,
300 .loadadj = 3,
301 .tmds_termadj = 0xf,
302 .tx_pu_value = 0,
303 .bg_temp_coef = 3,
304 .bg_vref_level = 8,
305 .avdd10_level = 4,
306 .avdd14_level = 4,
307 .sparepll = 0x44,
308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
310 }, {
311 .frequency = 150000000,
312 .vcocap = 3,
313 .filter = 5,
314 .ichpmp = 5,
315 .loadadj = 3,
316 .tmds_termadj = 15,
317 .tx_pu_value = 0x66 /* 0 */,
318 .bg_temp_coef = 3,
319 .bg_vref_level = 8,
320 .avdd10_level = 4,
321 .avdd14_level = 4,
322 .sparepll = 0x00, /* 0x34 */
323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
325 }, {
326 .frequency = 300000000,
327 .vcocap = 3,
328 .filter = 5,
329 .ichpmp = 5,
330 .loadadj = 3,
331 .tmds_termadj = 15,
332 .tx_pu_value = 64,
333 .bg_temp_coef = 3,
334 .bg_vref_level = 8,
335 .avdd10_level = 4,
336 .avdd14_level = 4,
337 .sparepll = 0x34,
338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
340 }, {
341 .frequency = 600000000,
342 .vcocap = 3,
343 .filter = 5,
344 .ichpmp = 5,
345 .loadadj = 3,
346 .tmds_termadj = 12,
347 .tx_pu_value = 96,
348 .bg_temp_coef = 3,
349 .bg_vref_level = 8,
350 .avdd10_level = 4,
351 .avdd14_level = 4,
352 .sparepll = 0x34,
353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
355 }
356};
357
358struct tegra_sor_regs {
359 unsigned int head_state0;
360 unsigned int head_state1;
361 unsigned int head_state2;
362 unsigned int head_state3;
363 unsigned int head_state4;
364 unsigned int head_state5;
365 unsigned int pll0;
366 unsigned int pll1;
367 unsigned int pll2;
368 unsigned int pll3;
369 unsigned int dp_padctl0;
370 unsigned int dp_padctl2;
371};
372
373struct tegra_sor_soc {
374 bool supports_lvds;
375 bool supports_hdmi;
376 bool supports_dp;
377 bool supports_audio;
378 bool supports_hdcp;
379
380 const struct tegra_sor_regs *regs;
381 bool has_nvdisplay;
382
383 const struct tegra_sor_hdmi_settings *settings;
384 unsigned int num_settings;
385
386 const u8 *xbar_cfg;
387 const u8 *lane_map;
388
389 const u8 (*voltage_swing)[4][4];
390 const u8 (*pre_emphasis)[4][4];
391 const u8 (*post_cursor)[4][4];
392 const u8 (*tx_pu)[4][4];
393};
394
395struct tegra_sor;
396
397struct tegra_sor_ops {
398 const char *name;
399 int (*probe)(struct tegra_sor *sor);
400 void (*audio_enable)(struct tegra_sor *sor);
401 void (*audio_disable)(struct tegra_sor *sor);
402};
403
404struct tegra_sor {
405 struct host1x_client client;
406 struct tegra_output output;
407 struct device *dev;
408
409 const struct tegra_sor_soc *soc;
410 void __iomem *regs;
411 unsigned int index;
412 unsigned int irq;
413
414 struct reset_control *rst;
415 struct clk *clk_parent;
416 struct clk *clk_safe;
417 struct clk *clk_out;
418 struct clk *clk_pad;
419 struct clk *clk_dp;
420 struct clk *clk;
421
422 u8 xbar_cfg[5];
423
424 struct drm_dp_link link;
425 struct drm_dp_aux *aux;
426
427 struct drm_info_list *debugfs_files;
428
429 const struct tegra_sor_ops *ops;
430 enum tegra_io_pad pad;
431
432 /* for HDMI 2.0 */
433 struct tegra_sor_hdmi_settings *settings;
434 unsigned int num_settings;
435
436 struct regulator *avdd_io_supply;
437 struct regulator *vdd_pll_supply;
438 struct regulator *hdmi_supply;
439
440 struct delayed_work scdc;
441 bool scdc_enabled;
442
443 struct tegra_hda_format format;
444};
445
446struct tegra_sor_state {
447 struct drm_connector_state base;
448
449 unsigned int link_speed;
450 unsigned long pclk;
451 unsigned int bpc;
452};
453
454static inline struct tegra_sor_state *
455to_sor_state(struct drm_connector_state *state)
456{
457 return container_of(state, struct tegra_sor_state, base);
458}
459
460struct tegra_sor_config {
461 u32 bits_per_pixel;
462
463 u32 active_polarity;
464 u32 active_count;
465 u32 tu_size;
466 u32 active_frac;
467 u32 watermark;
468
469 u32 hblank_symbols;
470 u32 vblank_symbols;
471};
472
473static inline struct tegra_sor *
474host1x_client_to_sor(struct host1x_client *client)
475{
476 return container_of(client, struct tegra_sor, client);
477}
478
479static inline struct tegra_sor *to_sor(struct tegra_output *output)
480{
481 return container_of(output, struct tegra_sor, output);
482}
483
484static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
485{
486 u32 value = readl(sor->regs + (offset << 2));
487
488 trace_sor_readl(sor->dev, offset, value);
489
490 return value;
491}
492
493static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
494 unsigned int offset)
495{
496 trace_sor_writel(sor->dev, offset, value);
497 writel(value, sor->regs + (offset << 2));
498}
499
500static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
501{
502 int err;
503
504 clk_disable_unprepare(sor->clk);
505
506 err = clk_set_parent(sor->clk_out, parent);
507 if (err < 0)
508 return err;
509
510 err = clk_prepare_enable(sor->clk);
511 if (err < 0)
512 return err;
513
514 return 0;
515}
516
517struct tegra_clk_sor_pad {
518 struct clk_hw hw;
519 struct tegra_sor *sor;
520};
521
522static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
523{
524 return container_of(hw, struct tegra_clk_sor_pad, hw);
525}
526
527static const char * const tegra_clk_sor_pad_parents[2][2] = {
528 { "pll_d_out0", "pll_dp" },
529 { "pll_d2_out0", "pll_dp" },
530};
531
532/*
533 * Implementing ->set_parent() here isn't really required because the parent
534 * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
535 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
536 * Tegra186 and later SoC generations where the BPMP implements this clock
537 * and doesn't expose the mux via the common clock framework.
538 */
539
540static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
541{
542 struct tegra_clk_sor_pad *pad = to_pad(hw);
543 struct tegra_sor *sor = pad->sor;
544 u32 value;
545
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
548
549 switch (index) {
550 case 0:
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
552 break;
553
554 case 1:
555 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
556 break;
557 }
558
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
560
561 return 0;
562}
563
564static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
565{
566 struct tegra_clk_sor_pad *pad = to_pad(hw);
567 struct tegra_sor *sor = pad->sor;
568 u8 parent = U8_MAX;
569 u32 value;
570
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
572
573 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
574 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
575 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
576 parent = 0;
577 break;
578
579 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
580 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
581 parent = 1;
582 break;
583 }
584
585 return parent;
586}
587
588static const struct clk_ops tegra_clk_sor_pad_ops = {
589 .set_parent = tegra_clk_sor_pad_set_parent,
590 .get_parent = tegra_clk_sor_pad_get_parent,
591};
592
593static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
594 const char *name)
595{
596 struct tegra_clk_sor_pad *pad;
597 struct clk_init_data init;
598 struct clk *clk;
599
600 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
601 if (!pad)
602 return ERR_PTR(-ENOMEM);
603
604 pad->sor = sor;
605
606 init.name = name;
607 init.flags = 0;
608 init.parent_names = tegra_clk_sor_pad_parents[sor->index];
609 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
610 init.ops = &tegra_clk_sor_pad_ops;
611
612 pad->hw.init = &init;
613
614 clk = devm_clk_register(sor->dev, &pad->hw);
615
616 return clk;
617}
618
619static void tegra_sor_filter_rates(struct tegra_sor *sor)
620{
621 struct drm_dp_link *link = &sor->link;
622 unsigned int i;
623
624 /* Tegra only supports RBR, HBR and HBR2 */
625 for (i = 0; i < link->num_rates; i++) {
626 switch (link->rates[i]) {
627 case 1620000:
628 case 2700000:
629 case 5400000:
630 break;
631
632 default:
633 DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
634 link->rates[i]);
635 link->rates[i] = 0;
636 break;
637 }
638 }
639
640 drm_dp_link_update_rates(link);
641}
642
643static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
644{
645 unsigned long timeout;
646 u32 value;
647
648 /*
649 * Clear or set the PD_TXD bit corresponding to each lane, depending
650 * on whether it is used or not.
651 */
652 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
653
654 if (lanes <= 2)
655 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
656 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
657 else
658 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
660
661 if (lanes <= 1)
662 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
663 else
664 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
665
666 if (lanes == 0)
667 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
668 else
669 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
670
671 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
672
673 /* start lane sequencer */
674 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
675 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
676 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
677
678 timeout = jiffies + msecs_to_jiffies(250);
679
680 while (time_before(jiffies, timeout)) {
681 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
682 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
683 break;
684
685 usleep_range(250, 1000);
686 }
687
688 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
689 return -ETIMEDOUT;
690
691 return 0;
692}
693
694static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
695{
696 unsigned long timeout;
697 u32 value;
698
699 /* power down all lanes */
700 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
701 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
702 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
703 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
704
705 /* start lane sequencer */
706 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
707 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
708 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
709
710 timeout = jiffies + msecs_to_jiffies(250);
711
712 while (time_before(jiffies, timeout)) {
713 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
714 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
715 break;
716
717 usleep_range(25, 100);
718 }
719
720 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
721 return -ETIMEDOUT;
722
723 return 0;
724}
725
726static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
727{
728 u32 value;
729
730 /* pre-charge all used lanes */
731 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
732
733 if (lanes <= 2)
734 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
735 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
736 else
737 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
738 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
739
740 if (lanes <= 1)
741 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
742 else
743 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
744
745 if (lanes == 0)
746 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
747 else
748 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
749
750 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
751
752 usleep_range(15, 100);
753
754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
755 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
756 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
757 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
758}
759
760static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
761{
762 u32 mask = 0x08, adj = 0, value;
763
764 /* enable pad calibration logic */
765 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
766 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
767 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
768
769 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
770 value |= SOR_PLL1_TMDS_TERM;
771 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
772
773 while (mask) {
774 adj |= mask;
775
776 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
777 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
778 value |= SOR_PLL1_TMDS_TERMADJ(adj);
779 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
780
781 usleep_range(100, 200);
782
783 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
784 if (value & SOR_PLL1_TERM_COMPOUT)
785 adj &= ~mask;
786
787 mask >>= 1;
788 }
789
790 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
791 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
792 value |= SOR_PLL1_TMDS_TERMADJ(adj);
793 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
794
795 /* disable pad calibration logic */
796 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
797 value |= SOR_DP_PADCTL_PAD_CAL_PD;
798 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
799}
800
801static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
802{
803 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
804 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
805 const struct tegra_sor_soc *soc = sor->soc;
806 u32 pattern = 0, tx_pu = 0, value;
807 unsigned int i;
808
809 for (value = 0, i = 0; i < link->lanes; i++) {
810 u8 vs = link->train.request.voltage_swing[i];
811 u8 pe = link->train.request.pre_emphasis[i];
812 u8 pc = link->train.request.post_cursor[i];
813 u8 shift = sor->soc->lane_map[i] << 3;
814
815 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
816 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
817 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
818
819 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
820 tx_pu = sor->soc->tx_pu[pc][vs][pe];
821
822 switch (link->train.pattern) {
823 case DP_TRAINING_PATTERN_DISABLE:
824 value = SOR_DP_TPG_SCRAMBLER_GALIOS |
825 SOR_DP_TPG_PATTERN_NONE;
826 break;
827
828 case DP_TRAINING_PATTERN_1:
829 value = SOR_DP_TPG_SCRAMBLER_NONE |
830 SOR_DP_TPG_PATTERN_TRAIN1;
831 break;
832
833 case DP_TRAINING_PATTERN_2:
834 value = SOR_DP_TPG_SCRAMBLER_NONE |
835 SOR_DP_TPG_PATTERN_TRAIN2;
836 break;
837
838 case DP_TRAINING_PATTERN_3:
839 value = SOR_DP_TPG_SCRAMBLER_NONE |
840 SOR_DP_TPG_PATTERN_TRAIN3;
841 break;
842
843 default:
844 return -EINVAL;
845 }
846
847 if (link->caps.channel_coding)
848 value |= SOR_DP_TPG_CHANNEL_CODING;
849
850 pattern = pattern << 8 | value;
851 }
852
853 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
854 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
855
856 if (link->caps.tps3_supported)
857 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
858
859 tegra_sor_writel(sor, pattern, SOR_DP_TPG);
860
861 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
862 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
863 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
864 value |= SOR_DP_PADCTL_TX_PU(tx_pu);
865 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
866
867 usleep_range(20, 100);
868
869 return 0;
870}
871
872static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
873{
874 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
875 unsigned int rate, lanes;
876 u32 value;
877 int err;
878
879 rate = drm_dp_link_rate_to_bw_code(link->rate);
880 lanes = link->lanes;
881
882 /* configure link speed and lane count */
883 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
884 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
885 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
886 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
887
888 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
889 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
890 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
891
892 if (link->caps.enhanced_framing)
893 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
894
895 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
896
897 usleep_range(400, 1000);
898
899 /* configure load pulse position adjustment */
900 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
901 value &= ~SOR_PLL1_LOADADJ_MASK;
902
903 switch (rate) {
904 case DP_LINK_BW_1_62:
905 value |= SOR_PLL1_LOADADJ(0x3);
906 break;
907
908 case DP_LINK_BW_2_7:
909 value |= SOR_PLL1_LOADADJ(0x4);
910 break;
911
912 case DP_LINK_BW_5_4:
913 value |= SOR_PLL1_LOADADJ(0x6);
914 break;
915 }
916
917 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
918
919 /* use alternate scrambler reset for eDP */
920 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
921
922 if (link->edp == 0)
923 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
924 else
925 value |= SOR_DP_SPARE_PANEL_INTERNAL;
926
927 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
928
929 err = tegra_sor_power_down_lanes(sor);
930 if (err < 0) {
931 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
932 return err;
933 }
934
935 /* power up and pre-charge lanes */
936 err = tegra_sor_power_up_lanes(sor, lanes);
937 if (err < 0) {
938 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
939 lanes, (lanes != 1) ? "s" : "", err);
940 return err;
941 }
942
943 tegra_sor_dp_precharge(sor, lanes);
944
945 return 0;
946}
947
948static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
949 .apply_training = tegra_sor_dp_link_apply_training,
950 .configure = tegra_sor_dp_link_configure,
951};
952
953static void tegra_sor_super_update(struct tegra_sor *sor)
954{
955 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
956 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
957 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
958}
959
960static void tegra_sor_update(struct tegra_sor *sor)
961{
962 tegra_sor_writel(sor, 0, SOR_STATE0);
963 tegra_sor_writel(sor, 1, SOR_STATE0);
964 tegra_sor_writel(sor, 0, SOR_STATE0);
965}
966
967static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
968{
969 u32 value;
970
971 value = tegra_sor_readl(sor, SOR_PWM_DIV);
972 value &= ~SOR_PWM_DIV_MASK;
973 value |= 0x400; /* period */
974 tegra_sor_writel(sor, value, SOR_PWM_DIV);
975
976 value = tegra_sor_readl(sor, SOR_PWM_CTL);
977 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
978 value |= 0x400; /* duty cycle */
979 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
980 value |= SOR_PWM_CTL_TRIGGER;
981 tegra_sor_writel(sor, value, SOR_PWM_CTL);
982
983 timeout = jiffies + msecs_to_jiffies(timeout);
984
985 while (time_before(jiffies, timeout)) {
986 value = tegra_sor_readl(sor, SOR_PWM_CTL);
987 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
988 return 0;
989
990 usleep_range(25, 100);
991 }
992
993 return -ETIMEDOUT;
994}
995
996static int tegra_sor_attach(struct tegra_sor *sor)
997{
998 unsigned long value, timeout;
999
1000 /* wake up in normal mode */
1001 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1002 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1003 value |= SOR_SUPER_STATE_MODE_NORMAL;
1004 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1005 tegra_sor_super_update(sor);
1006
1007 /* attach */
1008 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1009 value |= SOR_SUPER_STATE_ATTACHED;
1010 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1011 tegra_sor_super_update(sor);
1012
1013 timeout = jiffies + msecs_to_jiffies(250);
1014
1015 while (time_before(jiffies, timeout)) {
1016 value = tegra_sor_readl(sor, SOR_TEST);
1017 if ((value & SOR_TEST_ATTACHED) != 0)
1018 return 0;
1019
1020 usleep_range(25, 100);
1021 }
1022
1023 return -ETIMEDOUT;
1024}
1025
1026static int tegra_sor_wakeup(struct tegra_sor *sor)
1027{
1028 unsigned long value, timeout;
1029
1030 timeout = jiffies + msecs_to_jiffies(250);
1031
1032 /* wait for head to wake up */
1033 while (time_before(jiffies, timeout)) {
1034 value = tegra_sor_readl(sor, SOR_TEST);
1035 value &= SOR_TEST_HEAD_MODE_MASK;
1036
1037 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1038 return 0;
1039
1040 usleep_range(25, 100);
1041 }
1042
1043 return -ETIMEDOUT;
1044}
1045
1046static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1047{
1048 u32 value;
1049
1050 value = tegra_sor_readl(sor, SOR_PWR);
1051 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1052 tegra_sor_writel(sor, value, SOR_PWR);
1053
1054 timeout = jiffies + msecs_to_jiffies(timeout);
1055
1056 while (time_before(jiffies, timeout)) {
1057 value = tegra_sor_readl(sor, SOR_PWR);
1058 if ((value & SOR_PWR_TRIGGER) == 0)
1059 return 0;
1060
1061 usleep_range(25, 100);
1062 }
1063
1064 return -ETIMEDOUT;
1065}
1066
1067struct tegra_sor_params {
1068 /* number of link clocks per line */
1069 unsigned int num_clocks;
1070 /* ratio between input and output */
1071 u64 ratio;
1072 /* precision factor */
1073 u64 precision;
1074
1075 unsigned int active_polarity;
1076 unsigned int active_count;
1077 unsigned int active_frac;
1078 unsigned int tu_size;
1079 unsigned int error;
1080};
1081
1082static int tegra_sor_compute_params(struct tegra_sor *sor,
1083 struct tegra_sor_params *params,
1084 unsigned int tu_size)
1085{
1086 u64 active_sym, active_count, frac, approx;
1087 u32 active_polarity, active_frac = 0;
1088 const u64 f = params->precision;
1089 s64 error;
1090
1091 active_sym = params->ratio * tu_size;
1092 active_count = div_u64(active_sym, f) * f;
1093 frac = active_sym - active_count;
1094
1095 /* fraction < 0.5 */
1096 if (frac >= (f / 2)) {
1097 active_polarity = 1;
1098 frac = f - frac;
1099 } else {
1100 active_polarity = 0;
1101 }
1102
1103 if (frac != 0) {
1104 frac = div_u64(f * f, frac); /* 1/fraction */
1105 if (frac <= (15 * f)) {
1106 active_frac = div_u64(frac, f);
1107
1108 /* round up */
1109 if (active_polarity)
1110 active_frac++;
1111 } else {
1112 active_frac = active_polarity ? 1 : 15;
1113 }
1114 }
1115
1116 if (active_frac == 1)
1117 active_polarity = 0;
1118
1119 if (active_polarity == 1) {
1120 if (active_frac) {
1121 approx = active_count + (active_frac * (f - 1)) * f;
1122 approx = div_u64(approx, active_frac * f);
1123 } else {
1124 approx = active_count + f;
1125 }
1126 } else {
1127 if (active_frac)
1128 approx = active_count + div_u64(f, active_frac);
1129 else
1130 approx = active_count;
1131 }
1132
1133 error = div_s64(active_sym - approx, tu_size);
1134 error *= params->num_clocks;
1135
1136 if (error <= 0 && abs(error) < params->error) {
1137 params->active_count = div_u64(active_count, f);
1138 params->active_polarity = active_polarity;
1139 params->active_frac = active_frac;
1140 params->error = abs(error);
1141 params->tu_size = tu_size;
1142
1143 if (error == 0)
1144 return true;
1145 }
1146
1147 return false;
1148}
1149
1150static int tegra_sor_compute_config(struct tegra_sor *sor,
1151 const struct drm_display_mode *mode,
1152 struct tegra_sor_config *config,
1153 struct drm_dp_link *link)
1154{
1155 const u64 f = 100000, link_rate = link->rate * 1000;
1156 const u64 pclk = mode->clock * 1000;
1157 u64 input, output, watermark, num;
1158 struct tegra_sor_params params;
1159 u32 num_syms_per_line;
1160 unsigned int i;
1161
1162 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1163 return -EINVAL;
1164
1165 input = pclk * config->bits_per_pixel;
1166 output = link_rate * 8 * link->lanes;
1167
1168 if (input >= output)
1169 return -ERANGE;
1170
1171 memset(¶ms, 0, sizeof(params));
1172 params.ratio = div64_u64(input * f, output);
1173 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1174 params.precision = f;
1175 params.error = 64 * f;
1176 params.tu_size = 64;
1177
1178 for (i = params.tu_size; i >= 32; i--)
1179 if (tegra_sor_compute_params(sor, ¶ms, i))
1180 break;
1181
1182 if (params.active_frac == 0) {
1183 config->active_polarity = 0;
1184 config->active_count = params.active_count;
1185
1186 if (!params.active_polarity)
1187 config->active_count--;
1188
1189 config->tu_size = params.tu_size;
1190 config->active_frac = 1;
1191 } else {
1192 config->active_polarity = params.active_polarity;
1193 config->active_count = params.active_count;
1194 config->active_frac = params.active_frac;
1195 config->tu_size = params.tu_size;
1196 }
1197
1198 dev_dbg(sor->dev,
1199 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1200 config->active_polarity, config->active_count,
1201 config->tu_size, config->active_frac);
1202
1203 watermark = params.ratio * config->tu_size * (f - params.ratio);
1204 watermark = div_u64(watermark, f);
1205
1206 watermark = div_u64(watermark + params.error, f);
1207 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1208 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1209 (link->lanes * 8);
1210
1211 if (config->watermark > 30) {
1212 config->watermark = 30;
1213 dev_err(sor->dev,
1214 "unable to compute TU size, forcing watermark to %u\n",
1215 config->watermark);
1216 } else if (config->watermark > num_syms_per_line) {
1217 config->watermark = num_syms_per_line;
1218 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1219 config->watermark);
1220 }
1221
1222 /* compute the number of symbols per horizontal blanking interval */
1223 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1224 config->hblank_symbols = div_u64(num, pclk);
1225
1226 if (link->caps.enhanced_framing)
1227 config->hblank_symbols -= 3;
1228
1229 config->hblank_symbols -= 12 / link->lanes;
1230
1231 /* compute the number of symbols per vertical blanking interval */
1232 num = (mode->hdisplay - 25) * link_rate;
1233 config->vblank_symbols = div_u64(num, pclk);
1234 config->vblank_symbols -= 36 / link->lanes + 4;
1235
1236 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1237 config->vblank_symbols);
1238
1239 return 0;
1240}
1241
1242static void tegra_sor_apply_config(struct tegra_sor *sor,
1243 const struct tegra_sor_config *config)
1244{
1245 u32 value;
1246
1247 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1248 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1249 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1250 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1251
1252 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1253 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1254 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1255
1256 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1257 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1258
1259 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1261
1262 if (config->active_polarity)
1263 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1264 else
1265 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1266
1267 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1268 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1269 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1270
1271 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1272 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1273 value |= config->hblank_symbols & 0xffff;
1274 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1275
1276 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1277 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1278 value |= config->vblank_symbols & 0xffff;
1279 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1280}
1281
1282static void tegra_sor_mode_set(struct tegra_sor *sor,
1283 const struct drm_display_mode *mode,
1284 struct tegra_sor_state *state)
1285{
1286 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1287 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1288 u32 value;
1289
1290 value = tegra_sor_readl(sor, SOR_STATE1);
1291 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1292 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1293 value &= ~SOR_STATE_ASY_OWNER_MASK;
1294
1295 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1296 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1297
1298 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1299 value &= ~SOR_STATE_ASY_HSYNCPOL;
1300
1301 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1302 value |= SOR_STATE_ASY_HSYNCPOL;
1303
1304 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1305 value &= ~SOR_STATE_ASY_VSYNCPOL;
1306
1307 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1308 value |= SOR_STATE_ASY_VSYNCPOL;
1309
1310 switch (state->bpc) {
1311 case 16:
1312 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1313 break;
1314
1315 case 12:
1316 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1317 break;
1318
1319 case 10:
1320 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1321 break;
1322
1323 case 8:
1324 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1325 break;
1326
1327 case 6:
1328 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1329 break;
1330
1331 default:
1332 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1333 break;
1334 }
1335
1336 tegra_sor_writel(sor, value, SOR_STATE1);
1337
1338 /*
1339 * TODO: The video timing programming below doesn't seem to match the
1340 * register definitions.
1341 */
1342
1343 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1344 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1345
1346 /* sync end = sync width - 1 */
1347 vse = mode->vsync_end - mode->vsync_start - 1;
1348 hse = mode->hsync_end - mode->hsync_start - 1;
1349
1350 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1351 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1352
1353 /* blank end = sync end + back porch */
1354 vbe = vse + (mode->vtotal - mode->vsync_end);
1355 hbe = hse + (mode->htotal - mode->hsync_end);
1356
1357 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1358 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1359
1360 /* blank start = blank end + active */
1361 vbs = vbe + mode->vdisplay;
1362 hbs = hbe + mode->hdisplay;
1363
1364 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1365 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1366
1367 /* XXX interlacing support */
1368 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1369}
1370
1371static int tegra_sor_detach(struct tegra_sor *sor)
1372{
1373 unsigned long value, timeout;
1374
1375 /* switch to safe mode */
1376 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1377 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1378 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1379 tegra_sor_super_update(sor);
1380
1381 timeout = jiffies + msecs_to_jiffies(250);
1382
1383 while (time_before(jiffies, timeout)) {
1384 value = tegra_sor_readl(sor, SOR_PWR);
1385 if (value & SOR_PWR_MODE_SAFE)
1386 break;
1387 }
1388
1389 if ((value & SOR_PWR_MODE_SAFE) == 0)
1390 return -ETIMEDOUT;
1391
1392 /* go to sleep */
1393 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1394 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1395 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1396 tegra_sor_super_update(sor);
1397
1398 /* detach */
1399 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1400 value &= ~SOR_SUPER_STATE_ATTACHED;
1401 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1402 tegra_sor_super_update(sor);
1403
1404 timeout = jiffies + msecs_to_jiffies(250);
1405
1406 while (time_before(jiffies, timeout)) {
1407 value = tegra_sor_readl(sor, SOR_TEST);
1408 if ((value & SOR_TEST_ATTACHED) == 0)
1409 break;
1410
1411 usleep_range(25, 100);
1412 }
1413
1414 if ((value & SOR_TEST_ATTACHED) != 0)
1415 return -ETIMEDOUT;
1416
1417 return 0;
1418}
1419
1420static int tegra_sor_power_down(struct tegra_sor *sor)
1421{
1422 unsigned long value, timeout;
1423 int err;
1424
1425 value = tegra_sor_readl(sor, SOR_PWR);
1426 value &= ~SOR_PWR_NORMAL_STATE_PU;
1427 value |= SOR_PWR_TRIGGER;
1428 tegra_sor_writel(sor, value, SOR_PWR);
1429
1430 timeout = jiffies + msecs_to_jiffies(250);
1431
1432 while (time_before(jiffies, timeout)) {
1433 value = tegra_sor_readl(sor, SOR_PWR);
1434 if ((value & SOR_PWR_TRIGGER) == 0)
1435 return 0;
1436
1437 usleep_range(25, 100);
1438 }
1439
1440 if ((value & SOR_PWR_TRIGGER) != 0)
1441 return -ETIMEDOUT;
1442
1443 /* switch to safe parent clock */
1444 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1445 if (err < 0) {
1446 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1447 return err;
1448 }
1449
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1451 value |= SOR_PLL2_PORT_POWERDOWN;
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1453
1454 usleep_range(20, 100);
1455
1456 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1457 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1458 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1459
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1461 value |= SOR_PLL2_SEQ_PLLCAPPD;
1462 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1464
1465 usleep_range(20, 100);
1466
1467 return 0;
1468}
1469
1470static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1471{
1472 u32 value;
1473
1474 timeout = jiffies + msecs_to_jiffies(timeout);
1475
1476 while (time_before(jiffies, timeout)) {
1477 value = tegra_sor_readl(sor, SOR_CRCA);
1478 if (value & SOR_CRCA_VALID)
1479 return 0;
1480
1481 usleep_range(100, 200);
1482 }
1483
1484 return -ETIMEDOUT;
1485}
1486
1487static int tegra_sor_show_crc(struct seq_file *s, void *data)
1488{
1489 struct drm_info_node *node = s->private;
1490 struct tegra_sor *sor = node->info_ent->data;
1491 struct drm_crtc *crtc = sor->output.encoder.crtc;
1492 struct drm_device *drm = node->minor->dev;
1493 int err = 0;
1494 u32 value;
1495
1496 drm_modeset_lock_all(drm);
1497
1498 if (!crtc || !crtc->state->active) {
1499 err = -EBUSY;
1500 goto unlock;
1501 }
1502
1503 value = tegra_sor_readl(sor, SOR_STATE1);
1504 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1505 tegra_sor_writel(sor, value, SOR_STATE1);
1506
1507 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1508 value |= SOR_CRC_CNTRL_ENABLE;
1509 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1510
1511 value = tegra_sor_readl(sor, SOR_TEST);
1512 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1513 tegra_sor_writel(sor, value, SOR_TEST);
1514
1515 err = tegra_sor_crc_wait(sor, 100);
1516 if (err < 0)
1517 goto unlock;
1518
1519 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1520 value = tegra_sor_readl(sor, SOR_CRCB);
1521
1522 seq_printf(s, "%08x\n", value);
1523
1524unlock:
1525 drm_modeset_unlock_all(drm);
1526 return err;
1527}
1528
1529#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1530
1531static const struct debugfs_reg32 tegra_sor_regs[] = {
1532 DEBUGFS_REG32(SOR_CTXSW),
1533 DEBUGFS_REG32(SOR_SUPER_STATE0),
1534 DEBUGFS_REG32(SOR_SUPER_STATE1),
1535 DEBUGFS_REG32(SOR_STATE0),
1536 DEBUGFS_REG32(SOR_STATE1),
1537 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1538 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1539 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1540 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1541 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1542 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1543 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1544 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1545 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1546 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1547 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1548 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1549 DEBUGFS_REG32(SOR_CRC_CNTRL),
1550 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1551 DEBUGFS_REG32(SOR_CLK_CNTRL),
1552 DEBUGFS_REG32(SOR_CAP),
1553 DEBUGFS_REG32(SOR_PWR),
1554 DEBUGFS_REG32(SOR_TEST),
1555 DEBUGFS_REG32(SOR_PLL0),
1556 DEBUGFS_REG32(SOR_PLL1),
1557 DEBUGFS_REG32(SOR_PLL2),
1558 DEBUGFS_REG32(SOR_PLL3),
1559 DEBUGFS_REG32(SOR_CSTM),
1560 DEBUGFS_REG32(SOR_LVDS),
1561 DEBUGFS_REG32(SOR_CRCA),
1562 DEBUGFS_REG32(SOR_CRCB),
1563 DEBUGFS_REG32(SOR_BLANK),
1564 DEBUGFS_REG32(SOR_SEQ_CTL),
1565 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1566 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1567 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1568 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1569 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1570 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1571 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1572 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1573 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1574 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1575 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1576 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1577 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1578 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1579 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1580 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1581 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1582 DEBUGFS_REG32(SOR_PWM_DIV),
1583 DEBUGFS_REG32(SOR_PWM_CTL),
1584 DEBUGFS_REG32(SOR_VCRC_A0),
1585 DEBUGFS_REG32(SOR_VCRC_A1),
1586 DEBUGFS_REG32(SOR_VCRC_B0),
1587 DEBUGFS_REG32(SOR_VCRC_B1),
1588 DEBUGFS_REG32(SOR_CCRC_A0),
1589 DEBUGFS_REG32(SOR_CCRC_A1),
1590 DEBUGFS_REG32(SOR_CCRC_B0),
1591 DEBUGFS_REG32(SOR_CCRC_B1),
1592 DEBUGFS_REG32(SOR_EDATA_A0),
1593 DEBUGFS_REG32(SOR_EDATA_A1),
1594 DEBUGFS_REG32(SOR_EDATA_B0),
1595 DEBUGFS_REG32(SOR_EDATA_B1),
1596 DEBUGFS_REG32(SOR_COUNT_A0),
1597 DEBUGFS_REG32(SOR_COUNT_A1),
1598 DEBUGFS_REG32(SOR_COUNT_B0),
1599 DEBUGFS_REG32(SOR_COUNT_B1),
1600 DEBUGFS_REG32(SOR_DEBUG_A0),
1601 DEBUGFS_REG32(SOR_DEBUG_A1),
1602 DEBUGFS_REG32(SOR_DEBUG_B0),
1603 DEBUGFS_REG32(SOR_DEBUG_B1),
1604 DEBUGFS_REG32(SOR_TRIG),
1605 DEBUGFS_REG32(SOR_MSCHECK),
1606 DEBUGFS_REG32(SOR_XBAR_CTRL),
1607 DEBUGFS_REG32(SOR_XBAR_POL),
1608 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1609 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1610 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1611 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1612 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1613 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1614 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1615 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1616 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1617 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1618 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1619 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1620 DEBUGFS_REG32(SOR_DP_CONFIG0),
1621 DEBUGFS_REG32(SOR_DP_CONFIG1),
1622 DEBUGFS_REG32(SOR_DP_MN0),
1623 DEBUGFS_REG32(SOR_DP_MN1),
1624 DEBUGFS_REG32(SOR_DP_PADCTL0),
1625 DEBUGFS_REG32(SOR_DP_PADCTL1),
1626 DEBUGFS_REG32(SOR_DP_PADCTL2),
1627 DEBUGFS_REG32(SOR_DP_DEBUG0),
1628 DEBUGFS_REG32(SOR_DP_DEBUG1),
1629 DEBUGFS_REG32(SOR_DP_SPARE0),
1630 DEBUGFS_REG32(SOR_DP_SPARE1),
1631 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1632 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1633 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1634 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1635 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1636 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1637 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1638 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1639 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1640 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1641 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1642 DEBUGFS_REG32(SOR_DP_TPG),
1643 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1644 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1645 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1646 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1647};
1648
1649static int tegra_sor_show_regs(struct seq_file *s, void *data)
1650{
1651 struct drm_info_node *node = s->private;
1652 struct tegra_sor *sor = node->info_ent->data;
1653 struct drm_crtc *crtc = sor->output.encoder.crtc;
1654 struct drm_device *drm = node->minor->dev;
1655 unsigned int i;
1656 int err = 0;
1657
1658 drm_modeset_lock_all(drm);
1659
1660 if (!crtc || !crtc->state->active) {
1661 err = -EBUSY;
1662 goto unlock;
1663 }
1664
1665 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1666 unsigned int offset = tegra_sor_regs[i].offset;
1667
1668 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1669 offset, tegra_sor_readl(sor, offset));
1670 }
1671
1672unlock:
1673 drm_modeset_unlock_all(drm);
1674 return err;
1675}
1676
1677static const struct drm_info_list debugfs_files[] = {
1678 { "crc", tegra_sor_show_crc, 0, NULL },
1679 { "regs", tegra_sor_show_regs, 0, NULL },
1680};
1681
1682static int tegra_sor_late_register(struct drm_connector *connector)
1683{
1684 struct tegra_output *output = connector_to_output(connector);
1685 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1686 struct drm_minor *minor = connector->dev->primary;
1687 struct dentry *root = connector->debugfs_entry;
1688 struct tegra_sor *sor = to_sor(output);
1689
1690 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1691 GFP_KERNEL);
1692 if (!sor->debugfs_files)
1693 return -ENOMEM;
1694
1695 for (i = 0; i < count; i++)
1696 sor->debugfs_files[i].data = sor;
1697
1698 drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1699
1700 return 0;
1701}
1702
1703static void tegra_sor_early_unregister(struct drm_connector *connector)
1704{
1705 struct tegra_output *output = connector_to_output(connector);
1706 unsigned int count = ARRAY_SIZE(debugfs_files);
1707 struct tegra_sor *sor = to_sor(output);
1708
1709 drm_debugfs_remove_files(sor->debugfs_files, count,
1710 connector->dev->primary);
1711 kfree(sor->debugfs_files);
1712 sor->debugfs_files = NULL;
1713}
1714
1715static void tegra_sor_connector_reset(struct drm_connector *connector)
1716{
1717 struct tegra_sor_state *state;
1718
1719 state = kzalloc(sizeof(*state), GFP_KERNEL);
1720 if (!state)
1721 return;
1722
1723 if (connector->state) {
1724 __drm_atomic_helper_connector_destroy_state(connector->state);
1725 kfree(connector->state);
1726 }
1727
1728 __drm_atomic_helper_connector_reset(connector, &state->base);
1729}
1730
1731static enum drm_connector_status
1732tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1733{
1734 struct tegra_output *output = connector_to_output(connector);
1735 struct tegra_sor *sor = to_sor(output);
1736
1737 if (sor->aux)
1738 return drm_dp_aux_detect(sor->aux);
1739
1740 return tegra_output_connector_detect(connector, force);
1741}
1742
1743static struct drm_connector_state *
1744tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1745{
1746 struct tegra_sor_state *state = to_sor_state(connector->state);
1747 struct tegra_sor_state *copy;
1748
1749 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1750 if (!copy)
1751 return NULL;
1752
1753 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1754
1755 return ©->base;
1756}
1757
1758static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1759 .reset = tegra_sor_connector_reset,
1760 .detect = tegra_sor_connector_detect,
1761 .fill_modes = drm_helper_probe_single_connector_modes,
1762 .destroy = tegra_output_connector_destroy,
1763 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1764 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1765 .late_register = tegra_sor_late_register,
1766 .early_unregister = tegra_sor_early_unregister,
1767};
1768
1769static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1770{
1771 struct tegra_output *output = connector_to_output(connector);
1772 struct tegra_sor *sor = to_sor(output);
1773 int err;
1774
1775 if (sor->aux)
1776 drm_dp_aux_enable(sor->aux);
1777
1778 err = tegra_output_connector_get_modes(connector);
1779
1780 if (sor->aux)
1781 drm_dp_aux_disable(sor->aux);
1782
1783 return err;
1784}
1785
1786static enum drm_mode_status
1787tegra_sor_connector_mode_valid(struct drm_connector *connector,
1788 struct drm_display_mode *mode)
1789{
1790 return MODE_OK;
1791}
1792
1793static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1794 .get_modes = tegra_sor_connector_get_modes,
1795 .mode_valid = tegra_sor_connector_mode_valid,
1796};
1797
1798static int
1799tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1800 struct drm_crtc_state *crtc_state,
1801 struct drm_connector_state *conn_state)
1802{
1803 struct tegra_output *output = encoder_to_output(encoder);
1804 struct tegra_sor_state *state = to_sor_state(conn_state);
1805 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1806 unsigned long pclk = crtc_state->mode.clock * 1000;
1807 struct tegra_sor *sor = to_sor(output);
1808 struct drm_display_info *info;
1809 int err;
1810
1811 info = &output->connector.display_info;
1812
1813 /*
1814 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1815 * the pixel clock must be corrected accordingly.
1816 */
1817 if (pclk >= 340000000) {
1818 state->link_speed = 20;
1819 state->pclk = pclk / 2;
1820 } else {
1821 state->link_speed = 10;
1822 state->pclk = pclk;
1823 }
1824
1825 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1826 pclk, 0);
1827 if (err < 0) {
1828 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1829 return err;
1830 }
1831
1832 switch (info->bpc) {
1833 case 8:
1834 case 6:
1835 state->bpc = info->bpc;
1836 break;
1837
1838 default:
1839 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1840 state->bpc = 8;
1841 break;
1842 }
1843
1844 return 0;
1845}
1846
1847static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1848{
1849 u32 value = 0;
1850 size_t i;
1851
1852 for (i = size; i > 0; i--)
1853 value = (value << 8) | ptr[i - 1];
1854
1855 return value;
1856}
1857
1858static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1859 const void *data, size_t size)
1860{
1861 const u8 *ptr = data;
1862 unsigned long offset;
1863 size_t i, j;
1864 u32 value;
1865
1866 switch (ptr[0]) {
1867 case HDMI_INFOFRAME_TYPE_AVI:
1868 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1869 break;
1870
1871 case HDMI_INFOFRAME_TYPE_AUDIO:
1872 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1873 break;
1874
1875 case HDMI_INFOFRAME_TYPE_VENDOR:
1876 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1877 break;
1878
1879 default:
1880 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1881 ptr[0]);
1882 return;
1883 }
1884
1885 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1886 INFOFRAME_HEADER_VERSION(ptr[1]) |
1887 INFOFRAME_HEADER_LEN(ptr[2]);
1888 tegra_sor_writel(sor, value, offset);
1889 offset++;
1890
1891 /*
1892 * Each subpack contains 7 bytes, divided into:
1893 * - subpack_low: bytes 0 - 3
1894 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1895 */
1896 for (i = 3, j = 0; i < size; i += 7, j += 8) {
1897 size_t rem = size - i, num = min_t(size_t, rem, 4);
1898
1899 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1900 tegra_sor_writel(sor, value, offset++);
1901
1902 num = min_t(size_t, rem - num, 3);
1903
1904 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1905 tegra_sor_writel(sor, value, offset++);
1906 }
1907}
1908
1909static int
1910tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1911 const struct drm_display_mode *mode)
1912{
1913 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1914 struct hdmi_avi_infoframe frame;
1915 u32 value;
1916 int err;
1917
1918 /* disable AVI infoframe */
1919 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1920 value &= ~INFOFRAME_CTRL_SINGLE;
1921 value &= ~INFOFRAME_CTRL_OTHER;
1922 value &= ~INFOFRAME_CTRL_ENABLE;
1923 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1924
1925 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1926 &sor->output.connector, mode);
1927 if (err < 0) {
1928 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1929 return err;
1930 }
1931
1932 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1933 if (err < 0) {
1934 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1935 return err;
1936 }
1937
1938 tegra_sor_hdmi_write_infopack(sor, buffer, err);
1939
1940 /* enable AVI infoframe */
1941 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1942 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1943 value |= INFOFRAME_CTRL_ENABLE;
1944 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1945
1946 return 0;
1947}
1948
1949static void tegra_sor_write_eld(struct tegra_sor *sor)
1950{
1951 size_t length = drm_eld_size(sor->output.connector.eld), i;
1952
1953 for (i = 0; i < length; i++)
1954 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1955 SOR_AUDIO_HDA_ELD_BUFWR);
1956
1957 /*
1958 * The HDA codec will always report an ELD buffer size of 96 bytes and
1959 * the HDA codec driver will check that each byte read from the buffer
1960 * is valid. Therefore every byte must be written, even if no 96 bytes
1961 * were parsed from EDID.
1962 */
1963 for (i = length; i < 96; i++)
1964 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1965}
1966
1967static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1968{
1969 u32 value;
1970
1971 /*
1972 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1973 * is used for interoperability between the HDA codec driver and the
1974 * HDMI/DP driver.
1975 */
1976 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1977 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1978 tegra_sor_writel(sor, value, SOR_INT_MASK);
1979
1980 tegra_sor_write_eld(sor);
1981
1982 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1983 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1984}
1985
1986static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1987{
1988 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1989 tegra_sor_writel(sor, 0, SOR_INT_MASK);
1990 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
1991}
1992
1993static void tegra_sor_audio_enable(struct tegra_sor *sor)
1994{
1995 u32 value;
1996
1997 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
1998
1999 /* select HDA audio input */
2000 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2001 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2002
2003 /* inject null samples */
2004 if (sor->format.channels != 2)
2005 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2006 else
2007 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2008
2009 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2010
2011 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2012
2013 /* enable advertising HBR capability */
2014 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2015}
2016
2017static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2018{
2019 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2020 struct hdmi_audio_infoframe frame;
2021 u32 value;
2022 int err;
2023
2024 err = hdmi_audio_infoframe_init(&frame);
2025 if (err < 0) {
2026 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2027 return err;
2028 }
2029
2030 frame.channels = sor->format.channels;
2031
2032 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2033 if (err < 0) {
2034 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2035 return err;
2036 }
2037
2038 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2039
2040 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2041 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2042 value |= INFOFRAME_CTRL_ENABLE;
2043 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2044
2045 return 0;
2046}
2047
2048static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2049{
2050 u32 value;
2051
2052 tegra_sor_audio_enable(sor);
2053
2054 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2055
2056 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2057 SOR_HDMI_SPARE_CTS_RESET(1) |
2058 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2059 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2060
2061 /* enable HW CTS */
2062 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2063 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2064
2065 /* allow packet to be sent */
2066 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2068
2069 /* reset N counter and enable lookup */
2070 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2071 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2072
2073 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2074 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2075 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2076
2077 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2078 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2079
2080 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2081 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2082
2083 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2084 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2085
2086 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2087 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2088 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2089
2090 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2092 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2093
2094 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2096 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2097
2098 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2099 value &= ~SOR_HDMI_AUDIO_N_RESET;
2100 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2101
2102 tegra_sor_hdmi_enable_audio_infoframe(sor);
2103}
2104
2105static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2106{
2107 u32 value;
2108
2109 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2110 value &= ~INFOFRAME_CTRL_ENABLE;
2111 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2112}
2113
2114static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2115{
2116 tegra_sor_hdmi_disable_audio_infoframe(sor);
2117}
2118
2119static struct tegra_sor_hdmi_settings *
2120tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2121{
2122 unsigned int i;
2123
2124 for (i = 0; i < sor->num_settings; i++)
2125 if (frequency <= sor->settings[i].frequency)
2126 return &sor->settings[i];
2127
2128 return NULL;
2129}
2130
2131static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2132{
2133 u32 value;
2134
2135 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2136 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2137 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2138 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2139}
2140
2141static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2142{
2143 struct i2c_adapter *ddc = sor->output.ddc;
2144
2145 drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2146 drm_scdc_set_scrambling(ddc, false);
2147
2148 tegra_sor_hdmi_disable_scrambling(sor);
2149}
2150
2151static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2152{
2153 if (sor->scdc_enabled) {
2154 cancel_delayed_work_sync(&sor->scdc);
2155 tegra_sor_hdmi_scdc_disable(sor);
2156 }
2157}
2158
2159static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2160{
2161 u32 value;
2162
2163 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2164 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2165 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2166 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2167}
2168
2169static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2170{
2171 struct i2c_adapter *ddc = sor->output.ddc;
2172
2173 drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2174 drm_scdc_set_scrambling(ddc, true);
2175
2176 tegra_sor_hdmi_enable_scrambling(sor);
2177}
2178
2179static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2180{
2181 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2182 struct i2c_adapter *ddc = sor->output.ddc;
2183
2184 if (!drm_scdc_get_scrambling_status(ddc)) {
2185 DRM_DEBUG_KMS("SCDC not scrambled\n");
2186 tegra_sor_hdmi_scdc_enable(sor);
2187 }
2188
2189 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2190}
2191
2192static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2193{
2194 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2195 struct drm_display_mode *mode;
2196
2197 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2198
2199 if (mode->clock >= 340000 && scdc->supported) {
2200 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2201 tegra_sor_hdmi_scdc_enable(sor);
2202 sor->scdc_enabled = true;
2203 }
2204}
2205
2206static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2207{
2208 struct tegra_output *output = encoder_to_output(encoder);
2209 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2210 struct tegra_sor *sor = to_sor(output);
2211 u32 value;
2212 int err;
2213
2214 tegra_sor_audio_unprepare(sor);
2215 tegra_sor_hdmi_scdc_stop(sor);
2216
2217 err = tegra_sor_detach(sor);
2218 if (err < 0)
2219 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2220
2221 tegra_sor_writel(sor, 0, SOR_STATE1);
2222 tegra_sor_update(sor);
2223
2224 /* disable display to SOR clock */
2225 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2226
2227 if (!sor->soc->has_nvdisplay)
2228 value &= ~SOR1_TIMING_CYA;
2229
2230 value &= ~SOR_ENABLE(sor->index);
2231
2232 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2233
2234 tegra_dc_commit(dc);
2235
2236 err = tegra_sor_power_down(sor);
2237 if (err < 0)
2238 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2239
2240 err = tegra_io_pad_power_disable(sor->pad);
2241 if (err < 0)
2242 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2243
2244 host1x_client_suspend(&sor->client);
2245}
2246
2247static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2248{
2249 struct tegra_output *output = encoder_to_output(encoder);
2250 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2251 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2252 struct tegra_sor_hdmi_settings *settings;
2253 struct tegra_sor *sor = to_sor(output);
2254 struct tegra_sor_state *state;
2255 struct drm_display_mode *mode;
2256 unsigned long rate, pclk;
2257 unsigned int div, i;
2258 u32 value;
2259 int err;
2260
2261 state = to_sor_state(output->connector.state);
2262 mode = &encoder->crtc->state->adjusted_mode;
2263 pclk = mode->clock * 1000;
2264
2265 err = host1x_client_resume(&sor->client);
2266 if (err < 0) {
2267 dev_err(sor->dev, "failed to resume: %d\n", err);
2268 return;
2269 }
2270
2271 /* switch to safe parent clock */
2272 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2273 if (err < 0) {
2274 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2275 return;
2276 }
2277
2278 div = clk_get_rate(sor->clk) / 1000000 * 4;
2279
2280 err = tegra_io_pad_power_enable(sor->pad);
2281 if (err < 0)
2282 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2283
2284 usleep_range(20, 100);
2285
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2287 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2289
2290 usleep_range(20, 100);
2291
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2293 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2295
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2297 value &= ~SOR_PLL0_VCOPD;
2298 value &= ~SOR_PLL0_PWR;
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2300
2301 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2302 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2303 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2304
2305 usleep_range(200, 400);
2306
2307 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2308 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2309 value &= ~SOR_PLL2_PORT_POWERDOWN;
2310 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2311
2312 usleep_range(20, 100);
2313
2314 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2315 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2316 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2317 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2318
2319 while (true) {
2320 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2321 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2322 break;
2323
2324 usleep_range(250, 1000);
2325 }
2326
2327 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2328 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2329 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2330
2331 while (true) {
2332 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2333 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2334 break;
2335
2336 usleep_range(250, 1000);
2337 }
2338
2339 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2340 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2341 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2342
2343 if (mode->clock < 340000) {
2344 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2345 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2346 } else {
2347 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2348 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2349 }
2350
2351 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2352 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2353
2354 /* SOR pad PLL stabilization time */
2355 usleep_range(250, 1000);
2356
2357 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2358 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2359 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2360 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2361
2362 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2363 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2364 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2365 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2366 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2367 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2368
2369 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2370 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2371 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2372
2373 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2374 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2376 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2377
2378 if (!sor->soc->has_nvdisplay) {
2379 /* program the reference clock */
2380 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2381 tegra_sor_writel(sor, value, SOR_REFCLK);
2382 }
2383
2384 /* XXX not in TRM */
2385 for (value = 0, i = 0; i < 5; i++)
2386 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2387 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2388
2389 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2390 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2391
2392 /*
2393 * Switch the pad clock to the DP clock. Note that we cannot actually
2394 * do this because Tegra186 and later don't support clk_set_parent()
2395 * on the sorX_pad_clkout clocks. We already do the equivalent above
2396 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2397 */
2398#if 0
2399 err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2400 if (err < 0) {
2401 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2402 err);
2403 return;
2404 }
2405#endif
2406
2407 /* switch the SOR clock to the pad clock */
2408 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2409 if (err < 0) {
2410 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2411 err);
2412 return;
2413 }
2414
2415 /* switch the output clock to the parent pixel clock */
2416 err = clk_set_parent(sor->clk, sor->clk_parent);
2417 if (err < 0) {
2418 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2419 err);
2420 return;
2421 }
2422
2423 /* adjust clock rate for HDMI 2.0 modes */
2424 rate = clk_get_rate(sor->clk_parent);
2425
2426 if (mode->clock >= 340000)
2427 rate /= 2;
2428
2429 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2430
2431 clk_set_rate(sor->clk, rate);
2432
2433 if (!sor->soc->has_nvdisplay) {
2434 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2435
2436 /* XXX is this the proper check? */
2437 if (mode->clock < 75000)
2438 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2439
2440 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2441 }
2442
2443 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2444
2445 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2446 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2447 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2448
2449 if (!dc->soc->has_nvdisplay) {
2450 /* H_PULSE2 setup */
2451 pulse_start = h_ref_to_sync +
2452 (mode->hsync_end - mode->hsync_start) +
2453 (mode->htotal - mode->hsync_end) - 10;
2454
2455 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2456 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2457 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2458
2459 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2460 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2461
2462 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2463 value |= H_PULSE2_ENABLE;
2464 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2465 }
2466
2467 /* infoframe setup */
2468 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2469 if (err < 0)
2470 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2471
2472 /* XXX HDMI audio support not implemented yet */
2473 tegra_sor_hdmi_disable_audio_infoframe(sor);
2474
2475 /* use single TMDS protocol */
2476 value = tegra_sor_readl(sor, SOR_STATE1);
2477 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2478 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2479 tegra_sor_writel(sor, value, SOR_STATE1);
2480
2481 /* power up pad calibration */
2482 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2483 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2484 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2485
2486 /* production settings */
2487 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2488 if (!settings) {
2489 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2490 mode->clock * 1000);
2491 return;
2492 }
2493
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2495 value &= ~SOR_PLL0_ICHPMP_MASK;
2496 value &= ~SOR_PLL0_FILTER_MASK;
2497 value &= ~SOR_PLL0_VCOCAP_MASK;
2498 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2499 value |= SOR_PLL0_FILTER(settings->filter);
2500 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2502
2503 /* XXX not in TRM */
2504 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2505 value &= ~SOR_PLL1_LOADADJ_MASK;
2506 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2507 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2508 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2509 value |= SOR_PLL1_TMDS_TERM;
2510 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2511
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2513 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2514 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2515 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2516 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2517 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2518 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2519 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2520 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2522
2523 value = settings->drive_current[3] << 24 |
2524 settings->drive_current[2] << 16 |
2525 settings->drive_current[1] << 8 |
2526 settings->drive_current[0] << 0;
2527 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2528
2529 value = settings->preemphasis[3] << 24 |
2530 settings->preemphasis[2] << 16 |
2531 settings->preemphasis[1] << 8 |
2532 settings->preemphasis[0] << 0;
2533 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2534
2535 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2536 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2537 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2538 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2539 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2540
2541 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2542 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2543 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2544 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2545
2546 /* power down pad calibration */
2547 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2548 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2549 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2550
2551 if (!dc->soc->has_nvdisplay) {
2552 /* miscellaneous display controller settings */
2553 value = VSYNC_H_POSITION(1);
2554 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2555 }
2556
2557 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2558 value &= ~DITHER_CONTROL_MASK;
2559 value &= ~BASE_COLOR_SIZE_MASK;
2560
2561 switch (state->bpc) {
2562 case 6:
2563 value |= BASE_COLOR_SIZE_666;
2564 break;
2565
2566 case 8:
2567 value |= BASE_COLOR_SIZE_888;
2568 break;
2569
2570 case 10:
2571 value |= BASE_COLOR_SIZE_101010;
2572 break;
2573
2574 case 12:
2575 value |= BASE_COLOR_SIZE_121212;
2576 break;
2577
2578 default:
2579 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2580 value |= BASE_COLOR_SIZE_888;
2581 break;
2582 }
2583
2584 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2585
2586 /* XXX set display head owner */
2587 value = tegra_sor_readl(sor, SOR_STATE1);
2588 value &= ~SOR_STATE_ASY_OWNER_MASK;
2589 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2590 tegra_sor_writel(sor, value, SOR_STATE1);
2591
2592 err = tegra_sor_power_up(sor, 250);
2593 if (err < 0)
2594 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2595
2596 /* configure dynamic range of output */
2597 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2598 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2599 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2600 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2601
2602 /* configure colorspace */
2603 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2604 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2605 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2606 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2607
2608 tegra_sor_mode_set(sor, mode, state);
2609
2610 tegra_sor_update(sor);
2611
2612 /* program preamble timing in SOR (XXX) */
2613 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2614 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2615 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2616
2617 err = tegra_sor_attach(sor);
2618 if (err < 0)
2619 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2620
2621 /* enable display to SOR clock and generate HDMI preamble */
2622 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2623
2624 if (!sor->soc->has_nvdisplay)
2625 value |= SOR1_TIMING_CYA;
2626
2627 value |= SOR_ENABLE(sor->index);
2628
2629 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2630
2631 if (dc->soc->has_nvdisplay) {
2632 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2633 value &= ~PROTOCOL_MASK;
2634 value |= PROTOCOL_SINGLE_TMDS_A;
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2636 }
2637
2638 tegra_dc_commit(dc);
2639
2640 err = tegra_sor_wakeup(sor);
2641 if (err < 0)
2642 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2643
2644 tegra_sor_hdmi_scdc_start(sor);
2645 tegra_sor_audio_prepare(sor);
2646}
2647
2648static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2649 .disable = tegra_sor_hdmi_disable,
2650 .enable = tegra_sor_hdmi_enable,
2651 .atomic_check = tegra_sor_encoder_atomic_check,
2652};
2653
2654static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2655{
2656 struct tegra_output *output = encoder_to_output(encoder);
2657 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2658 struct tegra_sor *sor = to_sor(output);
2659 u32 value;
2660 int err;
2661
2662 if (output->panel)
2663 drm_panel_disable(output->panel);
2664
2665 /*
2666 * Do not attempt to power down a DP link if we're not connected since
2667 * the AUX transactions would just be timing out.
2668 */
2669 if (output->connector.status != connector_status_disconnected) {
2670 err = drm_dp_link_power_down(sor->aux, &sor->link);
2671 if (err < 0)
2672 dev_err(sor->dev, "failed to power down link: %d\n",
2673 err);
2674 }
2675
2676 err = tegra_sor_detach(sor);
2677 if (err < 0)
2678 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2679
2680 tegra_sor_writel(sor, 0, SOR_STATE1);
2681 tegra_sor_update(sor);
2682
2683 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2684 value &= ~SOR_ENABLE(sor->index);
2685 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2686 tegra_dc_commit(dc);
2687
2688 value = tegra_sor_readl(sor, SOR_STATE1);
2689 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2690 value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2691 value &= ~SOR_STATE_ASY_OWNER_MASK;
2692 tegra_sor_writel(sor, value, SOR_STATE1);
2693 tegra_sor_update(sor);
2694
2695 /* switch to safe parent clock */
2696 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2697 if (err < 0)
2698 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2699
2700 err = tegra_sor_power_down(sor);
2701 if (err < 0)
2702 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2703
2704 err = tegra_io_pad_power_disable(sor->pad);
2705 if (err < 0)
2706 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2707
2708 err = drm_dp_aux_disable(sor->aux);
2709 if (err < 0)
2710 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2711
2712 if (output->panel)
2713 drm_panel_unprepare(output->panel);
2714
2715 host1x_client_suspend(&sor->client);
2716}
2717
2718static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2719{
2720 struct tegra_output *output = encoder_to_output(encoder);
2721 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2722 struct tegra_sor *sor = to_sor(output);
2723 struct tegra_sor_config config;
2724 struct tegra_sor_state *state;
2725 struct drm_display_mode *mode;
2726 struct drm_display_info *info;
2727 unsigned int i;
2728 u32 value;
2729 int err;
2730
2731 state = to_sor_state(output->connector.state);
2732 mode = &encoder->crtc->state->adjusted_mode;
2733 info = &output->connector.display_info;
2734
2735 err = host1x_client_resume(&sor->client);
2736 if (err < 0) {
2737 dev_err(sor->dev, "failed to resume: %d\n", err);
2738 return;
2739 }
2740
2741 /* switch to safe parent clock */
2742 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2743 if (err < 0)
2744 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2745
2746 err = tegra_io_pad_power_enable(sor->pad);
2747 if (err < 0)
2748 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2749
2750 usleep_range(20, 100);
2751
2752 err = drm_dp_aux_enable(sor->aux);
2753 if (err < 0)
2754 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2755
2756 err = drm_dp_link_probe(sor->aux, &sor->link);
2757 if (err < 0)
2758 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2759
2760 tegra_sor_filter_rates(sor);
2761
2762 err = drm_dp_link_choose(&sor->link, mode, info);
2763 if (err < 0)
2764 dev_err(sor->dev, "failed to choose link: %d\n", err);
2765
2766 if (output->panel)
2767 drm_panel_prepare(output->panel);
2768
2769 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2770 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2771 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2772
2773 usleep_range(20, 40);
2774
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2776 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2778
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2780 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2782
2783 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2784 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2785 value |= SOR_PLL2_SEQ_PLLCAPPD;
2786 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2787
2788 usleep_range(200, 400);
2789
2790 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2791 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2792 value &= ~SOR_PLL2_PORT_POWERDOWN;
2793 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2794
2795 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2796 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2797
2798 if (output->panel)
2799 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2800 else
2801 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2802
2803 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2804
2805 usleep_range(200, 400);
2806
2807 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2808 /* XXX not in TRM */
2809 if (output->panel)
2810 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2811 else
2812 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2813
2814 value |= SOR_DP_SPARE_SEQ_ENABLE;
2815 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2816
2817 /* XXX not in TRM */
2818 tegra_sor_writel(sor, 0, SOR_LVDS);
2819
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2821 value &= ~SOR_PLL0_ICHPMP_MASK;
2822 value &= ~SOR_PLL0_VCOCAP_MASK;
2823 value |= SOR_PLL0_ICHPMP(0x1);
2824 value |= SOR_PLL0_VCOCAP(0x3);
2825 value |= SOR_PLL0_RESISTOR_EXT;
2826 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2827
2828 /* XXX not in TRM */
2829 for (value = 0, i = 0; i < 5; i++)
2830 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2831 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2832
2833 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2834 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2835
2836 /*
2837 * Switch the pad clock to the DP clock. Note that we cannot actually
2838 * do this because Tegra186 and later don't support clk_set_parent()
2839 * on the sorX_pad_clkout clocks. We already do the equivalent above
2840 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2841 */
2842#if 0
2843 err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2844 if (err < 0) {
2845 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2846 err);
2847 return;
2848 }
2849#endif
2850
2851 /* switch the SOR clock to the pad clock */
2852 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2853 if (err < 0) {
2854 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2855 err);
2856 return;
2857 }
2858
2859 /* switch the output clock to the parent pixel clock */
2860 err = clk_set_parent(sor->clk, sor->clk_parent);
2861 if (err < 0) {
2862 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2863 err);
2864 return;
2865 }
2866
2867 /* use DP-A protocol */
2868 value = tegra_sor_readl(sor, SOR_STATE1);
2869 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2870 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2871 tegra_sor_writel(sor, value, SOR_STATE1);
2872
2873 /* enable port */
2874 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2875 value |= SOR_DP_LINKCTL_ENABLE;
2876 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2877
2878 tegra_sor_dp_term_calibrate(sor);
2879
2880 err = drm_dp_link_train(&sor->link);
2881 if (err < 0)
2882 dev_err(sor->dev, "link training failed: %d\n", err);
2883 else
2884 dev_dbg(sor->dev, "link training succeeded\n");
2885
2886 err = drm_dp_link_power_up(sor->aux, &sor->link);
2887 if (err < 0)
2888 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2889
2890 /* compute configuration */
2891 memset(&config, 0, sizeof(config));
2892 config.bits_per_pixel = state->bpc * 3;
2893
2894 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2895 if (err < 0)
2896 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2897
2898 tegra_sor_apply_config(sor, &config);
2899 tegra_sor_mode_set(sor, mode, state);
2900
2901 if (output->panel) {
2902 /* CSTM (LVDS, link A/B, upper) */
2903 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2904 SOR_CSTM_UPPER;
2905 tegra_sor_writel(sor, value, SOR_CSTM);
2906
2907 /* PWM setup */
2908 err = tegra_sor_setup_pwm(sor, 250);
2909 if (err < 0)
2910 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2911 }
2912
2913 tegra_sor_update(sor);
2914
2915 err = tegra_sor_power_up(sor, 250);
2916 if (err < 0)
2917 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2918
2919 /* attach and wake up */
2920 err = tegra_sor_attach(sor);
2921 if (err < 0)
2922 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2923
2924 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2925 value |= SOR_ENABLE(sor->index);
2926 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2927
2928 tegra_dc_commit(dc);
2929
2930 err = tegra_sor_wakeup(sor);
2931 if (err < 0)
2932 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2933
2934 if (output->panel)
2935 drm_panel_enable(output->panel);
2936}
2937
2938static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2939 .disable = tegra_sor_dp_disable,
2940 .enable = tegra_sor_dp_enable,
2941 .atomic_check = tegra_sor_encoder_atomic_check,
2942};
2943
2944static void tegra_sor_disable_regulator(void *data)
2945{
2946 struct regulator *reg = data;
2947
2948 regulator_disable(reg);
2949}
2950
2951static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
2952{
2953 int err;
2954
2955 err = regulator_enable(reg);
2956 if (err)
2957 return err;
2958
2959 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2960}
2961
2962static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2963{
2964 int err;
2965
2966 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2967 if (IS_ERR(sor->avdd_io_supply)) {
2968 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2969 PTR_ERR(sor->avdd_io_supply));
2970 return PTR_ERR(sor->avdd_io_supply);
2971 }
2972
2973 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
2974 if (err < 0) {
2975 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2976 err);
2977 return err;
2978 }
2979
2980 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2981 if (IS_ERR(sor->vdd_pll_supply)) {
2982 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2983 PTR_ERR(sor->vdd_pll_supply));
2984 return PTR_ERR(sor->vdd_pll_supply);
2985 }
2986
2987 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
2988 if (err < 0) {
2989 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2990 err);
2991 return err;
2992 }
2993
2994 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2995 if (IS_ERR(sor->hdmi_supply)) {
2996 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2997 PTR_ERR(sor->hdmi_supply));
2998 return PTR_ERR(sor->hdmi_supply);
2999 }
3000
3001 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
3002 if (err < 0) {
3003 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3004 return err;
3005 }
3006
3007 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3008
3009 return 0;
3010}
3011
3012static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3013 .name = "HDMI",
3014 .probe = tegra_sor_hdmi_probe,
3015 .audio_enable = tegra_sor_hdmi_audio_enable,
3016 .audio_disable = tegra_sor_hdmi_audio_disable,
3017};
3018
3019static int tegra_sor_dp_probe(struct tegra_sor *sor)
3020{
3021 int err;
3022
3023 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3024 if (IS_ERR(sor->avdd_io_supply))
3025 return PTR_ERR(sor->avdd_io_supply);
3026
3027 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
3028 if (err < 0)
3029 return err;
3030
3031 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3032 if (IS_ERR(sor->vdd_pll_supply))
3033 return PTR_ERR(sor->vdd_pll_supply);
3034
3035 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
3036 if (err < 0)
3037 return err;
3038
3039 return 0;
3040}
3041
3042static const struct tegra_sor_ops tegra_sor_dp_ops = {
3043 .name = "DP",
3044 .probe = tegra_sor_dp_probe,
3045};
3046
3047static int tegra_sor_init(struct host1x_client *client)
3048{
3049 struct drm_device *drm = dev_get_drvdata(client->host);
3050 const struct drm_encoder_helper_funcs *helpers = NULL;
3051 struct tegra_sor *sor = host1x_client_to_sor(client);
3052 int connector = DRM_MODE_CONNECTOR_Unknown;
3053 int encoder = DRM_MODE_ENCODER_NONE;
3054 int err;
3055
3056 if (!sor->aux) {
3057 if (sor->ops == &tegra_sor_hdmi_ops) {
3058 connector = DRM_MODE_CONNECTOR_HDMIA;
3059 encoder = DRM_MODE_ENCODER_TMDS;
3060 helpers = &tegra_sor_hdmi_helpers;
3061 } else if (sor->soc->supports_lvds) {
3062 connector = DRM_MODE_CONNECTOR_LVDS;
3063 encoder = DRM_MODE_ENCODER_LVDS;
3064 }
3065 } else {
3066 if (sor->output.panel) {
3067 connector = DRM_MODE_CONNECTOR_eDP;
3068 encoder = DRM_MODE_ENCODER_TMDS;
3069 helpers = &tegra_sor_dp_helpers;
3070 } else {
3071 connector = DRM_MODE_CONNECTOR_DisplayPort;
3072 encoder = DRM_MODE_ENCODER_TMDS;
3073 helpers = &tegra_sor_dp_helpers;
3074 }
3075
3076 sor->link.ops = &tegra_sor_dp_link_ops;
3077 sor->link.aux = sor->aux;
3078 }
3079
3080 sor->output.dev = sor->dev;
3081
3082 drm_connector_init_with_ddc(drm, &sor->output.connector,
3083 &tegra_sor_connector_funcs,
3084 connector,
3085 sor->output.ddc);
3086 drm_connector_helper_add(&sor->output.connector,
3087 &tegra_sor_connector_helper_funcs);
3088 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3089
3090 drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3091 drm_encoder_helper_add(&sor->output.encoder, helpers);
3092
3093 drm_connector_attach_encoder(&sor->output.connector,
3094 &sor->output.encoder);
3095 drm_connector_register(&sor->output.connector);
3096
3097 err = tegra_output_init(drm, &sor->output);
3098 if (err < 0) {
3099 dev_err(client->dev, "failed to initialize output: %d\n", err);
3100 return err;
3101 }
3102
3103 tegra_output_find_possible_crtcs(&sor->output, drm);
3104
3105 if (sor->aux) {
3106 err = drm_dp_aux_attach(sor->aux, &sor->output);
3107 if (err < 0) {
3108 dev_err(sor->dev, "failed to attach DP: %d\n", err);
3109 return err;
3110 }
3111 }
3112
3113 /*
3114 * XXX: Remove this reset once proper hand-over from firmware to
3115 * kernel is possible.
3116 */
3117 if (sor->rst) {
3118 err = pm_runtime_resume_and_get(sor->dev);
3119 if (err < 0) {
3120 dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3121 return err;
3122 }
3123
3124 err = reset_control_acquire(sor->rst);
3125 if (err < 0) {
3126 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3127 err);
3128 goto rpm_put;
3129 }
3130
3131 err = reset_control_assert(sor->rst);
3132 if (err < 0) {
3133 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3134 err);
3135 goto rpm_put;
3136 }
3137 }
3138
3139 err = clk_prepare_enable(sor->clk);
3140 if (err < 0) {
3141 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3142 goto rpm_put;
3143 }
3144
3145 usleep_range(1000, 3000);
3146
3147 if (sor->rst) {
3148 err = reset_control_deassert(sor->rst);
3149 if (err < 0) {
3150 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3151 err);
3152 clk_disable_unprepare(sor->clk);
3153 goto rpm_put;
3154 }
3155
3156 reset_control_release(sor->rst);
3157 pm_runtime_put(sor->dev);
3158 }
3159
3160 err = clk_prepare_enable(sor->clk_safe);
3161 if (err < 0) {
3162 clk_disable_unprepare(sor->clk);
3163 return err;
3164 }
3165
3166 err = clk_prepare_enable(sor->clk_dp);
3167 if (err < 0) {
3168 clk_disable_unprepare(sor->clk_safe);
3169 clk_disable_unprepare(sor->clk);
3170 return err;
3171 }
3172
3173 return 0;
3174
3175rpm_put:
3176 if (sor->rst)
3177 pm_runtime_put(sor->dev);
3178
3179 return err;
3180}
3181
3182static int tegra_sor_exit(struct host1x_client *client)
3183{
3184 struct tegra_sor *sor = host1x_client_to_sor(client);
3185 int err;
3186
3187 tegra_output_exit(&sor->output);
3188
3189 if (sor->aux) {
3190 err = drm_dp_aux_detach(sor->aux);
3191 if (err < 0) {
3192 dev_err(sor->dev, "failed to detach DP: %d\n", err);
3193 return err;
3194 }
3195 }
3196
3197 clk_disable_unprepare(sor->clk_safe);
3198 clk_disable_unprepare(sor->clk_dp);
3199 clk_disable_unprepare(sor->clk);
3200
3201 return 0;
3202}
3203
3204static int tegra_sor_runtime_suspend(struct host1x_client *client)
3205{
3206 struct tegra_sor *sor = host1x_client_to_sor(client);
3207 struct device *dev = client->dev;
3208 int err;
3209
3210 if (sor->rst) {
3211 err = reset_control_assert(sor->rst);
3212 if (err < 0) {
3213 dev_err(dev, "failed to assert reset: %d\n", err);
3214 return err;
3215 }
3216
3217 reset_control_release(sor->rst);
3218 }
3219
3220 usleep_range(1000, 2000);
3221
3222 clk_disable_unprepare(sor->clk);
3223 pm_runtime_put_sync(dev);
3224
3225 return 0;
3226}
3227
3228static int tegra_sor_runtime_resume(struct host1x_client *client)
3229{
3230 struct tegra_sor *sor = host1x_client_to_sor(client);
3231 struct device *dev = client->dev;
3232 int err;
3233
3234 err = pm_runtime_resume_and_get(dev);
3235 if (err < 0) {
3236 dev_err(dev, "failed to get runtime PM: %d\n", err);
3237 return err;
3238 }
3239
3240 err = clk_prepare_enable(sor->clk);
3241 if (err < 0) {
3242 dev_err(dev, "failed to enable clock: %d\n", err);
3243 goto put_rpm;
3244 }
3245
3246 usleep_range(1000, 2000);
3247
3248 if (sor->rst) {
3249 err = reset_control_acquire(sor->rst);
3250 if (err < 0) {
3251 dev_err(dev, "failed to acquire reset: %d\n", err);
3252 goto disable_clk;
3253 }
3254
3255 err = reset_control_deassert(sor->rst);
3256 if (err < 0) {
3257 dev_err(dev, "failed to deassert reset: %d\n", err);
3258 goto release_reset;
3259 }
3260 }
3261
3262 return 0;
3263
3264release_reset:
3265 reset_control_release(sor->rst);
3266disable_clk:
3267 clk_disable_unprepare(sor->clk);
3268put_rpm:
3269 pm_runtime_put_sync(dev);
3270 return err;
3271}
3272
3273static const struct host1x_client_ops sor_client_ops = {
3274 .init = tegra_sor_init,
3275 .exit = tegra_sor_exit,
3276 .suspend = tegra_sor_runtime_suspend,
3277 .resume = tegra_sor_runtime_resume,
3278};
3279
3280static const u8 tegra124_sor_xbar_cfg[5] = {
3281 0, 1, 2, 3, 4
3282};
3283
3284static const struct tegra_sor_regs tegra124_sor_regs = {
3285 .head_state0 = 0x05,
3286 .head_state1 = 0x07,
3287 .head_state2 = 0x09,
3288 .head_state3 = 0x0b,
3289 .head_state4 = 0x0d,
3290 .head_state5 = 0x0f,
3291 .pll0 = 0x17,
3292 .pll1 = 0x18,
3293 .pll2 = 0x19,
3294 .pll3 = 0x1a,
3295 .dp_padctl0 = 0x5c,
3296 .dp_padctl2 = 0x73,
3297};
3298
3299/* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3300static const u8 tegra124_sor_lane_map[4] = {
3301 2, 1, 0, 3,
3302};
3303
3304static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3305 {
3306 { 0x13, 0x19, 0x1e, 0x28 },
3307 { 0x1e, 0x25, 0x2d, },
3308 { 0x28, 0x32, },
3309 { 0x3c, },
3310 }, {
3311 { 0x12, 0x17, 0x1b, 0x25 },
3312 { 0x1c, 0x23, 0x2a, },
3313 { 0x25, 0x2f, },
3314 { 0x39, }
3315 }, {
3316 { 0x12, 0x16, 0x1a, 0x22 },
3317 { 0x1b, 0x20, 0x27, },
3318 { 0x24, 0x2d, },
3319 { 0x36, },
3320 }, {
3321 { 0x11, 0x14, 0x17, 0x1f },
3322 { 0x19, 0x1e, 0x24, },
3323 { 0x22, 0x2a, },
3324 { 0x32, },
3325 },
3326};
3327
3328static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3329 {
3330 { 0x00, 0x09, 0x13, 0x25 },
3331 { 0x00, 0x0f, 0x1e, },
3332 { 0x00, 0x14, },
3333 { 0x00, },
3334 }, {
3335 { 0x00, 0x0a, 0x14, 0x28 },
3336 { 0x00, 0x0f, 0x1e, },
3337 { 0x00, 0x14, },
3338 { 0x00 },
3339 }, {
3340 { 0x00, 0x0a, 0x14, 0x28 },
3341 { 0x00, 0x0f, 0x1e, },
3342 { 0x00, 0x14, },
3343 { 0x00, },
3344 }, {
3345 { 0x00, 0x0a, 0x14, 0x28 },
3346 { 0x00, 0x0f, 0x1e, },
3347 { 0x00, 0x14, },
3348 { 0x00, },
3349 },
3350};
3351
3352static const u8 tegra124_sor_post_cursor[4][4][4] = {
3353 {
3354 { 0x00, 0x00, 0x00, 0x00 },
3355 { 0x00, 0x00, 0x00, },
3356 { 0x00, 0x00, },
3357 { 0x00, },
3358 }, {
3359 { 0x02, 0x02, 0x04, 0x05 },
3360 { 0x02, 0x04, 0x05, },
3361 { 0x04, 0x05, },
3362 { 0x05, },
3363 }, {
3364 { 0x04, 0x05, 0x08, 0x0b },
3365 { 0x05, 0x09, 0x0b, },
3366 { 0x08, 0x0a, },
3367 { 0x0b, },
3368 }, {
3369 { 0x05, 0x09, 0x0b, 0x12 },
3370 { 0x09, 0x0d, 0x12, },
3371 { 0x0b, 0x0f, },
3372 { 0x12, },
3373 },
3374};
3375
3376static const u8 tegra124_sor_tx_pu[4][4][4] = {
3377 {
3378 { 0x20, 0x30, 0x40, 0x60 },
3379 { 0x30, 0x40, 0x60, },
3380 { 0x40, 0x60, },
3381 { 0x60, },
3382 }, {
3383 { 0x20, 0x20, 0x30, 0x50 },
3384 { 0x30, 0x40, 0x50, },
3385 { 0x40, 0x50, },
3386 { 0x60, },
3387 }, {
3388 { 0x20, 0x20, 0x30, 0x40, },
3389 { 0x30, 0x30, 0x40, },
3390 { 0x40, 0x50, },
3391 { 0x60, },
3392 }, {
3393 { 0x20, 0x20, 0x20, 0x40, },
3394 { 0x30, 0x30, 0x40, },
3395 { 0x40, 0x40, },
3396 { 0x60, },
3397 },
3398};
3399
3400static const struct tegra_sor_soc tegra124_sor = {
3401 .supports_lvds = true,
3402 .supports_hdmi = false,
3403 .supports_dp = true,
3404 .supports_audio = false,
3405 .supports_hdcp = false,
3406 .regs = &tegra124_sor_regs,
3407 .has_nvdisplay = false,
3408 .xbar_cfg = tegra124_sor_xbar_cfg,
3409 .lane_map = tegra124_sor_lane_map,
3410 .voltage_swing = tegra124_sor_voltage_swing,
3411 .pre_emphasis = tegra124_sor_pre_emphasis,
3412 .post_cursor = tegra124_sor_post_cursor,
3413 .tx_pu = tegra124_sor_tx_pu,
3414};
3415
3416static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3417 {
3418 { 0x00, 0x08, 0x12, 0x24 },
3419 { 0x01, 0x0e, 0x1d, },
3420 { 0x01, 0x13, },
3421 { 0x00, },
3422 }, {
3423 { 0x00, 0x08, 0x12, 0x24 },
3424 { 0x00, 0x0e, 0x1d, },
3425 { 0x00, 0x13, },
3426 { 0x00 },
3427 }, {
3428 { 0x00, 0x08, 0x12, 0x24 },
3429 { 0x00, 0x0e, 0x1d, },
3430 { 0x00, 0x13, },
3431 { 0x00, },
3432 }, {
3433 { 0x00, 0x08, 0x12, 0x24 },
3434 { 0x00, 0x0e, 0x1d, },
3435 { 0x00, 0x13, },
3436 { 0x00, },
3437 },
3438};
3439
3440static const struct tegra_sor_soc tegra132_sor = {
3441 .supports_lvds = true,
3442 .supports_hdmi = false,
3443 .supports_dp = true,
3444 .supports_audio = false,
3445 .supports_hdcp = false,
3446 .regs = &tegra124_sor_regs,
3447 .has_nvdisplay = false,
3448 .xbar_cfg = tegra124_sor_xbar_cfg,
3449 .lane_map = tegra124_sor_lane_map,
3450 .voltage_swing = tegra124_sor_voltage_swing,
3451 .pre_emphasis = tegra132_sor_pre_emphasis,
3452 .post_cursor = tegra124_sor_post_cursor,
3453 .tx_pu = tegra124_sor_tx_pu,
3454};
3455
3456static const struct tegra_sor_regs tegra210_sor_regs = {
3457 .head_state0 = 0x05,
3458 .head_state1 = 0x07,
3459 .head_state2 = 0x09,
3460 .head_state3 = 0x0b,
3461 .head_state4 = 0x0d,
3462 .head_state5 = 0x0f,
3463 .pll0 = 0x17,
3464 .pll1 = 0x18,
3465 .pll2 = 0x19,
3466 .pll3 = 0x1a,
3467 .dp_padctl0 = 0x5c,
3468 .dp_padctl2 = 0x73,
3469};
3470
3471static const u8 tegra210_sor_xbar_cfg[5] = {
3472 2, 1, 0, 3, 4
3473};
3474
3475static const u8 tegra210_sor_lane_map[4] = {
3476 0, 1, 2, 3,
3477};
3478
3479static const struct tegra_sor_soc tegra210_sor = {
3480 .supports_lvds = false,
3481 .supports_hdmi = false,
3482 .supports_dp = true,
3483 .supports_audio = false,
3484 .supports_hdcp = false,
3485
3486 .regs = &tegra210_sor_regs,
3487 .has_nvdisplay = false,
3488
3489 .xbar_cfg = tegra210_sor_xbar_cfg,
3490 .lane_map = tegra210_sor_lane_map,
3491 .voltage_swing = tegra124_sor_voltage_swing,
3492 .pre_emphasis = tegra124_sor_pre_emphasis,
3493 .post_cursor = tegra124_sor_post_cursor,
3494 .tx_pu = tegra124_sor_tx_pu,
3495};
3496
3497static const struct tegra_sor_soc tegra210_sor1 = {
3498 .supports_lvds = false,
3499 .supports_hdmi = true,
3500 .supports_dp = true,
3501 .supports_audio = true,
3502 .supports_hdcp = true,
3503
3504 .regs = &tegra210_sor_regs,
3505 .has_nvdisplay = false,
3506
3507 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3508 .settings = tegra210_sor_hdmi_defaults,
3509 .xbar_cfg = tegra210_sor_xbar_cfg,
3510 .lane_map = tegra210_sor_lane_map,
3511 .voltage_swing = tegra124_sor_voltage_swing,
3512 .pre_emphasis = tegra124_sor_pre_emphasis,
3513 .post_cursor = tegra124_sor_post_cursor,
3514 .tx_pu = tegra124_sor_tx_pu,
3515};
3516
3517static const struct tegra_sor_regs tegra186_sor_regs = {
3518 .head_state0 = 0x151,
3519 .head_state1 = 0x154,
3520 .head_state2 = 0x157,
3521 .head_state3 = 0x15a,
3522 .head_state4 = 0x15d,
3523 .head_state5 = 0x160,
3524 .pll0 = 0x163,
3525 .pll1 = 0x164,
3526 .pll2 = 0x165,
3527 .pll3 = 0x166,
3528 .dp_padctl0 = 0x168,
3529 .dp_padctl2 = 0x16a,
3530};
3531
3532static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3533 {
3534 { 0x13, 0x19, 0x1e, 0x28 },
3535 { 0x1e, 0x25, 0x2d, },
3536 { 0x28, 0x32, },
3537 { 0x39, },
3538 }, {
3539 { 0x12, 0x16, 0x1b, 0x25 },
3540 { 0x1c, 0x23, 0x2a, },
3541 { 0x25, 0x2f, },
3542 { 0x37, }
3543 }, {
3544 { 0x12, 0x16, 0x1a, 0x22 },
3545 { 0x1b, 0x20, 0x27, },
3546 { 0x24, 0x2d, },
3547 { 0x35, },
3548 }, {
3549 { 0x11, 0x14, 0x17, 0x1f },
3550 { 0x19, 0x1e, 0x24, },
3551 { 0x22, 0x2a, },
3552 { 0x32, },
3553 },
3554};
3555
3556static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3557 {
3558 { 0x00, 0x08, 0x12, 0x24 },
3559 { 0x01, 0x0e, 0x1d, },
3560 { 0x01, 0x13, },
3561 { 0x00, },
3562 }, {
3563 { 0x00, 0x08, 0x12, 0x24 },
3564 { 0x00, 0x0e, 0x1d, },
3565 { 0x00, 0x13, },
3566 { 0x00 },
3567 }, {
3568 { 0x00, 0x08, 0x14, 0x24 },
3569 { 0x00, 0x0e, 0x1d, },
3570 { 0x00, 0x13, },
3571 { 0x00, },
3572 }, {
3573 { 0x00, 0x08, 0x12, 0x24 },
3574 { 0x00, 0x0e, 0x1d, },
3575 { 0x00, 0x13, },
3576 { 0x00, },
3577 },
3578};
3579
3580static const struct tegra_sor_soc tegra186_sor = {
3581 .supports_lvds = false,
3582 .supports_hdmi = true,
3583 .supports_dp = true,
3584 .supports_audio = true,
3585 .supports_hdcp = true,
3586
3587 .regs = &tegra186_sor_regs,
3588 .has_nvdisplay = true,
3589
3590 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3591 .settings = tegra186_sor_hdmi_defaults,
3592 .xbar_cfg = tegra124_sor_xbar_cfg,
3593 .lane_map = tegra124_sor_lane_map,
3594 .voltage_swing = tegra186_sor_voltage_swing,
3595 .pre_emphasis = tegra186_sor_pre_emphasis,
3596 .post_cursor = tegra124_sor_post_cursor,
3597 .tx_pu = tegra124_sor_tx_pu,
3598};
3599
3600static const struct tegra_sor_regs tegra194_sor_regs = {
3601 .head_state0 = 0x151,
3602 .head_state1 = 0x155,
3603 .head_state2 = 0x159,
3604 .head_state3 = 0x15d,
3605 .head_state4 = 0x161,
3606 .head_state5 = 0x165,
3607 .pll0 = 0x169,
3608 .pll1 = 0x16a,
3609 .pll2 = 0x16b,
3610 .pll3 = 0x16c,
3611 .dp_padctl0 = 0x16e,
3612 .dp_padctl2 = 0x16f,
3613};
3614
3615static const struct tegra_sor_soc tegra194_sor = {
3616 .supports_lvds = false,
3617 .supports_hdmi = true,
3618 .supports_dp = true,
3619 .supports_audio = true,
3620 .supports_hdcp = true,
3621
3622 .regs = &tegra194_sor_regs,
3623 .has_nvdisplay = true,
3624
3625 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3626 .settings = tegra194_sor_hdmi_defaults,
3627
3628 .xbar_cfg = tegra210_sor_xbar_cfg,
3629 .lane_map = tegra124_sor_lane_map,
3630 .voltage_swing = tegra186_sor_voltage_swing,
3631 .pre_emphasis = tegra186_sor_pre_emphasis,
3632 .post_cursor = tegra124_sor_post_cursor,
3633 .tx_pu = tegra124_sor_tx_pu,
3634};
3635
3636static const struct of_device_id tegra_sor_of_match[] = {
3637 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3638 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3639 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3640 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3641 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3642 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3643 { },
3644};
3645MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3646
3647static int tegra_sor_parse_dt(struct tegra_sor *sor)
3648{
3649 struct device_node *np = sor->dev->of_node;
3650 u32 xbar_cfg[5];
3651 unsigned int i;
3652 u32 value;
3653 int err;
3654
3655 if (sor->soc->has_nvdisplay) {
3656 err = of_property_read_u32(np, "nvidia,interface", &value);
3657 if (err < 0)
3658 return err;
3659
3660 sor->index = value;
3661
3662 /*
3663 * override the default that we already set for Tegra210 and
3664 * earlier
3665 */
3666 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3667 } else {
3668 if (!sor->soc->supports_audio)
3669 sor->index = 0;
3670 else
3671 sor->index = 1;
3672 }
3673
3674 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3675 if (err < 0) {
3676 /* fall back to default per-SoC XBAR configuration */
3677 for (i = 0; i < 5; i++)
3678 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3679 } else {
3680 /* copy cells to SOR XBAR configuration */
3681 for (i = 0; i < 5; i++)
3682 sor->xbar_cfg[i] = xbar_cfg[i];
3683 }
3684
3685 return 0;
3686}
3687
3688static irqreturn_t tegra_sor_irq(int irq, void *data)
3689{
3690 struct tegra_sor *sor = data;
3691 u32 value;
3692
3693 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3694 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3695
3696 if (value & SOR_INT_CODEC_SCRATCH0) {
3697 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3698
3699 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3700 unsigned int format;
3701
3702 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3703
3704 tegra_hda_parse_format(format, &sor->format);
3705
3706 if (sor->ops->audio_enable)
3707 sor->ops->audio_enable(sor);
3708 } else {
3709 if (sor->ops->audio_disable)
3710 sor->ops->audio_disable(sor);
3711 }
3712 }
3713
3714 return IRQ_HANDLED;
3715}
3716
3717static int tegra_sor_probe(struct platform_device *pdev)
3718{
3719 struct device_node *np;
3720 struct tegra_sor *sor;
3721 struct resource *regs;
3722 int err;
3723
3724 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3725 if (!sor)
3726 return -ENOMEM;
3727
3728 sor->soc = of_device_get_match_data(&pdev->dev);
3729 sor->output.dev = sor->dev = &pdev->dev;
3730
3731 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3732 sor->soc->num_settings *
3733 sizeof(*sor->settings),
3734 GFP_KERNEL);
3735 if (!sor->settings)
3736 return -ENOMEM;
3737
3738 sor->num_settings = sor->soc->num_settings;
3739
3740 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3741 if (np) {
3742 sor->aux = drm_dp_aux_find_by_of_node(np);
3743 of_node_put(np);
3744
3745 if (!sor->aux)
3746 return -EPROBE_DEFER;
3747
3748 if (get_device(sor->aux->dev))
3749 sor->output.ddc = &sor->aux->ddc;
3750 }
3751
3752 if (!sor->aux) {
3753 if (sor->soc->supports_hdmi) {
3754 sor->ops = &tegra_sor_hdmi_ops;
3755 sor->pad = TEGRA_IO_PAD_HDMI;
3756 } else if (sor->soc->supports_lvds) {
3757 dev_err(&pdev->dev, "LVDS not supported yet\n");
3758 return -ENODEV;
3759 } else {
3760 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3761 return -ENODEV;
3762 }
3763 } else {
3764 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3765 /*
3766 * No need to keep this around since we only use it as a check
3767 * to see if a panel is connected (eDP) or not (DP).
3768 */
3769 of_node_put(np);
3770
3771 sor->ops = &tegra_sor_dp_ops;
3772 sor->pad = TEGRA_IO_PAD_LVDS;
3773 }
3774
3775 err = tegra_sor_parse_dt(sor);
3776 if (err < 0)
3777 goto put_aux;
3778
3779 err = tegra_output_probe(&sor->output);
3780 if (err < 0) {
3781 dev_err_probe(&pdev->dev, err, "failed to probe output\n");
3782 goto put_aux;
3783 }
3784
3785 if (sor->ops && sor->ops->probe) {
3786 err = sor->ops->probe(sor);
3787 if (err < 0) {
3788 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3789 sor->ops->name, err);
3790 goto remove;
3791 }
3792 }
3793
3794 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3795 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3796 if (IS_ERR(sor->regs)) {
3797 err = PTR_ERR(sor->regs);
3798 goto remove;
3799 }
3800
3801 err = platform_get_irq(pdev, 0);
3802 if (err < 0) {
3803 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3804 goto remove;
3805 }
3806
3807 sor->irq = err;
3808
3809 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3810 dev_name(sor->dev), sor);
3811 if (err < 0) {
3812 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3813 goto remove;
3814 }
3815
3816 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3817 if (IS_ERR(sor->rst)) {
3818 err = PTR_ERR(sor->rst);
3819
3820 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3821 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3822 err);
3823 goto remove;
3824 }
3825
3826 /*
3827 * At this point, the reset control is most likely being used
3828 * by the generic power domain implementation. With any luck
3829 * the power domain will have taken care of resetting the SOR
3830 * and we don't have to do anything.
3831 */
3832 sor->rst = NULL;
3833 }
3834
3835 sor->clk = devm_clk_get(&pdev->dev, NULL);
3836 if (IS_ERR(sor->clk)) {
3837 err = PTR_ERR(sor->clk);
3838 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3839 goto remove;
3840 }
3841
3842 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3843 struct device_node *np = pdev->dev.of_node;
3844 const char *name;
3845
3846 /*
3847 * For backwards compatibility with Tegra210 device trees,
3848 * fall back to the old clock name "source" if the new "out"
3849 * clock is not available.
3850 */
3851 if (of_property_match_string(np, "clock-names", "out") < 0)
3852 name = "source";
3853 else
3854 name = "out";
3855
3856 sor->clk_out = devm_clk_get(&pdev->dev, name);
3857 if (IS_ERR(sor->clk_out)) {
3858 err = PTR_ERR(sor->clk_out);
3859 dev_err(sor->dev, "failed to get %s clock: %d\n",
3860 name, err);
3861 goto remove;
3862 }
3863 } else {
3864 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3865 sor->clk_out = sor->clk;
3866 }
3867
3868 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3869 if (IS_ERR(sor->clk_parent)) {
3870 err = PTR_ERR(sor->clk_parent);
3871 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3872 goto remove;
3873 }
3874
3875 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3876 if (IS_ERR(sor->clk_safe)) {
3877 err = PTR_ERR(sor->clk_safe);
3878 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3879 goto remove;
3880 }
3881
3882 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3883 if (IS_ERR(sor->clk_dp)) {
3884 err = PTR_ERR(sor->clk_dp);
3885 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3886 goto remove;
3887 }
3888
3889 /*
3890 * Starting with Tegra186, the BPMP provides an implementation for
3891 * the pad output clock, so we have to look it up from device tree.
3892 */
3893 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3894 if (IS_ERR(sor->clk_pad)) {
3895 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3896 err = PTR_ERR(sor->clk_pad);
3897 goto remove;
3898 }
3899
3900 /*
3901 * If the pad output clock is not available, then we assume
3902 * we're on Tegra210 or earlier and have to provide our own
3903 * implementation.
3904 */
3905 sor->clk_pad = NULL;
3906 }
3907
3908 /*
3909 * The bootloader may have set up the SOR such that it's module clock
3910 * is sourced by one of the display PLLs. However, that doesn't work
3911 * without properly having set up other bits of the SOR.
3912 */
3913 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3914 if (err < 0) {
3915 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3916 goto remove;
3917 }
3918
3919 platform_set_drvdata(pdev, sor);
3920 pm_runtime_enable(&pdev->dev);
3921
3922 host1x_client_init(&sor->client);
3923 sor->client.ops = &sor_client_ops;
3924 sor->client.dev = &pdev->dev;
3925
3926 /*
3927 * On Tegra210 and earlier, provide our own implementation for the
3928 * pad output clock.
3929 */
3930 if (!sor->clk_pad) {
3931 char *name;
3932
3933 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3934 sor->index);
3935 if (!name) {
3936 err = -ENOMEM;
3937 goto uninit;
3938 }
3939
3940 err = host1x_client_resume(&sor->client);
3941 if (err < 0) {
3942 dev_err(sor->dev, "failed to resume: %d\n", err);
3943 goto uninit;
3944 }
3945
3946 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3947 host1x_client_suspend(&sor->client);
3948 }
3949
3950 if (IS_ERR(sor->clk_pad)) {
3951 err = PTR_ERR(sor->clk_pad);
3952 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3953 err);
3954 goto uninit;
3955 }
3956
3957 err = __host1x_client_register(&sor->client);
3958 if (err < 0) {
3959 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3960 err);
3961 goto uninit;
3962 }
3963
3964 return 0;
3965
3966uninit:
3967 host1x_client_exit(&sor->client);
3968 pm_runtime_disable(&pdev->dev);
3969remove:
3970 if (sor->aux)
3971 sor->output.ddc = NULL;
3972
3973 tegra_output_remove(&sor->output);
3974put_aux:
3975 if (sor->aux)
3976 put_device(sor->aux->dev);
3977
3978 return err;
3979}
3980
3981static int tegra_sor_remove(struct platform_device *pdev)
3982{
3983 struct tegra_sor *sor = platform_get_drvdata(pdev);
3984 int err;
3985
3986 err = host1x_client_unregister(&sor->client);
3987 if (err < 0) {
3988 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3989 err);
3990 return err;
3991 }
3992
3993 pm_runtime_disable(&pdev->dev);
3994
3995 if (sor->aux) {
3996 put_device(sor->aux->dev);
3997 sor->output.ddc = NULL;
3998 }
3999
4000 tegra_output_remove(&sor->output);
4001
4002 return 0;
4003}
4004
4005static int __maybe_unused tegra_sor_suspend(struct device *dev)
4006{
4007 struct tegra_sor *sor = dev_get_drvdata(dev);
4008 int err;
4009
4010 err = tegra_output_suspend(&sor->output);
4011 if (err < 0) {
4012 dev_err(dev, "failed to suspend output: %d\n", err);
4013 return err;
4014 }
4015
4016 if (sor->hdmi_supply) {
4017 err = regulator_disable(sor->hdmi_supply);
4018 if (err < 0) {
4019 tegra_output_resume(&sor->output);
4020 return err;
4021 }
4022 }
4023
4024 return 0;
4025}
4026
4027static int __maybe_unused tegra_sor_resume(struct device *dev)
4028{
4029 struct tegra_sor *sor = dev_get_drvdata(dev);
4030 int err;
4031
4032 if (sor->hdmi_supply) {
4033 err = regulator_enable(sor->hdmi_supply);
4034 if (err < 0)
4035 return err;
4036 }
4037
4038 err = tegra_output_resume(&sor->output);
4039 if (err < 0) {
4040 dev_err(dev, "failed to resume output: %d\n", err);
4041
4042 if (sor->hdmi_supply)
4043 regulator_disable(sor->hdmi_supply);
4044
4045 return err;
4046 }
4047
4048 return 0;
4049}
4050
4051static const struct dev_pm_ops tegra_sor_pm_ops = {
4052 SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4053};
4054
4055struct platform_driver tegra_sor_driver = {
4056 .driver = {
4057 .name = "tegra-sor",
4058 .of_match_table = tegra_sor_of_match,
4059 .pm = &tegra_sor_pm_ops,
4060 },
4061 .probe = tegra_sor_probe,
4062 .remove = tegra_sor_remove,
4063};