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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4
5#include <linux/clk.h>
6#include <linux/reset.h>
7#include <linux/platform_device.h>
8#include <linux/pm_domain.h>
9#include <linux/pm_runtime.h>
10#include <linux/regulator/consumer.h>
11
12#include "panfrost_device.h"
13#include "panfrost_devfreq.h"
14#include "panfrost_features.h"
15#include "panfrost_issues.h"
16#include "panfrost_gpu.h"
17#include "panfrost_job.h"
18#include "panfrost_mmu.h"
19#include "panfrost_perfcnt.h"
20
21static int panfrost_reset_init(struct panfrost_device *pfdev)
22{
23 pfdev->rstc = devm_reset_control_array_get_optional_exclusive(pfdev->dev);
24 if (IS_ERR(pfdev->rstc)) {
25 dev_err(pfdev->dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc));
26 return PTR_ERR(pfdev->rstc);
27 }
28
29 return reset_control_deassert(pfdev->rstc);
30}
31
32static void panfrost_reset_fini(struct panfrost_device *pfdev)
33{
34 reset_control_assert(pfdev->rstc);
35}
36
37static int panfrost_clk_init(struct panfrost_device *pfdev)
38{
39 int err;
40 unsigned long rate;
41
42 pfdev->clock = devm_clk_get(pfdev->dev, NULL);
43 if (IS_ERR(pfdev->clock)) {
44 dev_err(pfdev->dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock));
45 return PTR_ERR(pfdev->clock);
46 }
47
48 rate = clk_get_rate(pfdev->clock);
49 dev_info(pfdev->dev, "clock rate = %lu\n", rate);
50
51 err = clk_prepare_enable(pfdev->clock);
52 if (err)
53 return err;
54
55 pfdev->bus_clock = devm_clk_get_optional(pfdev->dev, "bus");
56 if (IS_ERR(pfdev->bus_clock)) {
57 dev_err(pfdev->dev, "get bus_clock failed %ld\n",
58 PTR_ERR(pfdev->bus_clock));
59 err = PTR_ERR(pfdev->bus_clock);
60 goto disable_clock;
61 }
62
63 if (pfdev->bus_clock) {
64 rate = clk_get_rate(pfdev->bus_clock);
65 dev_info(pfdev->dev, "bus_clock rate = %lu\n", rate);
66
67 err = clk_prepare_enable(pfdev->bus_clock);
68 if (err)
69 goto disable_clock;
70 }
71
72 return 0;
73
74disable_clock:
75 clk_disable_unprepare(pfdev->clock);
76
77 return err;
78}
79
80static void panfrost_clk_fini(struct panfrost_device *pfdev)
81{
82 clk_disable_unprepare(pfdev->bus_clock);
83 clk_disable_unprepare(pfdev->clock);
84}
85
86static int panfrost_regulator_init(struct panfrost_device *pfdev)
87{
88 int ret, i;
89
90 pfdev->regulators = devm_kcalloc(pfdev->dev, pfdev->comp->num_supplies,
91 sizeof(*pfdev->regulators),
92 GFP_KERNEL);
93 if (!pfdev->regulators)
94 return -ENOMEM;
95
96 for (i = 0; i < pfdev->comp->num_supplies; i++)
97 pfdev->regulators[i].supply = pfdev->comp->supply_names[i];
98
99 ret = devm_regulator_bulk_get(pfdev->dev,
100 pfdev->comp->num_supplies,
101 pfdev->regulators);
102 if (ret < 0) {
103 if (ret != -EPROBE_DEFER)
104 dev_err(pfdev->dev, "failed to get regulators: %d\n",
105 ret);
106 return ret;
107 }
108
109 ret = regulator_bulk_enable(pfdev->comp->num_supplies,
110 pfdev->regulators);
111 if (ret < 0) {
112 dev_err(pfdev->dev, "failed to enable regulators: %d\n", ret);
113 return ret;
114 }
115
116 return 0;
117}
118
119static void panfrost_regulator_fini(struct panfrost_device *pfdev)
120{
121 if (!pfdev->regulators)
122 return;
123
124 regulator_bulk_disable(pfdev->comp->num_supplies, pfdev->regulators);
125}
126
127static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
128{
129 int i;
130
131 for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
132 if (!pfdev->pm_domain_devs[i])
133 break;
134
135 if (pfdev->pm_domain_links[i])
136 device_link_del(pfdev->pm_domain_links[i]);
137
138 dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
139 }
140}
141
142static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
143{
144 int err;
145 int i, num_domains;
146
147 num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
148 "power-domains",
149 "#power-domain-cells");
150
151 /*
152 * Single domain is handled by the core, and, if only a single power
153 * the power domain is requested, the property is optional.
154 */
155 if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
156 return 0;
157
158 if (num_domains != pfdev->comp->num_pm_domains) {
159 dev_err(pfdev->dev,
160 "Incorrect number of power domains: %d provided, %d needed\n",
161 num_domains, pfdev->comp->num_pm_domains);
162 return -EINVAL;
163 }
164
165 if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
166 "Too many supplies in compatible structure.\n"))
167 return -EINVAL;
168
169 for (i = 0; i < num_domains; i++) {
170 pfdev->pm_domain_devs[i] =
171 dev_pm_domain_attach_by_name(pfdev->dev,
172 pfdev->comp->pm_domain_names[i]);
173 if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
174 err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
175 pfdev->pm_domain_devs[i] = NULL;
176 dev_err(pfdev->dev,
177 "failed to get pm-domain %s(%d): %d\n",
178 pfdev->comp->pm_domain_names[i], i, err);
179 goto err;
180 }
181
182 pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
183 pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
184 DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
185 if (!pfdev->pm_domain_links[i]) {
186 dev_err(pfdev->pm_domain_devs[i],
187 "adding device link failed!\n");
188 err = -ENODEV;
189 goto err;
190 }
191 }
192
193 return 0;
194
195err:
196 panfrost_pm_domain_fini(pfdev);
197 return err;
198}
199
200int panfrost_device_init(struct panfrost_device *pfdev)
201{
202 int err;
203
204 mutex_init(&pfdev->sched_lock);
205 INIT_LIST_HEAD(&pfdev->scheduled_jobs);
206 INIT_LIST_HEAD(&pfdev->as_lru_list);
207
208 spin_lock_init(&pfdev->as_lock);
209
210 spin_lock_init(&pfdev->cycle_counter.lock);
211
212 err = panfrost_clk_init(pfdev);
213 if (err) {
214 dev_err(pfdev->dev, "clk init failed %d\n", err);
215 return err;
216 }
217
218 err = panfrost_devfreq_init(pfdev);
219 if (err) {
220 if (err != -EPROBE_DEFER)
221 dev_err(pfdev->dev, "devfreq init failed %d\n", err);
222 goto out_clk;
223 }
224
225 /* OPP will handle regulators */
226 if (!pfdev->pfdevfreq.opp_of_table_added) {
227 err = panfrost_regulator_init(pfdev);
228 if (err)
229 goto out_devfreq;
230 }
231
232 err = panfrost_reset_init(pfdev);
233 if (err) {
234 dev_err(pfdev->dev, "reset init failed %d\n", err);
235 goto out_regulator;
236 }
237
238 err = panfrost_pm_domain_init(pfdev);
239 if (err)
240 goto out_reset;
241
242 pfdev->iomem = devm_platform_ioremap_resource(pfdev->pdev, 0);
243 if (IS_ERR(pfdev->iomem)) {
244 err = PTR_ERR(pfdev->iomem);
245 goto out_pm_domain;
246 }
247
248 err = panfrost_gpu_init(pfdev);
249 if (err)
250 goto out_pm_domain;
251
252 err = panfrost_mmu_init(pfdev);
253 if (err)
254 goto out_gpu;
255
256 err = panfrost_job_init(pfdev);
257 if (err)
258 goto out_mmu;
259
260 err = panfrost_perfcnt_init(pfdev);
261 if (err)
262 goto out_job;
263
264 return 0;
265out_job:
266 panfrost_job_fini(pfdev);
267out_mmu:
268 panfrost_mmu_fini(pfdev);
269out_gpu:
270 panfrost_gpu_fini(pfdev);
271out_pm_domain:
272 panfrost_pm_domain_fini(pfdev);
273out_reset:
274 panfrost_reset_fini(pfdev);
275out_regulator:
276 panfrost_regulator_fini(pfdev);
277out_devfreq:
278 panfrost_devfreq_fini(pfdev);
279out_clk:
280 panfrost_clk_fini(pfdev);
281 return err;
282}
283
284void panfrost_device_fini(struct panfrost_device *pfdev)
285{
286 panfrost_perfcnt_fini(pfdev);
287 panfrost_job_fini(pfdev);
288 panfrost_mmu_fini(pfdev);
289 panfrost_gpu_fini(pfdev);
290 panfrost_pm_domain_fini(pfdev);
291 panfrost_reset_fini(pfdev);
292 panfrost_devfreq_fini(pfdev);
293 panfrost_regulator_fini(pfdev);
294 panfrost_clk_fini(pfdev);
295}
296
297#define PANFROST_EXCEPTION(id) \
298 [DRM_PANFROST_EXCEPTION_ ## id] = { \
299 .name = #id, \
300 }
301
302struct panfrost_exception_info {
303 const char *name;
304};
305
306static const struct panfrost_exception_info panfrost_exception_infos[] = {
307 PANFROST_EXCEPTION(OK),
308 PANFROST_EXCEPTION(DONE),
309 PANFROST_EXCEPTION(INTERRUPTED),
310 PANFROST_EXCEPTION(STOPPED),
311 PANFROST_EXCEPTION(TERMINATED),
312 PANFROST_EXCEPTION(KABOOM),
313 PANFROST_EXCEPTION(EUREKA),
314 PANFROST_EXCEPTION(ACTIVE),
315 PANFROST_EXCEPTION(JOB_CONFIG_FAULT),
316 PANFROST_EXCEPTION(JOB_POWER_FAULT),
317 PANFROST_EXCEPTION(JOB_READ_FAULT),
318 PANFROST_EXCEPTION(JOB_WRITE_FAULT),
319 PANFROST_EXCEPTION(JOB_AFFINITY_FAULT),
320 PANFROST_EXCEPTION(JOB_BUS_FAULT),
321 PANFROST_EXCEPTION(INSTR_INVALID_PC),
322 PANFROST_EXCEPTION(INSTR_INVALID_ENC),
323 PANFROST_EXCEPTION(INSTR_TYPE_MISMATCH),
324 PANFROST_EXCEPTION(INSTR_OPERAND_FAULT),
325 PANFROST_EXCEPTION(INSTR_TLS_FAULT),
326 PANFROST_EXCEPTION(INSTR_BARRIER_FAULT),
327 PANFROST_EXCEPTION(INSTR_ALIGN_FAULT),
328 PANFROST_EXCEPTION(DATA_INVALID_FAULT),
329 PANFROST_EXCEPTION(TILE_RANGE_FAULT),
330 PANFROST_EXCEPTION(ADDR_RANGE_FAULT),
331 PANFROST_EXCEPTION(IMPRECISE_FAULT),
332 PANFROST_EXCEPTION(OOM),
333 PANFROST_EXCEPTION(OOM_AFBC),
334 PANFROST_EXCEPTION(UNKNOWN),
335 PANFROST_EXCEPTION(DELAYED_BUS_FAULT),
336 PANFROST_EXCEPTION(GPU_SHAREABILITY_FAULT),
337 PANFROST_EXCEPTION(SYS_SHAREABILITY_FAULT),
338 PANFROST_EXCEPTION(GPU_CACHEABILITY_FAULT),
339 PANFROST_EXCEPTION(TRANSLATION_FAULT_0),
340 PANFROST_EXCEPTION(TRANSLATION_FAULT_1),
341 PANFROST_EXCEPTION(TRANSLATION_FAULT_2),
342 PANFROST_EXCEPTION(TRANSLATION_FAULT_3),
343 PANFROST_EXCEPTION(TRANSLATION_FAULT_4),
344 PANFROST_EXCEPTION(TRANSLATION_FAULT_IDENTITY),
345 PANFROST_EXCEPTION(PERM_FAULT_0),
346 PANFROST_EXCEPTION(PERM_FAULT_1),
347 PANFROST_EXCEPTION(PERM_FAULT_2),
348 PANFROST_EXCEPTION(PERM_FAULT_3),
349 PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_0),
350 PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_1),
351 PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_2),
352 PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_3),
353 PANFROST_EXCEPTION(ACCESS_FLAG_0),
354 PANFROST_EXCEPTION(ACCESS_FLAG_1),
355 PANFROST_EXCEPTION(ACCESS_FLAG_2),
356 PANFROST_EXCEPTION(ACCESS_FLAG_3),
357 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN0),
358 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN1),
359 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN2),
360 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN3),
361 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT0),
362 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT1),
363 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT2),
364 PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT3),
365 PANFROST_EXCEPTION(MEM_ATTR_FAULT_0),
366 PANFROST_EXCEPTION(MEM_ATTR_FAULT_1),
367 PANFROST_EXCEPTION(MEM_ATTR_FAULT_2),
368 PANFROST_EXCEPTION(MEM_ATTR_FAULT_3),
369 PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_0),
370 PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_1),
371 PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_2),
372 PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_3),
373};
374
375const char *panfrost_exception_name(u32 exception_code)
376{
377 if (WARN_ON(exception_code >= ARRAY_SIZE(panfrost_exception_infos) ||
378 !panfrost_exception_infos[exception_code].name))
379 return "Unknown exception type";
380
381 return panfrost_exception_infos[exception_code].name;
382}
383
384bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
385 u32 exception_code)
386{
387 /* If an occlusion query write causes a bus fault on affected GPUs,
388 * future fragment jobs may hang. Reset to workaround.
389 */
390 if (exception_code == DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT)
391 return panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_3076);
392
393 /* No other GPUs we support need a reset */
394 return false;
395}
396
397void panfrost_device_reset(struct panfrost_device *pfdev)
398{
399 panfrost_gpu_soft_reset(pfdev);
400
401 panfrost_gpu_power_on(pfdev);
402 panfrost_mmu_reset(pfdev);
403 panfrost_job_enable_interrupts(pfdev);
404}
405
406static int panfrost_device_runtime_resume(struct device *dev)
407{
408 struct panfrost_device *pfdev = dev_get_drvdata(dev);
409
410 panfrost_device_reset(pfdev);
411 panfrost_devfreq_resume(pfdev);
412
413 return 0;
414}
415
416static int panfrost_device_runtime_suspend(struct device *dev)
417{
418 struct panfrost_device *pfdev = dev_get_drvdata(dev);
419
420 if (!panfrost_job_is_idle(pfdev))
421 return -EBUSY;
422
423 panfrost_devfreq_suspend(pfdev);
424 panfrost_job_suspend_irq(pfdev);
425 panfrost_mmu_suspend_irq(pfdev);
426 panfrost_gpu_suspend_irq(pfdev);
427 panfrost_gpu_power_off(pfdev);
428
429 return 0;
430}
431
432static int panfrost_device_resume(struct device *dev)
433{
434 struct panfrost_device *pfdev = dev_get_drvdata(dev);
435 int ret;
436
437 if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) {
438 unsigned long freq = pfdev->pfdevfreq.fast_rate;
439 struct dev_pm_opp *opp;
440
441 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
442 if (IS_ERR(opp))
443 return PTR_ERR(opp);
444 dev_pm_opp_set_opp(dev, opp);
445 dev_pm_opp_put(opp);
446 }
447
448 if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) {
449 ret = clk_enable(pfdev->clock);
450 if (ret)
451 goto err_clk;
452
453 if (pfdev->bus_clock) {
454 ret = clk_enable(pfdev->bus_clock);
455 if (ret)
456 goto err_bus_clk;
457 }
458 }
459
460 ret = pm_runtime_force_resume(dev);
461 if (ret)
462 goto err_resume;
463
464 return 0;
465
466err_resume:
467 if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS) && pfdev->bus_clock)
468 clk_disable(pfdev->bus_clock);
469err_bus_clk:
470 if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS))
471 clk_disable(pfdev->clock);
472err_clk:
473 if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF))
474 dev_pm_opp_set_opp(dev, NULL);
475 return ret;
476}
477
478static int panfrost_device_suspend(struct device *dev)
479{
480 struct panfrost_device *pfdev = dev_get_drvdata(dev);
481 int ret;
482
483 ret = pm_runtime_force_suspend(dev);
484 if (ret)
485 return ret;
486
487 if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) {
488 if (pfdev->bus_clock)
489 clk_disable(pfdev->bus_clock);
490
491 clk_disable(pfdev->clock);
492 }
493
494 if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF))
495 dev_pm_opp_set_opp(dev, NULL);
496
497 return 0;
498}
499
500EXPORT_GPL_DEV_PM_OPS(panfrost_pm_ops) = {
501 RUNTIME_PM_OPS(panfrost_device_runtime_suspend, panfrost_device_runtime_resume, NULL)
502 SYSTEM_SLEEP_PM_OPS(panfrost_device_suspend, panfrost_device_resume)
503};
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4
5#include <linux/clk.h>
6#include <linux/reset.h>
7#include <linux/platform_device.h>
8#include <linux/pm_domain.h>
9#include <linux/regulator/consumer.h>
10
11#include "panfrost_device.h"
12#include "panfrost_devfreq.h"
13#include "panfrost_features.h"
14#include "panfrost_gpu.h"
15#include "panfrost_job.h"
16#include "panfrost_mmu.h"
17#include "panfrost_perfcnt.h"
18
19static int panfrost_reset_init(struct panfrost_device *pfdev)
20{
21 pfdev->rstc = devm_reset_control_array_get_optional_exclusive(pfdev->dev);
22 if (IS_ERR(pfdev->rstc)) {
23 dev_err(pfdev->dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc));
24 return PTR_ERR(pfdev->rstc);
25 }
26
27 return reset_control_deassert(pfdev->rstc);
28}
29
30static void panfrost_reset_fini(struct panfrost_device *pfdev)
31{
32 reset_control_assert(pfdev->rstc);
33}
34
35static int panfrost_clk_init(struct panfrost_device *pfdev)
36{
37 int err;
38 unsigned long rate;
39
40 pfdev->clock = devm_clk_get(pfdev->dev, NULL);
41 if (IS_ERR(pfdev->clock)) {
42 dev_err(pfdev->dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock));
43 return PTR_ERR(pfdev->clock);
44 }
45
46 rate = clk_get_rate(pfdev->clock);
47 dev_info(pfdev->dev, "clock rate = %lu\n", rate);
48
49 err = clk_prepare_enable(pfdev->clock);
50 if (err)
51 return err;
52
53 pfdev->bus_clock = devm_clk_get_optional(pfdev->dev, "bus");
54 if (IS_ERR(pfdev->bus_clock)) {
55 dev_err(pfdev->dev, "get bus_clock failed %ld\n",
56 PTR_ERR(pfdev->bus_clock));
57 err = PTR_ERR(pfdev->bus_clock);
58 goto disable_clock;
59 }
60
61 if (pfdev->bus_clock) {
62 rate = clk_get_rate(pfdev->bus_clock);
63 dev_info(pfdev->dev, "bus_clock rate = %lu\n", rate);
64
65 err = clk_prepare_enable(pfdev->bus_clock);
66 if (err)
67 goto disable_clock;
68 }
69
70 return 0;
71
72disable_clock:
73 clk_disable_unprepare(pfdev->clock);
74
75 return err;
76}
77
78static void panfrost_clk_fini(struct panfrost_device *pfdev)
79{
80 clk_disable_unprepare(pfdev->bus_clock);
81 clk_disable_unprepare(pfdev->clock);
82}
83
84static int panfrost_regulator_init(struct panfrost_device *pfdev)
85{
86 int ret, i;
87
88 pfdev->regulators = devm_kcalloc(pfdev->dev, pfdev->comp->num_supplies,
89 sizeof(*pfdev->regulators),
90 GFP_KERNEL);
91 if (!pfdev->regulators)
92 return -ENOMEM;
93
94 for (i = 0; i < pfdev->comp->num_supplies; i++)
95 pfdev->regulators[i].supply = pfdev->comp->supply_names[i];
96
97 ret = devm_regulator_bulk_get(pfdev->dev,
98 pfdev->comp->num_supplies,
99 pfdev->regulators);
100 if (ret < 0) {
101 if (ret != -EPROBE_DEFER)
102 dev_err(pfdev->dev, "failed to get regulators: %d\n",
103 ret);
104 return ret;
105 }
106
107 ret = regulator_bulk_enable(pfdev->comp->num_supplies,
108 pfdev->regulators);
109 if (ret < 0) {
110 dev_err(pfdev->dev, "failed to enable regulators: %d\n", ret);
111 return ret;
112 }
113
114 return 0;
115}
116
117static void panfrost_regulator_fini(struct panfrost_device *pfdev)
118{
119 if (!pfdev->regulators)
120 return;
121
122 regulator_bulk_disable(pfdev->comp->num_supplies, pfdev->regulators);
123}
124
125static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
126{
127 int i;
128
129 for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
130 if (!pfdev->pm_domain_devs[i])
131 break;
132
133 if (pfdev->pm_domain_links[i])
134 device_link_del(pfdev->pm_domain_links[i]);
135
136 dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
137 }
138}
139
140static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
141{
142 int err;
143 int i, num_domains;
144
145 num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
146 "power-domains",
147 "#power-domain-cells");
148
149 /*
150 * Single domain is handled by the core, and, if only a single power
151 * the power domain is requested, the property is optional.
152 */
153 if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
154 return 0;
155
156 if (num_domains != pfdev->comp->num_pm_domains) {
157 dev_err(pfdev->dev,
158 "Incorrect number of power domains: %d provided, %d needed\n",
159 num_domains, pfdev->comp->num_pm_domains);
160 return -EINVAL;
161 }
162
163 if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
164 "Too many supplies in compatible structure.\n"))
165 return -EINVAL;
166
167 for (i = 0; i < num_domains; i++) {
168 pfdev->pm_domain_devs[i] =
169 dev_pm_domain_attach_by_name(pfdev->dev,
170 pfdev->comp->pm_domain_names[i]);
171 if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
172 err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
173 pfdev->pm_domain_devs[i] = NULL;
174 dev_err(pfdev->dev,
175 "failed to get pm-domain %s(%d): %d\n",
176 pfdev->comp->pm_domain_names[i], i, err);
177 goto err;
178 }
179
180 pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
181 pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
182 DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
183 if (!pfdev->pm_domain_links[i]) {
184 dev_err(pfdev->pm_domain_devs[i],
185 "adding device link failed!\n");
186 err = -ENODEV;
187 goto err;
188 }
189 }
190
191 return 0;
192
193err:
194 panfrost_pm_domain_fini(pfdev);
195 return err;
196}
197
198int panfrost_device_init(struct panfrost_device *pfdev)
199{
200 int err;
201 struct resource *res;
202
203 mutex_init(&pfdev->sched_lock);
204 INIT_LIST_HEAD(&pfdev->scheduled_jobs);
205 INIT_LIST_HEAD(&pfdev->as_lru_list);
206
207 spin_lock_init(&pfdev->as_lock);
208
209 err = panfrost_clk_init(pfdev);
210 if (err) {
211 dev_err(pfdev->dev, "clk init failed %d\n", err);
212 return err;
213 }
214
215 err = panfrost_devfreq_init(pfdev);
216 if (err) {
217 if (err != -EPROBE_DEFER)
218 dev_err(pfdev->dev, "devfreq init failed %d\n", err);
219 goto out_clk;
220 }
221
222 /* OPP will handle regulators */
223 if (!pfdev->pfdevfreq.opp_of_table_added) {
224 err = panfrost_regulator_init(pfdev);
225 if (err)
226 goto out_devfreq;
227 }
228
229 err = panfrost_reset_init(pfdev);
230 if (err) {
231 dev_err(pfdev->dev, "reset init failed %d\n", err);
232 goto out_regulator;
233 }
234
235 err = panfrost_pm_domain_init(pfdev);
236 if (err)
237 goto out_reset;
238
239 res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
240 pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
241 if (IS_ERR(pfdev->iomem)) {
242 err = PTR_ERR(pfdev->iomem);
243 goto out_pm_domain;
244 }
245
246 err = panfrost_gpu_init(pfdev);
247 if (err)
248 goto out_pm_domain;
249
250 err = panfrost_mmu_init(pfdev);
251 if (err)
252 goto out_gpu;
253
254 err = panfrost_job_init(pfdev);
255 if (err)
256 goto out_mmu;
257
258 err = panfrost_perfcnt_init(pfdev);
259 if (err)
260 goto out_job;
261
262 return 0;
263out_job:
264 panfrost_job_fini(pfdev);
265out_mmu:
266 panfrost_mmu_fini(pfdev);
267out_gpu:
268 panfrost_gpu_fini(pfdev);
269out_pm_domain:
270 panfrost_pm_domain_fini(pfdev);
271out_reset:
272 panfrost_reset_fini(pfdev);
273out_regulator:
274 panfrost_regulator_fini(pfdev);
275out_devfreq:
276 panfrost_devfreq_fini(pfdev);
277out_clk:
278 panfrost_clk_fini(pfdev);
279 return err;
280}
281
282void panfrost_device_fini(struct panfrost_device *pfdev)
283{
284 panfrost_perfcnt_fini(pfdev);
285 panfrost_job_fini(pfdev);
286 panfrost_mmu_fini(pfdev);
287 panfrost_gpu_fini(pfdev);
288 panfrost_pm_domain_fini(pfdev);
289 panfrost_reset_fini(pfdev);
290 panfrost_devfreq_fini(pfdev);
291 panfrost_regulator_fini(pfdev);
292 panfrost_clk_fini(pfdev);
293}
294
295const char *panfrost_exception_name(struct panfrost_device *pfdev, u32 exception_code)
296{
297 switch (exception_code) {
298 /* Non-Fault Status code */
299 case 0x00: return "NOT_STARTED/IDLE/OK";
300 case 0x01: return "DONE";
301 case 0x02: return "INTERRUPTED";
302 case 0x03: return "STOPPED";
303 case 0x04: return "TERMINATED";
304 case 0x08: return "ACTIVE";
305 /* Job exceptions */
306 case 0x40: return "JOB_CONFIG_FAULT";
307 case 0x41: return "JOB_POWER_FAULT";
308 case 0x42: return "JOB_READ_FAULT";
309 case 0x43: return "JOB_WRITE_FAULT";
310 case 0x44: return "JOB_AFFINITY_FAULT";
311 case 0x48: return "JOB_BUS_FAULT";
312 case 0x50: return "INSTR_INVALID_PC";
313 case 0x51: return "INSTR_INVALID_ENC";
314 case 0x52: return "INSTR_TYPE_MISMATCH";
315 case 0x53: return "INSTR_OPERAND_FAULT";
316 case 0x54: return "INSTR_TLS_FAULT";
317 case 0x55: return "INSTR_BARRIER_FAULT";
318 case 0x56: return "INSTR_ALIGN_FAULT";
319 case 0x58: return "DATA_INVALID_FAULT";
320 case 0x59: return "TILE_RANGE_FAULT";
321 case 0x5A: return "ADDR_RANGE_FAULT";
322 case 0x60: return "OUT_OF_MEMORY";
323 /* GPU exceptions */
324 case 0x80: return "DELAYED_BUS_FAULT";
325 case 0x88: return "SHAREABILITY_FAULT";
326 /* MMU exceptions */
327 case 0xC1: return "TRANSLATION_FAULT_LEVEL1";
328 case 0xC2: return "TRANSLATION_FAULT_LEVEL2";
329 case 0xC3: return "TRANSLATION_FAULT_LEVEL3";
330 case 0xC4: return "TRANSLATION_FAULT_LEVEL4";
331 case 0xC8: return "PERMISSION_FAULT";
332 case 0xC9 ... 0xCF: return "PERMISSION_FAULT";
333 case 0xD1: return "TRANSTAB_BUS_FAULT_LEVEL1";
334 case 0xD2: return "TRANSTAB_BUS_FAULT_LEVEL2";
335 case 0xD3: return "TRANSTAB_BUS_FAULT_LEVEL3";
336 case 0xD4: return "TRANSTAB_BUS_FAULT_LEVEL4";
337 case 0xD8: return "ACCESS_FLAG";
338 case 0xD9 ... 0xDF: return "ACCESS_FLAG";
339 case 0xE0 ... 0xE7: return "ADDRESS_SIZE_FAULT";
340 case 0xE8 ... 0xEF: return "MEMORY_ATTRIBUTES_FAULT";
341 }
342
343 return "UNKNOWN";
344}
345
346void panfrost_device_reset(struct panfrost_device *pfdev)
347{
348 panfrost_gpu_soft_reset(pfdev);
349
350 panfrost_gpu_power_on(pfdev);
351 panfrost_mmu_reset(pfdev);
352 panfrost_job_enable_interrupts(pfdev);
353}
354
355#ifdef CONFIG_PM
356int panfrost_device_resume(struct device *dev)
357{
358 struct platform_device *pdev = to_platform_device(dev);
359 struct panfrost_device *pfdev = platform_get_drvdata(pdev);
360
361 panfrost_device_reset(pfdev);
362 panfrost_devfreq_resume(pfdev);
363
364 return 0;
365}
366
367int panfrost_device_suspend(struct device *dev)
368{
369 struct platform_device *pdev = to_platform_device(dev);
370 struct panfrost_device *pfdev = platform_get_drvdata(pdev);
371
372 if (!panfrost_job_is_idle(pfdev))
373 return -EBUSY;
374
375 panfrost_devfreq_suspend(pfdev);
376 panfrost_gpu_power_off(pfdev);
377
378 return 0;
379}
380#endif