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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28#ifndef __AST_DRV_H__
29#define __AST_DRV_H__
30
31#include <linux/io.h>
32#include <linux/types.h>
33
34#include <drm/drm_connector.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_encoder.h>
37#include <drm/drm_mode.h>
38#include <drm/drm_framebuffer.h>
39
40#include "ast_reg.h"
41
42#define DRIVER_AUTHOR "Dave Airlie"
43
44#define DRIVER_NAME "ast"
45#define DRIVER_DESC "AST"
46#define DRIVER_DATE "20120228"
47
48#define DRIVER_MAJOR 0
49#define DRIVER_MINOR 1
50#define DRIVER_PATCHLEVEL 0
51
52#define PCI_CHIP_AST2000 0x2000
53#define PCI_CHIP_AST2100 0x2010
54
55#define __AST_CHIP(__gen, __index) ((__gen) << 16 | (__index))
56
57enum ast_chip {
58 /* 1st gen */
59 AST1000 = __AST_CHIP(1, 0), // unused
60 AST2000 = __AST_CHIP(1, 1),
61 /* 2nd gen */
62 AST1100 = __AST_CHIP(2, 0),
63 AST2100 = __AST_CHIP(2, 1),
64 AST2050 = __AST_CHIP(2, 2), // unused
65 /* 3rd gen */
66 AST2200 = __AST_CHIP(3, 0),
67 AST2150 = __AST_CHIP(3, 1),
68 /* 4th gen */
69 AST2300 = __AST_CHIP(4, 0),
70 AST1300 = __AST_CHIP(4, 1),
71 AST1050 = __AST_CHIP(4, 2), // unused
72 /* 5th gen */
73 AST2400 = __AST_CHIP(5, 0),
74 AST1400 = __AST_CHIP(5, 1),
75 AST1250 = __AST_CHIP(5, 2), // unused
76 /* 6th gen */
77 AST2500 = __AST_CHIP(6, 0),
78 AST2510 = __AST_CHIP(6, 1),
79 AST2520 = __AST_CHIP(6, 2), // unused
80 /* 7th gen */
81 AST2600 = __AST_CHIP(7, 0),
82 AST2620 = __AST_CHIP(7, 1), // unused
83};
84
85#define __AST_CHIP_GEN(__chip) (((unsigned long)(__chip)) >> 16)
86
87enum ast_tx_chip {
88 AST_TX_NONE,
89 AST_TX_SIL164,
90 AST_TX_DP501,
91 AST_TX_ASTDP,
92};
93
94enum ast_config_mode {
95 ast_use_p2a,
96 ast_use_dt,
97 ast_use_defaults
98};
99
100#define AST_DRAM_512Mx16 0
101#define AST_DRAM_1Gx16 1
102#define AST_DRAM_512Mx32 2
103#define AST_DRAM_1Gx32 3
104#define AST_DRAM_2Gx16 6
105#define AST_DRAM_4Gx16 7
106#define AST_DRAM_8Gx16 8
107
108/*
109 * Hardware cursor
110 */
111
112#define AST_MAX_HWC_WIDTH 64
113#define AST_MAX_HWC_HEIGHT 64
114
115#define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
116#define AST_HWC_SIGNATURE_SIZE 32
117
118/* define for signature structure */
119#define AST_HWC_SIGNATURE_CHECKSUM 0x00
120#define AST_HWC_SIGNATURE_SizeX 0x04
121#define AST_HWC_SIGNATURE_SizeY 0x08
122#define AST_HWC_SIGNATURE_X 0x0C
123#define AST_HWC_SIGNATURE_Y 0x10
124#define AST_HWC_SIGNATURE_HOTSPOTX 0x14
125#define AST_HWC_SIGNATURE_HOTSPOTY 0x18
126
127/*
128 * Planes
129 */
130
131struct ast_plane {
132 struct drm_plane base;
133
134 void __iomem *vaddr;
135 u64 offset;
136 unsigned long size;
137};
138
139static inline struct ast_plane *to_ast_plane(struct drm_plane *plane)
140{
141 return container_of(plane, struct ast_plane, base);
142}
143
144/*
145 * Connector
146 */
147
148struct ast_connector {
149 struct drm_connector base;
150
151 enum drm_connector_status physical_status;
152};
153
154static inline struct ast_connector *
155to_ast_connector(struct drm_connector *connector)
156{
157 return container_of(connector, struct ast_connector, base);
158}
159
160/*
161 * Device
162 */
163
164struct ast_device {
165 struct drm_device base;
166
167 void __iomem *regs;
168 void __iomem *ioregs;
169 void __iomem *dp501_fw_buf;
170
171 enum ast_config_mode config_mode;
172 enum ast_chip chip;
173
174 uint32_t dram_bus_width;
175 uint32_t dram_type;
176 uint32_t mclk;
177
178 void __iomem *vram;
179 unsigned long vram_base;
180 unsigned long vram_size;
181 unsigned long vram_fb_available;
182
183 struct mutex modeset_lock; /* Protects access to modeset I/O registers in ioregs */
184
185 enum ast_tx_chip tx_chip;
186
187 struct ast_plane primary_plane;
188 struct ast_plane cursor_plane;
189 struct drm_crtc crtc;
190 union {
191 struct {
192 struct drm_encoder encoder;
193 struct ast_connector connector;
194 } vga;
195 struct {
196 struct drm_encoder encoder;
197 struct ast_connector connector;
198 } sil164;
199 struct {
200 struct drm_encoder encoder;
201 struct ast_connector connector;
202 } dp501;
203 struct {
204 struct drm_encoder encoder;
205 struct ast_connector connector;
206 } astdp;
207 } output;
208
209 bool support_wide_screen;
210
211 u8 *dp501_fw_addr;
212 const struct firmware *dp501_fw; /* dp501 fw */
213};
214
215static inline struct ast_device *to_ast_device(struct drm_device *dev)
216{
217 return container_of(dev, struct ast_device, base);
218}
219
220struct drm_device *ast_device_create(struct pci_dev *pdev,
221 const struct drm_driver *drv,
222 enum ast_chip chip,
223 enum ast_config_mode config_mode,
224 void __iomem *regs,
225 void __iomem *ioregs,
226 bool need_post);
227
228static inline unsigned long __ast_gen(struct ast_device *ast)
229{
230 return __AST_CHIP_GEN(ast->chip);
231}
232#define AST_GEN(__ast) __ast_gen(__ast)
233
234static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen)
235{
236 return __ast_gen(ast) == gen;
237}
238#define IS_AST_GEN1(__ast) __ast_gen_is_eq(__ast, 1)
239#define IS_AST_GEN2(__ast) __ast_gen_is_eq(__ast, 2)
240#define IS_AST_GEN3(__ast) __ast_gen_is_eq(__ast, 3)
241#define IS_AST_GEN4(__ast) __ast_gen_is_eq(__ast, 4)
242#define IS_AST_GEN5(__ast) __ast_gen_is_eq(__ast, 5)
243#define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6)
244#define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7)
245
246static inline u8 __ast_read8(const void __iomem *addr, u32 reg)
247{
248 return ioread8(addr + reg);
249}
250
251static inline u32 __ast_read32(const void __iomem *addr, u32 reg)
252{
253 return ioread32(addr + reg);
254}
255
256static inline void __ast_write8(void __iomem *addr, u32 reg, u8 val)
257{
258 iowrite8(val, addr + reg);
259}
260
261static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val)
262{
263 iowrite32(val, addr + reg);
264}
265
266static inline u8 __ast_read8_i(void __iomem *addr, u32 reg, u8 index)
267{
268 __ast_write8(addr, reg, index);
269 return __ast_read8(addr, reg + 1);
270}
271
272static inline u8 __ast_read8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask)
273{
274 u8 val = __ast_read8_i(addr, reg, index);
275
276 return val & read_mask;
277}
278
279static inline void __ast_write8_i(void __iomem *addr, u32 reg, u8 index, u8 val)
280{
281 __ast_write8(addr, reg, index);
282 __ast_write8(addr, reg + 1, val);
283}
284
285static inline void __ast_write8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask,
286 u8 val)
287{
288 u8 tmp = __ast_read8_i_masked(addr, reg, index, read_mask);
289
290 tmp |= val;
291 __ast_write8_i(addr, reg, index, tmp);
292}
293
294static inline u32 ast_read32(struct ast_device *ast, u32 reg)
295{
296 return __ast_read32(ast->regs, reg);
297}
298
299static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
300{
301 __ast_write32(ast->regs, reg, val);
302}
303
304static inline u8 ast_io_read8(struct ast_device *ast, u32 reg)
305{
306 return __ast_read8(ast->ioregs, reg);
307}
308
309static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
310{
311 __ast_write8(ast->ioregs, reg, val);
312}
313
314static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index)
315{
316 return __ast_read8_i(ast->ioregs, base, index);
317}
318
319static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
320 u8 preserve_mask)
321{
322 return __ast_read8_i_masked(ast->ioregs, base, index, preserve_mask);
323}
324
325static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
326{
327 __ast_write8_i(ast->ioregs, base, index, val);
328}
329
330static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
331 u8 preserve_mask, u8 val)
332{
333 __ast_write8_i_masked(ast->ioregs, base, index, preserve_mask, val);
334}
335
336#define AST_VIDMEM_SIZE_8M 0x00800000
337#define AST_VIDMEM_SIZE_16M 0x01000000
338#define AST_VIDMEM_SIZE_32M 0x02000000
339#define AST_VIDMEM_SIZE_64M 0x04000000
340#define AST_VIDMEM_SIZE_128M 0x08000000
341
342#define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
343
344struct ast_vbios_stdtable {
345 u8 misc;
346 u8 seq[4];
347 u8 crtc[25];
348 u8 ar[20];
349 u8 gr[9];
350};
351
352struct ast_vbios_enhtable {
353 u32 ht;
354 u32 hde;
355 u32 hfp;
356 u32 hsync;
357 u32 vt;
358 u32 vde;
359 u32 vfp;
360 u32 vsync;
361 u32 dclk_index;
362 u32 flags;
363 u32 refresh_rate;
364 u32 refresh_rate_index;
365 u32 mode_id;
366};
367
368struct ast_vbios_dclk_info {
369 u8 param1;
370 u8 param2;
371 u8 param3;
372};
373
374struct ast_vbios_mode_info {
375 const struct ast_vbios_stdtable *std_table;
376 const struct ast_vbios_enhtable *enh_table;
377};
378
379struct ast_crtc_state {
380 struct drm_crtc_state base;
381
382 /* Last known format of primary plane */
383 const struct drm_format_info *format;
384
385 struct ast_vbios_mode_info vbios_mode_info;
386};
387
388#define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
389
390int ast_mode_config_init(struct ast_device *ast);
391
392#define AST_MM_ALIGN_SHIFT 4
393#define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
394
395#define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
396#define AST_DP501_FW_VERSION_1 BIT(4)
397#define AST_DP501_PNP_CONNECTED BIT(1)
398
399#define AST_DP501_DEFAULT_DCLK 65
400
401#define AST_DP501_GBL_VERSION 0xf000
402#define AST_DP501_PNPMONITOR 0xf010
403#define AST_DP501_LINKRATE 0xf014
404#define AST_DP501_EDID_DATA 0xf020
405
406/*
407 * ASTDP resoultion table:
408 * EX: ASTDP_A_B_C:
409 * A: Resolution
410 * B: Refresh Rate
411 * C: Misc information, such as CVT, Reduce Blanked
412 */
413#define ASTDP_640x480_60 0x00
414#define ASTDP_640x480_72 0x01
415#define ASTDP_640x480_75 0x02
416#define ASTDP_640x480_85 0x03
417#define ASTDP_800x600_56 0x04
418#define ASTDP_800x600_60 0x05
419#define ASTDP_800x600_72 0x06
420#define ASTDP_800x600_75 0x07
421#define ASTDP_800x600_85 0x08
422#define ASTDP_1024x768_60 0x09
423#define ASTDP_1024x768_70 0x0A
424#define ASTDP_1024x768_75 0x0B
425#define ASTDP_1024x768_85 0x0C
426#define ASTDP_1280x1024_60 0x0D
427#define ASTDP_1280x1024_75 0x0E
428#define ASTDP_1280x1024_85 0x0F
429#define ASTDP_1600x1200_60 0x10
430#define ASTDP_320x240_60 0x11
431#define ASTDP_400x300_60 0x12
432#define ASTDP_512x384_60 0x13
433#define ASTDP_1920x1200_60 0x14
434#define ASTDP_1920x1080_60 0x15
435#define ASTDP_1280x800_60 0x16
436#define ASTDP_1280x800_60_RB 0x17
437#define ASTDP_1440x900_60 0x18
438#define ASTDP_1440x900_60_RB 0x19
439#define ASTDP_1680x1050_60 0x1A
440#define ASTDP_1680x1050_60_RB 0x1B
441#define ASTDP_1600x900_60 0x1C
442#define ASTDP_1600x900_60_RB 0x1D
443#define ASTDP_1366x768_60 0x1E
444#define ASTDP_1152x864_75 0x1F
445
446int ast_mm_init(struct ast_device *ast);
447
448/* ast post */
449void ast_post_gpu(struct ast_device *ast);
450u32 ast_mindwm(struct ast_device *ast, u32 r);
451void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
452void ast_patch_ahb_2500(void __iomem *regs);
453
454int ast_vga_output_init(struct ast_device *ast);
455int ast_sil164_output_init(struct ast_device *ast);
456
457/* ast dp501 */
458bool ast_backup_fw(struct ast_device *ast, u8 *addr, u32 size);
459void ast_init_3rdtx(struct ast_device *ast);
460int ast_dp501_output_init(struct ast_device *ast);
461
462/* aspeed DP */
463int ast_dp_launch(struct ast_device *ast);
464int ast_astdp_output_init(struct ast_device *ast);
465
466#endif
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28#ifndef __AST_DRV_H__
29#define __AST_DRV_H__
30
31#include <linux/i2c.h>
32#include <linux/i2c-algo-bit.h>
33#include <linux/io.h>
34#include <linux/types.h>
35
36#include <drm/drm_connector.h>
37#include <drm/drm_crtc.h>
38#include <drm/drm_encoder.h>
39#include <drm/drm_mode.h>
40#include <drm/drm_framebuffer.h>
41#include <drm/drm_fb_helper.h>
42
43#define DRIVER_AUTHOR "Dave Airlie"
44
45#define DRIVER_NAME "ast"
46#define DRIVER_DESC "AST"
47#define DRIVER_DATE "20120228"
48
49#define DRIVER_MAJOR 0
50#define DRIVER_MINOR 1
51#define DRIVER_PATCHLEVEL 0
52
53#define PCI_CHIP_AST2000 0x2000
54#define PCI_CHIP_AST2100 0x2010
55
56
57enum ast_chip {
58 AST2000,
59 AST2100,
60 AST1100,
61 AST2200,
62 AST2150,
63 AST2300,
64 AST2400,
65 AST2500,
66 AST2600,
67};
68
69enum ast_tx_chip {
70 AST_TX_NONE,
71 AST_TX_SIL164,
72 AST_TX_ITE66121,
73 AST_TX_DP501,
74};
75
76#define AST_DRAM_512Mx16 0
77#define AST_DRAM_1Gx16 1
78#define AST_DRAM_512Mx32 2
79#define AST_DRAM_1Gx32 3
80#define AST_DRAM_2Gx16 6
81#define AST_DRAM_4Gx16 7
82#define AST_DRAM_8Gx16 8
83
84/*
85 * Cursor plane
86 */
87
88#define AST_MAX_HWC_WIDTH 64
89#define AST_MAX_HWC_HEIGHT 64
90
91#define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
92#define AST_HWC_SIGNATURE_SIZE 32
93
94#define AST_DEFAULT_HWC_NUM 2
95
96/* define for signature structure */
97#define AST_HWC_SIGNATURE_CHECKSUM 0x00
98#define AST_HWC_SIGNATURE_SizeX 0x04
99#define AST_HWC_SIGNATURE_SizeY 0x08
100#define AST_HWC_SIGNATURE_X 0x0C
101#define AST_HWC_SIGNATURE_Y 0x10
102#define AST_HWC_SIGNATURE_HOTSPOTX 0x14
103#define AST_HWC_SIGNATURE_HOTSPOTY 0x18
104
105struct ast_cursor_plane {
106 struct drm_plane base;
107
108 struct {
109 struct drm_gem_vram_object *gbo;
110 struct dma_buf_map map;
111 u64 off;
112 } hwc[AST_DEFAULT_HWC_NUM];
113
114 unsigned int next_hwc_index;
115};
116
117static inline struct ast_cursor_plane *
118to_ast_cursor_plane(struct drm_plane *plane)
119{
120 return container_of(plane, struct ast_cursor_plane, base);
121}
122
123/*
124 * Connector with i2c channel
125 */
126
127struct ast_i2c_chan {
128 struct i2c_adapter adapter;
129 struct drm_device *dev;
130 struct i2c_algo_bit_data bit;
131};
132
133struct ast_connector {
134 struct drm_connector base;
135 struct ast_i2c_chan *i2c;
136};
137
138static inline struct ast_connector *
139to_ast_connector(struct drm_connector *connector)
140{
141 return container_of(connector, struct ast_connector, base);
142}
143
144/*
145 * Device
146 */
147
148struct ast_private {
149 struct drm_device base;
150
151 void __iomem *regs;
152 void __iomem *ioregs;
153 void __iomem *dp501_fw_buf;
154
155 enum ast_chip chip;
156 bool vga2_clone;
157 uint32_t dram_bus_width;
158 uint32_t dram_type;
159 uint32_t mclk;
160
161 int fb_mtrr;
162
163 struct drm_plane primary_plane;
164 struct ast_cursor_plane cursor_plane;
165 struct drm_crtc crtc;
166 struct drm_encoder encoder;
167 struct ast_connector connector;
168
169 bool support_wide_screen;
170 enum {
171 ast_use_p2a,
172 ast_use_dt,
173 ast_use_defaults
174 } config_mode;
175
176 enum ast_tx_chip tx_chip_type;
177 u8 dp501_maxclk;
178 u8 *dp501_fw_addr;
179 const struct firmware *dp501_fw; /* dp501 fw */
180};
181
182static inline struct ast_private *to_ast_private(struct drm_device *dev)
183{
184 return container_of(dev, struct ast_private, base);
185}
186
187struct ast_private *ast_device_create(const struct drm_driver *drv,
188 struct pci_dev *pdev,
189 unsigned long flags);
190
191#define AST_IO_AR_PORT_WRITE (0x40)
192#define AST_IO_MISC_PORT_WRITE (0x42)
193#define AST_IO_VGA_ENABLE_PORT (0x43)
194#define AST_IO_SEQ_PORT (0x44)
195#define AST_IO_DAC_INDEX_READ (0x47)
196#define AST_IO_DAC_INDEX_WRITE (0x48)
197#define AST_IO_DAC_DATA (0x49)
198#define AST_IO_GR_PORT (0x4E)
199#define AST_IO_CRTC_PORT (0x54)
200#define AST_IO_INPUT_STATUS1_READ (0x5A)
201#define AST_IO_MISC_PORT_READ (0x4C)
202
203#define AST_IO_MM_OFFSET (0x380)
204
205#define AST_IO_VGAIR1_VREFRESH BIT(3)
206
207#define AST_IO_VGACRCB_HWC_ENABLED BIT(1)
208#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
209
210#define __ast_read(x) \
211static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
212u##x val = 0;\
213val = ioread##x(ast->regs + reg); \
214return val;\
215}
216
217__ast_read(8);
218__ast_read(16);
219__ast_read(32)
220
221#define __ast_io_read(x) \
222static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
223u##x val = 0;\
224val = ioread##x(ast->ioregs + reg); \
225return val;\
226}
227
228__ast_io_read(8);
229__ast_io_read(16);
230__ast_io_read(32);
231
232#define __ast_write(x) \
233static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
234 iowrite##x(val, ast->regs + reg);\
235 }
236
237__ast_write(8);
238__ast_write(16);
239__ast_write(32);
240
241#define __ast_io_write(x) \
242static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
243 iowrite##x(val, ast->ioregs + reg);\
244 }
245
246__ast_io_write(8);
247__ast_io_write(16);
248#undef __ast_io_write
249
250static inline void ast_set_index_reg(struct ast_private *ast,
251 uint32_t base, uint8_t index,
252 uint8_t val)
253{
254 ast_io_write16(ast, base, ((u16)val << 8) | index);
255}
256
257void ast_set_index_reg_mask(struct ast_private *ast,
258 uint32_t base, uint8_t index,
259 uint8_t mask, uint8_t val);
260uint8_t ast_get_index_reg(struct ast_private *ast,
261 uint32_t base, uint8_t index);
262uint8_t ast_get_index_reg_mask(struct ast_private *ast,
263 uint32_t base, uint8_t index, uint8_t mask);
264
265static inline void ast_open_key(struct ast_private *ast)
266{
267 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
268}
269
270#define AST_VIDMEM_SIZE_8M 0x00800000
271#define AST_VIDMEM_SIZE_16M 0x01000000
272#define AST_VIDMEM_SIZE_32M 0x02000000
273#define AST_VIDMEM_SIZE_64M 0x04000000
274#define AST_VIDMEM_SIZE_128M 0x08000000
275
276#define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
277
278struct ast_vbios_stdtable {
279 u8 misc;
280 u8 seq[4];
281 u8 crtc[25];
282 u8 ar[20];
283 u8 gr[9];
284};
285
286struct ast_vbios_enhtable {
287 u32 ht;
288 u32 hde;
289 u32 hfp;
290 u32 hsync;
291 u32 vt;
292 u32 vde;
293 u32 vfp;
294 u32 vsync;
295 u32 dclk_index;
296 u32 flags;
297 u32 refresh_rate;
298 u32 refresh_rate_index;
299 u32 mode_id;
300};
301
302struct ast_vbios_dclk_info {
303 u8 param1;
304 u8 param2;
305 u8 param3;
306};
307
308struct ast_vbios_mode_info {
309 const struct ast_vbios_stdtable *std_table;
310 const struct ast_vbios_enhtable *enh_table;
311};
312
313struct ast_crtc_state {
314 struct drm_crtc_state base;
315
316 /* Last known format of primary plane */
317 const struct drm_format_info *format;
318
319 struct ast_vbios_mode_info vbios_mode_info;
320};
321
322#define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
323
324int ast_mode_config_init(struct ast_private *ast);
325
326#define AST_MM_ALIGN_SHIFT 4
327#define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
328
329#define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
330#define AST_DP501_FW_VERSION_1 BIT(4)
331#define AST_DP501_PNP_CONNECTED BIT(1)
332
333#define AST_DP501_DEFAULT_DCLK 65
334
335#define AST_DP501_GBL_VERSION 0xf000
336#define AST_DP501_PNPMONITOR 0xf010
337#define AST_DP501_LINKRATE 0xf014
338#define AST_DP501_EDID_DATA 0xf020
339
340/* Define for Soc scratched reg */
341#define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6)
342//#define AST_VRAM_INIT_BY_BMC BIT(7)
343//#define AST_VRAM_INIT_READY BIT(6)
344
345int ast_mm_init(struct ast_private *ast);
346
347/* ast post */
348void ast_enable_vga(struct drm_device *dev);
349void ast_enable_mmio(struct drm_device *dev);
350bool ast_is_vga_enabled(struct drm_device *dev);
351void ast_post_gpu(struct drm_device *dev);
352u32 ast_mindwm(struct ast_private *ast, u32 r);
353void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
354void ast_patch_ahb_2500(struct ast_private *ast);
355/* ast dp501 */
356void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
357bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
358bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
359u8 ast_get_dp501_max_clk(struct drm_device *dev);
360void ast_init_3rdtx(struct drm_device *dev);
361
362#endif