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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/delay.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32#include "vi.h"
33#include "vid.h"
34
35#include "oss/oss_2_4_d.h"
36#include "oss/oss_2_4_sh_mask.h"
37
38#include "gmc/gmc_7_1_d.h"
39#include "gmc/gmc_7_1_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44
45#include "bif/bif_5_0_d.h"
46#include "bif/bif_5_0_sh_mask.h"
47
48#include "iceland_sdma_pkt_open.h"
49
50#include "ivsrcid/ivsrcid_vislands30.h"
51
52static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
53static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
54static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
55static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
56
57MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
58MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
59
60static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = {
61 SDMA0_REGISTER_OFFSET,
62 SDMA1_REGISTER_OFFSET
63};
64
65static const u32 golden_settings_iceland_a11[] = {
66 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
67 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
68 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
69 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
70};
71
72static const u32 iceland_mgcg_cgcg_init[] = {
73 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
74 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
75};
76
77/*
78 * sDMA - System DMA
79 * Starting with CIK, the GPU has new asynchronous
80 * DMA engines. These engines are used for compute
81 * and gfx. There are two DMA engines (SDMA0, SDMA1)
82 * and each one supports 1 ring buffer used for gfx
83 * and 2 queues used for compute.
84 *
85 * The programming model is very similar to the CP
86 * (ring buffer, IBs, etc.), but sDMA has it's own
87 * packet format that is different from the PM4 format
88 * used by the CP. sDMA supports copying data, writing
89 * embedded data, solid fills, and a number of other
90 * things. It also has support for tiling/detiling of
91 * buffers.
92 */
93
94static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
95{
96 switch (adev->asic_type) {
97 case CHIP_TOPAZ:
98 amdgpu_device_program_register_sequence(adev,
99 iceland_mgcg_cgcg_init,
100 ARRAY_SIZE(iceland_mgcg_cgcg_init));
101 amdgpu_device_program_register_sequence(adev,
102 golden_settings_iceland_a11,
103 ARRAY_SIZE(golden_settings_iceland_a11));
104 break;
105 default:
106 break;
107 }
108}
109
110static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
111{
112 int i;
113
114 for (i = 0; i < adev->sdma.num_instances; i++)
115 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
116}
117
118/**
119 * sdma_v2_4_init_microcode - load ucode images from disk
120 *
121 * @adev: amdgpu_device pointer
122 *
123 * Use the firmware interface to load the ucode images into
124 * the driver (not loaded into hw).
125 * Returns 0 on success, error on failure.
126 */
127static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
128{
129 const char *chip_name;
130 int err = 0, i;
131 struct amdgpu_firmware_info *info = NULL;
132 const struct common_firmware_header *header = NULL;
133 const struct sdma_firmware_header_v1_0 *hdr;
134
135 DRM_DEBUG("\n");
136
137 switch (adev->asic_type) {
138 case CHIP_TOPAZ:
139 chip_name = "topaz";
140 break;
141 default:
142 BUG();
143 }
144
145 for (i = 0; i < adev->sdma.num_instances; i++) {
146 if (i == 0)
147 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
148 "amdgpu/%s_sdma.bin", chip_name);
149 else
150 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
151 "amdgpu/%s_sdma1.bin", chip_name);
152 if (err)
153 goto out;
154 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
155 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
156 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
157 if (adev->sdma.instance[i].feature_version >= 20)
158 adev->sdma.instance[i].burst_nop = true;
159
160 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
161 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
162 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
163 info->fw = adev->sdma.instance[i].fw;
164 header = (const struct common_firmware_header *)info->fw->data;
165 adev->firmware.fw_size +=
166 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
167 }
168 }
169
170out:
171 if (err) {
172 pr_err("sdma_v2_4: Failed to load firmware \"%s_sdma%s.bin\"\n",
173 chip_name, i == 0 ? "" : "1");
174 for (i = 0; i < adev->sdma.num_instances; i++)
175 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
176 }
177 return err;
178}
179
180/**
181 * sdma_v2_4_ring_get_rptr - get the current read pointer
182 *
183 * @ring: amdgpu ring pointer
184 *
185 * Get the current rptr from the hardware (VI+).
186 */
187static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
188{
189 /* XXX check if swapping is necessary on BE */
190 return *ring->rptr_cpu_addr >> 2;
191}
192
193/**
194 * sdma_v2_4_ring_get_wptr - get the current write pointer
195 *
196 * @ring: amdgpu ring pointer
197 *
198 * Get the current wptr from the hardware (VI+).
199 */
200static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
201{
202 struct amdgpu_device *adev = ring->adev;
203 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
204
205 return wptr;
206}
207
208/**
209 * sdma_v2_4_ring_set_wptr - commit the write pointer
210 *
211 * @ring: amdgpu ring pointer
212 *
213 * Write the wptr back to the hardware (VI+).
214 */
215static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
216{
217 struct amdgpu_device *adev = ring->adev;
218
219 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
220}
221
222static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
223{
224 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
225 int i;
226
227 for (i = 0; i < count; i++)
228 if (sdma && sdma->burst_nop && (i == 0))
229 amdgpu_ring_write(ring, ring->funcs->nop |
230 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
231 else
232 amdgpu_ring_write(ring, ring->funcs->nop);
233}
234
235/**
236 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
237 *
238 * @ring: amdgpu ring pointer
239 * @job: job to retrieve vmid from
240 * @ib: IB object to schedule
241 * @flags: unused
242 *
243 * Schedule an IB in the DMA ring (VI).
244 */
245static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
246 struct amdgpu_job *job,
247 struct amdgpu_ib *ib,
248 uint32_t flags)
249{
250 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
251
252 /* IB packet must end on a 8 DW boundary */
253 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
254
255 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
256 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
257 /* base must be 32 byte aligned */
258 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
259 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
260 amdgpu_ring_write(ring, ib->length_dw);
261 amdgpu_ring_write(ring, 0);
262 amdgpu_ring_write(ring, 0);
263
264}
265
266/**
267 * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
268 *
269 * @ring: amdgpu ring pointer
270 *
271 * Emit an hdp flush packet on the requested DMA ring.
272 */
273static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
274{
275 u32 ref_and_mask = 0;
276
277 if (ring->me == 0)
278 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
279 else
280 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
281
282 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
283 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
284 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
285 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
286 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
287 amdgpu_ring_write(ring, ref_and_mask); /* reference */
288 amdgpu_ring_write(ring, ref_and_mask); /* mask */
289 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
290 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
291}
292
293/**
294 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
295 *
296 * @ring: amdgpu ring pointer
297 * @addr: address
298 * @seq: sequence number
299 * @flags: fence related flags
300 *
301 * Add a DMA fence packet to the ring to write
302 * the fence seq number and DMA trap packet to generate
303 * an interrupt if needed (VI).
304 */
305static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
306 unsigned flags)
307{
308 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
309 /* write the fence */
310 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
311 amdgpu_ring_write(ring, lower_32_bits(addr));
312 amdgpu_ring_write(ring, upper_32_bits(addr));
313 amdgpu_ring_write(ring, lower_32_bits(seq));
314
315 /* optionally write high bits as well */
316 if (write64bit) {
317 addr += 4;
318 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
319 amdgpu_ring_write(ring, lower_32_bits(addr));
320 amdgpu_ring_write(ring, upper_32_bits(addr));
321 amdgpu_ring_write(ring, upper_32_bits(seq));
322 }
323
324 /* generate an interrupt */
325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
326 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
327}
328
329/**
330 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
331 *
332 * @adev: amdgpu_device pointer
333 *
334 * Stop the gfx async dma ring buffers (VI).
335 */
336static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
337{
338 u32 rb_cntl, ib_cntl;
339 int i;
340
341 for (i = 0; i < adev->sdma.num_instances; i++) {
342 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
343 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
344 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
345 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
346 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
347 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
348 }
349}
350
351/**
352 * sdma_v2_4_rlc_stop - stop the compute async dma engines
353 *
354 * @adev: amdgpu_device pointer
355 *
356 * Stop the compute async dma queues (VI).
357 */
358static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
359{
360 /* XXX todo */
361}
362
363/**
364 * sdma_v2_4_enable - stop the async dma engines
365 *
366 * @adev: amdgpu_device pointer
367 * @enable: enable/disable the DMA MEs.
368 *
369 * Halt or unhalt the async dma engines (VI).
370 */
371static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
372{
373 u32 f32_cntl;
374 int i;
375
376 if (!enable) {
377 sdma_v2_4_gfx_stop(adev);
378 sdma_v2_4_rlc_stop(adev);
379 }
380
381 for (i = 0; i < adev->sdma.num_instances; i++) {
382 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
383 if (enable)
384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
385 else
386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
387 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
388 }
389}
390
391/**
392 * sdma_v2_4_gfx_resume - setup and start the async dma engines
393 *
394 * @adev: amdgpu_device pointer
395 *
396 * Set up the gfx DMA ring buffers and enable them (VI).
397 * Returns 0 for success, error for failure.
398 */
399static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
400{
401 struct amdgpu_ring *ring;
402 u32 rb_cntl, ib_cntl;
403 u32 rb_bufsz;
404 int i, j, r;
405
406 for (i = 0; i < adev->sdma.num_instances; i++) {
407 ring = &adev->sdma.instance[i].ring;
408
409 mutex_lock(&adev->srbm_mutex);
410 for (j = 0; j < 16; j++) {
411 vi_srbm_select(adev, 0, 0, 0, j);
412 /* SDMA GFX */
413 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
414 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
415 }
416 vi_srbm_select(adev, 0, 0, 0, 0);
417 mutex_unlock(&adev->srbm_mutex);
418
419 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
420 adev->gfx.config.gb_addr_config & 0x70);
421
422 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
423
424 /* Set ring buffer size in dwords */
425 rb_bufsz = order_base_2(ring->ring_size / 4);
426 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
427 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
428#ifdef __BIG_ENDIAN
429 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
430 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
431 RPTR_WRITEBACK_SWAP_ENABLE, 1);
432#endif
433 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
434
435 /* Initialize the ring buffer's read and write pointers */
436 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
437 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
438 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
439 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
440
441 /* set the wb address whether it's enabled or not */
442 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
443 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
444 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
445 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
446
447 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
448
449 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
450 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
451
452 ring->wptr = 0;
453 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
454
455 /* enable DMA RB */
456 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
457 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
458
459 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
460 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
461#ifdef __BIG_ENDIAN
462 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
463#endif
464 /* enable DMA IBs */
465 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
466 }
467
468 sdma_v2_4_enable(adev, true);
469 for (i = 0; i < adev->sdma.num_instances; i++) {
470 ring = &adev->sdma.instance[i].ring;
471 r = amdgpu_ring_test_helper(ring);
472 if (r)
473 return r;
474 }
475
476 return 0;
477}
478
479/**
480 * sdma_v2_4_rlc_resume - setup and start the async dma engines
481 *
482 * @adev: amdgpu_device pointer
483 *
484 * Set up the compute DMA queues and enable them (VI).
485 * Returns 0 for success, error for failure.
486 */
487static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
488{
489 /* XXX todo */
490 return 0;
491}
492
493
494/**
495 * sdma_v2_4_start - setup and start the async dma engines
496 *
497 * @adev: amdgpu_device pointer
498 *
499 * Set up the DMA engines and enable them (VI).
500 * Returns 0 for success, error for failure.
501 */
502static int sdma_v2_4_start(struct amdgpu_device *adev)
503{
504 int r;
505
506 /* halt the engine before programing */
507 sdma_v2_4_enable(adev, false);
508
509 /* start the gfx rings and rlc compute queues */
510 r = sdma_v2_4_gfx_resume(adev);
511 if (r)
512 return r;
513 r = sdma_v2_4_rlc_resume(adev);
514 if (r)
515 return r;
516
517 return 0;
518}
519
520/**
521 * sdma_v2_4_ring_test_ring - simple async dma engine test
522 *
523 * @ring: amdgpu_ring structure holding ring information
524 *
525 * Test the DMA engine by writing using it to write an
526 * value to memory. (VI).
527 * Returns 0 for success, error for failure.
528 */
529static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
530{
531 struct amdgpu_device *adev = ring->adev;
532 unsigned i;
533 unsigned index;
534 int r;
535 u32 tmp;
536 u64 gpu_addr;
537
538 r = amdgpu_device_wb_get(adev, &index);
539 if (r)
540 return r;
541
542 gpu_addr = adev->wb.gpu_addr + (index * 4);
543 tmp = 0xCAFEDEAD;
544 adev->wb.wb[index] = cpu_to_le32(tmp);
545
546 r = amdgpu_ring_alloc(ring, 5);
547 if (r)
548 goto error_free_wb;
549
550 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
551 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
552 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
553 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
554 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
555 amdgpu_ring_write(ring, 0xDEADBEEF);
556 amdgpu_ring_commit(ring);
557
558 for (i = 0; i < adev->usec_timeout; i++) {
559 tmp = le32_to_cpu(adev->wb.wb[index]);
560 if (tmp == 0xDEADBEEF)
561 break;
562 udelay(1);
563 }
564
565 if (i >= adev->usec_timeout)
566 r = -ETIMEDOUT;
567
568error_free_wb:
569 amdgpu_device_wb_free(adev, index);
570 return r;
571}
572
573/**
574 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
575 *
576 * @ring: amdgpu_ring structure holding ring information
577 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
578 *
579 * Test a simple IB in the DMA ring (VI).
580 * Returns 0 on success, error on failure.
581 */
582static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
583{
584 struct amdgpu_device *adev = ring->adev;
585 struct amdgpu_ib ib;
586 struct dma_fence *f = NULL;
587 unsigned index;
588 u32 tmp = 0;
589 u64 gpu_addr;
590 long r;
591
592 r = amdgpu_device_wb_get(adev, &index);
593 if (r)
594 return r;
595
596 gpu_addr = adev->wb.gpu_addr + (index * 4);
597 tmp = 0xCAFEDEAD;
598 adev->wb.wb[index] = cpu_to_le32(tmp);
599 memset(&ib, 0, sizeof(ib));
600 r = amdgpu_ib_get(adev, NULL, 256,
601 AMDGPU_IB_POOL_DIRECT, &ib);
602 if (r)
603 goto err0;
604
605 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
606 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
607 ib.ptr[1] = lower_32_bits(gpu_addr);
608 ib.ptr[2] = upper_32_bits(gpu_addr);
609 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
610 ib.ptr[4] = 0xDEADBEEF;
611 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
612 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
613 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
614 ib.length_dw = 8;
615
616 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
617 if (r)
618 goto err1;
619
620 r = dma_fence_wait_timeout(f, false, timeout);
621 if (r == 0) {
622 r = -ETIMEDOUT;
623 goto err1;
624 } else if (r < 0) {
625 goto err1;
626 }
627 tmp = le32_to_cpu(adev->wb.wb[index]);
628 if (tmp == 0xDEADBEEF)
629 r = 0;
630 else
631 r = -EINVAL;
632
633err1:
634 amdgpu_ib_free(adev, &ib, NULL);
635 dma_fence_put(f);
636err0:
637 amdgpu_device_wb_free(adev, index);
638 return r;
639}
640
641/**
642 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
643 *
644 * @ib: indirect buffer to fill with commands
645 * @pe: addr of the page entry
646 * @src: src addr to copy from
647 * @count: number of page entries to update
648 *
649 * Update PTEs by copying them from the GART using sDMA (CIK).
650 */
651static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
652 uint64_t pe, uint64_t src,
653 unsigned count)
654{
655 unsigned bytes = count * 8;
656
657 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
658 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
659 ib->ptr[ib->length_dw++] = bytes;
660 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
661 ib->ptr[ib->length_dw++] = lower_32_bits(src);
662 ib->ptr[ib->length_dw++] = upper_32_bits(src);
663 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
664 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
665}
666
667/**
668 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
669 *
670 * @ib: indirect buffer to fill with commands
671 * @pe: addr of the page entry
672 * @value: dst addr to write into pe
673 * @count: number of page entries to update
674 * @incr: increase next addr by incr bytes
675 *
676 * Update PTEs by writing them manually using sDMA (CIK).
677 */
678static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
679 uint64_t value, unsigned count,
680 uint32_t incr)
681{
682 unsigned ndw = count * 2;
683
684 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
685 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
686 ib->ptr[ib->length_dw++] = pe;
687 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
688 ib->ptr[ib->length_dw++] = ndw;
689 for (; ndw > 0; ndw -= 2) {
690 ib->ptr[ib->length_dw++] = lower_32_bits(value);
691 ib->ptr[ib->length_dw++] = upper_32_bits(value);
692 value += incr;
693 }
694}
695
696/**
697 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
698 *
699 * @ib: indirect buffer to fill with commands
700 * @pe: addr of the page entry
701 * @addr: dst addr to write into pe
702 * @count: number of page entries to update
703 * @incr: increase next addr by incr bytes
704 * @flags: access flags
705 *
706 * Update the page tables using sDMA (CIK).
707 */
708static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
709 uint64_t addr, unsigned count,
710 uint32_t incr, uint64_t flags)
711{
712 /* for physically contiguous pages (vram) */
713 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
714 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
715 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
716 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
717 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
718 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
719 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
720 ib->ptr[ib->length_dw++] = incr; /* increment size */
721 ib->ptr[ib->length_dw++] = 0;
722 ib->ptr[ib->length_dw++] = count; /* number of entries */
723}
724
725/**
726 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
727 *
728 * @ring: amdgpu_ring structure holding ring information
729 * @ib: indirect buffer to fill with padding
730 *
731 */
732static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
733{
734 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
735 u32 pad_count;
736 int i;
737
738 pad_count = (-ib->length_dw) & 7;
739 for (i = 0; i < pad_count; i++)
740 if (sdma && sdma->burst_nop && (i == 0))
741 ib->ptr[ib->length_dw++] =
742 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
743 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
744 else
745 ib->ptr[ib->length_dw++] =
746 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
747}
748
749/**
750 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
751 *
752 * @ring: amdgpu_ring pointer
753 *
754 * Make sure all previous operations are completed (CIK).
755 */
756static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
757{
758 uint32_t seq = ring->fence_drv.sync_seq;
759 uint64_t addr = ring->fence_drv.gpu_addr;
760
761 /* wait for idle */
762 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
763 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
764 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
765 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
766 amdgpu_ring_write(ring, addr & 0xfffffffc);
767 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
768 amdgpu_ring_write(ring, seq); /* reference */
769 amdgpu_ring_write(ring, 0xffffffff); /* mask */
770 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
771 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
772}
773
774/**
775 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
776 *
777 * @ring: amdgpu_ring pointer
778 * @vmid: vmid number to use
779 * @pd_addr: address
780 *
781 * Update the page table base and flush the VM TLB
782 * using sDMA (VI).
783 */
784static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
785 unsigned vmid, uint64_t pd_addr)
786{
787 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
788
789 /* wait for flush */
790 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
791 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
792 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
793 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
794 amdgpu_ring_write(ring, 0);
795 amdgpu_ring_write(ring, 0); /* reference */
796 amdgpu_ring_write(ring, 0); /* mask */
797 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
798 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
799}
800
801static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
802 uint32_t reg, uint32_t val)
803{
804 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
805 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
806 amdgpu_ring_write(ring, reg);
807 amdgpu_ring_write(ring, val);
808}
809
810static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block)
811{
812 struct amdgpu_device *adev = ip_block->adev;
813 int r;
814
815 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
816
817 r = sdma_v2_4_init_microcode(adev);
818 if (r)
819 return r;
820
821 sdma_v2_4_set_ring_funcs(adev);
822 sdma_v2_4_set_buffer_funcs(adev);
823 sdma_v2_4_set_vm_pte_funcs(adev);
824 sdma_v2_4_set_irq_funcs(adev);
825
826 return 0;
827}
828
829static int sdma_v2_4_sw_init(struct amdgpu_ip_block *ip_block)
830{
831 struct amdgpu_ring *ring;
832 int r, i;
833 struct amdgpu_device *adev = ip_block->adev;
834
835 /* SDMA trap event */
836 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
837 &adev->sdma.trap_irq);
838 if (r)
839 return r;
840
841 /* SDMA Privileged inst */
842 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
843 &adev->sdma.illegal_inst_irq);
844 if (r)
845 return r;
846
847 /* SDMA Privileged inst */
848 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
849 &adev->sdma.illegal_inst_irq);
850 if (r)
851 return r;
852
853 for (i = 0; i < adev->sdma.num_instances; i++) {
854 ring = &adev->sdma.instance[i].ring;
855 ring->ring_obj = NULL;
856 ring->use_doorbell = false;
857 sprintf(ring->name, "sdma%d", i);
858 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
859 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
860 AMDGPU_SDMA_IRQ_INSTANCE1,
861 AMDGPU_RING_PRIO_DEFAULT, NULL);
862 if (r)
863 return r;
864 }
865
866 return r;
867}
868
869static int sdma_v2_4_sw_fini(struct amdgpu_ip_block *ip_block)
870{
871 struct amdgpu_device *adev = ip_block->adev;
872 int i;
873
874 for (i = 0; i < adev->sdma.num_instances; i++)
875 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
876
877 sdma_v2_4_free_microcode(adev);
878 return 0;
879}
880
881static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block)
882{
883 int r;
884 struct amdgpu_device *adev = ip_block->adev;
885
886 sdma_v2_4_init_golden_registers(adev);
887
888 r = sdma_v2_4_start(adev);
889 if (r)
890 return r;
891
892 return r;
893}
894
895static int sdma_v2_4_hw_fini(struct amdgpu_ip_block *ip_block)
896{
897 sdma_v2_4_enable(ip_block->adev, false);
898
899 return 0;
900}
901
902static int sdma_v2_4_suspend(struct amdgpu_ip_block *ip_block)
903{
904 return sdma_v2_4_hw_fini(ip_block);
905}
906
907static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block)
908{
909 return sdma_v2_4_hw_init(ip_block);
910}
911
912static bool sdma_v2_4_is_idle(void *handle)
913{
914 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
915 u32 tmp = RREG32(mmSRBM_STATUS2);
916
917 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
918 SRBM_STATUS2__SDMA1_BUSY_MASK))
919 return false;
920
921 return true;
922}
923
924static int sdma_v2_4_wait_for_idle(struct amdgpu_ip_block *ip_block)
925{
926 unsigned i;
927 u32 tmp;
928 struct amdgpu_device *adev = ip_block->adev;
929
930 for (i = 0; i < adev->usec_timeout; i++) {
931 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
932 SRBM_STATUS2__SDMA1_BUSY_MASK);
933
934 if (!tmp)
935 return 0;
936 udelay(1);
937 }
938 return -ETIMEDOUT;
939}
940
941static int sdma_v2_4_soft_reset(struct amdgpu_ip_block *ip_block)
942{
943 u32 srbm_soft_reset = 0;
944 struct amdgpu_device *adev = ip_block->adev;
945 u32 tmp = RREG32(mmSRBM_STATUS2);
946
947 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
948 /* sdma0 */
949 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
950 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
951 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
952 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
953 }
954 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
955 /* sdma1 */
956 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
957 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
958 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
959 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
960 }
961
962 if (srbm_soft_reset) {
963 tmp = RREG32(mmSRBM_SOFT_RESET);
964 tmp |= srbm_soft_reset;
965 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
966 WREG32(mmSRBM_SOFT_RESET, tmp);
967 tmp = RREG32(mmSRBM_SOFT_RESET);
968
969 udelay(50);
970
971 tmp &= ~srbm_soft_reset;
972 WREG32(mmSRBM_SOFT_RESET, tmp);
973 tmp = RREG32(mmSRBM_SOFT_RESET);
974
975 /* Wait a little for things to settle down */
976 udelay(50);
977 }
978
979 return 0;
980}
981
982static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
983 struct amdgpu_irq_src *src,
984 unsigned type,
985 enum amdgpu_interrupt_state state)
986{
987 u32 sdma_cntl;
988
989 switch (type) {
990 case AMDGPU_SDMA_IRQ_INSTANCE0:
991 switch (state) {
992 case AMDGPU_IRQ_STATE_DISABLE:
993 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
994 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
995 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
996 break;
997 case AMDGPU_IRQ_STATE_ENABLE:
998 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
999 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1000 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1001 break;
1002 default:
1003 break;
1004 }
1005 break;
1006 case AMDGPU_SDMA_IRQ_INSTANCE1:
1007 switch (state) {
1008 case AMDGPU_IRQ_STATE_DISABLE:
1009 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1010 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1011 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1012 break;
1013 case AMDGPU_IRQ_STATE_ENABLE:
1014 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1015 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1016 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1017 break;
1018 default:
1019 break;
1020 }
1021 break;
1022 default:
1023 break;
1024 }
1025 return 0;
1026}
1027
1028static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1029 struct amdgpu_irq_src *source,
1030 struct amdgpu_iv_entry *entry)
1031{
1032 u8 instance_id, queue_id;
1033
1034 instance_id = (entry->ring_id & 0x3) >> 0;
1035 queue_id = (entry->ring_id & 0xc) >> 2;
1036 DRM_DEBUG("IH: SDMA trap\n");
1037 switch (instance_id) {
1038 case 0:
1039 switch (queue_id) {
1040 case 0:
1041 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1042 break;
1043 case 1:
1044 /* XXX compute */
1045 break;
1046 case 2:
1047 /* XXX compute */
1048 break;
1049 }
1050 break;
1051 case 1:
1052 switch (queue_id) {
1053 case 0:
1054 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1055 break;
1056 case 1:
1057 /* XXX compute */
1058 break;
1059 case 2:
1060 /* XXX compute */
1061 break;
1062 }
1063 break;
1064 }
1065 return 0;
1066}
1067
1068static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1069 struct amdgpu_irq_src *source,
1070 struct amdgpu_iv_entry *entry)
1071{
1072 u8 instance_id, queue_id;
1073
1074 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1075 instance_id = (entry->ring_id & 0x3) >> 0;
1076 queue_id = (entry->ring_id & 0xc) >> 2;
1077
1078 if (instance_id <= 1 && queue_id == 0)
1079 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1080 return 0;
1081}
1082
1083static int sdma_v2_4_set_clockgating_state(void *handle,
1084 enum amd_clockgating_state state)
1085{
1086 /* XXX handled via the smc on VI */
1087 return 0;
1088}
1089
1090static int sdma_v2_4_set_powergating_state(void *handle,
1091 enum amd_powergating_state state)
1092{
1093 return 0;
1094}
1095
1096static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1097 .name = "sdma_v2_4",
1098 .early_init = sdma_v2_4_early_init,
1099 .sw_init = sdma_v2_4_sw_init,
1100 .sw_fini = sdma_v2_4_sw_fini,
1101 .hw_init = sdma_v2_4_hw_init,
1102 .hw_fini = sdma_v2_4_hw_fini,
1103 .suspend = sdma_v2_4_suspend,
1104 .resume = sdma_v2_4_resume,
1105 .is_idle = sdma_v2_4_is_idle,
1106 .wait_for_idle = sdma_v2_4_wait_for_idle,
1107 .soft_reset = sdma_v2_4_soft_reset,
1108 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1109 .set_powergating_state = sdma_v2_4_set_powergating_state,
1110};
1111
1112static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1113 .type = AMDGPU_RING_TYPE_SDMA,
1114 .align_mask = 0xf,
1115 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1116 .support_64bit_ptrs = false,
1117 .secure_submission_supported = true,
1118 .get_rptr = sdma_v2_4_ring_get_rptr,
1119 .get_wptr = sdma_v2_4_ring_get_wptr,
1120 .set_wptr = sdma_v2_4_ring_set_wptr,
1121 .emit_frame_size =
1122 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1123 3 + /* hdp invalidate */
1124 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1125 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1126 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1127 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1128 .emit_ib = sdma_v2_4_ring_emit_ib,
1129 .emit_fence = sdma_v2_4_ring_emit_fence,
1130 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1131 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1132 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1133 .test_ring = sdma_v2_4_ring_test_ring,
1134 .test_ib = sdma_v2_4_ring_test_ib,
1135 .insert_nop = sdma_v2_4_ring_insert_nop,
1136 .pad_ib = sdma_v2_4_ring_pad_ib,
1137 .emit_wreg = sdma_v2_4_ring_emit_wreg,
1138};
1139
1140static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1141{
1142 int i;
1143
1144 for (i = 0; i < adev->sdma.num_instances; i++) {
1145 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1146 adev->sdma.instance[i].ring.me = i;
1147 }
1148}
1149
1150static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1151 .set = sdma_v2_4_set_trap_irq_state,
1152 .process = sdma_v2_4_process_trap_irq,
1153};
1154
1155static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1156 .process = sdma_v2_4_process_illegal_inst_irq,
1157};
1158
1159static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1160{
1161 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1162 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1163 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1164}
1165
1166/**
1167 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1168 *
1169 * @ib: indirect buffer to copy to
1170 * @src_offset: src GPU address
1171 * @dst_offset: dst GPU address
1172 * @byte_count: number of bytes to xfer
1173 * @copy_flags: unused
1174 *
1175 * Copy GPU buffers using the DMA engine (VI).
1176 * Used by the amdgpu ttm implementation to move pages if
1177 * registered as the asic copy callback.
1178 */
1179static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1180 uint64_t src_offset,
1181 uint64_t dst_offset,
1182 uint32_t byte_count,
1183 uint32_t copy_flags)
1184{
1185 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1186 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1187 ib->ptr[ib->length_dw++] = byte_count;
1188 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1189 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1190 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1191 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1192 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1193}
1194
1195/**
1196 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1197 *
1198 * @ib: indirect buffer to copy to
1199 * @src_data: value to write to buffer
1200 * @dst_offset: dst GPU address
1201 * @byte_count: number of bytes to xfer
1202 *
1203 * Fill GPU buffers using the DMA engine (VI).
1204 */
1205static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1206 uint32_t src_data,
1207 uint64_t dst_offset,
1208 uint32_t byte_count)
1209{
1210 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1211 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1212 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1213 ib->ptr[ib->length_dw++] = src_data;
1214 ib->ptr[ib->length_dw++] = byte_count;
1215}
1216
1217static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1218 .copy_max_bytes = 0x1fffff,
1219 .copy_num_dw = 7,
1220 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1221
1222 .fill_max_bytes = 0x1fffff,
1223 .fill_num_dw = 7,
1224 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1225};
1226
1227static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1228{
1229 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1230 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1231}
1232
1233static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1234 .copy_pte_num_dw = 7,
1235 .copy_pte = sdma_v2_4_vm_copy_pte,
1236
1237 .write_pte = sdma_v2_4_vm_write_pte,
1238 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1239};
1240
1241static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1242{
1243 unsigned i;
1244
1245 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1246 for (i = 0; i < adev->sdma.num_instances; i++) {
1247 adev->vm_manager.vm_pte_scheds[i] =
1248 &adev->sdma.instance[i].ring.sched;
1249 }
1250 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1251}
1252
1253const struct amdgpu_ip_block_version sdma_v2_4_ip_block = {
1254 .type = AMD_IP_BLOCK_TYPE_SDMA,
1255 .major = 2,
1256 .minor = 4,
1257 .rev = 0,
1258 .funcs = &sdma_v2_4_ip_funcs,
1259};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/delay.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32#include "vi.h"
33#include "vid.h"
34
35#include "oss/oss_2_4_d.h"
36#include "oss/oss_2_4_sh_mask.h"
37
38#include "gmc/gmc_7_1_d.h"
39#include "gmc/gmc_7_1_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44
45#include "bif/bif_5_0_d.h"
46#include "bif/bif_5_0_sh_mask.h"
47
48#include "iceland_sdma_pkt_open.h"
49
50#include "ivsrcid/ivsrcid_vislands30.h"
51
52static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
53static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
54static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
55static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
56
57MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
58MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
59
60static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
61{
62 SDMA0_REGISTER_OFFSET,
63 SDMA1_REGISTER_OFFSET
64};
65
66static const u32 golden_settings_iceland_a11[] =
67{
68 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
69 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
70 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
71 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
72};
73
74static const u32 iceland_mgcg_cgcg_init[] =
75{
76 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
77 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
78};
79
80/*
81 * sDMA - System DMA
82 * Starting with CIK, the GPU has new asynchronous
83 * DMA engines. These engines are used for compute
84 * and gfx. There are two DMA engines (SDMA0, SDMA1)
85 * and each one supports 1 ring buffer used for gfx
86 * and 2 queues used for compute.
87 *
88 * The programming model is very similar to the CP
89 * (ring buffer, IBs, etc.), but sDMA has it's own
90 * packet format that is different from the PM4 format
91 * used by the CP. sDMA supports copying data, writing
92 * embedded data, solid fills, and a number of other
93 * things. It also has support for tiling/detiling of
94 * buffers.
95 */
96
97static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
98{
99 switch (adev->asic_type) {
100 case CHIP_TOPAZ:
101 amdgpu_device_program_register_sequence(adev,
102 iceland_mgcg_cgcg_init,
103 ARRAY_SIZE(iceland_mgcg_cgcg_init));
104 amdgpu_device_program_register_sequence(adev,
105 golden_settings_iceland_a11,
106 ARRAY_SIZE(golden_settings_iceland_a11));
107 break;
108 default:
109 break;
110 }
111}
112
113static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
114{
115 int i;
116 for (i = 0; i < adev->sdma.num_instances; i++) {
117 release_firmware(adev->sdma.instance[i].fw);
118 adev->sdma.instance[i].fw = NULL;
119 }
120}
121
122/**
123 * sdma_v2_4_init_microcode - load ucode images from disk
124 *
125 * @adev: amdgpu_device pointer
126 *
127 * Use the firmware interface to load the ucode images into
128 * the driver (not loaded into hw).
129 * Returns 0 on success, error on failure.
130 */
131static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
132{
133 const char *chip_name;
134 char fw_name[30];
135 int err = 0, i;
136 struct amdgpu_firmware_info *info = NULL;
137 const struct common_firmware_header *header = NULL;
138 const struct sdma_firmware_header_v1_0 *hdr;
139
140 DRM_DEBUG("\n");
141
142 switch (adev->asic_type) {
143 case CHIP_TOPAZ:
144 chip_name = "topaz";
145 break;
146 default: BUG();
147 }
148
149 for (i = 0; i < adev->sdma.num_instances; i++) {
150 if (i == 0)
151 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
152 else
153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
154 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
155 if (err)
156 goto out;
157 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
158 if (err)
159 goto out;
160 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
161 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
162 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
163 if (adev->sdma.instance[i].feature_version >= 20)
164 adev->sdma.instance[i].burst_nop = true;
165
166 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
167 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
168 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
169 info->fw = adev->sdma.instance[i].fw;
170 header = (const struct common_firmware_header *)info->fw->data;
171 adev->firmware.fw_size +=
172 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
173 }
174 }
175
176out:
177 if (err) {
178 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
179 for (i = 0; i < adev->sdma.num_instances; i++) {
180 release_firmware(adev->sdma.instance[i].fw);
181 adev->sdma.instance[i].fw = NULL;
182 }
183 }
184 return err;
185}
186
187/**
188 * sdma_v2_4_ring_get_rptr - get the current read pointer
189 *
190 * @ring: amdgpu ring pointer
191 *
192 * Get the current rptr from the hardware (VI+).
193 */
194static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
195{
196 /* XXX check if swapping is necessary on BE */
197 return ring->adev->wb.wb[ring->rptr_offs] >> 2;
198}
199
200/**
201 * sdma_v2_4_ring_get_wptr - get the current write pointer
202 *
203 * @ring: amdgpu ring pointer
204 *
205 * Get the current wptr from the hardware (VI+).
206 */
207static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
208{
209 struct amdgpu_device *adev = ring->adev;
210 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
211
212 return wptr;
213}
214
215/**
216 * sdma_v2_4_ring_set_wptr - commit the write pointer
217 *
218 * @ring: amdgpu ring pointer
219 *
220 * Write the wptr back to the hardware (VI+).
221 */
222static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
223{
224 struct amdgpu_device *adev = ring->adev;
225
226 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
227}
228
229static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
230{
231 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
232 int i;
233
234 for (i = 0; i < count; i++)
235 if (sdma && sdma->burst_nop && (i == 0))
236 amdgpu_ring_write(ring, ring->funcs->nop |
237 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
238 else
239 amdgpu_ring_write(ring, ring->funcs->nop);
240}
241
242/**
243 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
244 *
245 * @ring: amdgpu ring pointer
246 * @job: job to retrieve vmid from
247 * @ib: IB object to schedule
248 * @flags: unused
249 *
250 * Schedule an IB in the DMA ring (VI).
251 */
252static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
253 struct amdgpu_job *job,
254 struct amdgpu_ib *ib,
255 uint32_t flags)
256{
257 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
258
259 /* IB packet must end on a 8 DW boundary */
260 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
261
262 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
263 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
264 /* base must be 32 byte aligned */
265 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
266 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
267 amdgpu_ring_write(ring, ib->length_dw);
268 amdgpu_ring_write(ring, 0);
269 amdgpu_ring_write(ring, 0);
270
271}
272
273/**
274 * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
275 *
276 * @ring: amdgpu ring pointer
277 *
278 * Emit an hdp flush packet on the requested DMA ring.
279 */
280static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
281{
282 u32 ref_and_mask = 0;
283
284 if (ring->me == 0)
285 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
286 else
287 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
288
289 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
290 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
291 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
292 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
293 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
294 amdgpu_ring_write(ring, ref_and_mask); /* reference */
295 amdgpu_ring_write(ring, ref_and_mask); /* mask */
296 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
297 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
298}
299
300/**
301 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
302 *
303 * @ring: amdgpu ring pointer
304 * @addr: address
305 * @seq: sequence number
306 * @flags: fence related flags
307 *
308 * Add a DMA fence packet to the ring to write
309 * the fence seq number and DMA trap packet to generate
310 * an interrupt if needed (VI).
311 */
312static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
313 unsigned flags)
314{
315 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
316 /* write the fence */
317 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
318 amdgpu_ring_write(ring, lower_32_bits(addr));
319 amdgpu_ring_write(ring, upper_32_bits(addr));
320 amdgpu_ring_write(ring, lower_32_bits(seq));
321
322 /* optionally write high bits as well */
323 if (write64bit) {
324 addr += 4;
325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
326 amdgpu_ring_write(ring, lower_32_bits(addr));
327 amdgpu_ring_write(ring, upper_32_bits(addr));
328 amdgpu_ring_write(ring, upper_32_bits(seq));
329 }
330
331 /* generate an interrupt */
332 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
333 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
334}
335
336/**
337 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
338 *
339 * @adev: amdgpu_device pointer
340 *
341 * Stop the gfx async dma ring buffers (VI).
342 */
343static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
344{
345 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
346 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
347 u32 rb_cntl, ib_cntl;
348 int i;
349
350 if ((adev->mman.buffer_funcs_ring == sdma0) ||
351 (adev->mman.buffer_funcs_ring == sdma1))
352 amdgpu_ttm_set_buffer_funcs_status(adev, false);
353
354 for (i = 0; i < adev->sdma.num_instances; i++) {
355 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
356 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
357 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
358 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
359 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
360 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
361 }
362}
363
364/**
365 * sdma_v2_4_rlc_stop - stop the compute async dma engines
366 *
367 * @adev: amdgpu_device pointer
368 *
369 * Stop the compute async dma queues (VI).
370 */
371static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
372{
373 /* XXX todo */
374}
375
376/**
377 * sdma_v2_4_enable - stop the async dma engines
378 *
379 * @adev: amdgpu_device pointer
380 * @enable: enable/disable the DMA MEs.
381 *
382 * Halt or unhalt the async dma engines (VI).
383 */
384static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
385{
386 u32 f32_cntl;
387 int i;
388
389 if (!enable) {
390 sdma_v2_4_gfx_stop(adev);
391 sdma_v2_4_rlc_stop(adev);
392 }
393
394 for (i = 0; i < adev->sdma.num_instances; i++) {
395 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
396 if (enable)
397 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
398 else
399 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
400 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
401 }
402}
403
404/**
405 * sdma_v2_4_gfx_resume - setup and start the async dma engines
406 *
407 * @adev: amdgpu_device pointer
408 *
409 * Set up the gfx DMA ring buffers and enable them (VI).
410 * Returns 0 for success, error for failure.
411 */
412static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
413{
414 struct amdgpu_ring *ring;
415 u32 rb_cntl, ib_cntl;
416 u32 rb_bufsz;
417 u32 wb_offset;
418 int i, j, r;
419
420 for (i = 0; i < adev->sdma.num_instances; i++) {
421 ring = &adev->sdma.instance[i].ring;
422 wb_offset = (ring->rptr_offs * 4);
423
424 mutex_lock(&adev->srbm_mutex);
425 for (j = 0; j < 16; j++) {
426 vi_srbm_select(adev, 0, 0, 0, j);
427 /* SDMA GFX */
428 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
429 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
430 }
431 vi_srbm_select(adev, 0, 0, 0, 0);
432 mutex_unlock(&adev->srbm_mutex);
433
434 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
435 adev->gfx.config.gb_addr_config & 0x70);
436
437 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
438
439 /* Set ring buffer size in dwords */
440 rb_bufsz = order_base_2(ring->ring_size / 4);
441 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
442 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
443#ifdef __BIG_ENDIAN
444 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
445 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
446 RPTR_WRITEBACK_SWAP_ENABLE, 1);
447#endif
448 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
449
450 /* Initialize the ring buffer's read and write pointers */
451 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
452 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
453 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
454 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
455
456 /* set the wb address whether it's enabled or not */
457 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
458 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
459 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
460 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
461
462 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
463
464 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
465 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
466
467 ring->wptr = 0;
468 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
469
470 /* enable DMA RB */
471 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
472 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
473
474 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
475 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
476#ifdef __BIG_ENDIAN
477 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
478#endif
479 /* enable DMA IBs */
480 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
481
482 ring->sched.ready = true;
483 }
484
485 sdma_v2_4_enable(adev, true);
486 for (i = 0; i < adev->sdma.num_instances; i++) {
487 ring = &adev->sdma.instance[i].ring;
488 r = amdgpu_ring_test_helper(ring);
489 if (r)
490 return r;
491
492 if (adev->mman.buffer_funcs_ring == ring)
493 amdgpu_ttm_set_buffer_funcs_status(adev, true);
494 }
495
496 return 0;
497}
498
499/**
500 * sdma_v2_4_rlc_resume - setup and start the async dma engines
501 *
502 * @adev: amdgpu_device pointer
503 *
504 * Set up the compute DMA queues and enable them (VI).
505 * Returns 0 for success, error for failure.
506 */
507static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
508{
509 /* XXX todo */
510 return 0;
511}
512
513
514/**
515 * sdma_v2_4_start - setup and start the async dma engines
516 *
517 * @adev: amdgpu_device pointer
518 *
519 * Set up the DMA engines and enable them (VI).
520 * Returns 0 for success, error for failure.
521 */
522static int sdma_v2_4_start(struct amdgpu_device *adev)
523{
524 int r;
525
526 /* halt the engine before programing */
527 sdma_v2_4_enable(adev, false);
528
529 /* start the gfx rings and rlc compute queues */
530 r = sdma_v2_4_gfx_resume(adev);
531 if (r)
532 return r;
533 r = sdma_v2_4_rlc_resume(adev);
534 if (r)
535 return r;
536
537 return 0;
538}
539
540/**
541 * sdma_v2_4_ring_test_ring - simple async dma engine test
542 *
543 * @ring: amdgpu_ring structure holding ring information
544 *
545 * Test the DMA engine by writing using it to write an
546 * value to memory. (VI).
547 * Returns 0 for success, error for failure.
548 */
549static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
550{
551 struct amdgpu_device *adev = ring->adev;
552 unsigned i;
553 unsigned index;
554 int r;
555 u32 tmp;
556 u64 gpu_addr;
557
558 r = amdgpu_device_wb_get(adev, &index);
559 if (r)
560 return r;
561
562 gpu_addr = adev->wb.gpu_addr + (index * 4);
563 tmp = 0xCAFEDEAD;
564 adev->wb.wb[index] = cpu_to_le32(tmp);
565
566 r = amdgpu_ring_alloc(ring, 5);
567 if (r)
568 goto error_free_wb;
569
570 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
571 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
572 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
573 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
574 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
575 amdgpu_ring_write(ring, 0xDEADBEEF);
576 amdgpu_ring_commit(ring);
577
578 for (i = 0; i < adev->usec_timeout; i++) {
579 tmp = le32_to_cpu(adev->wb.wb[index]);
580 if (tmp == 0xDEADBEEF)
581 break;
582 udelay(1);
583 }
584
585 if (i >= adev->usec_timeout)
586 r = -ETIMEDOUT;
587
588error_free_wb:
589 amdgpu_device_wb_free(adev, index);
590 return r;
591}
592
593/**
594 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
595 *
596 * @ring: amdgpu_ring structure holding ring information
597 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
598 *
599 * Test a simple IB in the DMA ring (VI).
600 * Returns 0 on success, error on failure.
601 */
602static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
603{
604 struct amdgpu_device *adev = ring->adev;
605 struct amdgpu_ib ib;
606 struct dma_fence *f = NULL;
607 unsigned index;
608 u32 tmp = 0;
609 u64 gpu_addr;
610 long r;
611
612 r = amdgpu_device_wb_get(adev, &index);
613 if (r)
614 return r;
615
616 gpu_addr = adev->wb.gpu_addr + (index * 4);
617 tmp = 0xCAFEDEAD;
618 adev->wb.wb[index] = cpu_to_le32(tmp);
619 memset(&ib, 0, sizeof(ib));
620 r = amdgpu_ib_get(adev, NULL, 256,
621 AMDGPU_IB_POOL_DIRECT, &ib);
622 if (r)
623 goto err0;
624
625 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
626 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
627 ib.ptr[1] = lower_32_bits(gpu_addr);
628 ib.ptr[2] = upper_32_bits(gpu_addr);
629 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
630 ib.ptr[4] = 0xDEADBEEF;
631 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
632 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
633 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
634 ib.length_dw = 8;
635
636 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
637 if (r)
638 goto err1;
639
640 r = dma_fence_wait_timeout(f, false, timeout);
641 if (r == 0) {
642 r = -ETIMEDOUT;
643 goto err1;
644 } else if (r < 0) {
645 goto err1;
646 }
647 tmp = le32_to_cpu(adev->wb.wb[index]);
648 if (tmp == 0xDEADBEEF)
649 r = 0;
650 else
651 r = -EINVAL;
652
653err1:
654 amdgpu_ib_free(adev, &ib, NULL);
655 dma_fence_put(f);
656err0:
657 amdgpu_device_wb_free(adev, index);
658 return r;
659}
660
661/**
662 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
663 *
664 * @ib: indirect buffer to fill with commands
665 * @pe: addr of the page entry
666 * @src: src addr to copy from
667 * @count: number of page entries to update
668 *
669 * Update PTEs by copying them from the GART using sDMA (CIK).
670 */
671static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
672 uint64_t pe, uint64_t src,
673 unsigned count)
674{
675 unsigned bytes = count * 8;
676
677 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
678 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
679 ib->ptr[ib->length_dw++] = bytes;
680 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
681 ib->ptr[ib->length_dw++] = lower_32_bits(src);
682 ib->ptr[ib->length_dw++] = upper_32_bits(src);
683 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
684 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
685}
686
687/**
688 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
689 *
690 * @ib: indirect buffer to fill with commands
691 * @pe: addr of the page entry
692 * @value: dst addr to write into pe
693 * @count: number of page entries to update
694 * @incr: increase next addr by incr bytes
695 *
696 * Update PTEs by writing them manually using sDMA (CIK).
697 */
698static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
699 uint64_t value, unsigned count,
700 uint32_t incr)
701{
702 unsigned ndw = count * 2;
703
704 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
705 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
706 ib->ptr[ib->length_dw++] = pe;
707 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
708 ib->ptr[ib->length_dw++] = ndw;
709 for (; ndw > 0; ndw -= 2) {
710 ib->ptr[ib->length_dw++] = lower_32_bits(value);
711 ib->ptr[ib->length_dw++] = upper_32_bits(value);
712 value += incr;
713 }
714}
715
716/**
717 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
718 *
719 * @ib: indirect buffer to fill with commands
720 * @pe: addr of the page entry
721 * @addr: dst addr to write into pe
722 * @count: number of page entries to update
723 * @incr: increase next addr by incr bytes
724 * @flags: access flags
725 *
726 * Update the page tables using sDMA (CIK).
727 */
728static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
729 uint64_t addr, unsigned count,
730 uint32_t incr, uint64_t flags)
731{
732 /* for physically contiguous pages (vram) */
733 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
734 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
735 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
736 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
737 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
738 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
739 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
740 ib->ptr[ib->length_dw++] = incr; /* increment size */
741 ib->ptr[ib->length_dw++] = 0;
742 ib->ptr[ib->length_dw++] = count; /* number of entries */
743}
744
745/**
746 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
747 *
748 * @ring: amdgpu_ring structure holding ring information
749 * @ib: indirect buffer to fill with padding
750 *
751 */
752static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
753{
754 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
755 u32 pad_count;
756 int i;
757
758 pad_count = (-ib->length_dw) & 7;
759 for (i = 0; i < pad_count; i++)
760 if (sdma && sdma->burst_nop && (i == 0))
761 ib->ptr[ib->length_dw++] =
762 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
763 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
764 else
765 ib->ptr[ib->length_dw++] =
766 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
767}
768
769/**
770 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
771 *
772 * @ring: amdgpu_ring pointer
773 *
774 * Make sure all previous operations are completed (CIK).
775 */
776static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
777{
778 uint32_t seq = ring->fence_drv.sync_seq;
779 uint64_t addr = ring->fence_drv.gpu_addr;
780
781 /* wait for idle */
782 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
783 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
784 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
785 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
786 amdgpu_ring_write(ring, addr & 0xfffffffc);
787 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
788 amdgpu_ring_write(ring, seq); /* reference */
789 amdgpu_ring_write(ring, 0xffffffff); /* mask */
790 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
791 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
792}
793
794/**
795 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
796 *
797 * @ring: amdgpu_ring pointer
798 * @vmid: vmid number to use
799 * @pd_addr: address
800 *
801 * Update the page table base and flush the VM TLB
802 * using sDMA (VI).
803 */
804static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
805 unsigned vmid, uint64_t pd_addr)
806{
807 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
808
809 /* wait for flush */
810 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
811 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
812 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
813 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
814 amdgpu_ring_write(ring, 0);
815 amdgpu_ring_write(ring, 0); /* reference */
816 amdgpu_ring_write(ring, 0); /* mask */
817 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
818 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
819}
820
821static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
822 uint32_t reg, uint32_t val)
823{
824 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
825 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
826 amdgpu_ring_write(ring, reg);
827 amdgpu_ring_write(ring, val);
828}
829
830static int sdma_v2_4_early_init(void *handle)
831{
832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
833
834 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
835
836 sdma_v2_4_set_ring_funcs(adev);
837 sdma_v2_4_set_buffer_funcs(adev);
838 sdma_v2_4_set_vm_pte_funcs(adev);
839 sdma_v2_4_set_irq_funcs(adev);
840
841 return 0;
842}
843
844static int sdma_v2_4_sw_init(void *handle)
845{
846 struct amdgpu_ring *ring;
847 int r, i;
848 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
849
850 /* SDMA trap event */
851 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
852 &adev->sdma.trap_irq);
853 if (r)
854 return r;
855
856 /* SDMA Privileged inst */
857 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
858 &adev->sdma.illegal_inst_irq);
859 if (r)
860 return r;
861
862 /* SDMA Privileged inst */
863 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
864 &adev->sdma.illegal_inst_irq);
865 if (r)
866 return r;
867
868 r = sdma_v2_4_init_microcode(adev);
869 if (r) {
870 DRM_ERROR("Failed to load sdma firmware!\n");
871 return r;
872 }
873
874 for (i = 0; i < adev->sdma.num_instances; i++) {
875 ring = &adev->sdma.instance[i].ring;
876 ring->ring_obj = NULL;
877 ring->use_doorbell = false;
878 sprintf(ring->name, "sdma%d", i);
879 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
880 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
881 AMDGPU_SDMA_IRQ_INSTANCE1,
882 AMDGPU_RING_PRIO_DEFAULT, NULL);
883 if (r)
884 return r;
885 }
886
887 return r;
888}
889
890static int sdma_v2_4_sw_fini(void *handle)
891{
892 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
893 int i;
894
895 for (i = 0; i < adev->sdma.num_instances; i++)
896 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
897
898 sdma_v2_4_free_microcode(adev);
899 return 0;
900}
901
902static int sdma_v2_4_hw_init(void *handle)
903{
904 int r;
905 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
906
907 sdma_v2_4_init_golden_registers(adev);
908
909 r = sdma_v2_4_start(adev);
910 if (r)
911 return r;
912
913 return r;
914}
915
916static int sdma_v2_4_hw_fini(void *handle)
917{
918 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
919
920 sdma_v2_4_enable(adev, false);
921
922 return 0;
923}
924
925static int sdma_v2_4_suspend(void *handle)
926{
927 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
928
929 return sdma_v2_4_hw_fini(adev);
930}
931
932static int sdma_v2_4_resume(void *handle)
933{
934 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
935
936 return sdma_v2_4_hw_init(adev);
937}
938
939static bool sdma_v2_4_is_idle(void *handle)
940{
941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
942 u32 tmp = RREG32(mmSRBM_STATUS2);
943
944 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
945 SRBM_STATUS2__SDMA1_BUSY_MASK))
946 return false;
947
948 return true;
949}
950
951static int sdma_v2_4_wait_for_idle(void *handle)
952{
953 unsigned i;
954 u32 tmp;
955 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
956
957 for (i = 0; i < adev->usec_timeout; i++) {
958 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
959 SRBM_STATUS2__SDMA1_BUSY_MASK);
960
961 if (!tmp)
962 return 0;
963 udelay(1);
964 }
965 return -ETIMEDOUT;
966}
967
968static int sdma_v2_4_soft_reset(void *handle)
969{
970 u32 srbm_soft_reset = 0;
971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
972 u32 tmp = RREG32(mmSRBM_STATUS2);
973
974 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
975 /* sdma0 */
976 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
977 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
978 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
979 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
980 }
981 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
982 /* sdma1 */
983 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
984 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
985 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
986 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
987 }
988
989 if (srbm_soft_reset) {
990 tmp = RREG32(mmSRBM_SOFT_RESET);
991 tmp |= srbm_soft_reset;
992 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
993 WREG32(mmSRBM_SOFT_RESET, tmp);
994 tmp = RREG32(mmSRBM_SOFT_RESET);
995
996 udelay(50);
997
998 tmp &= ~srbm_soft_reset;
999 WREG32(mmSRBM_SOFT_RESET, tmp);
1000 tmp = RREG32(mmSRBM_SOFT_RESET);
1001
1002 /* Wait a little for things to settle down */
1003 udelay(50);
1004 }
1005
1006 return 0;
1007}
1008
1009static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1010 struct amdgpu_irq_src *src,
1011 unsigned type,
1012 enum amdgpu_interrupt_state state)
1013{
1014 u32 sdma_cntl;
1015
1016 switch (type) {
1017 case AMDGPU_SDMA_IRQ_INSTANCE0:
1018 switch (state) {
1019 case AMDGPU_IRQ_STATE_DISABLE:
1020 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1021 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1022 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1023 break;
1024 case AMDGPU_IRQ_STATE_ENABLE:
1025 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1026 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1027 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1028 break;
1029 default:
1030 break;
1031 }
1032 break;
1033 case AMDGPU_SDMA_IRQ_INSTANCE1:
1034 switch (state) {
1035 case AMDGPU_IRQ_STATE_DISABLE:
1036 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1037 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1038 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1039 break;
1040 case AMDGPU_IRQ_STATE_ENABLE:
1041 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1042 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1043 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1044 break;
1045 default:
1046 break;
1047 }
1048 break;
1049 default:
1050 break;
1051 }
1052 return 0;
1053}
1054
1055static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1056 struct amdgpu_irq_src *source,
1057 struct amdgpu_iv_entry *entry)
1058{
1059 u8 instance_id, queue_id;
1060
1061 instance_id = (entry->ring_id & 0x3) >> 0;
1062 queue_id = (entry->ring_id & 0xc) >> 2;
1063 DRM_DEBUG("IH: SDMA trap\n");
1064 switch (instance_id) {
1065 case 0:
1066 switch (queue_id) {
1067 case 0:
1068 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1069 break;
1070 case 1:
1071 /* XXX compute */
1072 break;
1073 case 2:
1074 /* XXX compute */
1075 break;
1076 }
1077 break;
1078 case 1:
1079 switch (queue_id) {
1080 case 0:
1081 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1082 break;
1083 case 1:
1084 /* XXX compute */
1085 break;
1086 case 2:
1087 /* XXX compute */
1088 break;
1089 }
1090 break;
1091 }
1092 return 0;
1093}
1094
1095static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1096 struct amdgpu_irq_src *source,
1097 struct amdgpu_iv_entry *entry)
1098{
1099 u8 instance_id, queue_id;
1100
1101 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1102 instance_id = (entry->ring_id & 0x3) >> 0;
1103 queue_id = (entry->ring_id & 0xc) >> 2;
1104
1105 if (instance_id <= 1 && queue_id == 0)
1106 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1107 return 0;
1108}
1109
1110static int sdma_v2_4_set_clockgating_state(void *handle,
1111 enum amd_clockgating_state state)
1112{
1113 /* XXX handled via the smc on VI */
1114 return 0;
1115}
1116
1117static int sdma_v2_4_set_powergating_state(void *handle,
1118 enum amd_powergating_state state)
1119{
1120 return 0;
1121}
1122
1123static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1124 .name = "sdma_v2_4",
1125 .early_init = sdma_v2_4_early_init,
1126 .late_init = NULL,
1127 .sw_init = sdma_v2_4_sw_init,
1128 .sw_fini = sdma_v2_4_sw_fini,
1129 .hw_init = sdma_v2_4_hw_init,
1130 .hw_fini = sdma_v2_4_hw_fini,
1131 .suspend = sdma_v2_4_suspend,
1132 .resume = sdma_v2_4_resume,
1133 .is_idle = sdma_v2_4_is_idle,
1134 .wait_for_idle = sdma_v2_4_wait_for_idle,
1135 .soft_reset = sdma_v2_4_soft_reset,
1136 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1137 .set_powergating_state = sdma_v2_4_set_powergating_state,
1138};
1139
1140static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1141 .type = AMDGPU_RING_TYPE_SDMA,
1142 .align_mask = 0xf,
1143 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1144 .support_64bit_ptrs = false,
1145 .get_rptr = sdma_v2_4_ring_get_rptr,
1146 .get_wptr = sdma_v2_4_ring_get_wptr,
1147 .set_wptr = sdma_v2_4_ring_set_wptr,
1148 .emit_frame_size =
1149 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1150 3 + /* hdp invalidate */
1151 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1152 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1153 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1154 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1155 .emit_ib = sdma_v2_4_ring_emit_ib,
1156 .emit_fence = sdma_v2_4_ring_emit_fence,
1157 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1158 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1159 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1160 .test_ring = sdma_v2_4_ring_test_ring,
1161 .test_ib = sdma_v2_4_ring_test_ib,
1162 .insert_nop = sdma_v2_4_ring_insert_nop,
1163 .pad_ib = sdma_v2_4_ring_pad_ib,
1164 .emit_wreg = sdma_v2_4_ring_emit_wreg,
1165};
1166
1167static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1168{
1169 int i;
1170
1171 for (i = 0; i < adev->sdma.num_instances; i++) {
1172 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1173 adev->sdma.instance[i].ring.me = i;
1174 }
1175}
1176
1177static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1178 .set = sdma_v2_4_set_trap_irq_state,
1179 .process = sdma_v2_4_process_trap_irq,
1180};
1181
1182static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1183 .process = sdma_v2_4_process_illegal_inst_irq,
1184};
1185
1186static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1187{
1188 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1189 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1190 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1191}
1192
1193/**
1194 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1195 *
1196 * @ib: indirect buffer to copy to
1197 * @src_offset: src GPU address
1198 * @dst_offset: dst GPU address
1199 * @byte_count: number of bytes to xfer
1200 * @tmz: unused
1201 *
1202 * Copy GPU buffers using the DMA engine (VI).
1203 * Used by the amdgpu ttm implementation to move pages if
1204 * registered as the asic copy callback.
1205 */
1206static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1207 uint64_t src_offset,
1208 uint64_t dst_offset,
1209 uint32_t byte_count,
1210 bool tmz)
1211{
1212 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1213 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1214 ib->ptr[ib->length_dw++] = byte_count;
1215 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1216 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1217 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1218 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1219 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1220}
1221
1222/**
1223 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1224 *
1225 * @ib: indirect buffer to copy to
1226 * @src_data: value to write to buffer
1227 * @dst_offset: dst GPU address
1228 * @byte_count: number of bytes to xfer
1229 *
1230 * Fill GPU buffers using the DMA engine (VI).
1231 */
1232static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1233 uint32_t src_data,
1234 uint64_t dst_offset,
1235 uint32_t byte_count)
1236{
1237 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1238 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1239 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1240 ib->ptr[ib->length_dw++] = src_data;
1241 ib->ptr[ib->length_dw++] = byte_count;
1242}
1243
1244static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1245 .copy_max_bytes = 0x1fffff,
1246 .copy_num_dw = 7,
1247 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1248
1249 .fill_max_bytes = 0x1fffff,
1250 .fill_num_dw = 7,
1251 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1252};
1253
1254static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1255{
1256 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1257 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1258}
1259
1260static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1261 .copy_pte_num_dw = 7,
1262 .copy_pte = sdma_v2_4_vm_copy_pte,
1263
1264 .write_pte = sdma_v2_4_vm_write_pte,
1265 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1266};
1267
1268static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1269{
1270 unsigned i;
1271
1272 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1273 for (i = 0; i < adev->sdma.num_instances; i++) {
1274 adev->vm_manager.vm_pte_scheds[i] =
1275 &adev->sdma.instance[i].ring.sched;
1276 }
1277 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1278}
1279
1280const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1281{
1282 .type = AMD_IP_BLOCK_TYPE_SDMA,
1283 .major = 2,
1284 .minor = 4,
1285 .rev = 0,
1286 .funcs = &sdma_v2_4_ip_funcs,
1287};