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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 *
5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 */
8
9#include <linux/acpi.h>
10#include <linux/bitops.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/kernel.h>
17#include <linux/mod_devicetable.h>
18#include <linux/platform_device.h>
19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/property.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24
25#define MPC8XXX_GPIO_PINS 32
26
27#define GPIO_DIR 0x00
28#define GPIO_ODR 0x04
29#define GPIO_DAT 0x08
30#define GPIO_IER 0x0c
31#define GPIO_IMR 0x10
32#define GPIO_ICR 0x14
33#define GPIO_ICR2 0x18
34#define GPIO_IBE 0x18
35
36struct mpc8xxx_gpio_chip {
37 struct gpio_chip gc;
38 void __iomem *regs;
39 raw_spinlock_t lock;
40
41 int (*direction_output)(struct gpio_chip *chip,
42 unsigned offset, int value);
43
44 struct irq_domain *irq;
45 int irqn;
46};
47
48/*
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
50 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
51 * This inline helper give the right bitmask for a certain line.
52 */
53static inline u32 mpc_pin2mask(unsigned int offset)
54{
55 return BIT(31 - offset);
56}
57
58/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
59 * defined as output cannot be determined by reading GPDAT register,
60 * so we use shadow data register instead. The status of input pins
61 * is determined by reading GPDAT register.
62 */
63static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
64{
65 u32 val;
66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
67 u32 out_mask, out_shadow;
68
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
71 out_shadow = gc->bgpio_data & out_mask;
72
73 return !!((val | out_shadow) & mpc_pin2mask(gpio));
74}
75
76static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
78{
79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
80 /* GPIO 28..31 are input only on MPC5121 */
81 if (gpio >= 28)
82 return -EINVAL;
83
84 return mpc8xxx_gc->direction_output(gc, gpio, val);
85}
86
87static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
88 unsigned int gpio, int val)
89{
90 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
91 /* GPIO 0..3 are input only on MPC5125 */
92 if (gpio <= 3)
93 return -EINVAL;
94
95 return mpc8xxx_gc->direction_output(gc, gpio, val);
96}
97
98static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
99{
100 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
101
102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
103 return irq_create_mapping(mpc8xxx_gc->irq, offset);
104 else
105 return -ENXIO;
106}
107
108static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
109{
110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
111 struct gpio_chip *gc = &mpc8xxx_gc->gc;
112 unsigned long mask;
113 int i;
114
115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
117 for_each_set_bit(i, &mask, 32)
118 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
119
120 return IRQ_HANDLED;
121}
122
123static void mpc8xxx_irq_unmask(struct irq_data *d)
124{
125 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
126 struct gpio_chip *gc = &mpc8xxx_gc->gc;
127 unsigned long flags;
128
129 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
130
131 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
132 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
133 | mpc_pin2mask(irqd_to_hwirq(d)));
134
135 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
136}
137
138static void mpc8xxx_irq_mask(struct irq_data *d)
139{
140 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
141 struct gpio_chip *gc = &mpc8xxx_gc->gc;
142 unsigned long flags;
143
144 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
145
146 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
147 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
148 & ~mpc_pin2mask(irqd_to_hwirq(d)));
149
150 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
151}
152
153static void mpc8xxx_irq_ack(struct irq_data *d)
154{
155 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
156 struct gpio_chip *gc = &mpc8xxx_gc->gc;
157
158 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
159 mpc_pin2mask(irqd_to_hwirq(d)));
160}
161
162static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
163{
164 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
165 struct gpio_chip *gc = &mpc8xxx_gc->gc;
166 unsigned long flags;
167
168 switch (flow_type) {
169 case IRQ_TYPE_EDGE_FALLING:
170 case IRQ_TYPE_LEVEL_LOW:
171 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
172 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
173 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
174 | mpc_pin2mask(irqd_to_hwirq(d)));
175 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
176 break;
177
178 case IRQ_TYPE_EDGE_BOTH:
179 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
180 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
181 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
182 & ~mpc_pin2mask(irqd_to_hwirq(d)));
183 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
184 break;
185
186 default:
187 return -EINVAL;
188 }
189
190 return 0;
191}
192
193static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
194{
195 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
196 struct gpio_chip *gc = &mpc8xxx_gc->gc;
197 unsigned long gpio = irqd_to_hwirq(d);
198 void __iomem *reg;
199 unsigned int shift;
200 unsigned long flags;
201
202 if (gpio < 16) {
203 reg = mpc8xxx_gc->regs + GPIO_ICR;
204 shift = (15 - gpio) * 2;
205 } else {
206 reg = mpc8xxx_gc->regs + GPIO_ICR2;
207 shift = (15 - (gpio % 16)) * 2;
208 }
209
210 switch (flow_type) {
211 case IRQ_TYPE_EDGE_FALLING:
212 case IRQ_TYPE_LEVEL_LOW:
213 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
214 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
215 | (2 << shift));
216 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
217 break;
218
219 case IRQ_TYPE_EDGE_RISING:
220 case IRQ_TYPE_LEVEL_HIGH:
221 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
222 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
223 | (1 << shift));
224 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
225 break;
226
227 case IRQ_TYPE_EDGE_BOTH:
228 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
229 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
230 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
231 break;
232
233 default:
234 return -EINVAL;
235 }
236
237 return 0;
238}
239
240static struct irq_chip mpc8xxx_irq_chip = {
241 .name = "mpc8xxx-gpio",
242 .irq_unmask = mpc8xxx_irq_unmask,
243 .irq_mask = mpc8xxx_irq_mask,
244 .irq_ack = mpc8xxx_irq_ack,
245 /* this might get overwritten in mpc8xxx_probe() */
246 .irq_set_type = mpc8xxx_irq_set_type,
247};
248
249static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
250 irq_hw_number_t hwirq)
251{
252 irq_set_chip_data(irq, h->host_data);
253 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
254
255 return 0;
256}
257
258static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
259 .map = mpc8xxx_gpio_irq_map,
260 .xlate = irq_domain_xlate_twocell,
261};
262
263struct mpc8xxx_gpio_devtype {
264 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
265 int (*gpio_get)(struct gpio_chip *, unsigned int);
266 int (*irq_set_type)(struct irq_data *, unsigned int);
267};
268
269static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
270 .gpio_dir_out = mpc5121_gpio_dir_out,
271 .irq_set_type = mpc512x_irq_set_type,
272};
273
274static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
275 .gpio_dir_out = mpc5125_gpio_dir_out,
276 .irq_set_type = mpc512x_irq_set_type,
277};
278
279static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
280 .gpio_get = mpc8572_gpio_get,
281};
282
283static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
284 .irq_set_type = mpc8xxx_irq_set_type,
285};
286
287static const struct of_device_id mpc8xxx_gpio_ids[] = {
288 { .compatible = "fsl,mpc8349-gpio", },
289 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
290 { .compatible = "fsl,mpc8610-gpio", },
291 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
292 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
293 { .compatible = "fsl,pq3-gpio", },
294 { .compatible = "fsl,ls1028a-gpio", },
295 { .compatible = "fsl,ls1088a-gpio", },
296 { .compatible = "fsl,qoriq-gpio", },
297 {}
298};
299
300static int mpc8xxx_probe(struct platform_device *pdev)
301{
302 const struct mpc8xxx_gpio_devtype *devtype = NULL;
303 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
304 struct device *dev = &pdev->dev;
305 struct fwnode_handle *fwnode;
306 struct gpio_chip *gc;
307 int ret;
308
309 mpc8xxx_gc = devm_kzalloc(dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
310 if (!mpc8xxx_gc)
311 return -ENOMEM;
312
313 platform_set_drvdata(pdev, mpc8xxx_gc);
314
315 raw_spin_lock_init(&mpc8xxx_gc->lock);
316
317 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
318 if (IS_ERR(mpc8xxx_gc->regs))
319 return PTR_ERR(mpc8xxx_gc->regs);
320
321 gc = &mpc8xxx_gc->gc;
322 gc->parent = dev;
323
324 if (device_property_read_bool(dev, "little-endian")) {
325 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT,
326 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR,
327 NULL, BGPIOF_BIG_ENDIAN);
328 if (ret)
329 return ret;
330 dev_dbg(dev, "GPIO registers are LITTLE endian\n");
331 } else {
332 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT,
333 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR,
334 NULL, BGPIOF_BIG_ENDIAN
335 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
336 if (ret)
337 return ret;
338 dev_dbg(dev, "GPIO registers are BIG endian\n");
339 }
340
341 mpc8xxx_gc->direction_output = gc->direction_output;
342
343 devtype = device_get_match_data(dev);
344 if (!devtype)
345 devtype = &mpc8xxx_gpio_devtype_default;
346
347 /*
348 * It's assumed that only a single type of gpio controller is available
349 * on the current machine, so overwriting global data is fine.
350 */
351 if (devtype->irq_set_type)
352 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
353
354 if (devtype->gpio_dir_out)
355 gc->direction_output = devtype->gpio_dir_out;
356 if (devtype->gpio_get)
357 gc->get = devtype->gpio_get;
358
359 gc->to_irq = mpc8xxx_gpio_to_irq;
360
361 /*
362 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
363 * the input enable of each individual GPIO port. When an individual
364 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
365 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
366 * the port value to the GPIO Data Register.
367 */
368 fwnode = dev_fwnode(dev);
369 if (device_is_compatible(dev, "fsl,qoriq-gpio") ||
370 device_is_compatible(dev, "fsl,ls1028a-gpio") ||
371 device_is_compatible(dev, "fsl,ls1088a-gpio") ||
372 is_acpi_node(fwnode)) {
373 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
374 /* Also, latch state of GPIOs configured as output by bootloader. */
375 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) &
376 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
377 }
378
379 ret = devm_gpiochip_add_data(dev, gc, mpc8xxx_gc);
380 if (ret) {
381 dev_err(dev,
382 "GPIO chip registration failed with status %d\n", ret);
383 return ret;
384 }
385
386 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
387 if (mpc8xxx_gc->irqn < 0)
388 return mpc8xxx_gc->irqn;
389
390 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
391 MPC8XXX_GPIO_PINS,
392 &mpc8xxx_gpio_irq_ops,
393 mpc8xxx_gc);
394
395 if (!mpc8xxx_gc->irq)
396 return 0;
397
398 /* ack and mask all irqs */
399 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
400 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
401
402 ret = devm_request_irq(dev, mpc8xxx_gc->irqn,
403 mpc8xxx_gpio_irq_cascade,
404 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
405 mpc8xxx_gc);
406 if (ret) {
407 dev_err(dev, "failed to devm_request_irq(%d), ret = %d\n",
408 mpc8xxx_gc->irqn, ret);
409 goto err;
410 }
411
412 device_init_wakeup(dev, true);
413
414 return 0;
415err:
416 irq_domain_remove(mpc8xxx_gc->irq);
417 return ret;
418}
419
420static void mpc8xxx_remove(struct platform_device *pdev)
421{
422 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
423
424 if (mpc8xxx_gc->irq) {
425 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
426 irq_domain_remove(mpc8xxx_gc->irq);
427 }
428}
429
430static int mpc8xxx_suspend(struct device *dev)
431{
432 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev);
433
434 if (mpc8xxx_gc->irqn && device_may_wakeup(dev))
435 enable_irq_wake(mpc8xxx_gc->irqn);
436
437 return 0;
438}
439
440static int mpc8xxx_resume(struct device *dev)
441{
442 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev);
443
444 if (mpc8xxx_gc->irqn && device_may_wakeup(dev))
445 disable_irq_wake(mpc8xxx_gc->irqn);
446
447 return 0;
448}
449
450static DEFINE_RUNTIME_DEV_PM_OPS(mpc8xx_pm_ops,
451 mpc8xxx_suspend, mpc8xxx_resume, NULL);
452
453#ifdef CONFIG_ACPI
454static const struct acpi_device_id gpio_acpi_ids[] = {
455 {"NXP0031",},
456 { }
457};
458MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
459#endif
460
461static struct platform_driver mpc8xxx_plat_driver = {
462 .probe = mpc8xxx_probe,
463 .remove = mpc8xxx_remove,
464 .driver = {
465 .name = "gpio-mpc8xxx",
466 .of_match_table = mpc8xxx_gpio_ids,
467 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
468 .pm = pm_ptr(&mpc8xx_pm_ops),
469 },
470};
471
472static int __init mpc8xxx_init(void)
473{
474 return platform_driver_register(&mpc8xxx_plat_driver);
475}
476
477arch_initcall(mpc8xxx_init);
1/*
2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/acpi.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/spinlock.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_gpio.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_platform.h>
22#include <linux/property.h>
23#include <linux/mod_devicetable.h>
24#include <linux/slab.h>
25#include <linux/irq.h>
26#include <linux/gpio/driver.h>
27#include <linux/bitops.h>
28#include <linux/interrupt.h>
29
30#define MPC8XXX_GPIO_PINS 32
31
32#define GPIO_DIR 0x00
33#define GPIO_ODR 0x04
34#define GPIO_DAT 0x08
35#define GPIO_IER 0x0c
36#define GPIO_IMR 0x10
37#define GPIO_ICR 0x14
38#define GPIO_ICR2 0x18
39#define GPIO_IBE 0x18
40
41struct mpc8xxx_gpio_chip {
42 struct gpio_chip gc;
43 void __iomem *regs;
44 raw_spinlock_t lock;
45
46 int (*direction_output)(struct gpio_chip *chip,
47 unsigned offset, int value);
48
49 struct irq_domain *irq;
50 unsigned int irqn;
51};
52
53/*
54 * This hardware has a big endian bit assignment such that GPIO line 0 is
55 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
56 * This inline helper give the right bitmask for a certain line.
57 */
58static inline u32 mpc_pin2mask(unsigned int offset)
59{
60 return BIT(31 - offset);
61}
62
63/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
64 * defined as output cannot be determined by reading GPDAT register,
65 * so we use shadow data register instead. The status of input pins
66 * is determined by reading GPDAT register.
67 */
68static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
69{
70 u32 val;
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
72 u32 out_mask, out_shadow;
73
74 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
75 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
76 out_shadow = gc->bgpio_data & out_mask;
77
78 return !!((val | out_shadow) & mpc_pin2mask(gpio));
79}
80
81static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
82 unsigned int gpio, int val)
83{
84 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
85 /* GPIO 28..31 are input only on MPC5121 */
86 if (gpio >= 28)
87 return -EINVAL;
88
89 return mpc8xxx_gc->direction_output(gc, gpio, val);
90}
91
92static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
93 unsigned int gpio, int val)
94{
95 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
96 /* GPIO 0..3 are input only on MPC5125 */
97 if (gpio <= 3)
98 return -EINVAL;
99
100 return mpc8xxx_gc->direction_output(gc, gpio, val);
101}
102
103static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
104{
105 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
106
107 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
108 return irq_create_mapping(mpc8xxx_gc->irq, offset);
109 else
110 return -ENXIO;
111}
112
113static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
114{
115 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
116 struct gpio_chip *gc = &mpc8xxx_gc->gc;
117 unsigned long mask;
118 int i;
119
120 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
121 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
122 for_each_set_bit(i, &mask, 32)
123 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
124
125 return IRQ_HANDLED;
126}
127
128static void mpc8xxx_irq_unmask(struct irq_data *d)
129{
130 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
131 struct gpio_chip *gc = &mpc8xxx_gc->gc;
132 unsigned long flags;
133
134 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
135
136 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
138 | mpc_pin2mask(irqd_to_hwirq(d)));
139
140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
141}
142
143static void mpc8xxx_irq_mask(struct irq_data *d)
144{
145 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
146 struct gpio_chip *gc = &mpc8xxx_gc->gc;
147 unsigned long flags;
148
149 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
150
151 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
152 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
153 & ~mpc_pin2mask(irqd_to_hwirq(d)));
154
155 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
156}
157
158static void mpc8xxx_irq_ack(struct irq_data *d)
159{
160 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
161 struct gpio_chip *gc = &mpc8xxx_gc->gc;
162
163 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
164 mpc_pin2mask(irqd_to_hwirq(d)));
165}
166
167static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
168{
169 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
170 struct gpio_chip *gc = &mpc8xxx_gc->gc;
171 unsigned long flags;
172
173 switch (flow_type) {
174 case IRQ_TYPE_EDGE_FALLING:
175 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
176 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
177 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
178 | mpc_pin2mask(irqd_to_hwirq(d)));
179 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
180 break;
181
182 case IRQ_TYPE_EDGE_BOTH:
183 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
184 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
185 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
186 & ~mpc_pin2mask(irqd_to_hwirq(d)));
187 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
188 break;
189
190 default:
191 return -EINVAL;
192 }
193
194 return 0;
195}
196
197static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
198{
199 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
200 struct gpio_chip *gc = &mpc8xxx_gc->gc;
201 unsigned long gpio = irqd_to_hwirq(d);
202 void __iomem *reg;
203 unsigned int shift;
204 unsigned long flags;
205
206 if (gpio < 16) {
207 reg = mpc8xxx_gc->regs + GPIO_ICR;
208 shift = (15 - gpio) * 2;
209 } else {
210 reg = mpc8xxx_gc->regs + GPIO_ICR2;
211 shift = (15 - (gpio % 16)) * 2;
212 }
213
214 switch (flow_type) {
215 case IRQ_TYPE_EDGE_FALLING:
216 case IRQ_TYPE_LEVEL_LOW:
217 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
218 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
219 | (2 << shift));
220 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
221 break;
222
223 case IRQ_TYPE_EDGE_RISING:
224 case IRQ_TYPE_LEVEL_HIGH:
225 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
226 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
227 | (1 << shift));
228 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
229 break;
230
231 case IRQ_TYPE_EDGE_BOTH:
232 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
233 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
234 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
235 break;
236
237 default:
238 return -EINVAL;
239 }
240
241 return 0;
242}
243
244static struct irq_chip mpc8xxx_irq_chip = {
245 .name = "mpc8xxx-gpio",
246 .irq_unmask = mpc8xxx_irq_unmask,
247 .irq_mask = mpc8xxx_irq_mask,
248 .irq_ack = mpc8xxx_irq_ack,
249 /* this might get overwritten in mpc8xxx_probe() */
250 .irq_set_type = mpc8xxx_irq_set_type,
251};
252
253static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
254 irq_hw_number_t hwirq)
255{
256 irq_set_chip_data(irq, h->host_data);
257 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
258
259 return 0;
260}
261
262static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
263 .map = mpc8xxx_gpio_irq_map,
264 .xlate = irq_domain_xlate_twocell,
265};
266
267struct mpc8xxx_gpio_devtype {
268 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
269 int (*gpio_get)(struct gpio_chip *, unsigned int);
270 int (*irq_set_type)(struct irq_data *, unsigned int);
271};
272
273static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
274 .gpio_dir_out = mpc5121_gpio_dir_out,
275 .irq_set_type = mpc512x_irq_set_type,
276};
277
278static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
279 .gpio_dir_out = mpc5125_gpio_dir_out,
280 .irq_set_type = mpc512x_irq_set_type,
281};
282
283static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
284 .gpio_get = mpc8572_gpio_get,
285};
286
287static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
288 .irq_set_type = mpc8xxx_irq_set_type,
289};
290
291static const struct of_device_id mpc8xxx_gpio_ids[] = {
292 { .compatible = "fsl,mpc8349-gpio", },
293 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
294 { .compatible = "fsl,mpc8610-gpio", },
295 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
296 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
297 { .compatible = "fsl,pq3-gpio", },
298 { .compatible = "fsl,ls1028a-gpio", },
299 { .compatible = "fsl,ls1088a-gpio", },
300 { .compatible = "fsl,qoriq-gpio", },
301 {}
302};
303
304static int mpc8xxx_probe(struct platform_device *pdev)
305{
306 struct device_node *np = pdev->dev.of_node;
307 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
308 struct gpio_chip *gc;
309 const struct mpc8xxx_gpio_devtype *devtype = NULL;
310 struct fwnode_handle *fwnode;
311 int ret;
312
313 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
314 if (!mpc8xxx_gc)
315 return -ENOMEM;
316
317 platform_set_drvdata(pdev, mpc8xxx_gc);
318
319 raw_spin_lock_init(&mpc8xxx_gc->lock);
320
321 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
322 if (IS_ERR(mpc8xxx_gc->regs))
323 return PTR_ERR(mpc8xxx_gc->regs);
324
325 gc = &mpc8xxx_gc->gc;
326 gc->parent = &pdev->dev;
327
328 if (device_property_read_bool(&pdev->dev, "little-endian")) {
329 ret = bgpio_init(gc, &pdev->dev, 4,
330 mpc8xxx_gc->regs + GPIO_DAT,
331 NULL, NULL,
332 mpc8xxx_gc->regs + GPIO_DIR, NULL,
333 BGPIOF_BIG_ENDIAN);
334 if (ret)
335 return ret;
336 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
337 } else {
338 ret = bgpio_init(gc, &pdev->dev, 4,
339 mpc8xxx_gc->regs + GPIO_DAT,
340 NULL, NULL,
341 mpc8xxx_gc->regs + GPIO_DIR, NULL,
342 BGPIOF_BIG_ENDIAN
343 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
344 if (ret)
345 return ret;
346 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
347 }
348
349 mpc8xxx_gc->direction_output = gc->direction_output;
350
351 devtype = device_get_match_data(&pdev->dev);
352 if (!devtype)
353 devtype = &mpc8xxx_gpio_devtype_default;
354
355 /*
356 * It's assumed that only a single type of gpio controller is available
357 * on the current machine, so overwriting global data is fine.
358 */
359 if (devtype->irq_set_type)
360 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
361
362 if (devtype->gpio_dir_out)
363 gc->direction_output = devtype->gpio_dir_out;
364 if (devtype->gpio_get)
365 gc->get = devtype->gpio_get;
366
367 gc->to_irq = mpc8xxx_gpio_to_irq;
368
369 /*
370 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
371 * the input enable of each individual GPIO port. When an individual
372 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
373 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
374 * the port value to the GPIO Data Register.
375 */
376 fwnode = dev_fwnode(&pdev->dev);
377 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
378 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
379 of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
380 is_acpi_node(fwnode))
381 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
382
383 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
384 if (ret) {
385 dev_err(&pdev->dev,
386 "GPIO chip registration failed with status %d\n", ret);
387 return ret;
388 }
389
390 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
391 if (!mpc8xxx_gc->irqn)
392 return 0;
393
394 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
395 MPC8XXX_GPIO_PINS,
396 &mpc8xxx_gpio_irq_ops,
397 mpc8xxx_gc);
398
399 if (!mpc8xxx_gc->irq)
400 return 0;
401
402 /* ack and mask all irqs */
403 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
404 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
405
406 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
407 mpc8xxx_gpio_irq_cascade,
408 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
409 mpc8xxx_gc);
410 if (ret) {
411 dev_err(&pdev->dev,
412 "failed to devm_request_irq(%d), ret = %d\n",
413 mpc8xxx_gc->irqn, ret);
414 goto err;
415 }
416
417 return 0;
418err:
419 irq_domain_remove(mpc8xxx_gc->irq);
420 return ret;
421}
422
423static int mpc8xxx_remove(struct platform_device *pdev)
424{
425 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
426
427 if (mpc8xxx_gc->irq) {
428 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
429 irq_domain_remove(mpc8xxx_gc->irq);
430 }
431
432 return 0;
433}
434
435#ifdef CONFIG_ACPI
436static const struct acpi_device_id gpio_acpi_ids[] = {
437 {"NXP0031",},
438 { }
439};
440MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
441#endif
442
443static struct platform_driver mpc8xxx_plat_driver = {
444 .probe = mpc8xxx_probe,
445 .remove = mpc8xxx_remove,
446 .driver = {
447 .name = "gpio-mpc8xxx",
448 .of_match_table = mpc8xxx_gpio_ids,
449 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
450 },
451};
452
453static int __init mpc8xxx_init(void)
454{
455 return platform_driver_register(&mpc8xxx_plat_driver);
456}
457
458arch_initcall(mpc8xxx_init);