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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_KVM_X86_H
3#define ARCH_X86_KVM_X86_H
4
5#include <linux/kvm_host.h>
6#include <asm/fpu/xstate.h>
7#include <asm/mce.h>
8#include <asm/pvclock.h>
9#include "kvm_cache_regs.h"
10#include "kvm_emulate.h"
11#include "cpuid.h"
12
13struct kvm_caps {
14 /* control of guest tsc rate supported? */
15 bool has_tsc_control;
16 /* maximum supported tsc_khz for guests */
17 u32 max_guest_tsc_khz;
18 /* number of bits of the fractional part of the TSC scaling ratio */
19 u8 tsc_scaling_ratio_frac_bits;
20 /* maximum allowed value of TSC scaling ratio */
21 u64 max_tsc_scaling_ratio;
22 /* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */
23 u64 default_tsc_scaling_ratio;
24 /* bus lock detection supported? */
25 bool has_bus_lock_exit;
26 /* notify VM exit supported? */
27 bool has_notify_vmexit;
28 /* bit mask of VM types */
29 u32 supported_vm_types;
30
31 u64 supported_mce_cap;
32 u64 supported_xcr0;
33 u64 supported_xss;
34 u64 supported_perf_cap;
35};
36
37struct kvm_host_values {
38 /*
39 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical
40 * address bits irrespective of features that repurpose legal bits,
41 * e.g. MKTME.
42 */
43 u8 maxphyaddr;
44
45 u64 efer;
46 u64 xcr0;
47 u64 xss;
48 u64 arch_capabilities;
49};
50
51void kvm_spurious_fault(void);
52
53#define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
54({ \
55 bool failed = (consistency_check); \
56 if (failed) \
57 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
58 failed; \
59})
60
61/*
62 * The first...last VMX feature MSRs that are emulated by KVM. This may or may
63 * not cover all known VMX MSRs, as KVM doesn't emulate an MSR until there's an
64 * associated feature that KVM supports for nested virtualization.
65 */
66#define KVM_FIRST_EMULATED_VMX_MSR MSR_IA32_VMX_BASIC
67#define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_VMFUNC
68
69#define KVM_DEFAULT_PLE_GAP 128
70#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
71#define KVM_DEFAULT_PLE_WINDOW_GROW 2
72#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
73#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
74#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
75#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
76
77static inline unsigned int __grow_ple_window(unsigned int val,
78 unsigned int base, unsigned int modifier, unsigned int max)
79{
80 u64 ret = val;
81
82 if (modifier < 1)
83 return base;
84
85 if (modifier < base)
86 ret *= modifier;
87 else
88 ret += modifier;
89
90 return min(ret, (u64)max);
91}
92
93static inline unsigned int __shrink_ple_window(unsigned int val,
94 unsigned int base, unsigned int modifier, unsigned int min)
95{
96 if (modifier < 1)
97 return base;
98
99 if (modifier < base)
100 val /= modifier;
101 else
102 val -= modifier;
103
104 return max(val, min);
105}
106
107#define MSR_IA32_CR_PAT_DEFAULT \
108 PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC)
109
110void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
111int kvm_check_nested_events(struct kvm_vcpu *vcpu);
112
113/* Forcibly leave the nested mode in cases like a vCPU reset */
114static inline void kvm_leave_nested(struct kvm_vcpu *vcpu)
115{
116 kvm_x86_ops.nested_ops->leave_nested(vcpu);
117}
118
119static inline bool kvm_vcpu_has_run(struct kvm_vcpu *vcpu)
120{
121 return vcpu->arch.last_vmentry_cpu != -1;
122}
123
124static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu)
125{
126 return vcpu->arch.exception.pending ||
127 vcpu->arch.exception_vmexit.pending ||
128 kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
129}
130
131static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
132{
133 vcpu->arch.exception.pending = false;
134 vcpu->arch.exception.injected = false;
135 vcpu->arch.exception_vmexit.pending = false;
136}
137
138static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
139 bool soft)
140{
141 vcpu->arch.interrupt.injected = true;
142 vcpu->arch.interrupt.soft = soft;
143 vcpu->arch.interrupt.nr = vector;
144}
145
146static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
147{
148 vcpu->arch.interrupt.injected = false;
149}
150
151static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
152{
153 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
154 vcpu->arch.nmi_injected;
155}
156
157static inline bool kvm_exception_is_soft(unsigned int nr)
158{
159 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
160}
161
162static inline bool is_protmode(struct kvm_vcpu *vcpu)
163{
164 return kvm_is_cr0_bit_set(vcpu, X86_CR0_PE);
165}
166
167static inline bool is_long_mode(struct kvm_vcpu *vcpu)
168{
169#ifdef CONFIG_X86_64
170 return !!(vcpu->arch.efer & EFER_LMA);
171#else
172 return false;
173#endif
174}
175
176static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
177{
178 int cs_db, cs_l;
179
180 WARN_ON_ONCE(vcpu->arch.guest_state_protected);
181
182 if (!is_long_mode(vcpu))
183 return false;
184 kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
185 return cs_l;
186}
187
188static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu)
189{
190 /*
191 * If running with protected guest state, the CS register is not
192 * accessible. The hypercall register values will have had to been
193 * provided in 64-bit mode, so assume the guest is in 64-bit.
194 */
195 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu);
196}
197
198static inline bool x86_exception_has_error_code(unsigned int vector)
199{
200 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
201 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
202 BIT(PF_VECTOR) | BIT(AC_VECTOR);
203
204 return (1U << vector) & exception_has_error_code;
205}
206
207static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
208{
209 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
210}
211
212static inline bool is_pae(struct kvm_vcpu *vcpu)
213{
214 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PAE);
215}
216
217static inline bool is_pse(struct kvm_vcpu *vcpu)
218{
219 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PSE);
220}
221
222static inline bool is_paging(struct kvm_vcpu *vcpu)
223{
224 return likely(kvm_is_cr0_bit_set(vcpu, X86_CR0_PG));
225}
226
227static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
228{
229 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
230}
231
232static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
233{
234 return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48;
235}
236
237static inline u8 max_host_virt_addr_bits(void)
238{
239 return kvm_cpu_cap_has(X86_FEATURE_LA57) ? 57 : 48;
240}
241
242/*
243 * x86 MSRs which contain linear addresses, x86 hidden segment bases, and
244 * IDT/GDT bases have static canonicality checks, the size of which depends
245 * only on the CPU's support for 5-level paging, rather than on the state of
246 * CR4.LA57. This applies to both WRMSR and to other instructions that set
247 * their values, e.g. SGDT.
248 *
249 * KVM passes through most of these MSRS and also doesn't intercept the
250 * instructions that set the hidden segment bases.
251 *
252 * Because of this, to be consistent with hardware, even if the guest doesn't
253 * have LA57 enabled in its CPUID, perform canonicality checks based on *host*
254 * support for 5 level paging.
255 *
256 * Finally, instructions which are related to MMU invalidation of a given
257 * linear address, also have a similar static canonical check on address.
258 * This allows for example to invalidate 5-level addresses of a guest from a
259 * host which uses 4-level paging.
260 */
261static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu,
262 unsigned int flags)
263{
264 if (flags & (X86EMUL_F_INVLPG | X86EMUL_F_MSR | X86EMUL_F_DT_LOAD))
265 return !__is_canonical_address(la, max_host_virt_addr_bits());
266 else
267 return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu));
268}
269
270static inline bool is_noncanonical_msr_address(u64 la, struct kvm_vcpu *vcpu)
271{
272 return is_noncanonical_address(la, vcpu, X86EMUL_F_MSR);
273}
274
275static inline bool is_noncanonical_base_address(u64 la, struct kvm_vcpu *vcpu)
276{
277 return is_noncanonical_address(la, vcpu, X86EMUL_F_DT_LOAD);
278}
279
280static inline bool is_noncanonical_invlpg_address(u64 la, struct kvm_vcpu *vcpu)
281{
282 return is_noncanonical_address(la, vcpu, X86EMUL_F_INVLPG);
283}
284
285static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
286 gva_t gva, gfn_t gfn, unsigned access)
287{
288 u64 gen = kvm_memslots(vcpu->kvm)->generation;
289
290 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
291 return;
292
293 /*
294 * If this is a shadow nested page table, the "GVA" is
295 * actually a nGPA.
296 */
297 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
298 vcpu->arch.mmio_access = access;
299 vcpu->arch.mmio_gfn = gfn;
300 vcpu->arch.mmio_gen = gen;
301}
302
303static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
304{
305 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
306}
307
308/*
309 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
310 * clear all mmio cache info.
311 */
312#define MMIO_GVA_ANY (~(gva_t)0)
313
314static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
315{
316 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
317 return;
318
319 vcpu->arch.mmio_gva = 0;
320}
321
322static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
323{
324 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
325 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
326 return true;
327
328 return false;
329}
330
331static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
332{
333 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
334 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
335 return true;
336
337 return false;
338}
339
340static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
341{
342 unsigned long val = kvm_register_read_raw(vcpu, reg);
343
344 return is_64_bit_mode(vcpu) ? val : (u32)val;
345}
346
347static inline void kvm_register_write(struct kvm_vcpu *vcpu,
348 int reg, unsigned long val)
349{
350 if (!is_64_bit_mode(vcpu))
351 val = (u32)val;
352 return kvm_register_write_raw(vcpu, reg, val);
353}
354
355static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
356{
357 return !(kvm->arch.disabled_quirks & quirk);
358}
359
360void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
361
362u64 get_kvmclock_ns(struct kvm *kvm);
363uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm);
364bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp);
365
366int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
367 gva_t addr, void *val, unsigned int bytes,
368 struct x86_exception *exception);
369
370int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
371 gva_t addr, void *val, unsigned int bytes,
372 struct x86_exception *exception);
373
374int handle_ud(struct kvm_vcpu *vcpu);
375
376void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
377 struct kvm_queued_exception *ex);
378
379int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
380int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
381bool kvm_vector_hashing_enabled(void);
382void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
383int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
384 void *insn, int insn_len);
385int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
386 int emulation_type, void *insn, int insn_len);
387fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
388fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu);
389
390extern struct kvm_caps kvm_caps;
391extern struct kvm_host_values kvm_host;
392
393extern bool enable_pmu;
394
395/*
396 * Get a filtered version of KVM's supported XCR0 that strips out dynamic
397 * features for which the current process doesn't (yet) have permission to use.
398 * This is intended to be used only when enumerating support to userspace,
399 * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to be
400 * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if
401 * userspace attempts to enable unpermitted features.
402 */
403static inline u64 kvm_get_filtered_xcr0(void)
404{
405 u64 permitted_xcr0 = kvm_caps.supported_xcr0;
406
407 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
408
409 if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) {
410 permitted_xcr0 &= xstate_get_guest_group_perm();
411
412 /*
413 * Treat XTILE_CFG as unsupported if the current process isn't
414 * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in
415 * XCR0 without setting XTILE_DATA is architecturally illegal.
416 */
417 if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA))
418 permitted_xcr0 &= ~XFEATURE_MASK_XTILE_CFG;
419 }
420 return permitted_xcr0;
421}
422
423static inline bool kvm_mpx_supported(void)
424{
425 return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
426 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
427}
428
429extern unsigned int min_timer_period_us;
430
431extern bool enable_vmware_backdoor;
432
433extern int pi_inject_timer;
434
435extern bool report_ignored_msrs;
436
437extern bool eager_page_split;
438
439static inline void kvm_pr_unimpl_wrmsr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
440{
441 if (report_ignored_msrs)
442 vcpu_unimpl(vcpu, "Unhandled WRMSR(0x%x) = 0x%llx\n", msr, data);
443}
444
445static inline void kvm_pr_unimpl_rdmsr(struct kvm_vcpu *vcpu, u32 msr)
446{
447 if (report_ignored_msrs)
448 vcpu_unimpl(vcpu, "Unhandled RDMSR(0x%x)\n", msr);
449}
450
451static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
452{
453 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
454 vcpu->arch.virtual_tsc_shift);
455}
456
457/* Same "calling convention" as do_div:
458 * - divide (n << 32) by base
459 * - put result in n
460 * - return remainder
461 */
462#define do_shl32_div32(n, base) \
463 ({ \
464 u32 __quot, __rem; \
465 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
466 : "rm" (base), "0" (0), "1" ((u32) n)); \
467 n = __quot; \
468 __rem; \
469 })
470
471static inline bool kvm_mwait_in_guest(struct kvm *kvm)
472{
473 return kvm->arch.mwait_in_guest;
474}
475
476static inline bool kvm_hlt_in_guest(struct kvm *kvm)
477{
478 return kvm->arch.hlt_in_guest;
479}
480
481static inline bool kvm_pause_in_guest(struct kvm *kvm)
482{
483 return kvm->arch.pause_in_guest;
484}
485
486static inline bool kvm_cstate_in_guest(struct kvm *kvm)
487{
488 return kvm->arch.cstate_in_guest;
489}
490
491static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm)
492{
493 return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED;
494}
495
496static __always_inline void kvm_before_interrupt(struct kvm_vcpu *vcpu,
497 enum kvm_intr_type intr)
498{
499 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr);
500}
501
502static __always_inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
503{
504 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0);
505}
506
507static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu)
508{
509 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI;
510}
511
512static inline bool kvm_pat_valid(u64 data)
513{
514 if (data & 0xF8F8F8F8F8F8F8F8ull)
515 return false;
516 /* 0, 1, 4, 5, 6, 7 are valid values. */
517 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
518}
519
520static inline bool kvm_dr7_valid(u64 data)
521{
522 /* Bits [63:32] are reserved */
523 return !(data >> 32);
524}
525static inline bool kvm_dr6_valid(u64 data)
526{
527 /* Bits [63:32] are reserved */
528 return !(data >> 32);
529}
530
531/*
532 * Trigger machine check on the host. We assume all the MSRs are already set up
533 * by the CPU and that we still run on the same CPU as the MCE occurred on.
534 * We pass a fake environment to the machine check handler because we want
535 * the guest to be always treated like user space, no matter what context
536 * it used internally.
537 */
538static inline void kvm_machine_check(void)
539{
540#if defined(CONFIG_X86_MCE)
541 struct pt_regs regs = {
542 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
543 .flags = X86_EFLAGS_IF,
544 };
545
546 do_machine_check(®s);
547#endif
548}
549
550void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
551void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
552int kvm_spec_ctrl_test_value(u64 value);
553bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
554int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
555 struct x86_exception *e);
556int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
557bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
558
559enum kvm_msr_access {
560 MSR_TYPE_R = BIT(0),
561 MSR_TYPE_W = BIT(1),
562 MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W,
563};
564
565/*
566 * Internal error codes that are used to indicate that MSR emulation encountered
567 * an error that should result in #GP in the guest, unless userspace handles it.
568 * Note, '1', '0', and negative numbers are off limits, as they are used by KVM
569 * as part of KVM's lightly documented internal KVM_RUN return codes.
570 *
571 * UNSUPPORTED - The MSR isn't supported, either because it is completely
572 * unknown to KVM, or because the MSR should not exist according
573 * to the vCPU model.
574 *
575 * FILTERED - Access to the MSR is denied by a userspace MSR filter.
576 */
577#define KVM_MSR_RET_UNSUPPORTED 2
578#define KVM_MSR_RET_FILTERED 3
579
580#define __cr4_reserved_bits(__cpu_has, __c) \
581({ \
582 u64 __reserved_bits = CR4_RESERVED_BITS; \
583 \
584 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
585 __reserved_bits |= X86_CR4_OSXSAVE; \
586 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
587 __reserved_bits |= X86_CR4_SMEP; \
588 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
589 __reserved_bits |= X86_CR4_SMAP; \
590 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
591 __reserved_bits |= X86_CR4_FSGSBASE; \
592 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
593 __reserved_bits |= X86_CR4_PKE; \
594 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
595 __reserved_bits |= X86_CR4_LA57; \
596 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
597 __reserved_bits |= X86_CR4_UMIP; \
598 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
599 __reserved_bits |= X86_CR4_VMXE; \
600 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
601 __reserved_bits |= X86_CR4_PCIDE; \
602 if (!__cpu_has(__c, X86_FEATURE_LAM)) \
603 __reserved_bits |= X86_CR4_LAM_SUP; \
604 __reserved_bits; \
605})
606
607int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
608 void *dst);
609int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
610 void *dst);
611int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
612 unsigned int port, void *data, unsigned int count,
613 int in);
614
615#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_KVM_X86_H
3#define ARCH_X86_KVM_X86_H
4
5#include <linux/kvm_host.h>
6#include <asm/mce.h>
7#include <asm/pvclock.h>
8#include "kvm_cache_regs.h"
9#include "kvm_emulate.h"
10
11static __always_inline void kvm_guest_enter_irqoff(void)
12{
13 /*
14 * VMENTER enables interrupts (host state), but the kernel state is
15 * interrupts disabled when this is invoked. Also tell RCU about
16 * it. This is the same logic as for exit_to_user_mode().
17 *
18 * This ensures that e.g. latency analysis on the host observes
19 * guest mode as interrupt enabled.
20 *
21 * guest_enter_irqoff() informs context tracking about the
22 * transition to guest mode and if enabled adjusts RCU state
23 * accordingly.
24 */
25 instrumentation_begin();
26 trace_hardirqs_on_prepare();
27 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
28 instrumentation_end();
29
30 guest_enter_irqoff();
31 lockdep_hardirqs_on(CALLER_ADDR0);
32}
33
34static __always_inline void kvm_guest_exit_irqoff(void)
35{
36 /*
37 * VMEXIT disables interrupts (host state), but tracing and lockdep
38 * have them in state 'on' as recorded before entering guest mode.
39 * Same as enter_from_user_mode().
40 *
41 * context_tracking_guest_exit() restores host context and reinstates
42 * RCU if enabled and required.
43 *
44 * This needs to be done immediately after VM-Exit, before any code
45 * that might contain tracepoints or call out to the greater world,
46 * e.g. before x86_spec_ctrl_restore_host().
47 */
48 lockdep_hardirqs_off(CALLER_ADDR0);
49 context_tracking_guest_exit();
50
51 instrumentation_begin();
52 trace_hardirqs_off_finish();
53 instrumentation_end();
54}
55
56#define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
57({ \
58 bool failed = (consistency_check); \
59 if (failed) \
60 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
61 failed; \
62})
63
64#define KVM_DEFAULT_PLE_GAP 128
65#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
66#define KVM_DEFAULT_PLE_WINDOW_GROW 2
67#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
68#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
69#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
70#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
71
72static inline unsigned int __grow_ple_window(unsigned int val,
73 unsigned int base, unsigned int modifier, unsigned int max)
74{
75 u64 ret = val;
76
77 if (modifier < 1)
78 return base;
79
80 if (modifier < base)
81 ret *= modifier;
82 else
83 ret += modifier;
84
85 return min(ret, (u64)max);
86}
87
88static inline unsigned int __shrink_ple_window(unsigned int val,
89 unsigned int base, unsigned int modifier, unsigned int min)
90{
91 if (modifier < 1)
92 return base;
93
94 if (modifier < base)
95 val /= modifier;
96 else
97 val -= modifier;
98
99 return max(val, min);
100}
101
102#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
103
104int kvm_check_nested_events(struct kvm_vcpu *vcpu);
105
106static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
107{
108 vcpu->arch.exception.pending = false;
109 vcpu->arch.exception.injected = false;
110}
111
112static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
113 bool soft)
114{
115 vcpu->arch.interrupt.injected = true;
116 vcpu->arch.interrupt.soft = soft;
117 vcpu->arch.interrupt.nr = vector;
118}
119
120static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
121{
122 vcpu->arch.interrupt.injected = false;
123}
124
125static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
126{
127 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
128 vcpu->arch.nmi_injected;
129}
130
131static inline bool kvm_exception_is_soft(unsigned int nr)
132{
133 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
134}
135
136static inline bool is_protmode(struct kvm_vcpu *vcpu)
137{
138 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
139}
140
141static inline int is_long_mode(struct kvm_vcpu *vcpu)
142{
143#ifdef CONFIG_X86_64
144 return vcpu->arch.efer & EFER_LMA;
145#else
146 return 0;
147#endif
148}
149
150static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
151{
152 int cs_db, cs_l;
153
154 if (!is_long_mode(vcpu))
155 return false;
156 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
157 return cs_l;
158}
159
160static inline bool x86_exception_has_error_code(unsigned int vector)
161{
162 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
163 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
164 BIT(PF_VECTOR) | BIT(AC_VECTOR);
165
166 return (1U << vector) & exception_has_error_code;
167}
168
169static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
170{
171 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
172}
173
174static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
175{
176 ++vcpu->stat.tlb_flush;
177 static_call(kvm_x86_tlb_flush_current)(vcpu);
178}
179
180static inline int is_pae(struct kvm_vcpu *vcpu)
181{
182 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
183}
184
185static inline int is_pse(struct kvm_vcpu *vcpu)
186{
187 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
188}
189
190static inline int is_paging(struct kvm_vcpu *vcpu)
191{
192 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
193}
194
195static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
196{
197 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
198}
199
200static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
201{
202 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
203}
204
205static inline u64 get_canonical(u64 la, u8 vaddr_bits)
206{
207 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
208}
209
210static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
211{
212 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
213}
214
215static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
216 gva_t gva, gfn_t gfn, unsigned access)
217{
218 u64 gen = kvm_memslots(vcpu->kvm)->generation;
219
220 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
221 return;
222
223 /*
224 * If this is a shadow nested page table, the "GVA" is
225 * actually a nGPA.
226 */
227 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
228 vcpu->arch.mmio_access = access;
229 vcpu->arch.mmio_gfn = gfn;
230 vcpu->arch.mmio_gen = gen;
231}
232
233static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
234{
235 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
236}
237
238/*
239 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
240 * clear all mmio cache info.
241 */
242#define MMIO_GVA_ANY (~(gva_t)0)
243
244static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
245{
246 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
247 return;
248
249 vcpu->arch.mmio_gva = 0;
250}
251
252static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
253{
254 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
255 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
256 return true;
257
258 return false;
259}
260
261static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
262{
263 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
264 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
265 return true;
266
267 return false;
268}
269
270static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
271{
272 unsigned long val = kvm_register_read_raw(vcpu, reg);
273
274 return is_64_bit_mode(vcpu) ? val : (u32)val;
275}
276
277static inline void kvm_register_write(struct kvm_vcpu *vcpu,
278 int reg, unsigned long val)
279{
280 if (!is_64_bit_mode(vcpu))
281 val = (u32)val;
282 return kvm_register_write_raw(vcpu, reg, val);
283}
284
285static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
286{
287 return !(kvm->arch.disabled_quirks & quirk);
288}
289
290static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
291{
292 return is_smm(vcpu) || static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
293}
294
295void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs);
296void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
297
298u64 get_kvmclock_ns(struct kvm *kvm);
299
300int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
301 gva_t addr, void *val, unsigned int bytes,
302 struct x86_exception *exception);
303
304int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
305 gva_t addr, void *val, unsigned int bytes,
306 struct x86_exception *exception);
307
308int handle_ud(struct kvm_vcpu *vcpu);
309
310void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
311
312void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
313u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
314bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
315int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
316int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
317bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
318 int page_num);
319bool kvm_vector_hashing_enabled(void);
320void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
321int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
322 void *insn, int insn_len);
323int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
324 int emulation_type, void *insn, int insn_len);
325fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
326
327extern u64 host_xcr0;
328extern u64 supported_xcr0;
329extern u64 host_xss;
330extern u64 supported_xss;
331
332static inline bool kvm_mpx_supported(void)
333{
334 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
335 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
336}
337
338extern unsigned int min_timer_period_us;
339
340extern bool enable_vmware_backdoor;
341
342extern int pi_inject_timer;
343
344extern struct static_key kvm_no_apic_vcpu;
345
346extern bool report_ignored_msrs;
347
348static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
349{
350 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
351 vcpu->arch.virtual_tsc_shift);
352}
353
354/* Same "calling convention" as do_div:
355 * - divide (n << 32) by base
356 * - put result in n
357 * - return remainder
358 */
359#define do_shl32_div32(n, base) \
360 ({ \
361 u32 __quot, __rem; \
362 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
363 : "rm" (base), "0" (0), "1" ((u32) n)); \
364 n = __quot; \
365 __rem; \
366 })
367
368static inline bool kvm_mwait_in_guest(struct kvm *kvm)
369{
370 return kvm->arch.mwait_in_guest;
371}
372
373static inline bool kvm_hlt_in_guest(struct kvm *kvm)
374{
375 return kvm->arch.hlt_in_guest;
376}
377
378static inline bool kvm_pause_in_guest(struct kvm *kvm)
379{
380 return kvm->arch.pause_in_guest;
381}
382
383static inline bool kvm_cstate_in_guest(struct kvm *kvm)
384{
385 return kvm->arch.cstate_in_guest;
386}
387
388DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
389
390static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
391{
392 __this_cpu_write(current_vcpu, vcpu);
393}
394
395static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
396{
397 __this_cpu_write(current_vcpu, NULL);
398}
399
400
401static inline bool kvm_pat_valid(u64 data)
402{
403 if (data & 0xF8F8F8F8F8F8F8F8ull)
404 return false;
405 /* 0, 1, 4, 5, 6, 7 are valid values. */
406 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
407}
408
409static inline bool kvm_dr7_valid(u64 data)
410{
411 /* Bits [63:32] are reserved */
412 return !(data >> 32);
413}
414static inline bool kvm_dr6_valid(u64 data)
415{
416 /* Bits [63:32] are reserved */
417 return !(data >> 32);
418}
419
420/*
421 * Trigger machine check on the host. We assume all the MSRs are already set up
422 * by the CPU and that we still run on the same CPU as the MCE occurred on.
423 * We pass a fake environment to the machine check handler because we want
424 * the guest to be always treated like user space, no matter what context
425 * it used internally.
426 */
427static inline void kvm_machine_check(void)
428{
429#if defined(CONFIG_X86_MCE)
430 struct pt_regs regs = {
431 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
432 .flags = X86_EFLAGS_IF,
433 };
434
435 do_machine_check(®s);
436#endif
437}
438
439void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
440void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
441int kvm_spec_ctrl_test_value(u64 value);
442bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
443int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
444 struct x86_exception *e);
445int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
446bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
447
448/*
449 * Internal error codes that are used to indicate that MSR emulation encountered
450 * an error that should result in #GP in the guest, unless userspace
451 * handles it.
452 */
453#define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */
454#define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */
455
456#define __cr4_reserved_bits(__cpu_has, __c) \
457({ \
458 u64 __reserved_bits = CR4_RESERVED_BITS; \
459 \
460 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
461 __reserved_bits |= X86_CR4_OSXSAVE; \
462 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
463 __reserved_bits |= X86_CR4_SMEP; \
464 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
465 __reserved_bits |= X86_CR4_SMAP; \
466 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
467 __reserved_bits |= X86_CR4_FSGSBASE; \
468 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
469 __reserved_bits |= X86_CR4_PKE; \
470 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
471 __reserved_bits |= X86_CR4_LA57; \
472 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
473 __reserved_bits |= X86_CR4_UMIP; \
474 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
475 __reserved_bits |= X86_CR4_VMXE; \
476 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
477 __reserved_bits |= X86_CR4_PCIDE; \
478 __reserved_bits; \
479})
480
481int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
482 void *dst);
483int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
484 void *dst);
485int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
486 unsigned int port, void *data, unsigned int count,
487 int in);
488
489#endif