1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *  Copyright (C) 2012 Marvell Technology Group Ltd.
  4 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
  5 */
  6
  7#include <dt-bindings/clock/marvell,pxa168.h>
  8
  9/ {
 10	#address-cells = <1>;
 11	#size-cells = <1>;
 12
 13	aliases {
 14		serial0 = &uart1;
 15		serial1 = &uart2;
 16		serial2 = &uart3;
 17		i2c0 = &twsi1;
 18		i2c1 = &twsi2;
 19	};
 20
 21	soc {
 22		#address-cells = <1>;
 23		#size-cells = <1>;
 24		compatible = "simple-bus";
 25		interrupt-parent = <&intc>;
 26		ranges;
 27
 28		axi@d4200000 {	/* AXI */
 29			compatible = "mrvl,axi-bus", "simple-bus";
 30			#address-cells = <1>;
 31			#size-cells = <1>;
 32			reg = <0xd4200000 0x00200000>;
 33			ranges;
 34
 35			intc: interrupt-controller@d4282000 {
 36				compatible = "mrvl,mmp-intc";
 37				interrupt-controller;
 38				#interrupt-cells = <1>;
 39				reg = <0xd4282000 0x1000>;
 40				mrvl,intc-nr-irqs = <64>;
 41			};
 42
 43		};
 44
 45		apb@d4000000 {	/* APB */
 46			compatible = "mrvl,apb-bus", "simple-bus";
 47			#address-cells = <1>;
 48			#size-cells = <1>;
 49			reg = <0xd4000000 0x00200000>;
 50			ranges;
 51
 52			timer0: timer@d4014000 {
 53				compatible = "mrvl,mmp-timer";
 54				reg = <0xd4014000 0x100>;
 55				interrupts = <13>;
 56			};
 57
 58			uart1: serial@d4017000 {
 59				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 60				reg = <0xd4017000 0x1000>;
 61				reg-shift = <2>;
 62				interrupts = <27>;
 63				clocks = <&soc_clocks PXA168_CLK_UART0>;
 64				resets = <&soc_clocks PXA168_CLK_UART0>;
 65				status = "disabled";
 66			};
 67
 68			uart2: serial@d4018000 {
 69				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 70				reg = <0xd4018000 0x1000>;
 71				reg-shift = <2>;
 72				interrupts = <28>;
 73				clocks = <&soc_clocks PXA168_CLK_UART1>;
 74				resets = <&soc_clocks PXA168_CLK_UART1>;
 75				status = "disabled";
 76			};
 77
 78			uart3: serial@d4026000 {
 79				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 80				reg = <0xd4026000 0x1000>;
 81				reg-shift = <2>;
 82				interrupts = <29>;
 83				clocks = <&soc_clocks PXA168_CLK_UART2>;
 84				resets = <&soc_clocks PXA168_CLK_UART2>;
 85				status = "disabled";
 86			};
 87
 88			gpio@d4019000 {
 89				compatible = "marvell,mmp-gpio";
 90				#address-cells = <1>;
 91				#size-cells = <1>;
 92				reg = <0xd4019000 0x1000>;
 93				gpio-controller;
 94				#gpio-cells = <2>;
 95				interrupts = <49>;
 96				clocks = <&soc_clocks PXA168_CLK_GPIO>;
 97				resets = <&soc_clocks PXA168_CLK_GPIO>;
 98				interrupt-names = "gpio_mux";
 99				interrupt-controller;
100				#interrupt-cells = <2>;
101				ranges;
102
103				gcb0: gpio@d4019000 {
104					reg = <0xd4019000 0x4>;
105				};
106
107				gcb1: gpio@d4019004 {
108					reg = <0xd4019004 0x4>;
109				};
110
111				gcb2: gpio@d4019008 {
112					reg = <0xd4019008 0x4>;
113				};
114
115				gcb3: gpio@d4019100 {
116					reg = <0xd4019100 0x4>;
117				};
118			};
119
120			twsi1: i2c@d4011000 {
121				compatible = "mrvl,mmp-twsi";
122				#address-cells = <1>;
123				#size-cells = <0>;
124				reg = <0xd4011000 0x1000>;
125				interrupts = <7>;
126				clocks = <&soc_clocks PXA168_CLK_TWSI0>;
127				resets = <&soc_clocks PXA168_CLK_TWSI0>;
128				mrvl,i2c-fast-mode;
129				status = "disabled";
130			};
131
132			twsi2: i2c@d4025000 {
133				compatible = "mrvl,mmp-twsi";
134				#address-cells = <1>;
135				#size-cells = <0>;
136				reg = <0xd4025000 0x1000>;
137				interrupts = <58>;
138				clocks = <&soc_clocks PXA168_CLK_TWSI1>;
139				resets = <&soc_clocks PXA168_CLK_TWSI1>;
140				status = "disabled";
141			};
142
143			rtc: rtc@d4010000 {
144				compatible = "mrvl,mmp-rtc";
145				reg = <0xd4010000 0x1000>;
146				interrupts = <5>, <6>;
147				interrupt-names = "rtc 1Hz", "rtc alarm";
148				clocks = <&soc_clocks PXA168_CLK_RTC>;
149				resets = <&soc_clocks PXA168_CLK_RTC>;
150				status = "disabled";
151			};
152		};
153
154		soc_clocks: clocks{
155			compatible = "marvell,pxa168-clock";
156			reg = <0xd4050000 0x1000>,
157			      <0xd4282800 0x400>,
158			      <0xd4015000 0x1000>;
159			reg-names = "mpmu", "apmu", "apbc";
160			#clock-cells = <1>;
161			#reset-cells = <1>;
162		};
163	};
164};