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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include "imx6sl-pinfunc.h"
7#include <dt-bindings/clock/imx6sl-clock.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 /*
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
16 */
17 chosen {};
18
19 aliases {
20 ethernet0 = &fec;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 mmc2 = &usdhc3;
32 mmc3 = &usdhc4;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 serial4 = &uart5;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
42 usb0 = &usbotg1;
43 usb1 = &usbotg2;
44 usb2 = &usbh;
45 usbphy0 = &usbphy1;
46 usbphy1 = &usbphy2;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu@0 {
54 compatible = "arm,cortex-a9";
55 device_type = "cpu";
56 reg = <0x0>;
57 next-level-cache = <&L2>;
58 operating-points = <
59 /* kHz uV */
60 996000 1275000
61 792000 1175000
62 396000 975000
63 >;
64 fsl,soc-operating-points = <
65 /* ARM kHz SOC-PU uV */
66 996000 1225000
67 792000 1175000
68 396000 1175000
69 >;
70 clock-latency = <61036>; /* two CLK32 periods */
71 #cooling-cells = <2>;
72 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
73 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
74 <&clks IMX6SL_CLK_PLL1_SYS>;
75 clock-names = "arm", "pll2_pfd2_396m", "step",
76 "pll1_sw", "pll1_sys";
77 arm-supply = <®_arm>;
78 pu-supply = <®_pu>;
79 soc-supply = <®_soc>;
80 nvmem-cells = <&cpu_speed_grade>;
81 nvmem-cell-names = "speed_grade";
82 };
83 };
84
85 clocks {
86 ckil {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <32768>;
90 };
91
92 osc {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <24000000>;
96 };
97 };
98
99 pmu {
100 compatible = "arm,cortex-a9-pmu";
101 interrupt-parent = <&gpc>;
102 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
103 };
104
105 usbphynop1: usbphynop1 {
106 compatible = "usb-nop-xceiv";
107 #phy-cells = <0>;
108 };
109
110 soc {
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "simple-bus";
114 interrupt-parent = <&gpc>;
115 ranges;
116
117 ocram: sram@900000 {
118 compatible = "mmio-sram";
119 reg = <0x00900000 0x20000>;
120 clocks = <&clks IMX6SL_CLK_OCRAM>;
121 };
122
123 intc: interrupt-controller@a01000 {
124 compatible = "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
126 interrupt-controller;
127 reg = <0x00a01000 0x1000>,
128 <0x00a00100 0x100>;
129 interrupt-parent = <&intc>;
130 };
131
132 L2: cache-controller@a02000 {
133 compatible = "arm,pl310-cache";
134 reg = <0x00a02000 0x1000>;
135 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
136 cache-unified;
137 cache-level = <2>;
138 arm,tag-latency = <4 2 3>;
139 arm,data-latency = <4 2 3>;
140 };
141
142 aips1: bus@2000000 {
143 compatible = "fsl,aips-bus", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
146 reg = <0x02000000 0x100000>;
147 ranges;
148
149 spba: spba-bus@2000000 {
150 compatible = "fsl,spba-bus", "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 reg = <0x02000000 0x40000>;
154 ranges;
155
156 spdif: spdif@2004000 {
157 compatible = "fsl,imx6sl-spdif",
158 "fsl,imx35-spdif";
159 reg = <0x02004000 0x4000>;
160 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
161 dmas = <&sdma 14 18 0>,
162 <&sdma 15 18 0>;
163 dma-names = "rx", "tx";
164 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
165 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
166 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
167 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
168 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
169 clock-names = "core", "rxtx0",
170 "rxtx1", "rxtx2",
171 "rxtx3", "rxtx4",
172 "rxtx5", "rxtx6",
173 "rxtx7", "spba";
174 status = "disabled";
175 };
176
177 ecspi1: spi@2008000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
181 reg = <0x02008000 0x4000>;
182 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&clks IMX6SL_CLK_ECSPI1>,
184 <&clks IMX6SL_CLK_ECSPI1>;
185 clock-names = "ipg", "per";
186 status = "disabled";
187 };
188
189 ecspi2: spi@200c000 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
193 reg = <0x0200c000 0x4000>;
194 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clks IMX6SL_CLK_ECSPI2>,
196 <&clks IMX6SL_CLK_ECSPI2>;
197 clock-names = "ipg", "per";
198 status = "disabled";
199 };
200
201 ecspi3: spi@2010000 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
205 reg = <0x02010000 0x4000>;
206 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clks IMX6SL_CLK_ECSPI3>,
208 <&clks IMX6SL_CLK_ECSPI3>;
209 clock-names = "ipg", "per";
210 status = "disabled";
211 };
212
213 ecspi4: spi@2014000 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
217 reg = <0x02014000 0x4000>;
218 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6SL_CLK_ECSPI4>,
220 <&clks IMX6SL_CLK_ECSPI4>;
221 clock-names = "ipg", "per";
222 status = "disabled";
223 };
224
225 uart5: serial@2018000 {
226 compatible = "fsl,imx6sl-uart",
227 "fsl,imx6q-uart", "fsl,imx21-uart";
228 reg = <0x02018000 0x4000>;
229 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6SL_CLK_UART>,
231 <&clks IMX6SL_CLK_UART_SERIAL>;
232 clock-names = "ipg", "per";
233 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
234 dma-names = "rx", "tx";
235 status = "disabled";
236 };
237
238 uart1: serial@2020000 {
239 compatible = "fsl,imx6sl-uart",
240 "fsl,imx6q-uart", "fsl,imx21-uart";
241 reg = <0x02020000 0x4000>;
242 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&clks IMX6SL_CLK_UART>,
244 <&clks IMX6SL_CLK_UART_SERIAL>;
245 clock-names = "ipg", "per";
246 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
247 dma-names = "rx", "tx";
248 status = "disabled";
249 };
250
251 uart2: serial@2024000 {
252 compatible = "fsl,imx6sl-uart",
253 "fsl,imx6q-uart", "fsl,imx21-uart";
254 reg = <0x02024000 0x4000>;
255 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&clks IMX6SL_CLK_UART>,
257 <&clks IMX6SL_CLK_UART_SERIAL>;
258 clock-names = "ipg", "per";
259 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
260 dma-names = "rx", "tx";
261 status = "disabled";
262 };
263
264 ssi1: ssi@2028000 {
265 #sound-dai-cells = <0>;
266 compatible = "fsl,imx6sl-ssi",
267 "fsl,imx51-ssi";
268 reg = <0x02028000 0x4000>;
269 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
271 <&clks IMX6SL_CLK_SSI1>;
272 clock-names = "ipg", "baud";
273 dmas = <&sdma 37 1 0>,
274 <&sdma 38 1 0>;
275 dma-names = "rx", "tx";
276 fsl,fifo-depth = <15>;
277 status = "disabled";
278 };
279
280 ssi2: ssi@202c000 {
281 #sound-dai-cells = <0>;
282 compatible = "fsl,imx6sl-ssi",
283 "fsl,imx51-ssi";
284 reg = <0x0202c000 0x4000>;
285 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
287 <&clks IMX6SL_CLK_SSI2>;
288 clock-names = "ipg", "baud";
289 dmas = <&sdma 41 1 0>,
290 <&sdma 42 1 0>;
291 dma-names = "rx", "tx";
292 fsl,fifo-depth = <15>;
293 status = "disabled";
294 };
295
296 ssi3: ssi@2030000 {
297 #sound-dai-cells = <0>;
298 compatible = "fsl,imx6sl-ssi",
299 "fsl,imx51-ssi";
300 reg = <0x02030000 0x4000>;
301 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
303 <&clks IMX6SL_CLK_SSI3>;
304 clock-names = "ipg", "baud";
305 dmas = <&sdma 45 1 0>,
306 <&sdma 46 1 0>;
307 dma-names = "rx", "tx";
308 fsl,fifo-depth = <15>;
309 status = "disabled";
310 };
311
312 uart3: serial@2034000 {
313 compatible = "fsl,imx6sl-uart",
314 "fsl,imx6q-uart", "fsl,imx21-uart";
315 reg = <0x02034000 0x4000>;
316 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clks IMX6SL_CLK_UART>,
318 <&clks IMX6SL_CLK_UART_SERIAL>;
319 clock-names = "ipg", "per";
320 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324
325 uart4: serial@2038000 {
326 compatible = "fsl,imx6sl-uart",
327 "fsl,imx6q-uart", "fsl,imx21-uart";
328 reg = <0x02038000 0x4000>;
329 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6SL_CLK_UART>,
331 <&clks IMX6SL_CLK_UART_SERIAL>;
332 clock-names = "ipg", "per";
333 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
334 dma-names = "rx", "tx";
335 status = "disabled";
336 };
337 };
338
339 pwm1: pwm@2080000 {
340 #pwm-cells = <3>;
341 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
342 reg = <0x02080000 0x4000>;
343 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clks IMX6SL_CLK_PERCLK>,
345 <&clks IMX6SL_CLK_PWM1>;
346 clock-names = "ipg", "per";
347 };
348
349 pwm2: pwm@2084000 {
350 #pwm-cells = <3>;
351 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
352 reg = <0x02084000 0x4000>;
353 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&clks IMX6SL_CLK_PERCLK>,
355 <&clks IMX6SL_CLK_PWM2>;
356 clock-names = "ipg", "per";
357 };
358
359 pwm3: pwm@2088000 {
360 #pwm-cells = <3>;
361 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
362 reg = <0x02088000 0x4000>;
363 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6SL_CLK_PERCLK>,
365 <&clks IMX6SL_CLK_PWM3>;
366 clock-names = "ipg", "per";
367 };
368
369 pwm4: pwm@208c000 {
370 #pwm-cells = <3>;
371 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
372 reg = <0x0208c000 0x4000>;
373 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clks IMX6SL_CLK_PERCLK>,
375 <&clks IMX6SL_CLK_PWM4>;
376 clock-names = "ipg", "per";
377 };
378
379 gpt: timer@2098000 {
380 compatible = "fsl,imx6sl-gpt";
381 reg = <0x02098000 0x4000>;
382 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&clks IMX6SL_CLK_GPT>,
384 <&clks IMX6SL_CLK_GPT_SERIAL>;
385 clock-names = "ipg", "per";
386 };
387
388 gpio1: gpio@209c000 {
389 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
390 reg = <0x0209c000 0x4000>;
391 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
392 <0 67 IRQ_TYPE_LEVEL_HIGH>;
393 gpio-controller;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
398 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
399 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
400 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
401 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
402 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
403 };
404
405 gpio2: gpio@20a0000 {
406 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
407 reg = <0x020a0000 0x4000>;
408 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
409 <0 69 IRQ_TYPE_LEVEL_HIGH>;
410 gpio-controller;
411 #gpio-cells = <2>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
414 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
415 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
416 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
417 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
418 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
419 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
420 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
421 };
422
423 gpio3: gpio@20a4000 {
424 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
425 reg = <0x020a4000 0x4000>;
426 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
427 <0 71 IRQ_TYPE_LEVEL_HIGH>;
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
433 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
434 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
435 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
436 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
437 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
438 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
439 <&iomuxc 31 102 1>;
440 };
441
442 gpio4: gpio@20a8000 {
443 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
444 reg = <0x020a8000 0x4000>;
445 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
446 <0 73 IRQ_TYPE_LEVEL_HIGH>;
447 gpio-controller;
448 #gpio-cells = <2>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
452 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
453 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
454 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
455 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
456 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
457 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
458 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
459 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
460 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
461 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
462 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
463 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
464 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
465 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
466 };
467
468 gpio5: gpio@20ac000 {
469 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
470 reg = <0x020ac000 0x4000>;
471 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
472 <0 75 IRQ_TYPE_LEVEL_HIGH>;
473 gpio-controller;
474 #gpio-cells = <2>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
477 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
478 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
479 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
480 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
481 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
482 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
483 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
484 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
485 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
486 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
487 <&iomuxc 21 161 1>;
488 };
489
490 kpp: keypad@20b8000 {
491 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
492 reg = <0x020b8000 0x4000>;
493 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clks IMX6SL_CLK_IPG>;
495 status = "disabled";
496 };
497
498 wdog1: watchdog@20bc000 {
499 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
500 reg = <0x020bc000 0x4000>;
501 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clks IMX6SL_CLK_IPG>;
503 };
504
505 wdog2: watchdog@20c0000 {
506 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
507 reg = <0x020c0000 0x4000>;
508 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clks IMX6SL_CLK_IPG>;
510 status = "disabled";
511 };
512
513 clks: clock-controller@20c4000 {
514 compatible = "fsl,imx6sl-ccm";
515 reg = <0x020c4000 0x4000>;
516 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
517 <0 88 IRQ_TYPE_LEVEL_HIGH>;
518 #clock-cells = <1>;
519 };
520
521 anatop: anatop@20c8000 {
522 compatible = "fsl,imx6sl-anatop",
523 "fsl,imx6q-anatop",
524 "syscon", "simple-mfd";
525 reg = <0x020c8000 0x1000>;
526 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
527 <0 54 IRQ_TYPE_LEVEL_HIGH>,
528 <0 127 IRQ_TYPE_LEVEL_HIGH>;
529
530 reg_vdd1p1: regulator-1p1 {
531 compatible = "fsl,anatop-regulator";
532 regulator-name = "vdd1p1";
533 regulator-min-microvolt = <1000000>;
534 regulator-max-microvolt = <1200000>;
535 regulator-always-on;
536 anatop-reg-offset = <0x110>;
537 anatop-vol-bit-shift = <8>;
538 anatop-vol-bit-width = <5>;
539 anatop-min-bit-val = <4>;
540 anatop-min-voltage = <800000>;
541 anatop-max-voltage = <1375000>;
542 anatop-enable-bit = <0>;
543 };
544
545 reg_vdd3p0: regulator-3p0 {
546 compatible = "fsl,anatop-regulator";
547 regulator-name = "vdd3p0";
548 regulator-min-microvolt = <2800000>;
549 regulator-max-microvolt = <3150000>;
550 regulator-always-on;
551 anatop-reg-offset = <0x120>;
552 anatop-vol-bit-shift = <8>;
553 anatop-vol-bit-width = <5>;
554 anatop-min-bit-val = <0>;
555 anatop-min-voltage = <2625000>;
556 anatop-max-voltage = <3400000>;
557 anatop-enable-bit = <0>;
558 };
559
560 reg_vdd2p5: regulator-2p5 {
561 compatible = "fsl,anatop-regulator";
562 regulator-name = "vdd2p5";
563 regulator-min-microvolt = <2250000>;
564 regulator-max-microvolt = <2750000>;
565 regulator-always-on;
566 anatop-reg-offset = <0x130>;
567 anatop-vol-bit-shift = <8>;
568 anatop-vol-bit-width = <5>;
569 anatop-min-bit-val = <0>;
570 anatop-min-voltage = <2100000>;
571 anatop-max-voltage = <2850000>;
572 anatop-enable-bit = <0>;
573 };
574
575 reg_arm: regulator-vddcore {
576 compatible = "fsl,anatop-regulator";
577 regulator-name = "vddarm";
578 regulator-min-microvolt = <725000>;
579 regulator-max-microvolt = <1450000>;
580 regulator-always-on;
581 anatop-reg-offset = <0x140>;
582 anatop-vol-bit-shift = <0>;
583 anatop-vol-bit-width = <5>;
584 anatop-delay-reg-offset = <0x170>;
585 anatop-delay-bit-shift = <24>;
586 anatop-delay-bit-width = <2>;
587 anatop-min-bit-val = <1>;
588 anatop-min-voltage = <725000>;
589 anatop-max-voltage = <1450000>;
590 };
591
592 reg_pu: regulator-vddpu {
593 compatible = "fsl,anatop-regulator";
594 regulator-name = "vddpu";
595 regulator-min-microvolt = <725000>;
596 regulator-max-microvolt = <1450000>;
597 anatop-reg-offset = <0x140>;
598 anatop-vol-bit-shift = <9>;
599 anatop-vol-bit-width = <5>;
600 anatop-delay-reg-offset = <0x170>;
601 anatop-delay-bit-shift = <26>;
602 anatop-delay-bit-width = <2>;
603 anatop-min-bit-val = <1>;
604 anatop-min-voltage = <725000>;
605 anatop-max-voltage = <1450000>;
606 };
607
608 reg_soc: regulator-vddsoc {
609 compatible = "fsl,anatop-regulator";
610 regulator-name = "vddsoc";
611 regulator-min-microvolt = <725000>;
612 regulator-max-microvolt = <1450000>;
613 regulator-always-on;
614 anatop-reg-offset = <0x140>;
615 anatop-vol-bit-shift = <18>;
616 anatop-vol-bit-width = <5>;
617 anatop-delay-reg-offset = <0x170>;
618 anatop-delay-bit-shift = <28>;
619 anatop-delay-bit-width = <2>;
620 anatop-min-bit-val = <1>;
621 anatop-min-voltage = <725000>;
622 anatop-max-voltage = <1450000>;
623 };
624
625 tempmon: tempmon {
626 compatible = "fsl,imx6q-tempmon";
627 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-parent = <&gpc>;
629 fsl,tempmon = <&anatop>;
630 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
631 nvmem-cell-names = "calib", "temp_grade";
632 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
633 };
634 };
635
636 usbphy1: usbphy@20c9000 {
637 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
638 reg = <0x020c9000 0x1000>;
639 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&clks IMX6SL_CLK_USBPHY1>;
641 fsl,anatop = <&anatop>;
642 };
643
644 usbphy2: usbphy@20ca000 {
645 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
646 reg = <0x020ca000 0x1000>;
647 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clks IMX6SL_CLK_USBPHY2>;
649 fsl,anatop = <&anatop>;
650 };
651
652 snvs: snvs@20cc000 {
653 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
654 reg = <0x020cc000 0x4000>;
655
656 snvs_rtc: snvs-rtc-lp {
657 compatible = "fsl,sec-v4.0-mon-rtc-lp";
658 regmap = <&snvs>;
659 offset = <0x34>;
660 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
661 <0 20 IRQ_TYPE_LEVEL_HIGH>;
662 };
663
664 snvs_poweroff: snvs-poweroff {
665 compatible = "syscon-poweroff";
666 regmap = <&snvs>;
667 offset = <0x38>;
668 value = <0x60>;
669 mask = <0x60>;
670 status = "disabled";
671 };
672 };
673
674 epit1: epit@20d0000 {
675 reg = <0x020d0000 0x4000>;
676 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
677 };
678
679 epit2: epit@20d4000 {
680 reg = <0x020d4000 0x4000>;
681 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
682 };
683
684 src: reset-controller@20d8000 {
685 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
686 reg = <0x020d8000 0x4000>;
687 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
688 <0 96 IRQ_TYPE_LEVEL_HIGH>;
689 #reset-cells = <1>;
690 };
691
692 gpc: gpc@20dc000 {
693 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
694 reg = <0x020dc000 0x4000>;
695 interrupt-controller;
696 #interrupt-cells = <3>;
697 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-parent = <&intc>;
699 clocks = <&clks IMX6SL_CLK_IPG>;
700 clock-names = "ipg";
701
702 pgc {
703 #address-cells = <1>;
704 #size-cells = <0>;
705
706 power-domain@0 {
707 reg = <0>;
708 #power-domain-cells = <0>;
709 };
710
711 pd_pu: power-domain@1 {
712 reg = <1>;
713 #power-domain-cells = <0>;
714 power-supply = <®_pu>;
715 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
716 <&clks IMX6SL_CLK_GPU2D_PODF>;
717 };
718
719 pd_disp: power-domain@2 {
720 reg = <2>;
721 #power-domain-cells = <0>;
722 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
723 <&clks IMX6SL_CLK_LCDIF_PIX>,
724 <&clks IMX6SL_CLK_EPDC_AXI>,
725 <&clks IMX6SL_CLK_EPDC_PIX>,
726 <&clks IMX6SL_CLK_PXP_AXI>;
727 };
728 };
729 };
730
731 gpr: iomuxc-gpr@20e0000 {
732 compatible = "fsl,imx6sl-iomuxc-gpr",
733 "fsl,imx6q-iomuxc-gpr", "syscon";
734 reg = <0x020e0000 0x38>;
735 };
736
737 iomuxc: pinctrl@20e0000 {
738 compatible = "fsl,imx6sl-iomuxc";
739 reg = <0x020e0000 0x4000>;
740 };
741
742 csi: csi@20e4000 {
743 reg = <0x020e4000 0x4000>;
744 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
745 };
746
747 spdc: spdc@20e8000 {
748 reg = <0x020e8000 0x4000>;
749 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
750 };
751
752 sdma: sdma@20ec000 {
753 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
754 reg = <0x020ec000 0x4000>;
755 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clks IMX6SL_CLK_SDMA>,
757 <&clks IMX6SL_CLK_AHB>;
758 clock-names = "ipg", "ahb";
759 #dma-cells = <3>;
760 /* imx6sl reuses imx6q sdma firmware */
761 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
762 };
763
764 pxp: pxp@20f0000 {
765 reg = <0x020f0000 0x4000>;
766 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
767 };
768
769 epdc: epdc@20f4000 {
770 reg = <0x020f4000 0x4000>;
771 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
772 };
773
774 lcdif: lcdif@20f8000 {
775 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
776 reg = <0x020f8000 0x4000>;
777 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
779 <&clks IMX6SL_CLK_LCDIF_AXI>,
780 <&clks IMX6SL_CLK_DUMMY>;
781 clock-names = "pix", "axi", "disp_axi";
782 status = "disabled";
783 power-domains = <&pd_disp>;
784 };
785
786 dcp: crypto@20fc000 {
787 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
788 reg = <0x020fc000 0x4000>;
789 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
790 <0 100 IRQ_TYPE_LEVEL_HIGH>,
791 <0 101 IRQ_TYPE_LEVEL_HIGH>;
792 };
793 };
794
795 aips2: bus@2100000 {
796 compatible = "fsl,aips-bus", "simple-bus";
797 #address-cells = <1>;
798 #size-cells = <1>;
799 reg = <0x02100000 0x100000>;
800 ranges;
801
802 usbotg1: usb@2184000 {
803 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
804 reg = <0x02184000 0x200>;
805 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6SL_CLK_USBOH3>;
807 fsl,usbphy = <&usbphy1>;
808 fsl,usbmisc = <&usbmisc 0>;
809 ahb-burst-config = <0x0>;
810 tx-burst-size-dword = <0x10>;
811 rx-burst-size-dword = <0x10>;
812 status = "disabled";
813 };
814
815 usbotg2: usb@2184200 {
816 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
817 reg = <0x02184200 0x200>;
818 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6SL_CLK_USBOH3>;
820 fsl,usbphy = <&usbphy2>;
821 fsl,usbmisc = <&usbmisc 1>;
822 ahb-burst-config = <0x0>;
823 tx-burst-size-dword = <0x10>;
824 rx-burst-size-dword = <0x10>;
825 status = "disabled";
826 };
827
828 usbh: usb@2184400 {
829 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
830 reg = <0x02184400 0x200>;
831 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clks IMX6SL_CLK_USBOH3>;
833 fsl,usbphy = <&usbphynop1>;
834 phy_type = "hsic";
835 fsl,usbmisc = <&usbmisc 2>;
836 dr_mode = "host";
837 ahb-burst-config = <0x0>;
838 tx-burst-size-dword = <0x10>;
839 rx-burst-size-dword = <0x10>;
840 status = "disabled";
841 };
842
843 usbmisc: usbmisc@2184800 {
844 #index-cells = <1>;
845 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
846 reg = <0x02184800 0x200>;
847 clocks = <&clks IMX6SL_CLK_USBOH3>;
848 };
849
850 fec: ethernet@2188000 {
851 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
852 reg = <0x02188000 0x4000>;
853 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&clks IMX6SL_CLK_ENET>,
855 <&clks IMX6SL_CLK_ENET_REF>;
856 clock-names = "ipg", "ahb";
857 status = "disabled";
858 };
859
860 usdhc1: mmc@2190000 {
861 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
862 reg = <0x02190000 0x4000>;
863 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clks IMX6SL_CLK_USDHC1>,
865 <&clks IMX6SL_CLK_USDHC1>,
866 <&clks IMX6SL_CLK_USDHC1>;
867 clock-names = "ipg", "ahb", "per";
868 bus-width = <4>;
869 status = "disabled";
870 };
871
872 usdhc2: mmc@2194000 {
873 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
874 reg = <0x02194000 0x4000>;
875 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clks IMX6SL_CLK_USDHC2>,
877 <&clks IMX6SL_CLK_USDHC2>,
878 <&clks IMX6SL_CLK_USDHC2>;
879 clock-names = "ipg", "ahb", "per";
880 bus-width = <4>;
881 status = "disabled";
882 };
883
884 usdhc3: mmc@2198000 {
885 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
886 reg = <0x02198000 0x4000>;
887 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clks IMX6SL_CLK_USDHC3>,
889 <&clks IMX6SL_CLK_USDHC3>,
890 <&clks IMX6SL_CLK_USDHC3>;
891 clock-names = "ipg", "ahb", "per";
892 bus-width = <4>;
893 status = "disabled";
894 };
895
896 usdhc4: mmc@219c000 {
897 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
898 reg = <0x0219c000 0x4000>;
899 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&clks IMX6SL_CLK_USDHC4>,
901 <&clks IMX6SL_CLK_USDHC4>,
902 <&clks IMX6SL_CLK_USDHC4>;
903 clock-names = "ipg", "ahb", "per";
904 bus-width = <4>;
905 status = "disabled";
906 };
907
908 i2c1: i2c@21a0000 {
909 #address-cells = <1>;
910 #size-cells = <0>;
911 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
912 reg = <0x021a0000 0x4000>;
913 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clks IMX6SL_CLK_I2C1>;
915 status = "disabled";
916 };
917
918 i2c2: i2c@21a4000 {
919 #address-cells = <1>;
920 #size-cells = <0>;
921 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
922 reg = <0x021a4000 0x4000>;
923 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&clks IMX6SL_CLK_I2C2>;
925 status = "disabled";
926 };
927
928 i2c3: i2c@21a8000 {
929 #address-cells = <1>;
930 #size-cells = <0>;
931 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
932 reg = <0x021a8000 0x4000>;
933 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&clks IMX6SL_CLK_I2C3>;
935 status = "disabled";
936 };
937
938 memory-controller@21b0000 {
939 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
940 reg = <0x021b0000 0x4000>;
941 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
942 };
943
944 rngb: rngb@21b4000 {
945 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
946 reg = <0x021b4000 0x4000>;
947 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&clks IMX6SL_CLK_DUMMY>;
949 };
950
951 weim: weim@21b8000 {
952 #address-cells = <2>;
953 #size-cells = <1>;
954 reg = <0x021b8000 0x4000>;
955 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
956 fsl,weim-cs-gpr = <&gpr>;
957 status = "disabled";
958 };
959
960 ocotp: efuse@21bc000 {
961 compatible = "fsl,imx6sl-ocotp", "syscon";
962 reg = <0x021bc000 0x4000>;
963 clocks = <&clks IMX6SL_CLK_OCOTP>;
964 #address-cells = <1>;
965 #size-cells = <1>;
966
967 cpu_speed_grade: speed-grade@10 {
968 reg = <0x10 4>;
969 };
970
971 tempmon_calib: calib@38 {
972 reg = <0x38 4>;
973 };
974
975 tempmon_temp_grade: temp-grade@20 {
976 reg = <0x20 4>;
977 };
978 };
979
980 audmux: audmux@21d8000 {
981 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
982 reg = <0x021d8000 0x4000>;
983 status = "disabled";
984 };
985 };
986
987 gpu_2d: gpu@2200000 {
988 compatible = "vivante,gc";
989 reg = <0x02200000 0x4000>;
990 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
992 <&clks IMX6SL_CLK_GPU2D_OVG>;
993 clock-names = "bus", "core";
994 power-domains = <&pd_pu>;
995 };
996
997 gpu_vg: gpu@2204000 {
998 compatible = "vivante,gc";
999 reg = <0x02204000 0x4000>;
1000 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
1002 <&clks IMX6SL_CLK_GPU2D_OVG>;
1003 clock-names = "bus", "core";
1004 power-domains = <&pd_pu>;
1005 };
1006 };
1007};