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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * rt715.c -- rt715 ALSA SoC audio driver
4 *
5 * Copyright(c) 2019 Realtek Semiconductor Corp.
6 *
7 * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
8 *
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/pm_runtime.h>
17#include <linux/pm.h>
18#include <linux/soundwire/sdw.h>
19#include <linux/regmap.h>
20#include <linux/slab.h>
21#include <linux/platform_device.h>
22#include <linux/regulator/consumer.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/sdw.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/hda_verbs.h>
32
33#include "rt715.h"
34
35static int rt715_index_write(struct regmap *regmap, unsigned int reg,
36 unsigned int value)
37{
38 int ret;
39 unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg;
40
41 ret = regmap_write(regmap, addr, value);
42 if (ret < 0) {
43 pr_err("%s: Failed to set private value: %08x <= %04x %d\n",
44 __func__, addr, value, ret);
45 }
46
47 return ret;
48}
49
50static int rt715_index_write_nid(struct regmap *regmap,
51 unsigned int nid, unsigned int reg, unsigned int value)
52{
53 int ret;
54 unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg;
55
56 ret = regmap_write(regmap, addr, value);
57 if (ret < 0)
58 pr_err("%s: Failed to set private value: %06x <= %04x ret=%d\n",
59 __func__, addr, value, ret);
60
61 return ret;
62}
63
64static int rt715_index_read_nid(struct regmap *regmap,
65 unsigned int nid, unsigned int reg, unsigned int *value)
66{
67 int ret;
68 unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg;
69
70 *value = 0;
71 ret = regmap_read(regmap, addr, value);
72 if (ret < 0)
73 pr_err("%s: Failed to get private value: %06x => %04x ret=%d\n",
74 __func__, addr, *value, ret);
75
76 return ret;
77}
78
79static int rt715_index_update_bits(struct regmap *regmap, unsigned int nid,
80 unsigned int reg, unsigned int mask, unsigned int val)
81{
82 unsigned int tmp, orig;
83 int ret;
84
85 ret = rt715_index_read_nid(regmap, nid, reg, &orig);
86 if (ret < 0)
87 return ret;
88
89 tmp = orig & ~mask;
90 tmp |= val & mask;
91
92 return rt715_index_write_nid(regmap, nid, reg, tmp);
93}
94
95static void rt715_reset(struct regmap *regmap)
96{
97 regmap_write(regmap, RT715_FUNC_RESET, 0);
98 rt715_index_update_bits(regmap, RT715_VENDOR_REGISTERS,
99 RT715_VD_CLEAR_CTRL, RT715_CLEAR_HIDDEN_REG,
100 RT715_CLEAR_HIDDEN_REG);
101}
102
103
104static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h,
105 unsigned int addr_l, unsigned int val_h,
106 unsigned int *r_val, unsigned int *l_val)
107{
108 int ret;
109 /* R Channel */
110 *r_val = val_h << 8;
111 ret = regmap_read(rt715->regmap, addr_l, r_val);
112 if (ret < 0)
113 pr_err("Failed to get R channel gain.\n");
114
115 /* L Channel */
116 val_h |= 0x20;
117 *l_val = val_h << 8;
118 ret = regmap_read(rt715->regmap, addr_h, l_val);
119 if (ret < 0)
120 pr_err("Failed to get L channel gain.\n");
121}
122
123/* For Verb-Set Amplifier Gain (Verb ID = 3h) */
124static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol,
125 struct snd_ctl_elem_value *ucontrol)
126{
127 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
128 struct snd_soc_dapm_context *dapm =
129 snd_soc_component_get_dapm(component);
130 struct soc_mixer_control *mc =
131 (struct soc_mixer_control *)kcontrol->private_value;
132 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
133 unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
134 unsigned int read_ll, read_rl, i;
135 unsigned int k_vol_changed = 0;
136
137 for (i = 0; i < 2; i++) {
138 if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) {
139 k_vol_changed = 1;
140 break;
141 }
142 }
143
144 /* Can't use update bit function, so read the original value first */
145 addr_h = mc->reg;
146 addr_l = mc->rreg;
147
148 if (mc->shift == RT715_DIR_OUT_SFT) /* output */
149 val_h = 0x80;
150 else /* input */
151 val_h = 0x0;
152
153 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
154
155 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
156 regmap_write(rt715->regmap,
157 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
158
159 /* L Channel */
160 rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0];
161 /* for gain */
162 val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
163 if (val_ll > mc->max)
164 val_ll = mc->max;
165 /* keep mute status */
166 val_ll |= read_ll & 0x80;
167
168 /* R Channel */
169 rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1];
170 /* for gain */
171 val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
172 if (val_lr > mc->max)
173 val_lr = mc->max;
174 /* keep mute status */
175 val_lr |= read_rl & 0x80;
176
177 for (i = 0; i < 3; i++) { /* retry 3 times at most */
178
179 if (val_ll == val_lr) {
180 /* Set both L/R channels at the same time */
181 val_h = (1 << mc->shift) | (3 << 4);
182 regmap_write(rt715->regmap, addr_h,
183 (val_h << 8) | val_ll);
184 regmap_write(rt715->regmap, addr_l,
185 (val_h << 8) | val_ll);
186 } else {
187 /* Lch*/
188 val_h = (1 << mc->shift) | (1 << 5);
189 regmap_write(rt715->regmap, addr_h,
190 (val_h << 8) | val_ll);
191 /* Rch */
192 val_h = (1 << mc->shift) | (1 << 4);
193 regmap_write(rt715->regmap, addr_l,
194 (val_h << 8) | val_lr);
195 }
196 /* check result */
197 if (mc->shift == RT715_DIR_OUT_SFT) /* output */
198 val_h = 0x80;
199 else /* input */
200 val_h = 0x0;
201
202 rt715_get_gain(rt715, addr_h, addr_l, val_h,
203 &read_rl, &read_ll);
204 if (read_rl == val_lr && read_ll == val_ll)
205 break;
206 }
207
208 /* D0:power on state, D3: power saving mode */
209 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
210 regmap_write(rt715->regmap,
211 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
212 return k_vol_changed;
213}
214
215static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol,
216 struct snd_ctl_elem_value *ucontrol)
217{
218 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
219 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
220 struct soc_mixer_control *mc =
221 (struct soc_mixer_control *)kcontrol->private_value;
222 unsigned int addr_h, addr_l, val_h;
223 unsigned int read_ll, read_rl;
224
225 addr_h = mc->reg;
226 addr_l = mc->rreg;
227 if (mc->shift == RT715_DIR_OUT_SFT) /* output */
228 val_h = 0x80;
229 else /* input */
230 val_h = 0x0;
231
232 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
233
234 if (mc->invert) {
235 /* for mute status */
236 read_ll = !(read_ll & 0x80);
237 read_rl = !(read_rl & 0x80);
238 } else {
239 /* for gain */
240 read_ll = read_ll & 0x7f;
241 read_rl = read_rl & 0x7f;
242 }
243 ucontrol->value.integer.value[0] = read_ll;
244 ucontrol->value.integer.value[1] = read_rl;
245
246 return 0;
247}
248
249static int rt715_set_main_switch_put(struct snd_kcontrol *kcontrol,
250 struct snd_ctl_elem_value *ucontrol)
251{
252 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
253 struct snd_soc_dapm_context *dapm =
254 snd_soc_component_get_dapm(component);
255 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
256 static const unsigned int capture_reg_H[] = {
257 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
258 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
259 static const unsigned int capture_reg_L[] = {
260 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
261 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
262 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
263 unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0;
264 unsigned int read_ll, read_rl, i, j, loop_cnt = 4;
265
266 for (i = 0; i < 8; i++) {
267 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i])
268 k_changed = 1;
269 }
270
271 for (j = 0; j < loop_cnt; j++) {
272 /* Can't use update bit function, so read the original value first */
273 addr_h = capture_reg_H[j];
274 addr_l = capture_reg_L[j];
275 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
276
277 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
278 regmap_write(rt715->regmap,
279 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
280
281 /* L Channel */
282 /* for mute */
283 rt715->kctl_8ch_switch_ori[j * 2] =
284 ucontrol->value.integer.value[j * 2];
285 val_ll = (!ucontrol->value.integer.value[j * 2]) << 7;
286 /* keep gain */
287 val_ll |= read_ll & 0x7f;
288
289 /* R Channel */
290 /* for mute */
291 rt715->kctl_8ch_switch_ori[j * 2 + 1] =
292 ucontrol->value.integer.value[j * 2 + 1];
293 val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7;
294 /* keep gain */
295 val_lr |= read_rl & 0x7f;
296
297 for (i = 0; i < 3; i++) { /* retry 3 times at most */
298
299 if (val_ll == val_lr) {
300 /* Set both L/R channels at the same time */
301 val_h = (1 << k_shift) | (3 << 4);
302 regmap_write(rt715->regmap, addr_h,
303 (val_h << 8) | val_ll);
304 regmap_write(rt715->regmap, addr_l,
305 (val_h << 8) | val_ll);
306 } else {
307 /* Lch*/
308 val_h = (1 << k_shift) | (1 << 5);
309 regmap_write(rt715->regmap, addr_h,
310 (val_h << 8) | val_ll);
311 /* Rch */
312 val_h = (1 << k_shift) | (1 << 4);
313 regmap_write(rt715->regmap, addr_l,
314 (val_h << 8) | val_lr);
315 }
316 val_h = 0x0;
317 rt715_get_gain(rt715, addr_h, addr_l, val_h,
318 &read_rl, &read_ll);
319 if (read_rl == val_lr && read_ll == val_ll)
320 break;
321 }
322 }
323
324 /* D0:power on state, D3: power saving mode */
325 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
326 regmap_write(rt715->regmap,
327 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
328 return k_changed;
329}
330
331static int rt715_set_main_switch_get(struct snd_kcontrol *kcontrol,
332 struct snd_ctl_elem_value *ucontrol)
333{
334 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
335 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
336 static const unsigned int capture_reg_H[] = {
337 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
338 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
339 static const unsigned int capture_reg_L[] = {
340 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
341 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
342 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
343 unsigned int read_ll, read_rl;
344
345 for (i = 0; i < loop_cnt; i++) {
346 addr_h = capture_reg_H[i];
347 addr_l = capture_reg_L[i];
348 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
349
350 ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80);
351 ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80);
352 }
353
354 return 0;
355}
356
357static int rt715_set_main_vol_put(struct snd_kcontrol *kcontrol,
358 struct snd_ctl_elem_value *ucontrol)
359{
360 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
361 struct snd_soc_dapm_context *dapm =
362 snd_soc_component_get_dapm(component);
363 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
364 static const unsigned int capture_reg_H[] = {
365 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
366 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
367 static const unsigned int capture_reg_L[] = {
368 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
369 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L};
370 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
371 unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0;
372 unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f;
373
374 for (i = 0; i < 8; i++) {
375 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i])
376 k_changed = 1;
377 }
378
379 for (j = 0; j < loop_cnt; j++) {
380 addr_h = capture_reg_H[j];
381 addr_l = capture_reg_L[j];
382 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
383
384 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
385 regmap_write(rt715->regmap,
386 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
387
388 /* L Channel */
389 /* for gain */
390 rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2];
391 val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f);
392 if (val_ll > k_max)
393 val_ll = k_max;
394 /* keep mute status */
395 val_ll |= read_ll & 0x80;
396
397 /* R Channel */
398 /* for gain */
399 rt715->kctl_8ch_vol_ori[j * 2 + 1] =
400 ucontrol->value.integer.value[j * 2 + 1];
401 val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f);
402 if (val_lr > k_max)
403 val_lr = k_max;
404 /* keep mute status */
405 val_lr |= read_rl & 0x80;
406
407 for (i = 0; i < 3; i++) { /* retry 3 times at most */
408 if (val_ll == val_lr) {
409 /* Set both L/R channels at the same time */
410 val_h = (1 << k_shift) | (3 << 4);
411 regmap_write(rt715->regmap, addr_h,
412 (val_h << 8) | val_ll);
413 regmap_write(rt715->regmap, addr_l,
414 (val_h << 8) | val_ll);
415 } else {
416 /* Lch*/
417 val_h = (1 << k_shift) | (1 << 5);
418 regmap_write(rt715->regmap, addr_h,
419 (val_h << 8) | val_ll);
420 /* Rch */
421 val_h = (1 << k_shift) | (1 << 4);
422 regmap_write(rt715->regmap, addr_l,
423 (val_h << 8) | val_lr);
424 }
425 val_h = 0x0;
426 rt715_get_gain(rt715, addr_h, addr_l, val_h,
427 &read_rl, &read_ll);
428 if (read_rl == val_lr && read_ll == val_ll)
429 break;
430 }
431 }
432
433 /* D0:power on state, D3: power saving mode */
434 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
435 regmap_write(rt715->regmap,
436 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
437 return k_changed;
438}
439
440static int rt715_set_main_vol_get(struct snd_kcontrol *kcontrol,
441 struct snd_ctl_elem_value *ucontrol)
442{
443 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
444 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
445 static const unsigned int capture_reg_H[] = {
446 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
447 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
448 static const unsigned int capture_reg_L[] = {
449 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
450 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
451 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
452 unsigned int read_ll, read_rl;
453
454 for (i = 0; i < loop_cnt; i++) {
455 addr_h = capture_reg_H[i];
456 addr_l = capture_reg_L[i];
457 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
458
459 ucontrol->value.integer.value[i * 2] = read_ll & 0x7f;
460 ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f;
461 }
462
463 return 0;
464}
465
466static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
467static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
468
469static int rt715_switch_info(struct snd_kcontrol *kcontrol,
470 struct snd_ctl_elem_info *uinfo)
471{
472 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
473 uinfo->count = 8;
474 uinfo->value.integer.min = 0;
475 uinfo->value.integer.max = 1;
476 return 0;
477}
478
479static int rt715_vol_info(struct snd_kcontrol *kcontrol,
480 struct snd_ctl_elem_info *uinfo)
481{
482 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
483 uinfo->count = 8;
484 uinfo->value.integer.min = 0;
485 uinfo->value.integer.max = 0x3f;
486 return 0;
487}
488
489#define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
490 xhandler_get, xhandler_put) \
491{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
492 .info = snd_soc_info_volsw, \
493 .get = xhandler_get, .put = xhandler_put, \
494 .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
495 xmax, xinvert) }
496
497#define RT715_MAIN_SWITCH_EXT(xname, xhandler_get, xhandler_put) \
498{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
499 .info = rt715_switch_info, \
500 .get = xhandler_get, .put = xhandler_put, \
501}
502
503#define RT715_MAIN_VOL_EXT_TLV(xname, xhandler_get, xhandler_put, tlv_array) \
504{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
505 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
506 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
507 .tlv.p = (tlv_array), \
508 .info = rt715_vol_info, \
509 .get = xhandler_get, .put = xhandler_put, \
510}
511
512static const struct snd_kcontrol_new rt715_snd_controls[] = {
513 /* Capture switch */
514 RT715_MAIN_SWITCH_EXT("Capture Switch",
515 rt715_set_main_switch_get, rt715_set_main_switch_put),
516 /* Volume Control */
517 RT715_MAIN_VOL_EXT_TLV("Capture Volume",
518 rt715_set_main_vol_get, rt715_set_main_vol_put, in_vol_tlv),
519 /* MIC Boost Control */
520 SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H,
521 RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
522 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
523 mic_vol_tlv),
524 SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H,
525 RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
526 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
527 mic_vol_tlv),
528 SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H,
529 RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
530 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
531 mic_vol_tlv),
532 SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H,
533 RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
534 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
535 mic_vol_tlv),
536 SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H,
537 RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
538 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
539 mic_vol_tlv),
540 SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H,
541 RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
542 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
543 mic_vol_tlv),
544 SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H,
545 RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
546 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
547 mic_vol_tlv),
548 SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H,
549 RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
550 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
551 mic_vol_tlv),
552};
553
554static int rt715_mux_get(struct snd_kcontrol *kcontrol,
555 struct snd_ctl_elem_value *ucontrol)
556{
557 struct snd_soc_component *component =
558 snd_soc_dapm_kcontrol_component(kcontrol);
559 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
560 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
561 unsigned int reg, val;
562 int ret;
563
564 /* nid = e->reg, vid = 0xf01 */
565 reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
566 ret = regmap_read(rt715->regmap, reg, &val);
567 if (ret < 0) {
568 dev_err(component->dev, "%s: sdw read failed: %d\n",
569 __func__, ret);
570 return ret;
571 }
572
573 /*
574 * The first two indices of ADC Mux 24/25 are routed to the same
575 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
576 * To have a unique set of inputs, we skip the index1 of the muxes.
577 */
578 if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))
579 val -= 1;
580 ucontrol->value.enumerated.item[0] = val;
581
582 return 0;
583}
584
585static int rt715_mux_put(struct snd_kcontrol *kcontrol,
586 struct snd_ctl_elem_value *ucontrol)
587{
588 struct snd_soc_component *component =
589 snd_soc_dapm_kcontrol_component(kcontrol);
590 struct snd_soc_dapm_context *dapm =
591 snd_soc_dapm_kcontrol_dapm(kcontrol);
592 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
593 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
594 unsigned int *item = ucontrol->value.enumerated.item;
595 unsigned int val, val2 = 0, change, reg;
596 int ret;
597
598 if (item[0] >= e->items)
599 return -EINVAL;
600
601 /* Verb ID = 0x701h, nid = e->reg */
602 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
603
604 reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
605 ret = regmap_read(rt715->regmap, reg, &val2);
606 if (ret < 0) {
607 dev_err(component->dev, "%s: sdw read failed: %d\n",
608 __func__, ret);
609 return ret;
610 }
611
612 if (val == val2)
613 change = 0;
614 else
615 change = 1;
616
617 if (change) {
618 reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
619 regmap_write(rt715->regmap, reg, val);
620 }
621
622 snd_soc_dapm_mux_update_power(dapm, kcontrol,
623 item[0], e, NULL);
624
625 return change;
626}
627
628static const char * const adc_22_23_mux_text[] = {
629 "MIC1",
630 "MIC2",
631 "LINE1",
632 "LINE2",
633 "DMIC1",
634 "DMIC2",
635 "DMIC3",
636 "DMIC4",
637};
638
639/*
640 * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
641 * 1 will be connected to the same dmic source, therefore we skip index 1 to
642 * avoid misunderstanding on usage of dapm routing.
643 */
644static const unsigned int rt715_adc_24_25_values[] = {
645 0,
646 2,
647 3,
648 4,
649 5,
650};
651
652static const char * const adc_24_mux_text[] = {
653 "MIC2",
654 "DMIC1",
655 "DMIC2",
656 "DMIC3",
657 "DMIC4",
658};
659
660static const char * const adc_25_mux_text[] = {
661 "MIC1",
662 "DMIC1",
663 "DMIC2",
664 "DMIC3",
665 "DMIC4",
666};
667
668static SOC_ENUM_SINGLE_DECL(
669 rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
670
671static SOC_ENUM_SINGLE_DECL(
672 rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
673
674static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
675 RT715_MUX_IN3, 0, 0xf,
676 adc_24_mux_text, rt715_adc_24_25_values);
677
678static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
679 RT715_MUX_IN4, 0, 0xf,
680 adc_25_mux_text, rt715_adc_24_25_values);
681
682static const struct snd_kcontrol_new rt715_adc22_mux =
683 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
684 rt715_mux_get, rt715_mux_put);
685
686static const struct snd_kcontrol_new rt715_adc23_mux =
687 SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
688 rt715_mux_get, rt715_mux_put);
689
690static const struct snd_kcontrol_new rt715_adc24_mux =
691 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
692 rt715_mux_get, rt715_mux_put);
693
694static const struct snd_kcontrol_new rt715_adc25_mux =
695 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
696 rt715_mux_get, rt715_mux_put);
697
698static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = {
699 SND_SOC_DAPM_INPUT("DMIC1"),
700 SND_SOC_DAPM_INPUT("DMIC2"),
701 SND_SOC_DAPM_INPUT("DMIC3"),
702 SND_SOC_DAPM_INPUT("DMIC4"),
703 SND_SOC_DAPM_INPUT("MIC1"),
704 SND_SOC_DAPM_INPUT("MIC2"),
705 SND_SOC_DAPM_INPUT("LINE1"),
706 SND_SOC_DAPM_INPUT("LINE2"),
707 SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
708 SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
709 SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
710 SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
711 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
712 &rt715_adc22_mux),
713 SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
714 &rt715_adc23_mux),
715 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
716 &rt715_adc24_mux),
717 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
718 &rt715_adc25_mux),
719 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
720 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
721};
722
723static const struct snd_soc_dapm_route rt715_audio_map[] = {
724 {"DP6TX", NULL, "ADC 09"},
725 {"DP6TX", NULL, "ADC 08"},
726 {"DP4TX", NULL, "ADC 07"},
727 {"DP4TX", NULL, "ADC 27"},
728 {"ADC 09", NULL, "ADC 22 Mux"},
729 {"ADC 08", NULL, "ADC 23 Mux"},
730 {"ADC 07", NULL, "ADC 24 Mux"},
731 {"ADC 27", NULL, "ADC 25 Mux"},
732 {"ADC 22 Mux", "MIC1", "MIC1"},
733 {"ADC 22 Mux", "MIC2", "MIC2"},
734 {"ADC 22 Mux", "LINE1", "LINE1"},
735 {"ADC 22 Mux", "LINE2", "LINE2"},
736 {"ADC 22 Mux", "DMIC1", "DMIC1"},
737 {"ADC 22 Mux", "DMIC2", "DMIC2"},
738 {"ADC 22 Mux", "DMIC3", "DMIC3"},
739 {"ADC 22 Mux", "DMIC4", "DMIC4"},
740 {"ADC 23 Mux", "MIC1", "MIC1"},
741 {"ADC 23 Mux", "MIC2", "MIC2"},
742 {"ADC 23 Mux", "LINE1", "LINE1"},
743 {"ADC 23 Mux", "LINE2", "LINE2"},
744 {"ADC 23 Mux", "DMIC1", "DMIC1"},
745 {"ADC 23 Mux", "DMIC2", "DMIC2"},
746 {"ADC 23 Mux", "DMIC3", "DMIC3"},
747 {"ADC 23 Mux", "DMIC4", "DMIC4"},
748 {"ADC 24 Mux", "MIC2", "MIC2"},
749 {"ADC 24 Mux", "DMIC1", "DMIC1"},
750 {"ADC 24 Mux", "DMIC2", "DMIC2"},
751 {"ADC 24 Mux", "DMIC3", "DMIC3"},
752 {"ADC 24 Mux", "DMIC4", "DMIC4"},
753 {"ADC 25 Mux", "MIC1", "MIC1"},
754 {"ADC 25 Mux", "DMIC1", "DMIC1"},
755 {"ADC 25 Mux", "DMIC2", "DMIC2"},
756 {"ADC 25 Mux", "DMIC3", "DMIC3"},
757 {"ADC 25 Mux", "DMIC4", "DMIC4"},
758};
759
760static int rt715_set_bias_level(struct snd_soc_component *component,
761 enum snd_soc_bias_level level)
762{
763 struct snd_soc_dapm_context *dapm =
764 snd_soc_component_get_dapm(component);
765 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
766
767 switch (level) {
768 case SND_SOC_BIAS_PREPARE:
769 if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
770 regmap_write(rt715->regmap,
771 RT715_SET_AUDIO_POWER_STATE,
772 AC_PWRST_D0);
773 msleep(RT715_POWER_UP_DELAY_MS);
774 }
775 break;
776
777 case SND_SOC_BIAS_STANDBY:
778 regmap_write(rt715->regmap,
779 RT715_SET_AUDIO_POWER_STATE,
780 AC_PWRST_D3);
781 break;
782
783 default:
784 break;
785 }
786 dapm->bias_level = level;
787 return 0;
788}
789
790static int rt715_probe(struct snd_soc_component *component)
791{
792 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
793 int ret;
794
795 if (!rt715->first_hw_init)
796 return 0;
797
798 ret = pm_runtime_resume(component->dev);
799 if (ret < 0 && ret != -EACCES)
800 return ret;
801
802 return 0;
803}
804
805static const struct snd_soc_component_driver soc_codec_dev_rt715 = {
806 .probe = rt715_probe,
807 .set_bias_level = rt715_set_bias_level,
808 .controls = rt715_snd_controls,
809 .num_controls = ARRAY_SIZE(rt715_snd_controls),
810 .dapm_widgets = rt715_dapm_widgets,
811 .num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets),
812 .dapm_routes = rt715_audio_map,
813 .num_dapm_routes = ARRAY_SIZE(rt715_audio_map),
814 .endianness = 1,
815};
816
817static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
818 int direction)
819{
820
821 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
822
823 return 0;
824}
825
826static void rt715_shutdown(struct snd_pcm_substream *substream,
827 struct snd_soc_dai *dai)
828
829{
830 snd_soc_dai_set_dma_data(dai, substream, NULL);
831}
832
833static int rt715_pcm_hw_params(struct snd_pcm_substream *substream,
834 struct snd_pcm_hw_params *params,
835 struct snd_soc_dai *dai)
836{
837 struct snd_soc_component *component = dai->component;
838 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
839 struct sdw_stream_config stream_config = {0};
840 struct sdw_port_config port_config = {0};
841 struct sdw_stream_runtime *sdw_stream;
842 int retval;
843 unsigned int val = 0;
844
845 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
846
847 if (!sdw_stream)
848 return -EINVAL;
849
850 if (!rt715->slave)
851 return -EINVAL;
852
853 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
854
855 switch (dai->id) {
856 case RT715_AIF1:
857 port_config.num = 6;
858 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);
859 break;
860 case RT715_AIF2:
861 port_config.num = 4;
862 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);
863 break;
864 default:
865 dev_err(component->dev, "%s: Invalid DAI id %d\n", __func__, dai->id);
866 return -EINVAL;
867 }
868
869 retval = sdw_stream_add_slave(rt715->slave, &stream_config,
870 &port_config, 1, sdw_stream);
871 if (retval) {
872 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
873 return retval;
874 }
875
876 switch (params_rate(params)) {
877 /* bit 14 0:48K 1:44.1K */
878 /* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */
879 case 44100:
880 val |= 0x40 << 8;
881 break;
882 case 48000:
883 val |= 0x0 << 8;
884 break;
885 default:
886 dev_err(component->dev, "%s: Unsupported sample rate %d\n",
887 __func__, params_rate(params));
888 return -EINVAL;
889 }
890
891 if (params_channels(params) <= 16) {
892 /* bit 3:0 Number of Channel */
893 val |= (params_channels(params) - 1);
894 } else {
895 dev_err(component->dev, "%s: Unsupported channels %d\n",
896 __func__, params_channels(params));
897 return -EINVAL;
898 }
899
900 switch (params_width(params)) {
901 /* bit 6:4 Bits per Sample */
902 case 8:
903 break;
904 case 16:
905 val |= (0x1 << 4);
906 break;
907 case 20:
908 val |= (0x2 << 4);
909 break;
910 case 24:
911 val |= (0x3 << 4);
912 break;
913 case 32:
914 val |= (0x4 << 4);
915 break;
916 default:
917 return -EINVAL;
918 }
919
920 regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val);
921 regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val);
922 regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val);
923 regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val);
924
925 return retval;
926}
927
928static int rt715_pcm_hw_free(struct snd_pcm_substream *substream,
929 struct snd_soc_dai *dai)
930{
931 struct snd_soc_component *component = dai->component;
932 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
933 struct sdw_stream_runtime *sdw_stream =
934 snd_soc_dai_get_dma_data(dai, substream);
935
936 if (!rt715->slave)
937 return -EINVAL;
938
939 sdw_stream_remove_slave(rt715->slave, sdw_stream);
940 return 0;
941}
942
943#define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
944#define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
945 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
946
947static const struct snd_soc_dai_ops rt715_ops = {
948 .hw_params = rt715_pcm_hw_params,
949 .hw_free = rt715_pcm_hw_free,
950 .set_stream = rt715_set_sdw_stream,
951 .shutdown = rt715_shutdown,
952};
953
954static struct snd_soc_dai_driver rt715_dai[] = {
955 {
956 .name = "rt715-aif1",
957 .id = RT715_AIF1,
958 .capture = {
959 .stream_name = "DP6 Capture",
960 .channels_min = 1,
961 .channels_max = 2,
962 .rates = RT715_STEREO_RATES,
963 .formats = RT715_FORMATS,
964 },
965 .ops = &rt715_ops,
966 },
967 {
968 .name = "rt715-aif2",
969 .id = RT715_AIF2,
970 .capture = {
971 .stream_name = "DP4 Capture",
972 .channels_min = 1,
973 .channels_max = 2,
974 .rates = RT715_STEREO_RATES,
975 .formats = RT715_FORMATS,
976 },
977 .ops = &rt715_ops,
978 },
979};
980
981/* Bus clock frequency */
982#define RT715_CLK_FREQ_9600000HZ 9600000
983#define RT715_CLK_FREQ_12000000HZ 12000000
984#define RT715_CLK_FREQ_6000000HZ 6000000
985#define RT715_CLK_FREQ_4800000HZ 4800000
986#define RT715_CLK_FREQ_2400000HZ 2400000
987#define RT715_CLK_FREQ_12288000HZ 12288000
988
989int rt715_clock_config(struct device *dev)
990{
991 struct rt715_priv *rt715 = dev_get_drvdata(dev);
992 unsigned int clk_freq, value;
993
994 clk_freq = (rt715->params.curr_dr_freq >> 1);
995
996 switch (clk_freq) {
997 case RT715_CLK_FREQ_12000000HZ:
998 value = 0x0;
999 break;
1000 case RT715_CLK_FREQ_6000000HZ:
1001 value = 0x1;
1002 break;
1003 case RT715_CLK_FREQ_9600000HZ:
1004 value = 0x2;
1005 break;
1006 case RT715_CLK_FREQ_4800000HZ:
1007 value = 0x3;
1008 break;
1009 case RT715_CLK_FREQ_2400000HZ:
1010 value = 0x4;
1011 break;
1012 case RT715_CLK_FREQ_12288000HZ:
1013 value = 0x5;
1014 break;
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 regmap_write(rt715->regmap, 0xe0, value);
1020 regmap_write(rt715->regmap, 0xf0, value);
1021
1022 return 0;
1023}
1024
1025int rt715_init(struct device *dev, struct regmap *sdw_regmap,
1026 struct regmap *regmap, struct sdw_slave *slave)
1027{
1028 struct rt715_priv *rt715;
1029 int ret;
1030
1031 rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
1032 if (!rt715)
1033 return -ENOMEM;
1034
1035 dev_set_drvdata(dev, rt715);
1036 rt715->slave = slave;
1037 rt715->regmap = regmap;
1038 rt715->sdw_regmap = sdw_regmap;
1039
1040 regcache_cache_only(rt715->regmap, true);
1041
1042 /*
1043 * Mark hw_init to false
1044 * HW init will be performed when device reports present
1045 */
1046 rt715->hw_init = false;
1047 rt715->first_hw_init = false;
1048
1049 ret = devm_snd_soc_register_component(dev,
1050 &soc_codec_dev_rt715,
1051 rt715_dai,
1052 ARRAY_SIZE(rt715_dai));
1053 if (ret < 0)
1054 return ret;
1055
1056 /* set autosuspend parameters */
1057 pm_runtime_set_autosuspend_delay(dev, 3000);
1058 pm_runtime_use_autosuspend(dev);
1059
1060 /* make sure the device does not suspend immediately */
1061 pm_runtime_mark_last_busy(dev);
1062
1063 pm_runtime_enable(dev);
1064
1065 /* important note: the device is NOT tagged as 'active' and will remain
1066 * 'suspended' until the hardware is enumerated/initialized. This is required
1067 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
1068 * fail with -EACCESS because of race conditions between card creation and enumeration
1069 */
1070
1071 return 0;
1072}
1073
1074int rt715_io_init(struct device *dev, struct sdw_slave *slave)
1075{
1076 struct rt715_priv *rt715 = dev_get_drvdata(dev);
1077
1078 if (rt715->hw_init)
1079 return 0;
1080
1081 regcache_cache_only(rt715->regmap, false);
1082
1083 /*
1084 * PM runtime status is marked as 'active' only when a Slave reports as Attached
1085 */
1086 if (!rt715->first_hw_init)
1087 /* update count of parent 'active' children */
1088 pm_runtime_set_active(&slave->dev);
1089
1090 pm_runtime_get_noresume(&slave->dev);
1091
1092 rt715_reset(rt715->regmap);
1093
1094 /* Mute nid=08h/09h */
1095 regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);
1096 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);
1097 /* Mute nid=07h/27h */
1098 regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);
1099 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);
1100
1101 /* Set Pin Widget */
1102 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);
1103 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);
1104 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);
1105 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);
1106 /* Set Converter Stream */
1107 regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);
1108 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);
1109 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);
1110 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);
1111 /* Set Configuration Default */
1112 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);
1113 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);
1114 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);
1115 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);
1116 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);
1117 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);
1118 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);
1119 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);
1120 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);
1121 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);
1122 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);
1123 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);
1124 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);
1125 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);
1126 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);
1127 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);
1128
1129 /* Finish Initial Settings, set power to D3 */
1130 regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
1131
1132 if (rt715->first_hw_init)
1133 regcache_mark_dirty(rt715->regmap);
1134 else
1135 rt715->first_hw_init = true;
1136
1137 /* Mark Slave initialization complete */
1138 rt715->hw_init = true;
1139
1140 pm_runtime_mark_last_busy(&slave->dev);
1141 pm_runtime_put_autosuspend(&slave->dev);
1142
1143 return 0;
1144}
1145
1146MODULE_DESCRIPTION("ASoC rt715 driver");
1147MODULE_DESCRIPTION("ASoC rt715 driver SDW");
1148MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1149MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * rt715.c -- rt715 ALSA SoC audio driver
4 *
5 * Copyright(c) 2019 Realtek Semiconductor Corp.
6 *
7 * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
8 *
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/pm_runtime.h>
17#include <linux/pm.h>
18#include <linux/soundwire/sdw.h>
19#include <linux/gpio.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>
22#include <linux/platform_device.h>
23#include <linux/regulator/consumer.h>
24#include <linux/gpio/consumer.h>
25#include <linux/of.h>
26#include <linux/of_gpio.h>
27#include <linux/of_device.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/hda_verbs.h>
36
37#include "rt715.h"
38
39static int rt715_index_write(struct regmap *regmap, unsigned int reg,
40 unsigned int value)
41{
42 int ret;
43 unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg;
44
45 ret = regmap_write(regmap, addr, value);
46 if (ret < 0) {
47 pr_err("Failed to set private value: %08x <= %04x %d\n", ret,
48 addr, value);
49 }
50
51 return ret;
52}
53
54static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h,
55 unsigned int addr_l, unsigned int val_h,
56 unsigned int *r_val, unsigned int *l_val)
57{
58 int ret;
59 /* R Channel */
60 *r_val = val_h << 8;
61 ret = regmap_read(rt715->regmap, addr_l, r_val);
62 if (ret < 0)
63 pr_err("Failed to get R channel gain.\n");
64
65 /* L Channel */
66 val_h |= 0x20;
67 *l_val = val_h << 8;
68 ret = regmap_read(rt715->regmap, addr_h, l_val);
69 if (ret < 0)
70 pr_err("Failed to get L channel gain.\n");
71}
72
73/* For Verb-Set Amplifier Gain (Verb ID = 3h) */
74static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol,
75 struct snd_ctl_elem_value *ucontrol)
76{
77 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
78 struct snd_soc_dapm_context *dapm =
79 snd_soc_component_get_dapm(component);
80 struct soc_mixer_control *mc =
81 (struct soc_mixer_control *)kcontrol->private_value;
82 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
83 unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
84 unsigned int read_ll, read_rl, i;
85 unsigned int k_vol_changed = 0;
86
87 for (i = 0; i < 2; i++) {
88 if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) {
89 k_vol_changed = 1;
90 break;
91 }
92 }
93
94 /* Can't use update bit function, so read the original value first */
95 addr_h = mc->reg;
96 addr_l = mc->rreg;
97
98 if (mc->shift == RT715_DIR_OUT_SFT) /* output */
99 val_h = 0x80;
100 else /* input */
101 val_h = 0x0;
102
103 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
104
105 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
106 regmap_write(rt715->regmap,
107 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
108
109 /* L Channel */
110 rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0];
111 /* for gain */
112 val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
113 if (val_ll > mc->max)
114 val_ll = mc->max;
115 /* keep mute status */
116 val_ll |= read_ll & 0x80;
117
118 /* R Channel */
119 rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1];
120 /* for gain */
121 val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
122 if (val_lr > mc->max)
123 val_lr = mc->max;
124 /* keep mute status */
125 val_lr |= read_rl & 0x80;
126
127 for (i = 0; i < 3; i++) { /* retry 3 times at most */
128
129 if (val_ll == val_lr) {
130 /* Set both L/R channels at the same time */
131 val_h = (1 << mc->shift) | (3 << 4);
132 regmap_write(rt715->regmap, addr_h,
133 (val_h << 8) | val_ll);
134 regmap_write(rt715->regmap, addr_l,
135 (val_h << 8) | val_ll);
136 } else {
137 /* Lch*/
138 val_h = (1 << mc->shift) | (1 << 5);
139 regmap_write(rt715->regmap, addr_h,
140 (val_h << 8) | val_ll);
141 /* Rch */
142 val_h = (1 << mc->shift) | (1 << 4);
143 regmap_write(rt715->regmap, addr_l,
144 (val_h << 8) | val_lr);
145 }
146 /* check result */
147 if (mc->shift == RT715_DIR_OUT_SFT) /* output */
148 val_h = 0x80;
149 else /* input */
150 val_h = 0x0;
151
152 rt715_get_gain(rt715, addr_h, addr_l, val_h,
153 &read_rl, &read_ll);
154 if (read_rl == val_lr && read_ll == val_ll)
155 break;
156 }
157
158 /* D0:power on state, D3: power saving mode */
159 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
160 regmap_write(rt715->regmap,
161 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
162 return k_vol_changed;
163}
164
165static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol,
166 struct snd_ctl_elem_value *ucontrol)
167{
168 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
169 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
170 struct soc_mixer_control *mc =
171 (struct soc_mixer_control *)kcontrol->private_value;
172 unsigned int addr_h, addr_l, val_h;
173 unsigned int read_ll, read_rl;
174
175 addr_h = mc->reg;
176 addr_l = mc->rreg;
177 if (mc->shift == RT715_DIR_OUT_SFT) /* output */
178 val_h = 0x80;
179 else /* input */
180 val_h = 0x0;
181
182 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
183
184 if (mc->invert) {
185 /* for mute status */
186 read_ll = !(read_ll & 0x80);
187 read_rl = !(read_rl & 0x80);
188 } else {
189 /* for gain */
190 read_ll = read_ll & 0x7f;
191 read_rl = read_rl & 0x7f;
192 }
193 ucontrol->value.integer.value[0] = read_ll;
194 ucontrol->value.integer.value[1] = read_rl;
195
196 return 0;
197}
198
199static int rt715_set_main_switch_put(struct snd_kcontrol *kcontrol,
200 struct snd_ctl_elem_value *ucontrol)
201{
202 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
203 struct snd_soc_dapm_context *dapm =
204 snd_soc_component_get_dapm(component);
205 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
206 unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
207 RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
208 RT715_SET_GAIN_MIX_ADC2_H};
209 unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
210 RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
211 RT715_SET_GAIN_MIX_ADC2_L};
212 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
213 unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0;
214 unsigned int read_ll, read_rl, i, j, loop_cnt = 4;
215
216 for (i = 0; i < 8; i++) {
217 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i])
218 k_changed = 1;
219 }
220
221 for (j = 0; j < loop_cnt; j++) {
222 /* Can't use update bit function, so read the original value first */
223 addr_h = capture_reg_H[j];
224 addr_l = capture_reg_L[j];
225 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
226
227 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
228 regmap_write(rt715->regmap,
229 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
230
231 /* L Channel */
232 /* for mute */
233 rt715->kctl_8ch_switch_ori[j * 2] =
234 ucontrol->value.integer.value[j * 2];
235 val_ll = (!ucontrol->value.integer.value[j * 2]) << 7;
236 /* keep gain */
237 val_ll |= read_ll & 0x7f;
238
239 /* R Channel */
240 /* for mute */
241 rt715->kctl_8ch_switch_ori[j * 2 + 1] =
242 ucontrol->value.integer.value[j * 2 + 1];
243 val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7;
244 /* keep gain */
245 val_lr |= read_rl & 0x7f;
246
247 for (i = 0; i < 3; i++) { /* retry 3 times at most */
248
249 if (val_ll == val_lr) {
250 /* Set both L/R channels at the same time */
251 val_h = (1 << k_shift) | (3 << 4);
252 regmap_write(rt715->regmap, addr_h,
253 (val_h << 8) | val_ll);
254 regmap_write(rt715->regmap, addr_l,
255 (val_h << 8) | val_ll);
256 } else {
257 /* Lch*/
258 val_h = (1 << k_shift) | (1 << 5);
259 regmap_write(rt715->regmap, addr_h,
260 (val_h << 8) | val_ll);
261 /* Rch */
262 val_h = (1 << k_shift) | (1 << 4);
263 regmap_write(rt715->regmap, addr_l,
264 (val_h << 8) | val_lr);
265 }
266 val_h = 0x0;
267 rt715_get_gain(rt715, addr_h, addr_l, val_h,
268 &read_rl, &read_ll);
269 if (read_rl == val_lr && read_ll == val_ll)
270 break;
271 }
272 }
273
274 /* D0:power on state, D3: power saving mode */
275 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
276 regmap_write(rt715->regmap,
277 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
278 return k_changed;
279}
280
281static int rt715_set_main_switch_get(struct snd_kcontrol *kcontrol,
282 struct snd_ctl_elem_value *ucontrol)
283{
284 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
285 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
286 unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
287 RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
288 RT715_SET_GAIN_MIX_ADC2_H};
289 unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
290 RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
291 RT715_SET_GAIN_MIX_ADC2_L};
292 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
293 unsigned int read_ll, read_rl;
294
295 for (i = 0; i < loop_cnt; i++) {
296 addr_h = capture_reg_H[i];
297 addr_l = capture_reg_L[i];
298 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
299
300 ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80);
301 ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80);
302 }
303
304 return 0;
305}
306
307static int rt715_set_main_vol_put(struct snd_kcontrol *kcontrol,
308 struct snd_ctl_elem_value *ucontrol)
309{
310 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
311 struct snd_soc_dapm_context *dapm =
312 snd_soc_component_get_dapm(component);
313 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
314 unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
315 RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
316 RT715_SET_GAIN_MIX_ADC2_H};
317 unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
318 RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
319 RT715_SET_GAIN_MIX_ADC2_L};
320 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
321 unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0;
322 unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f;
323
324 for (i = 0; i < 8; i++) {
325 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i])
326 k_changed = 1;
327 }
328
329 for (j = 0; j < loop_cnt; j++) {
330 addr_h = capture_reg_H[j];
331 addr_l = capture_reg_L[j];
332 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
333
334 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
335 regmap_write(rt715->regmap,
336 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
337
338 /* L Channel */
339 /* for gain */
340 rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2];
341 val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f);
342 if (val_ll > k_max)
343 val_ll = k_max;
344 /* keep mute status */
345 val_ll |= read_ll & 0x80;
346
347 /* R Channel */
348 /* for gain */
349 rt715->kctl_8ch_vol_ori[j * 2 + 1] =
350 ucontrol->value.integer.value[j * 2 + 1];
351 val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f);
352 if (val_lr > k_max)
353 val_lr = k_max;
354 /* keep mute status */
355 val_lr |= read_rl & 0x80;
356
357 for (i = 0; i < 3; i++) { /* retry 3 times at most */
358 if (val_ll == val_lr) {
359 /* Set both L/R channels at the same time */
360 val_h = (1 << k_shift) | (3 << 4);
361 regmap_write(rt715->regmap, addr_h,
362 (val_h << 8) | val_ll);
363 regmap_write(rt715->regmap, addr_l,
364 (val_h << 8) | val_ll);
365 } else {
366 /* Lch*/
367 val_h = (1 << k_shift) | (1 << 5);
368 regmap_write(rt715->regmap, addr_h,
369 (val_h << 8) | val_ll);
370 /* Rch */
371 val_h = (1 << k_shift) | (1 << 4);
372 regmap_write(rt715->regmap, addr_l,
373 (val_h << 8) | val_lr);
374 }
375 val_h = 0x0;
376 rt715_get_gain(rt715, addr_h, addr_l, val_h,
377 &read_rl, &read_ll);
378 if (read_rl == val_lr && read_ll == val_ll)
379 break;
380 }
381 }
382
383 /* D0:power on state, D3: power saving mode */
384 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
385 regmap_write(rt715->regmap,
386 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
387 return k_changed;
388}
389
390static int rt715_set_main_vol_get(struct snd_kcontrol *kcontrol,
391 struct snd_ctl_elem_value *ucontrol)
392{
393 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
394 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
395 unsigned int capture_reg_H[] = {RT715_SET_GAIN_MIC_ADC_H,
396 RT715_SET_GAIN_LINE_ADC_H, RT715_SET_GAIN_MIX_ADC_H,
397 RT715_SET_GAIN_MIX_ADC2_H};
398 unsigned int capture_reg_L[] = {RT715_SET_GAIN_MIC_ADC_L,
399 RT715_SET_GAIN_LINE_ADC_L, RT715_SET_GAIN_MIX_ADC_L,
400 RT715_SET_GAIN_MIX_ADC2_L};
401 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
402 unsigned int read_ll, read_rl;
403
404 for (i = 0; i < loop_cnt; i++) {
405 addr_h = capture_reg_H[i];
406 addr_l = capture_reg_L[i];
407 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
408
409 ucontrol->value.integer.value[i * 2] = read_ll & 0x7f;
410 ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f;
411 }
412
413 return 0;
414}
415
416static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
417static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
418
419static int rt715_switch_info(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_info *uinfo)
421{
422 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
423 uinfo->count = 8;
424 uinfo->value.integer.min = 0;
425 uinfo->value.integer.max = 1;
426 return 0;
427}
428
429static int rt715_vol_info(struct snd_kcontrol *kcontrol,
430 struct snd_ctl_elem_info *uinfo)
431{
432 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
433 uinfo->count = 8;
434 uinfo->value.integer.min = 0;
435 uinfo->value.integer.max = 0x3f;
436 return 0;
437}
438
439#define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
440 xhandler_get, xhandler_put) \
441{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
442 .info = snd_soc_info_volsw, \
443 .get = xhandler_get, .put = xhandler_put, \
444 .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
445 xmax, xinvert) }
446
447#define RT715_MAIN_SWITCH_EXT(xname, xhandler_get, xhandler_put) \
448{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
449 .info = rt715_switch_info, \
450 .get = xhandler_get, .put = xhandler_put, \
451}
452
453#define RT715_MAIN_VOL_EXT_TLV(xname, xhandler_get, xhandler_put, tlv_array) \
454{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
455 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
456 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
457 .tlv.p = (tlv_array), \
458 .info = rt715_vol_info, \
459 .get = xhandler_get, .put = xhandler_put, \
460}
461
462static const struct snd_kcontrol_new rt715_snd_controls[] = {
463 /* Capture switch */
464 RT715_MAIN_SWITCH_EXT("Capture Switch",
465 rt715_set_main_switch_get, rt715_set_main_switch_put),
466 /* Volume Control */
467 RT715_MAIN_VOL_EXT_TLV("Capture Volume",
468 rt715_set_main_vol_get, rt715_set_main_vol_put, in_vol_tlv),
469 /* MIC Boost Control */
470 SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H,
471 RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
472 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
473 mic_vol_tlv),
474 SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H,
475 RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
476 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
477 mic_vol_tlv),
478 SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H,
479 RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
480 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
481 mic_vol_tlv),
482 SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H,
483 RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
484 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
485 mic_vol_tlv),
486 SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H,
487 RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
488 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
489 mic_vol_tlv),
490 SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H,
491 RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
492 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
493 mic_vol_tlv),
494 SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H,
495 RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
496 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
497 mic_vol_tlv),
498 SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H,
499 RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
500 rt715_set_amp_gain_get, rt715_set_amp_gain_put,
501 mic_vol_tlv),
502};
503
504static int rt715_mux_get(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 struct snd_soc_component *component =
508 snd_soc_dapm_kcontrol_component(kcontrol);
509 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
510 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
511 unsigned int reg, val;
512 int ret;
513
514 /* nid = e->reg, vid = 0xf01 */
515 reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
516 ret = regmap_read(rt715->regmap, reg, &val);
517 if (ret < 0) {
518 dev_err(component->dev, "%s: sdw read failed: %d\n",
519 __func__, ret);
520 return ret;
521 }
522
523 /*
524 * The first two indices of ADC Mux 24/25 are routed to the same
525 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
526 * To have a unique set of inputs, we skip the index1 of the muxes.
527 */
528 if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))
529 val -= 1;
530 ucontrol->value.enumerated.item[0] = val;
531
532 return 0;
533}
534
535static int rt715_mux_put(struct snd_kcontrol *kcontrol,
536 struct snd_ctl_elem_value *ucontrol)
537{
538 struct snd_soc_component *component =
539 snd_soc_dapm_kcontrol_component(kcontrol);
540 struct snd_soc_dapm_context *dapm =
541 snd_soc_dapm_kcontrol_dapm(kcontrol);
542 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
543 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
544 unsigned int *item = ucontrol->value.enumerated.item;
545 unsigned int val, val2 = 0, change, reg;
546 int ret;
547
548 if (item[0] >= e->items)
549 return -EINVAL;
550
551 /* Verb ID = 0x701h, nid = e->reg */
552 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
553
554 reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
555 ret = regmap_read(rt715->regmap, reg, &val2);
556 if (ret < 0) {
557 dev_err(component->dev, "%s: sdw read failed: %d\n",
558 __func__, ret);
559 return ret;
560 }
561
562 if (val == val2)
563 change = 0;
564 else
565 change = 1;
566
567 if (change) {
568 reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
569 regmap_write(rt715->regmap, reg, val);
570 }
571
572 snd_soc_dapm_mux_update_power(dapm, kcontrol,
573 item[0], e, NULL);
574
575 return change;
576}
577
578static const char * const adc_22_23_mux_text[] = {
579 "MIC1",
580 "MIC2",
581 "LINE1",
582 "LINE2",
583 "DMIC1",
584 "DMIC2",
585 "DMIC3",
586 "DMIC4",
587};
588
589/*
590 * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
591 * 1 will be connected to the same dmic source, therefore we skip index 1 to
592 * avoid misunderstanding on usage of dapm routing.
593 */
594static const unsigned int rt715_adc_24_25_values[] = {
595 0,
596 2,
597 3,
598 4,
599 5,
600};
601
602static const char * const adc_24_mux_text[] = {
603 "MIC2",
604 "DMIC1",
605 "DMIC2",
606 "DMIC3",
607 "DMIC4",
608};
609
610static const char * const adc_25_mux_text[] = {
611 "MIC1",
612 "DMIC1",
613 "DMIC2",
614 "DMIC3",
615 "DMIC4",
616};
617
618static SOC_ENUM_SINGLE_DECL(
619 rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
620
621static SOC_ENUM_SINGLE_DECL(
622 rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
623
624static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
625 RT715_MUX_IN3, 0, 0xf,
626 adc_24_mux_text, rt715_adc_24_25_values);
627
628static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
629 RT715_MUX_IN4, 0, 0xf,
630 adc_25_mux_text, rt715_adc_24_25_values);
631
632static const struct snd_kcontrol_new rt715_adc22_mux =
633 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
634 rt715_mux_get, rt715_mux_put);
635
636static const struct snd_kcontrol_new rt715_adc23_mux =
637 SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
638 rt715_mux_get, rt715_mux_put);
639
640static const struct snd_kcontrol_new rt715_adc24_mux =
641 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
642 rt715_mux_get, rt715_mux_put);
643
644static const struct snd_kcontrol_new rt715_adc25_mux =
645 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
646 rt715_mux_get, rt715_mux_put);
647
648static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = {
649 SND_SOC_DAPM_INPUT("DMIC1"),
650 SND_SOC_DAPM_INPUT("DMIC2"),
651 SND_SOC_DAPM_INPUT("DMIC3"),
652 SND_SOC_DAPM_INPUT("DMIC4"),
653 SND_SOC_DAPM_INPUT("MIC1"),
654 SND_SOC_DAPM_INPUT("MIC2"),
655 SND_SOC_DAPM_INPUT("LINE1"),
656 SND_SOC_DAPM_INPUT("LINE2"),
657 SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
658 SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
659 SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
660 SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
661 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
662 &rt715_adc22_mux),
663 SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
664 &rt715_adc23_mux),
665 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
666 &rt715_adc24_mux),
667 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
668 &rt715_adc25_mux),
669 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
671};
672
673static const struct snd_soc_dapm_route rt715_audio_map[] = {
674 {"DP6TX", NULL, "ADC 09"},
675 {"DP6TX", NULL, "ADC 08"},
676 {"DP4TX", NULL, "ADC 07"},
677 {"DP4TX", NULL, "ADC 27"},
678 {"ADC 09", NULL, "ADC 22 Mux"},
679 {"ADC 08", NULL, "ADC 23 Mux"},
680 {"ADC 07", NULL, "ADC 24 Mux"},
681 {"ADC 27", NULL, "ADC 25 Mux"},
682 {"ADC 22 Mux", "MIC1", "MIC1"},
683 {"ADC 22 Mux", "MIC2", "MIC2"},
684 {"ADC 22 Mux", "LINE1", "LINE1"},
685 {"ADC 22 Mux", "LINE2", "LINE2"},
686 {"ADC 22 Mux", "DMIC1", "DMIC1"},
687 {"ADC 22 Mux", "DMIC2", "DMIC2"},
688 {"ADC 22 Mux", "DMIC3", "DMIC3"},
689 {"ADC 22 Mux", "DMIC4", "DMIC4"},
690 {"ADC 23 Mux", "MIC1", "MIC1"},
691 {"ADC 23 Mux", "MIC2", "MIC2"},
692 {"ADC 23 Mux", "LINE1", "LINE1"},
693 {"ADC 23 Mux", "LINE2", "LINE2"},
694 {"ADC 23 Mux", "DMIC1", "DMIC1"},
695 {"ADC 23 Mux", "DMIC2", "DMIC2"},
696 {"ADC 23 Mux", "DMIC3", "DMIC3"},
697 {"ADC 23 Mux", "DMIC4", "DMIC4"},
698 {"ADC 24 Mux", "MIC2", "MIC2"},
699 {"ADC 24 Mux", "DMIC1", "DMIC1"},
700 {"ADC 24 Mux", "DMIC2", "DMIC2"},
701 {"ADC 24 Mux", "DMIC3", "DMIC3"},
702 {"ADC 24 Mux", "DMIC4", "DMIC4"},
703 {"ADC 25 Mux", "MIC1", "MIC1"},
704 {"ADC 25 Mux", "DMIC1", "DMIC1"},
705 {"ADC 25 Mux", "DMIC2", "DMIC2"},
706 {"ADC 25 Mux", "DMIC3", "DMIC3"},
707 {"ADC 25 Mux", "DMIC4", "DMIC4"},
708};
709
710static int rt715_set_bias_level(struct snd_soc_component *component,
711 enum snd_soc_bias_level level)
712{
713 struct snd_soc_dapm_context *dapm =
714 snd_soc_component_get_dapm(component);
715 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
716
717 switch (level) {
718 case SND_SOC_BIAS_PREPARE:
719 if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
720 regmap_write(rt715->regmap,
721 RT715_SET_AUDIO_POWER_STATE,
722 AC_PWRST_D0);
723 msleep(RT715_POWER_UP_DELAY_MS);
724 }
725 break;
726
727 case SND_SOC_BIAS_STANDBY:
728 regmap_write(rt715->regmap,
729 RT715_SET_AUDIO_POWER_STATE,
730 AC_PWRST_D3);
731 break;
732
733 default:
734 break;
735 }
736 dapm->bias_level = level;
737 return 0;
738}
739
740static const struct snd_soc_component_driver soc_codec_dev_rt715 = {
741 .set_bias_level = rt715_set_bias_level,
742 .controls = rt715_snd_controls,
743 .num_controls = ARRAY_SIZE(rt715_snd_controls),
744 .dapm_widgets = rt715_dapm_widgets,
745 .num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets),
746 .dapm_routes = rt715_audio_map,
747 .num_dapm_routes = ARRAY_SIZE(rt715_audio_map),
748};
749
750static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
751 int direction)
752{
753
754 struct sdw_stream_data *stream;
755
756 if (!sdw_stream)
757 return 0;
758
759 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
760 if (!stream)
761 return -ENOMEM;
762
763 stream->sdw_stream = sdw_stream;
764
765 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
766 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
767 dai->playback_dma_data = stream;
768 else
769 dai->capture_dma_data = stream;
770
771 return 0;
772}
773
774static void rt715_shutdown(struct snd_pcm_substream *substream,
775 struct snd_soc_dai *dai)
776
777{
778 struct sdw_stream_data *stream;
779
780 stream = snd_soc_dai_get_dma_data(dai, substream);
781 snd_soc_dai_set_dma_data(dai, substream, NULL);
782 kfree(stream);
783}
784
785static int rt715_pcm_hw_params(struct snd_pcm_substream *substream,
786 struct snd_pcm_hw_params *params,
787 struct snd_soc_dai *dai)
788{
789 struct snd_soc_component *component = dai->component;
790 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
791 struct sdw_stream_config stream_config;
792 struct sdw_port_config port_config;
793 enum sdw_data_direction direction;
794 struct sdw_stream_data *stream;
795 int retval, port, num_channels;
796 unsigned int val = 0;
797
798 stream = snd_soc_dai_get_dma_data(dai, substream);
799
800 if (!stream)
801 return -EINVAL;
802
803 if (!rt715->slave)
804 return -EINVAL;
805
806 switch (dai->id) {
807 case RT715_AIF1:
808 direction = SDW_DATA_DIR_TX;
809 port = 6;
810 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);
811 break;
812 case RT715_AIF2:
813 direction = SDW_DATA_DIR_TX;
814 port = 4;
815 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);
816 break;
817 default:
818 dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
819 return -EINVAL;
820 }
821
822 stream_config.frame_rate = params_rate(params);
823 stream_config.ch_count = params_channels(params);
824 stream_config.bps = snd_pcm_format_width(params_format(params));
825 stream_config.direction = direction;
826
827 num_channels = params_channels(params);
828 port_config.ch_mask = (1 << (num_channels)) - 1;
829 port_config.num = port;
830
831 retval = sdw_stream_add_slave(rt715->slave, &stream_config,
832 &port_config, 1, stream->sdw_stream);
833 if (retval) {
834 dev_err(dai->dev, "Unable to configure port\n");
835 return retval;
836 }
837
838 switch (params_rate(params)) {
839 /* bit 14 0:48K 1:44.1K */
840 /* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */
841 case 44100:
842 val |= 0x40 << 8;
843 break;
844 case 48000:
845 val |= 0x0 << 8;
846 break;
847 default:
848 dev_err(component->dev, "Unsupported sample rate %d\n",
849 params_rate(params));
850 return -EINVAL;
851 }
852
853 if (params_channels(params) <= 16) {
854 /* bit 3:0 Number of Channel */
855 val |= (params_channels(params) - 1);
856 } else {
857 dev_err(component->dev, "Unsupported channels %d\n",
858 params_channels(params));
859 return -EINVAL;
860 }
861
862 switch (params_width(params)) {
863 /* bit 6:4 Bits per Sample */
864 case 8:
865 break;
866 case 16:
867 val |= (0x1 << 4);
868 break;
869 case 20:
870 val |= (0x2 << 4);
871 break;
872 case 24:
873 val |= (0x3 << 4);
874 break;
875 case 32:
876 val |= (0x4 << 4);
877 break;
878 default:
879 return -EINVAL;
880 }
881
882 regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val);
883 regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val);
884 regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val);
885 regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val);
886
887 return retval;
888}
889
890static int rt715_pcm_hw_free(struct snd_pcm_substream *substream,
891 struct snd_soc_dai *dai)
892{
893 struct snd_soc_component *component = dai->component;
894 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
895 struct sdw_stream_data *stream =
896 snd_soc_dai_get_dma_data(dai, substream);
897
898 if (!rt715->slave)
899 return -EINVAL;
900
901 sdw_stream_remove_slave(rt715->slave, stream->sdw_stream);
902 return 0;
903}
904
905#define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
906#define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
907 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
908
909static const struct snd_soc_dai_ops rt715_ops = {
910 .hw_params = rt715_pcm_hw_params,
911 .hw_free = rt715_pcm_hw_free,
912 .set_sdw_stream = rt715_set_sdw_stream,
913 .shutdown = rt715_shutdown,
914};
915
916static struct snd_soc_dai_driver rt715_dai[] = {
917 {
918 .name = "rt715-aif1",
919 .id = RT715_AIF1,
920 .capture = {
921 .stream_name = "DP6 Capture",
922 .channels_min = 1,
923 .channels_max = 2,
924 .rates = RT715_STEREO_RATES,
925 .formats = RT715_FORMATS,
926 },
927 .ops = &rt715_ops,
928 },
929 {
930 .name = "rt715-aif2",
931 .id = RT715_AIF2,
932 .capture = {
933 .stream_name = "DP4 Capture",
934 .channels_min = 1,
935 .channels_max = 2,
936 .rates = RT715_STEREO_RATES,
937 .formats = RT715_FORMATS,
938 },
939 .ops = &rt715_ops,
940 },
941};
942
943/* Bus clock frequency */
944#define RT715_CLK_FREQ_9600000HZ 9600000
945#define RT715_CLK_FREQ_12000000HZ 12000000
946#define RT715_CLK_FREQ_6000000HZ 6000000
947#define RT715_CLK_FREQ_4800000HZ 4800000
948#define RT715_CLK_FREQ_2400000HZ 2400000
949#define RT715_CLK_FREQ_12288000HZ 12288000
950
951int rt715_clock_config(struct device *dev)
952{
953 struct rt715_priv *rt715 = dev_get_drvdata(dev);
954 unsigned int clk_freq, value;
955
956 clk_freq = (rt715->params.curr_dr_freq >> 1);
957
958 switch (clk_freq) {
959 case RT715_CLK_FREQ_12000000HZ:
960 value = 0x0;
961 break;
962 case RT715_CLK_FREQ_6000000HZ:
963 value = 0x1;
964 break;
965 case RT715_CLK_FREQ_9600000HZ:
966 value = 0x2;
967 break;
968 case RT715_CLK_FREQ_4800000HZ:
969 value = 0x3;
970 break;
971 case RT715_CLK_FREQ_2400000HZ:
972 value = 0x4;
973 break;
974 case RT715_CLK_FREQ_12288000HZ:
975 value = 0x5;
976 break;
977 default:
978 return -EINVAL;
979 }
980
981 regmap_write(rt715->regmap, 0xe0, value);
982 regmap_write(rt715->regmap, 0xf0, value);
983
984 return 0;
985}
986
987int rt715_init(struct device *dev, struct regmap *sdw_regmap,
988 struct regmap *regmap, struct sdw_slave *slave)
989{
990 struct rt715_priv *rt715;
991 int ret;
992
993 rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
994 if (!rt715)
995 return -ENOMEM;
996
997 dev_set_drvdata(dev, rt715);
998 rt715->slave = slave;
999 rt715->regmap = regmap;
1000 rt715->sdw_regmap = sdw_regmap;
1001
1002 /*
1003 * Mark hw_init to false
1004 * HW init will be performed when device reports present
1005 */
1006 rt715->hw_init = false;
1007 rt715->first_hw_init = false;
1008
1009 ret = devm_snd_soc_register_component(dev,
1010 &soc_codec_dev_rt715,
1011 rt715_dai,
1012 ARRAY_SIZE(rt715_dai));
1013
1014 return ret;
1015}
1016
1017int rt715_io_init(struct device *dev, struct sdw_slave *slave)
1018{
1019 struct rt715_priv *rt715 = dev_get_drvdata(dev);
1020
1021 if (rt715->hw_init)
1022 return 0;
1023
1024 /*
1025 * PM runtime is only enabled when a Slave reports as Attached
1026 */
1027 if (!rt715->first_hw_init) {
1028 /* set autosuspend parameters */
1029 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
1030 pm_runtime_use_autosuspend(&slave->dev);
1031
1032 /* update count of parent 'active' children */
1033 pm_runtime_set_active(&slave->dev);
1034
1035 /* make sure the device does not suspend immediately */
1036 pm_runtime_mark_last_busy(&slave->dev);
1037
1038 pm_runtime_enable(&slave->dev);
1039 }
1040
1041 pm_runtime_get_noresume(&slave->dev);
1042
1043 /* Mute nid=08h/09h */
1044 regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);
1045 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);
1046 /* Mute nid=07h/27h */
1047 regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);
1048 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);
1049
1050 /* Set Pin Widget */
1051 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);
1052 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);
1053 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);
1054 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);
1055 /* Set Converter Stream */
1056 regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);
1057 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);
1058 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);
1059 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);
1060 /* Set Configuration Default */
1061 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);
1062 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);
1063 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);
1064 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);
1065 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);
1066 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);
1067 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);
1068 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);
1069 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);
1070 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);
1071 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);
1072 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);
1073 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);
1074 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);
1075 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);
1076 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);
1077
1078 /* Finish Initial Settings, set power to D3 */
1079 regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
1080
1081 if (rt715->first_hw_init)
1082 regcache_mark_dirty(rt715->regmap);
1083 else
1084 rt715->first_hw_init = true;
1085
1086 /* Mark Slave initialization complete */
1087 rt715->hw_init = true;
1088
1089 pm_runtime_mark_last_busy(&slave->dev);
1090 pm_runtime_put_autosuspend(&slave->dev);
1091
1092 return 0;
1093}
1094
1095MODULE_DESCRIPTION("ASoC rt715 driver");
1096MODULE_DESCRIPTION("ASoC rt715 driver SDW");
1097MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1098MODULE_LICENSE("GPL v2");