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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * cs42l42.h -- CS42L42 ALSA SoC audio driver header
4 *
5 * Copyright 2016-2022 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
10 */
11
12#ifndef __CS42L42_H__
13#define __CS42L42_H__
14
15#include <dt-bindings/sound/cs42l42.h>
16#include <linux/device.h>
17#include <linux/gpio/consumer.h>
18#include <linux/mutex.h>
19#include <linux/regmap.h>
20#include <linux/regulator/consumer.h>
21#include <linux/soundwire/sdw.h>
22#include <sound/jack.h>
23#include <sound/cs42l42.h>
24#include <sound/soc-component.h>
25#include <sound/soc-dai.h>
26
27struct cs42l42_private {
28 struct regmap *regmap;
29 struct device *dev;
30 struct regulator_bulk_data supplies[CS42L42_NUM_SUPPLIES];
31 struct gpio_desc *reset_gpio;
32 struct completion pdn_done;
33 struct snd_soc_jack *jack;
34 struct sdw_slave *sdw_peripheral;
35 struct mutex irq_lock;
36 int devid;
37 int irq;
38 int pll_config;
39 u32 sclk;
40 u32 sample_rate;
41 u32 bclk_ratio;
42 u8 plug_state;
43 u8 hs_type;
44 u8 ts_inv;
45 u8 ts_dbnc_rise;
46 u8 ts_dbnc_fall;
47 u8 btn_det_init_dbnce;
48 u8 btn_det_event_dbnce;
49 u8 bias_thresholds[CS42L42_NUM_BIASES];
50 u8 hs_bias_ramp_rate;
51 u8 hs_bias_ramp_time;
52 u8 hs_bias_sense_en;
53 u8 stream_use;
54 bool hp_adc_up_pending;
55 bool suspended;
56 bool sdw_waiting_first_unattach;
57 bool init_done;
58};
59
60extern const struct regmap_range_cfg cs42l42_page_range;
61extern const struct regmap_config cs42l42_regmap;
62extern const struct snd_soc_component_driver cs42l42_soc_component;
63extern struct snd_soc_dai_driver cs42l42_dai;
64
65bool cs42l42_readable_register(struct device *dev, unsigned int reg);
66bool cs42l42_volatile_register(struct device *dev, unsigned int reg);
67
68int cs42l42_pll_config(struct snd_soc_component *component,
69 unsigned int clk, unsigned int sample_rate);
70void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate);
71int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream);
72irqreturn_t cs42l42_irq_thread(int irq, void *data);
73int cs42l42_suspend(struct device *dev);
74int cs42l42_resume(struct device *dev);
75void cs42l42_resume_restore(struct device *dev);
76int cs42l42_common_probe(struct cs42l42_private *cs42l42,
77 const struct snd_soc_component_driver *component_drv,
78 struct snd_soc_dai_driver *dai);
79int cs42l42_init(struct cs42l42_private *cs42l42);
80void cs42l42_common_remove(struct cs42l42_private *cs42l42);
81
82#endif /* __CS42L42_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * cs42l42.h -- CS42L42 ALSA SoC audio driver header
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
10 */
11
12#ifndef __CS42L42_H__
13#define __CS42L42_H__
14
15#include <sound/jack.h>
16
17#define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
18#define CS42L42_WIN_START 0x00
19#define CS42L42_WIN_LEN 0x100
20#define CS42L42_RANGE_MIN 0x00
21#define CS42L42_RANGE_MAX 0x7F
22
23#define CS42L42_PAGE_10 0x1000
24#define CS42L42_PAGE_11 0x1100
25#define CS42L42_PAGE_12 0x1200
26#define CS42L42_PAGE_13 0x1300
27#define CS42L42_PAGE_15 0x1500
28#define CS42L42_PAGE_19 0x1900
29#define CS42L42_PAGE_1B 0x1B00
30#define CS42L42_PAGE_1C 0x1C00
31#define CS42L42_PAGE_1D 0x1D00
32#define CS42L42_PAGE_1F 0x1F00
33#define CS42L42_PAGE_20 0x2000
34#define CS42L42_PAGE_21 0x2100
35#define CS42L42_PAGE_23 0x2300
36#define CS42L42_PAGE_24 0x2400
37#define CS42L42_PAGE_25 0x2500
38#define CS42L42_PAGE_26 0x2600
39#define CS42L42_PAGE_28 0x2800
40#define CS42L42_PAGE_29 0x2900
41#define CS42L42_PAGE_2A 0x2A00
42#define CS42L42_PAGE_30 0x3000
43
44#define CS42L42_CHIP_ID 0x42A42
45
46/* Page 0x10 Global Registers */
47#define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
48#define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02)
49#define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03)
50#define CS42L42_FABID (CS42L42_PAGE_10 + 0x04)
51#define CS42L42_REVID (CS42L42_PAGE_10 + 0x05)
52#define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06)
53
54#define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07)
55#define CS42L42_SRC_BYPASS_DAC_SHIFT 1
56#define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT)
57
58#define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08)
59
60#define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09)
61#define CS42L42_INTERNAL_FS_SHIFT 1
62#define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT)
63
64#define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A)
65#define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E)
66#define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F)
67#define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10)
68
69/* Page 0x11 Power and Headset Detect Registers */
70#define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01)
71#define CS42L42_ASP_DAO_PDN_SHIFT 7
72#define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT)
73#define CS42L42_ASP_DAI_PDN_SHIFT 6
74#define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT)
75#define CS42L42_MIXER_PDN_SHIFT 5
76#define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT)
77#define CS42L42_EQ_PDN_SHIFT 4
78#define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT)
79#define CS42L42_HP_PDN_SHIFT 3
80#define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT)
81#define CS42L42_ADC_PDN_SHIFT 2
82#define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT)
83#define CS42L42_PDN_ALL_SHIFT 0
84#define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT)
85
86#define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02)
87#define CS42L42_ADC_SRC_PDNB_SHIFT 0
88#define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT)
89#define CS42L42_DAC_SRC_PDNB_SHIFT 1
90#define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT)
91#define CS42L42_ASP_DAI1_PDN_SHIFT 2
92#define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT)
93#define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3
94#define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT)
95#define CS42L42_DISCHARGE_FILT_SHIFT 4
96#define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT)
97
98#define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03)
99#define CS42L42_RING_SENSE_PDNB_SHIFT 1
100#define CS42L42_RING_SENSE_PDNB_MASK (1 << \
101 CS42L42_RING_SENSE_PDNB_SHIFT)
102#define CS42L42_VPMON_PDNB_SHIFT 2
103#define CS42L42_VPMON_PDNB_MASK (1 << \
104 CS42L42_VPMON_PDNB_SHIFT)
105#define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5
106#define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << \
107 CS42L42_SW_CLK_STP_STAT_SEL_SHIFT)
108
109#define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04)
110#define CS42L42_RS_TRIM_R_SHIFT 0
111#define CS42L42_RS_TRIM_R_MASK (1 << \
112 CS42L42_RS_TRIM_R_SHIFT)
113#define CS42L42_RS_TRIM_T_SHIFT 1
114#define CS42L42_RS_TRIM_T_MASK (1 << \
115 CS42L42_RS_TRIM_T_SHIFT)
116#define CS42L42_HPREF_RS_SHIFT 2
117#define CS42L42_HPREF_RS_MASK (1 << \
118 CS42L42_HPREF_RS_SHIFT)
119#define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3
120#define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << \
121 CS42L42_HSBIAS_FILT_REF_RS_SHIFT)
122#define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6
123#define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << \
124 CS42L42_RING_SENSE_PU_HIZ_SHIFT)
125
126#define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05)
127#define CS42L42_TS_RS_GATE_SHIFT 7
128#define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT)
129
130#define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07)
131#define CS42L42_SCLK_PRESENT_SHIFT 0
132#define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT)
133
134#define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09)
135#define CS42L42_OSC_SW_SEL_STAT_SHIFT 0
136#define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
137#define CS42L42_OSC_PDNB_STAT_SHIFT 2
138#define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
139
140#define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12)
141#define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0
142#define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << \
143 CS42L42_RS_RISE_DBNCE_TIME_SHIFT)
144#define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3
145#define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << \
146 CS42L42_RS_FALL_DBNCE_TIME_SHIFT)
147#define CS42L42_RS_PU_EN_SHIFT 6
148#define CS42L42_RS_PU_EN_MASK (1 << \
149 CS42L42_RS_PU_EN_SHIFT)
150#define CS42L42_RS_INV_SHIFT 7
151#define CS42L42_RS_INV_MASK (1 << \
152 CS42L42_RS_INV_SHIFT)
153
154#define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13)
155#define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0
156#define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << \
157 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)
158#define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3
159#define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << \
160 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)
161#define CS42L42_TS_INV_SHIFT 7
162#define CS42L42_TS_INV_MASK (1 << \
163 CS42L42_TS_INV_SHIFT)
164
165#define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14)
166#define CS42L42_D_RS_PLUG_DBNC_SHIFT 0
167#define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT)
168#define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1
169#define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT)
170#define CS42L42_D_TS_PLUG_DBNC_SHIFT 2
171#define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT)
172#define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3
173#define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT)
174
175#define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15)
176#define CS42L42_RS_PLUG_DBNC_SHIFT 0
177#define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT)
178#define CS42L42_RS_UNPLUG_DBNC_SHIFT 1
179#define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT)
180#define CS42L42_TS_PLUG_DBNC_SHIFT 2
181#define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT)
182#define CS42L42_TS_UNPLUG_DBNC_SHIFT 3
183#define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT)
184
185#define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F)
186#define CS42L42_HSDET_COMP1_LVL_SHIFT 0
187#define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT)
188#define CS42L42_HSDET_COMP2_LVL_SHIFT 4
189#define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT)
190
191#define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20)
192#define CS42L42_HSDET_AUTO_TIME_SHIFT 0
193#define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)
194#define CS42L42_HSBIAS_REF_SHIFT 3
195#define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT)
196#define CS42L42_HSDET_SET_SHIFT 4
197#define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT)
198#define CS42L42_HSDET_CTRL_SHIFT 6
199#define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT)
200
201#define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21)
202#define CS42L42_SW_GNDHS_HS4_SHIFT 0
203#define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT)
204#define CS42L42_SW_GNDHS_HS3_SHIFT 1
205#define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT)
206#define CS42L42_SW_HSB_HS4_SHIFT 2
207#define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT)
208#define CS42L42_SW_HSB_HS3_SHIFT 3
209#define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT)
210#define CS42L42_SW_HSB_FILT_HS4_SHIFT 4
211#define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT)
212#define CS42L42_SW_HSB_FILT_HS3_SHIFT 5
213#define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT)
214#define CS42L42_SW_REF_HS4_SHIFT 6
215#define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT)
216#define CS42L42_SW_REF_HS3_SHIFT 7
217#define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT)
218
219#define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24)
220#define CS42L42_HSDET_TYPE_SHIFT 0
221#define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT)
222#define CS42L42_HSDET_COMP1_OUT_SHIFT 6
223#define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT)
224#define CS42L42_HSDET_COMP2_OUT_SHIFT 7
225#define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT)
226#define CS42L42_PLUG_CTIA 0
227#define CS42L42_PLUG_OMTP 1
228#define CS42L42_PLUG_HEADPHONE 2
229#define CS42L42_PLUG_INVALID 3
230
231#define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29)
232#define CS42L42_HS_CLAMP_DISABLE_SHIFT 0
233#define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)
234
235/* Page 0x12 Clocking Registers */
236#define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01)
237#define CS42L42_MCLKDIV_SHIFT 1
238#define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT)
239#define CS42L42_MCLK_SRC_SEL_SHIFT 0
240#define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT)
241
242#define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02)
243#define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03)
244
245#define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04)
246#define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0
247#define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \
248 CS42L42_FSYNC_PULSE_WIDTH_SHIFT)
249
250#define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05)
251
252#define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06)
253#define CS42L42_FSYNC_PERIOD_SHIFT 0
254#define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
255
256#define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07)
257#define CS42L42_ASP_SCLK_EN_SHIFT 5
258#define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT)
259#define CS42L42_ASP_MASTER_MODE 0x01
260#define CS42L42_ASP_SLAVE_MODE 0x00
261#define CS42L42_ASP_MODE_SHIFT 4
262#define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT)
263#define CS42L42_ASP_SCPOL_SHIFT 2
264#define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT)
265#define CS42L42_ASP_SCPOL_NOR 3
266#define CS42L42_ASP_LCPOL_SHIFT 0
267#define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT)
268#define CS42L42_ASP_LCPOL_INV 3
269
270#define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08)
271#define CS42L42_ASP_STP_SHIFT 4
272#define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT)
273#define CS42L42_ASP_5050_SHIFT 3
274#define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT)
275#define CS42L42_ASP_FSD_SHIFT 0
276#define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT)
277#define CS42L42_ASP_FSD_0_5 1
278#define CS42L42_ASP_FSD_1_0 2
279#define CS42L42_ASP_FSD_1_5 3
280#define CS42L42_ASP_FSD_2_0 4
281
282#define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09)
283#define CS42L42_FS_EN_SHIFT 0
284#define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT)
285#define CS42L42_FS_EN_IASRC_96K 0x1
286#define CS42L42_FS_EN_OASRC_96K 0x2
287
288#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
289#define CS42L42_CLK_IASRC_SEL_SHIFT 0
290#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
291#define CS42L42_CLK_IASRC_SEL_12 1
292
293#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
294#define CS42L42_CLK_OASRC_SEL_SHIFT 0
295#define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT)
296#define CS42L42_CLK_OASRC_SEL_12 1
297
298#define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C)
299#define CS42L42_SCLK_PREDIV_SHIFT 0
300#define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT)
301
302/* Page 0x13 Interrupt Registers */
303/* Interrupts */
304#define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01)
305#define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02)
306#define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03)
307#define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04)
308#define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05)
309#define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08)
310#define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09)
311#define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A)
312#define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B)
313#define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D)
314#define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E)
315#define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F)
316/* Masks */
317#define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16)
318#define CS42L42_ADC_OVFL_SHIFT 0
319#define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT)
320#define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK
321
322#define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17)
323#define CS42L42_MIX_CHB_OVFL_SHIFT 0
324#define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT)
325#define CS42L42_MIX_CHA_OVFL_SHIFT 1
326#define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT)
327#define CS42L42_EQ_OVFL_SHIFT 2
328#define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT)
329#define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3
330#define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)
331#define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \
332 CS42L42_MIX_CHA_OVFL_MASK | \
333 CS42L42_EQ_OVFL_MASK | \
334 CS42L42_EQ_BIQUAD_OVFL_MASK)
335
336#define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18)
337#define CS42L42_SRC_ILK_SHIFT 0
338#define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT)
339#define CS42L42_SRC_OLK_SHIFT 1
340#define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT)
341#define CS42L42_SRC_IUNLK_SHIFT 2
342#define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT)
343#define CS42L42_SRC_OUNLK_SHIFT 3
344#define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT)
345#define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \
346 CS42L42_SRC_OLK_MASK | \
347 CS42L42_SRC_IUNLK_MASK | \
348 CS42L42_SRC_OUNLK_MASK)
349
350#define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19)
351#define CS42L42_ASPRX_NOLRCK_SHIFT 0
352#define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT)
353#define CS42L42_ASPRX_EARLY_SHIFT 1
354#define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT)
355#define CS42L42_ASPRX_LATE_SHIFT 2
356#define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT)
357#define CS42L42_ASPRX_ERROR_SHIFT 3
358#define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT)
359#define CS42L42_ASPRX_OVLD_SHIFT 4
360#define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT)
361#define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \
362 CS42L42_ASPRX_EARLY_MASK | \
363 CS42L42_ASPRX_LATE_MASK | \
364 CS42L42_ASPRX_ERROR_MASK | \
365 CS42L42_ASPRX_OVLD_MASK)
366
367#define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A)
368#define CS42L42_ASPTX_NOLRCK_SHIFT 0
369#define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT)
370#define CS42L42_ASPTX_EARLY_SHIFT 1
371#define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT)
372#define CS42L42_ASPTX_LATE_SHIFT 2
373#define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT)
374#define CS42L42_ASPTX_SMERROR_SHIFT 3
375#define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT)
376#define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \
377 CS42L42_ASPTX_EARLY_MASK | \
378 CS42L42_ASPTX_LATE_MASK | \
379 CS42L42_ASPTX_SMERROR_MASK)
380
381#define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B)
382#define CS42L42_PDN_DONE_SHIFT 0
383#define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT)
384#define CS42L42_HSDET_AUTO_DONE_SHIFT 1
385#define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)
386#define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \
387 CS42L42_HSDET_AUTO_DONE_MASK)
388
389#define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C)
390#define CS42L42_SRCPL_ADC_LK_SHIFT 0
391#define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT)
392#define CS42L42_SRCPL_DAC_LK_SHIFT 2
393#define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT)
394#define CS42L42_SRCPL_ADC_UNLK_SHIFT 5
395#define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT)
396#define CS42L42_SRCPL_DAC_UNLK_SHIFT 6
397#define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)
398#define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \
399 CS42L42_SRCPL_DAC_LK_MASK | \
400 CS42L42_SRCPL_ADC_UNLK_MASK | \
401 CS42L42_SRCPL_DAC_UNLK_MASK)
402
403#define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E)
404#define CS42L42_VPMON_SHIFT 0
405#define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT)
406#define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK
407
408#define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F)
409#define CS42L42_PLL_LOCK_SHIFT 0
410#define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT)
411#define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK
412
413#define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20)
414#define CS42L42_RS_PLUG_SHIFT 0
415#define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT)
416#define CS42L42_RS_UNPLUG_SHIFT 1
417#define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT)
418#define CS42L42_TS_PLUG_SHIFT 2
419#define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT)
420#define CS42L42_TS_UNPLUG_SHIFT 3
421#define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT)
422#define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \
423 CS42L42_RS_UNPLUG_MASK | \
424 CS42L42_TS_PLUG_MASK | \
425 CS42L42_TS_UNPLUG_MASK)
426#define CS42L42_TS_PLUG 3
427#define CS42L42_TS_UNPLUG 0
428#define CS42L42_TS_TRANS 1
429
430/* Page 0x15 Fractional-N PLL Registers */
431#define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01)
432#define CS42L42_PLL_START_SHIFT 0
433#define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT)
434
435#define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02)
436#define CS42L42_PLL_DIV_FRAC_SHIFT 0
437#define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
438
439#define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03)
440#define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04)
441
442#define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05)
443#define CS42L42_PLL_DIV_INT_SHIFT 0
444#define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT)
445
446#define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08)
447#define CS42L42_PLL_DIVOUT_SHIFT 0
448#define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT)
449
450#define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A)
451#define CS42L42_PLL_CAL_RATIO_SHIFT 0
452#define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
453
454#define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B)
455#define CS42L42_PLL_MODE_SHIFT 0
456#define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT)
457
458/* Page 0x19 HP Load Detect Registers */
459#define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25)
460#define CS42L42_RLA_STAT_SHIFT 0
461#define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT)
462#define CS42L42_RLA_STAT_15_OHM 0
463
464#define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26)
465#define CS42L42_HPLOAD_DET_DONE_SHIFT 0
466#define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT)
467
468#define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27)
469#define CS42L42_HP_LD_EN_SHIFT 0
470#define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT)
471
472/* Page 0x1B Headset Interface Registers */
473#define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70)
474#define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0
475#define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << \
476 CS42L42_HSBIAS_SENSE_TRIP_SHIFT)
477#define CS42L42_TIP_SENSE_EN_SHIFT 5
478#define CS42L42_TIP_SENSE_EN_MASK (1 << \
479 CS42L42_TIP_SENSE_EN_SHIFT)
480#define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6
481#define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << \
482 CS42L42_AUTO_HSBIAS_HIZ_SHIFT)
483#define CS42L42_HSBIAS_SENSE_EN_SHIFT 7
484#define CS42L42_HSBIAS_SENSE_EN_MASK (1 << \
485 CS42L42_HSBIAS_SENSE_EN_SHIFT)
486
487#define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71)
488#define CS42L42_WAKEB_CLEAR_SHIFT 0
489#define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT)
490#define CS42L42_WAKEB_MODE_SHIFT 5
491#define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT)
492#define CS42L42_M_HP_WAKE_SHIFT 6
493#define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT)
494#define CS42L42_M_MIC_WAKE_SHIFT 7
495#define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT)
496
497#define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72)
498#define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7
499#define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << \
500 CS42L42_ADC_DISABLE_S0_MUTE_SHIFT)
501
502#define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73)
503#define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0
504#define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << \
505 CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)
506#define CS42L42_TIP_SENSE_INV_SHIFT 5
507#define CS42L42_TIP_SENSE_INV_MASK (1 << \
508 CS42L42_TIP_SENSE_INV_SHIFT)
509#define CS42L42_TIP_SENSE_CTRL_SHIFT 6
510#define CS42L42_TIP_SENSE_CTRL_MASK (3 << \
511 CS42L42_TIP_SENSE_CTRL_SHIFT)
512
513#define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74)
514#define CS42L42_PDN_MIC_LVL_DET_SHIFT 0
515#define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)
516#define CS42L42_HSBIAS_CTL_SHIFT 1
517#define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT)
518#define CS42L42_DETECT_MODE_SHIFT 3
519#define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT)
520
521#define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75)
522#define CS42L42_HS_DET_LEVEL_SHIFT 0
523#define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
524#define CS42L42_EVENT_STAT_SEL_SHIFT 6
525#define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT)
526#define CS42L42_LATCH_TO_VP_SHIFT 7
527#define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT)
528
529#define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76)
530#define CS42L42_DEBOUNCE_TIME_SHIFT 5
531#define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
532
533#define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77)
534#define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6
535#define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT)
536#define CS42L42_TIP_SENSE_SHIFT 7
537#define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT)
538
539#define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78)
540#define CS42L42_SHORT_TRUE_SHIFT 0
541#define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT)
542#define CS42L42_HS_TRUE_SHIFT 1
543#define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT)
544
545#define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79)
546#define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5
547#define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT)
548#define CS42L42_TIP_SENSE_PLUG_SHIFT 6
549#define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT)
550#define CS42L42_HSBIAS_SENSE_SHIFT 7
551#define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT)
552#define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \
553 CS42L42_TIP_SENSE_PLUG_MASK | \
554 CS42L42_HSBIAS_SENSE_MASK)
555
556#define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A)
557#define CS42L42_M_SHORT_DET_SHIFT 0
558#define CS42L42_M_SHORT_DET_MASK (1 << \
559 CS42L42_M_SHORT_DET_SHIFT)
560#define CS42L42_M_SHORT_RLS_SHIFT 1
561#define CS42L42_M_SHORT_RLS_MASK (1 << \
562 CS42L42_M_SHORT_RLS_SHIFT)
563#define CS42L42_M_HSBIAS_HIZ_SHIFT 2
564#define CS42L42_M_HSBIAS_HIZ_MASK (1 << \
565 CS42L42_M_HSBIAS_HIZ_SHIFT)
566#define CS42L42_M_DETECT_FT_SHIFT 6
567#define CS42L42_M_DETECT_FT_MASK (1 << \
568 CS42L42_M_DETECT_FT_SHIFT)
569#define CS42L42_M_DETECT_TF_SHIFT 7
570#define CS42L42_M_DETECT_TF_MASK (1 << \
571 CS42L42_M_DETECT_TF_SHIFT)
572#define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \
573 CS42L42_M_SHORT_RLS_MASK | \
574 CS42L42_M_HSBIAS_HIZ_MASK | \
575 CS42L42_M_DETECT_FT_MASK | \
576 CS42L42_M_DETECT_TF_MASK)
577
578/* Page 0x1C Headset Bias Registers */
579#define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03)
580#define CS42L42_HSBIAS_RAMP_SHIFT 0
581#define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT)
582#define CS42L42_HSBIAS_PD_SHIFT 4
583#define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT)
584#define CS42L42_HSBIAS_CAPLESS_SHIFT 7
585#define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT)
586
587/* Page 0x1D ADC Registers */
588#define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01)
589#define CS42L42_ADC_NOTCH_DIS_SHIFT 5
590#define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4
591#define CS42L42_ADC_INV_SHIFT 2
592#define CS42L42_ADC_DIG_BOOST_SHIFT 0
593
594#define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03)
595#define CS42L42_ADC_VOL_SHIFT 0
596
597#define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04)
598#define CS42L42_ADC_WNF_CF_SHIFT 4
599#define CS42L42_ADC_WNF_EN_SHIFT 3
600#define CS42L42_ADC_HPF_CF_SHIFT 1
601#define CS42L42_ADC_HPF_EN_SHIFT 0
602
603/* Page 0x1F DAC Registers */
604#define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01)
605#define CS42L42_DACB_INV_SHIFT 1
606#define CS42L42_DACA_INV_SHIFT 0
607
608#define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06)
609#define CS42L42_HPOUT_PULLDOWN_SHIFT 4
610#define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT)
611#define CS42L42_HPOUT_LOAD_SHIFT 3
612#define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT)
613#define CS42L42_HPOUT_CLAMP_SHIFT 2
614#define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT)
615#define CS42L42_DAC_HPF_EN_SHIFT 1
616#define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT)
617#define CS42L42_DAC_MON_EN_SHIFT 0
618#define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT)
619
620/* Page 0x20 HP CTL Registers */
621#define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01)
622#define CS42L42_HP_ANA_BMUTE_SHIFT 3
623#define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT)
624#define CS42L42_HP_ANA_AMUTE_SHIFT 2
625#define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT)
626#define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1
627#define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT)
628
629/* Page 0x21 Class H Registers */
630#define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01)
631
632/* Page 0x23 Mixer Volume Registers */
633#define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01)
634#define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02)
635
636#define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03)
637#define CS42L42_MIXER_CH_VOL_SHIFT 0
638#define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
639
640/* Page 0x24 EQ Registers */
641#define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01)
642#define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02)
643#define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03)
644#define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04)
645#define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06)
646#define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07)
647#define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08)
648#define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09)
649#define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A)
650#define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B)
651#define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C)
652#define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E)
653
654/* Page 0x25 Audio Port Registers */
655#define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01)
656#define CS42L42_SP_RX_CHB_SEL_SHIFT 2
657#define CS42L42_SP_RX_CHB_SEL_MASK (3 << CS42L42_SP_RX_CHB_SEL_SHIFT)
658
659#define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02)
660#define CS42L42_SP_RX_RSYNC_SHIFT 6
661#define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT)
662#define CS42L42_SP_RX_NSB_POS_SHIFT 3
663#define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT)
664#define CS42L42_SP_RX_NFS_NSBB_SHIFT 2
665#define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT)
666#define CS42L42_SP_RX_ISOC_MODE_SHIFT 0
667#define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT)
668
669#define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03)
670#define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04)
671#define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05)
672#define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06)
673#define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07)
674
675/* Page 0x26 SRC Registers */
676#define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01)
677#define CS42L42_SRC_SDIN_FS_SHIFT 0
678#define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
679
680#define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
681
682/* Page 0x28 S/PDIF Registers */
683#define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
684#define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
685#define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03)
686#define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04)
687
688/* Page 0x29 Serial Port TX Registers */
689#define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01)
690#define CS42L42_ASP_TX_EN_SHIFT 0
691#define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02)
692#define CS42L42_ASP_TX0_CH2_SHIFT 1
693#define CS42L42_ASP_TX0_CH1_SHIFT 0
694
695#define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03)
696#define CS42L42_ASP_TX_CH1_AP_SHIFT 7
697#define CS42L42_ASP_TX_CH1_AP_MASK (1 << CS42L42_ASP_TX_CH1_AP_SHIFT)
698#define CS42L42_ASP_TX_CH2_AP_SHIFT 6
699#define CS42L42_ASP_TX_CH2_AP_MASK (1 << CS42L42_ASP_TX_CH2_AP_SHIFT)
700#define CS42L42_ASP_TX_CH2_RES_SHIFT 2
701#define CS42L42_ASP_TX_CH2_RES_MASK (3 << CS42L42_ASP_TX_CH2_RES_SHIFT)
702#define CS42L42_ASP_TX_CH1_RES_SHIFT 0
703#define CS42L42_ASP_TX_CH1_RES_MASK (3 << CS42L42_ASP_TX_CH1_RES_SHIFT)
704#define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04)
705#define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05)
706#define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06)
707#define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A)
708#define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B)
709
710/* Page 0x2A Serial Port RX Registers */
711#define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01)
712#define CS42L42_ASP_RX0_CH_EN_SHIFT 2
713#define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
714#define CS42L42_ASP_RX0_CH1_SHIFT 2
715#define CS42L42_ASP_RX0_CH2_SHIFT 3
716#define CS42L42_ASP_RX0_CH3_SHIFT 4
717#define CS42L42_ASP_RX0_CH4_SHIFT 5
718
719#define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02)
720#define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
721#define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
722#define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05)
723#define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
724#define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
725#define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08)
726#define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
727#define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
728#define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B)
729#define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
730#define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
731#define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E)
732#define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
733#define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
734#define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11)
735#define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
736#define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
737
738#define CS42L42_ASP_RX_CH_AP_SHIFT 6
739#define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT)
740#define CS42L42_ASP_RX_CH_AP_LOW 0
741#define CS42L42_ASP_RX_CH_AP_HI 1
742#define CS42L42_ASP_RX_CH_RES_SHIFT 0
743#define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT)
744#define CS42L42_ASP_RX_CH_RES_32 3
745#define CS42L42_ASP_RX_CH_RES_16 1
746#define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0
747#define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
748
749/* Page 0x30 ID Registers */
750#define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14)
751#define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14)
752
753/* Defines for fracturing values spread across multiple registers */
754#define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff)
755#define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8)
756#define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16)
757
758#define CS42L42_NUM_SUPPLIES 5
759#define CS42L42_BOOT_TIME_US 3000
760#define CS42L42_PLL_DIVOUT_TIME_US 800
761#define CS42L42_CLOCK_SWITCH_DELAY_US 150
762#define CS42L42_PLL_LOCK_POLL_US 250
763#define CS42L42_PLL_LOCK_TIMEOUT_US 1250
764
765static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
766 "VA",
767 "VP",
768 "VCP",
769 "VD_FILT",
770 "VL",
771};
772
773struct cs42l42_private {
774 struct regmap *regmap;
775 struct snd_soc_component *component;
776 struct regulator_bulk_data supplies[CS42L42_NUM_SUPPLIES];
777 struct gpio_desc *reset_gpio;
778 struct completion pdn_done;
779 struct snd_soc_jack *jack;
780 int pll_config;
781 int bclk;
782 u32 sclk;
783 u32 srate;
784 u8 pll_divout;
785 u8 plug_state;
786 u8 hs_type;
787 u8 ts_inv;
788 u8 ts_dbnc_rise;
789 u8 ts_dbnc_fall;
790 u8 btn_det_init_dbnce;
791 u8 btn_det_event_dbnce;
792 u8 bias_thresholds[CS42L42_NUM_BIASES];
793 u8 hs_bias_ramp_rate;
794 u8 hs_bias_ramp_time;
795 u8 hs_bias_sense_en;
796 u8 stream_use;
797};
798
799#endif /* __CS42L42_H__ */