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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_H_
5#define _IGC_H_
6
7#include <linux/kobject.h>
8#include <linux/pci.h>
9#include <linux/netdevice.h>
10#include <linux/vmalloc.h>
11#include <linux/ethtool.h>
12#include <linux/sctp.h>
13#include <linux/ptp_clock_kernel.h>
14#include <linux/timecounter.h>
15#include <linux/net_tstamp.h>
16#include <linux/bitfield.h>
17#include <linux/hrtimer.h>
18#include <net/xdp.h>
19
20#include "igc_hw.h"
21
22void igc_ethtool_set_ops(struct net_device *);
23
24/* Transmit and receive queues */
25#define IGC_MAX_RX_QUEUES 4
26#define IGC_MAX_TX_QUEUES 4
27
28#define MAX_Q_VECTORS 8
29#define MAX_STD_JUMBO_FRAME_SIZE 9216
30
31#define MAX_ETYPE_FILTER 8
32#define IGC_RETA_SIZE 128
33
34/* SDP support */
35#define IGC_N_EXTTS 2
36#define IGC_N_PEROUT 2
37#define IGC_N_SDP 4
38
39#define MAX_FLEX_FILTER 32
40
41#define IGC_MAX_TX_TSTAMP_REGS 4
42
43enum igc_mac_filter_type {
44 IGC_MAC_FILTER_TYPE_DST = 0,
45 IGC_MAC_FILTER_TYPE_SRC
46};
47
48struct igc_tx_queue_stats {
49 u64 packets;
50 u64 bytes;
51 u64 restart_queue;
52 u64 restart_queue2;
53};
54
55struct igc_rx_queue_stats {
56 u64 packets;
57 u64 bytes;
58 u64 drops;
59 u64 csum_err;
60 u64 alloc_failed;
61};
62
63struct igc_rx_packet_stats {
64 u64 ipv4_packets; /* IPv4 headers processed */
65 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
66 u64 ipv6_packets; /* IPv6 headers processed */
67 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
68 u64 tcp_packets; /* TCP headers processed */
69 u64 udp_packets; /* UDP headers processed */
70 u64 sctp_packets; /* SCTP headers processed */
71 u64 nfs_packets; /* NFS headers processe */
72 u64 other_packets;
73};
74
75enum igc_tx_buffer_type {
76 IGC_TX_BUFFER_TYPE_SKB,
77 IGC_TX_BUFFER_TYPE_XDP,
78 IGC_TX_BUFFER_TYPE_XSK,
79};
80
81/* wrapper around a pointer to a socket buffer,
82 * so a DMA handle can be stored along with the buffer
83 */
84struct igc_tx_buffer {
85 union igc_adv_tx_desc *next_to_watch;
86 unsigned long time_stamp;
87 enum igc_tx_buffer_type type;
88 union {
89 struct sk_buff *skb;
90 struct xdp_frame *xdpf;
91 };
92 unsigned int bytecount;
93 u16 gso_segs;
94 __be16 protocol;
95
96 DEFINE_DMA_UNMAP_ADDR(dma);
97 DEFINE_DMA_UNMAP_LEN(len);
98 u32 tx_flags;
99 bool xsk_pending_ts;
100};
101
102struct igc_tx_timestamp_request {
103 union { /* reference to the packet being timestamped */
104 struct sk_buff *skb;
105 struct igc_tx_buffer *xsk_tx_buffer;
106 };
107 enum igc_tx_buffer_type buffer_type;
108 unsigned long start; /* when the tstamp request started (jiffies) */
109 u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */
110 u32 regl; /* which TXSTMPL_{X} register should be used */
111 u32 regh; /* which TXSTMPH_{X} register should be used */
112 u32 flags; /* flags that should be added to the tx_buffer */
113 u8 xsk_queue_index; /* Tx queue which requesting timestamp */
114 struct xsk_tx_metadata_compl xsk_meta; /* ref to xsk Tx metadata */
115};
116
117struct igc_inline_rx_tstamps {
118 /* Timestamps are saved in little endian at the beginning of the packet
119 * buffer following the layout:
120 *
121 * DWORD: | 0 | 1 | 2 | 3 |
122 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
123 *
124 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
125 * part of the timestamp.
126 *
127 */
128 __le32 timer1[2];
129 __le32 timer0[2];
130};
131
132struct igc_ring_container {
133 struct igc_ring *ring; /* pointer to linked list of rings */
134 unsigned int total_bytes; /* total bytes processed this int */
135 unsigned int total_packets; /* total packets processed this int */
136 u16 work_limit; /* total work allowed per interrupt */
137 u8 count; /* total number of rings in vector */
138 u8 itr; /* current ITR setting for ring */
139};
140
141struct igc_ring {
142 struct igc_q_vector *q_vector; /* backlink to q_vector */
143 struct net_device *netdev; /* back pointer to net_device */
144 struct device *dev; /* device for dma mapping */
145 union { /* array of buffer info structs */
146 struct igc_tx_buffer *tx_buffer_info;
147 struct igc_rx_buffer *rx_buffer_info;
148 };
149 void *desc; /* descriptor ring memory */
150 unsigned long flags; /* ring specific flags */
151 void __iomem *tail; /* pointer to ring tail register */
152 dma_addr_t dma; /* phys address of the ring */
153 unsigned int size; /* length of desc. ring in bytes */
154
155 u16 count; /* number of desc. in the ring */
156 u8 queue_index; /* logical index of the ring*/
157 u8 reg_idx; /* physical index of the ring */
158 bool launchtime_enable; /* true if LaunchTime is enabled */
159 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
160 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
161
162 u32 start_time;
163 u32 end_time;
164 u32 max_sdu;
165 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */
166 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */
167
168 /* CBS parameters */
169 bool cbs_enable; /* indicates if CBS is enabled */
170 s32 idleslope; /* idleSlope in kbps */
171 s32 sendslope; /* sendSlope in kbps */
172 s32 hicredit; /* hiCredit in bytes */
173 s32 locredit; /* loCredit in bytes */
174
175 /* everything past this point are written often */
176 u16 next_to_clean;
177 u16 next_to_use;
178 u16 next_to_alloc;
179
180 union {
181 /* TX */
182 struct {
183 struct igc_tx_queue_stats tx_stats;
184 struct u64_stats_sync tx_syncp;
185 struct u64_stats_sync tx_syncp2;
186 };
187 /* RX */
188 struct {
189 struct igc_rx_queue_stats rx_stats;
190 struct igc_rx_packet_stats pkt_stats;
191 struct u64_stats_sync rx_syncp;
192 struct sk_buff *skb;
193 };
194 };
195
196 struct xdp_rxq_info xdp_rxq;
197 struct xsk_buff_pool *xsk_pool;
198} ____cacheline_internodealigned_in_smp;
199
200/* Board specific private data structure */
201struct igc_adapter {
202 struct net_device *netdev;
203
204 struct ethtool_keee eee;
205
206 unsigned long state;
207 unsigned int flags;
208 unsigned int num_q_vectors;
209
210 struct msix_entry *msix_entries;
211
212 /* TX */
213 u16 tx_work_limit;
214 u32 tx_timeout_count;
215 int num_tx_queues;
216 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
217
218 /* RX */
219 int num_rx_queues;
220 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
221
222 struct timer_list watchdog_timer;
223 struct timer_list dma_err_timer;
224 struct timer_list phy_info_timer;
225 struct hrtimer hrtimer;
226
227 u32 wol;
228 u32 en_mng_pt;
229 u16 link_speed;
230 u16 link_duplex;
231
232 u8 port_num;
233
234 u8 __iomem *io_addr;
235 /* Interrupt Throttle Rate */
236 u32 rx_itr_setting;
237 u32 tx_itr_setting;
238
239 struct work_struct reset_task;
240 struct work_struct watchdog_task;
241 struct work_struct dma_err_task;
242 bool fc_autoneg;
243
244 u8 tx_timeout_factor;
245
246 int msg_enable;
247 u32 max_frame_size;
248 u32 min_frame_size;
249
250 int tc_setup_type;
251 ktime_t base_time;
252 ktime_t cycle_time;
253 bool taprio_offload_enable;
254 u32 qbv_config_change_errors;
255 bool qbv_transition;
256 unsigned int qbv_count;
257 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition
258 * are protected by the qbv_tx_lock.
259 */
260 spinlock_t qbv_tx_lock;
261
262 bool strict_priority_enable;
263 u8 num_tc;
264 u16 queue_per_tc[IGC_MAX_TX_QUEUES];
265
266 /* OS defined structs */
267 struct pci_dev *pdev;
268 /* lock for statistics */
269 spinlock_t stats64_lock;
270 struct rtnl_link_stats64 stats64;
271
272 /* structs defined in igc_hw.h */
273 struct igc_hw hw;
274 struct igc_hw_stats stats;
275
276 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
277 u32 eims_enable_mask;
278 u32 eims_other;
279
280 u16 tx_ring_count;
281 u16 rx_ring_count;
282
283 u32 tx_hwtstamp_timeouts;
284 u32 tx_hwtstamp_skipped;
285 u32 rx_hwtstamp_cleared;
286
287 u32 rss_queues;
288 u32 rss_indir_tbl_init;
289
290 /* Any access to elements in nfc_rule_list is protected by the
291 * nfc_rule_lock.
292 */
293 struct mutex nfc_rule_lock;
294 struct list_head nfc_rule_list;
295 unsigned int nfc_rule_count;
296
297 u8 rss_indir_tbl[IGC_RETA_SIZE];
298
299 unsigned long link_check_timeout;
300 struct igc_info ei;
301
302 u32 test_icr;
303
304 struct ptp_clock *ptp_clock;
305 struct ptp_clock_info ptp_caps;
306 /* Access to ptp_tx_skb and ptp_tx_start are protected by the
307 * ptp_tx_lock.
308 */
309 spinlock_t ptp_tx_lock;
310 struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS];
311 struct hwtstamp_config tstamp_config;
312 unsigned int ptp_flags;
313 /* System time value lock */
314 spinlock_t tmreg_lock;
315 /* Free-running timer lock */
316 spinlock_t free_timer_lock;
317 struct cyclecounter cc;
318 struct timecounter tc;
319 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
320 ktime_t ptp_reset_start; /* Reset time in clock mono */
321 struct system_time_snapshot snapshot;
322
323 char fw_version[32];
324
325 struct bpf_prog *xdp_prog;
326
327 bool pps_sys_wrap_on;
328
329 struct ptp_pin_desc sdp_config[IGC_N_SDP];
330 struct {
331 struct timespec64 start;
332 struct timespec64 period;
333 } perout[IGC_N_PEROUT];
334
335 /* LEDs */
336 struct mutex led_mutex;
337 struct igc_led_classdev *leds;
338};
339
340void igc_up(struct igc_adapter *adapter);
341void igc_down(struct igc_adapter *adapter);
342int igc_open(struct net_device *netdev);
343int igc_close(struct net_device *netdev);
344int igc_setup_tx_resources(struct igc_ring *ring);
345int igc_setup_rx_resources(struct igc_ring *ring);
346void igc_free_tx_resources(struct igc_ring *ring);
347void igc_free_rx_resources(struct igc_ring *ring);
348unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
349void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
350 const u32 max_rss_queues);
351int igc_reinit_queues(struct igc_adapter *adapter);
352void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
353bool igc_has_link(struct igc_adapter *adapter);
354void igc_reset(struct igc_adapter *adapter);
355void igc_update_stats(struct igc_adapter *adapter);
356void igc_disable_rx_ring(struct igc_ring *ring);
357void igc_enable_rx_ring(struct igc_ring *ring);
358void igc_disable_tx_ring(struct igc_ring *ring);
359void igc_enable_tx_ring(struct igc_ring *ring);
360int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
361
362/* AF_XDP TX metadata operations */
363extern const struct xsk_tx_metadata_ops igc_xsk_tx_metadata_ops;
364
365/* igc_dump declarations */
366void igc_rings_dump(struct igc_adapter *adapter);
367void igc_regs_dump(struct igc_adapter *adapter);
368
369extern char igc_driver_name[];
370
371#define IGC_REGS_LEN 740
372
373/* flags controlling PTP/1588 function */
374#define IGC_PTP_ENABLED BIT(0)
375
376/* Flags definitions */
377#define IGC_FLAG_HAS_MSI BIT(0)
378#define IGC_FLAG_QUEUE_PAIRS BIT(3)
379#define IGC_FLAG_DMAC BIT(4)
380#define IGC_FLAG_PTP BIT(8)
381#define IGC_FLAG_WOL_SUPPORTED BIT(8)
382#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
383#define IGC_FLAG_HAS_MSIX BIT(13)
384#define IGC_FLAG_EEE BIT(14)
385#define IGC_FLAG_VLAN_PROMISC BIT(15)
386#define IGC_FLAG_RX_LEGACY BIT(16)
387#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
388#define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
389#define IGC_FLAG_TSN_LEGACY_ENABLED BIT(19)
390
391#define IGC_FLAG_TSN_ANY_ENABLED \
392 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED | \
393 IGC_FLAG_TSN_LEGACY_ENABLED)
394
395#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
396#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
397
398#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
399#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
400#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
401
402/* RX-desc Write-Back format RSS Type's */
403enum igc_rss_type_num {
404 IGC_RSS_TYPE_NO_HASH = 0,
405 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,
406 IGC_RSS_TYPE_HASH_IPV4 = 2,
407 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,
408 IGC_RSS_TYPE_HASH_IPV6_EX = 4,
409 IGC_RSS_TYPE_HASH_IPV6 = 5,
410 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,
411 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,
412 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,
413 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,
414 IGC_RSS_TYPE_MAX = 10,
415};
416#define IGC_RSS_TYPE_MAX_TABLE 16
417#define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
418
419/* igc_rss_type - Rx descriptor RSS type field */
420static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
421{
422 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
423 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
424 * is slightly slower than via u32 (wb.lower.lo_dword.data)
425 */
426 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
427}
428
429/* Interrupt defines */
430#define IGC_START_ITR 648 /* ~6000 ints/sec */
431#define IGC_4K_ITR 980
432#define IGC_20K_ITR 196
433#define IGC_70K_ITR 56
434
435#define IGC_DEFAULT_ITR 3 /* dynamic */
436#define IGC_MAX_ITR_USECS 10000
437#define IGC_MIN_ITR_USECS 10
438#define NON_Q_VECTORS 1
439#define MAX_MSIX_ENTRIES 10
440
441/* TX/RX descriptor defines */
442#define IGC_DEFAULT_TXD 256
443#define IGC_DEFAULT_TX_WORK 128
444#define IGC_MIN_TXD 64
445#define IGC_MAX_TXD 4096
446
447#define IGC_DEFAULT_RXD 256
448#define IGC_MIN_RXD 64
449#define IGC_MAX_RXD 4096
450
451/* Supported Rx Buffer Sizes */
452#define IGC_RXBUFFER_256 256
453#define IGC_RXBUFFER_2048 2048
454#define IGC_RXBUFFER_3072 3072
455
456#define AUTO_ALL_MODES 0
457#define IGC_RX_HDR_LEN IGC_RXBUFFER_256
458
459/* Transmit and receive latency (for PTP timestamps) */
460#define IGC_I225_TX_LATENCY_10 240
461#define IGC_I225_TX_LATENCY_100 58
462#define IGC_I225_TX_LATENCY_1000 80
463#define IGC_I225_TX_LATENCY_2500 1325
464#define IGC_I225_RX_LATENCY_10 6450
465#define IGC_I225_RX_LATENCY_100 185
466#define IGC_I225_RX_LATENCY_1000 300
467#define IGC_I225_RX_LATENCY_2500 1485
468
469/* RX and TX descriptor control thresholds.
470 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
471 * descriptors available in its onboard memory.
472 * Setting this to 0 disables RX descriptor prefetch.
473 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
474 * available in host memory.
475 * If PTHRESH is 0, this should also be 0.
476 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
477 * descriptors until either it has this many to write back, or the
478 * ITR timer expires.
479 */
480#define IGC_RX_PTHRESH 8
481#define IGC_RX_HTHRESH 8
482#define IGC_TX_PTHRESH 8
483#define IGC_TX_HTHRESH 1
484#define IGC_RX_WTHRESH 4
485#define IGC_TX_WTHRESH 16
486
487#define IGC_RX_DMA_ATTR \
488 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
489
490#define IGC_TS_HDR_LEN 16
491
492#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
493
494#if (PAGE_SIZE < 8192)
495#define IGC_MAX_FRAME_BUILD_SKB \
496 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
497#else
498#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
499#endif
500
501/* How many Rx Buffers do we bundle into one write to the hardware ? */
502#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
503
504/* VLAN info */
505#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
506#define IGC_TX_FLAGS_VLAN_SHIFT 16
507
508/* igc_test_staterr - tests bits within Rx descriptor status and error fields */
509static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
510 const u32 stat_err_bits)
511{
512 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
513}
514
515enum igc_state_t {
516 __IGC_TESTING,
517 __IGC_RESETTING,
518 __IGC_DOWN,
519};
520
521enum igc_tx_flags {
522 /* cmd_type flags */
523 IGC_TX_FLAGS_VLAN = 0x01,
524 IGC_TX_FLAGS_TSO = 0x02,
525 IGC_TX_FLAGS_TSTAMP = 0x04,
526
527 /* olinfo flags */
528 IGC_TX_FLAGS_IPV4 = 0x10,
529 IGC_TX_FLAGS_CSUM = 0x20,
530
531 IGC_TX_FLAGS_TSTAMP_1 = 0x100,
532 IGC_TX_FLAGS_TSTAMP_2 = 0x200,
533 IGC_TX_FLAGS_TSTAMP_3 = 0x400,
534
535 IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800,
536};
537
538enum igc_boards {
539 board_base,
540};
541
542/* The largest size we can write to the descriptor is 65535. In order to
543 * maintain a power of two alignment we have to limit ourselves to 32K.
544 */
545#define IGC_MAX_TXD_PWR 15
546#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
547
548/* Tx Descriptors needed, worst case */
549#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
550#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
551
552struct igc_rx_buffer {
553 union {
554 struct {
555 dma_addr_t dma;
556 struct page *page;
557#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
558 __u32 page_offset;
559#else
560 __u16 page_offset;
561#endif
562 __u16 pagecnt_bias;
563 };
564 struct xdp_buff *xdp;
565 };
566};
567
568/* context wrapper around xdp_buff to provide access to descriptor metadata */
569struct igc_xdp_buff {
570 struct xdp_buff xdp;
571 union igc_adv_rx_desc *rx_desc;
572 struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */
573};
574
575struct igc_metadata_request {
576 struct igc_tx_buffer *tx_buffer;
577 struct xsk_tx_metadata *meta;
578 struct igc_ring *tx_ring;
579 u32 cmd_type;
580};
581
582struct igc_q_vector {
583 struct igc_adapter *adapter; /* backlink */
584 void __iomem *itr_register;
585 u32 eims_value; /* EIMS mask value */
586
587 u16 itr_val;
588 u8 set_itr;
589
590 struct igc_ring_container rx, tx;
591
592 struct napi_struct napi;
593
594 struct rcu_head rcu; /* to avoid race with update stats on free */
595 char name[IFNAMSIZ + 9];
596
597 /* for dynamic allocation of rings associated with this q_vector */
598 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
599};
600
601enum igc_filter_match_flags {
602 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
603 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
604 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
605 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
606 IGC_FILTER_FLAG_USER_DATA = BIT(4),
607 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
608};
609
610struct igc_nfc_filter {
611 u8 match_flags;
612 u16 etype;
613 u16 vlan_etype;
614 u16 vlan_tci;
615 u16 vlan_tci_mask;
616 u8 src_addr[ETH_ALEN];
617 u8 dst_addr[ETH_ALEN];
618 u8 user_data[8];
619 u8 user_mask[8];
620 u8 flex_index;
621 u8 rx_queue;
622 u8 prio;
623 u8 immediate_irq;
624 u8 drop;
625};
626
627struct igc_nfc_rule {
628 struct list_head list;
629 struct igc_nfc_filter filter;
630 u32 location;
631 u16 action;
632 bool flex;
633};
634
635/* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
636 * based, 8 ethertype based and 32 Flex filter based rules.
637 */
638#define IGC_MAX_RXNFC_RULES 64
639
640struct igc_flex_filter {
641 u8 index;
642 u8 data[128];
643 u8 mask[16];
644 u8 length;
645 u8 rx_queue;
646 u8 prio;
647 u8 immediate_irq;
648 u8 drop;
649};
650
651/* igc_desc_unused - calculate if we have unused descriptors */
652static inline u16 igc_desc_unused(const struct igc_ring *ring)
653{
654 u16 ntc = ring->next_to_clean;
655 u16 ntu = ring->next_to_use;
656
657 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
658}
659
660static inline s32 igc_get_phy_info(struct igc_hw *hw)
661{
662 if (hw->phy.ops.get_phy_info)
663 return hw->phy.ops.get_phy_info(hw);
664
665 return 0;
666}
667
668static inline s32 igc_reset_phy(struct igc_hw *hw)
669{
670 if (hw->phy.ops.reset)
671 return hw->phy.ops.reset(hw);
672
673 return 0;
674}
675
676static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
677{
678 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
679}
680
681enum igc_ring_flags_t {
682 IGC_RING_FLAG_RX_3K_BUFFER,
683 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
684 IGC_RING_FLAG_RX_SCTP_CSUM,
685 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
686 IGC_RING_FLAG_TX_CTX_IDX,
687 IGC_RING_FLAG_TX_DETECT_HANG,
688 IGC_RING_FLAG_AF_XDP_ZC,
689 IGC_RING_FLAG_TX_HWTSTAMP,
690 IGC_RING_FLAG_RX_ALLOC_FAILED,
691};
692
693#define ring_uses_large_buffer(ring) \
694 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
695#define set_ring_uses_large_buffer(ring) \
696 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
697#define clear_ring_uses_large_buffer(ring) \
698 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
699
700#define ring_uses_build_skb(ring) \
701 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
702
703static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
704{
705#if (PAGE_SIZE < 8192)
706 if (ring_uses_large_buffer(ring))
707 return IGC_RXBUFFER_3072;
708
709 if (ring_uses_build_skb(ring))
710 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
711#endif
712 return IGC_RXBUFFER_2048;
713}
714
715static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
716{
717#if (PAGE_SIZE < 8192)
718 if (ring_uses_large_buffer(ring))
719 return 1;
720#endif
721 return 0;
722}
723
724static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
725{
726 if (hw->phy.ops.read_reg)
727 return hw->phy.ops.read_reg(hw, offset, data);
728
729 return -EOPNOTSUPP;
730}
731
732void igc_reinit_locked(struct igc_adapter *);
733struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
734 u32 location);
735int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
736void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
737
738void igc_ptp_init(struct igc_adapter *adapter);
739void igc_ptp_reset(struct igc_adapter *adapter);
740void igc_ptp_suspend(struct igc_adapter *adapter);
741void igc_ptp_stop(struct igc_adapter *adapter);
742ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
743int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
744int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
745void igc_ptp_tx_hang(struct igc_adapter *adapter);
746void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
747void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);
748
749int igc_led_setup(struct igc_adapter *adapter);
750void igc_led_free(struct igc_adapter *adapter);
751
752#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
753
754#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
755
756#define IGC_RX_DESC(R, i) \
757 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
758#define IGC_TX_DESC(R, i) \
759 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
760#define IGC_TX_CTXTDESC(R, i) \
761 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
762
763#endif /* _IGC_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_H_
5#define _IGC_H_
6
7#include <linux/kobject.h>
8#include <linux/pci.h>
9#include <linux/netdevice.h>
10#include <linux/vmalloc.h>
11#include <linux/ethtool.h>
12#include <linux/sctp.h>
13#include <linux/ptp_clock_kernel.h>
14#include <linux/timecounter.h>
15#include <linux/net_tstamp.h>
16
17#include "igc_hw.h"
18
19void igc_ethtool_set_ops(struct net_device *);
20
21/* Transmit and receive queues */
22#define IGC_MAX_RX_QUEUES 4
23#define IGC_MAX_TX_QUEUES 4
24
25#define MAX_Q_VECTORS 8
26#define MAX_STD_JUMBO_FRAME_SIZE 9216
27
28#define MAX_ETYPE_FILTER 8
29#define IGC_RETA_SIZE 128
30
31/* SDP support */
32#define IGC_N_EXTTS 2
33#define IGC_N_PEROUT 2
34#define IGC_N_SDP 4
35
36enum igc_mac_filter_type {
37 IGC_MAC_FILTER_TYPE_DST = 0,
38 IGC_MAC_FILTER_TYPE_SRC
39};
40
41struct igc_tx_queue_stats {
42 u64 packets;
43 u64 bytes;
44 u64 restart_queue;
45 u64 restart_queue2;
46};
47
48struct igc_rx_queue_stats {
49 u64 packets;
50 u64 bytes;
51 u64 drops;
52 u64 csum_err;
53 u64 alloc_failed;
54};
55
56struct igc_rx_packet_stats {
57 u64 ipv4_packets; /* IPv4 headers processed */
58 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
59 u64 ipv6_packets; /* IPv6 headers processed */
60 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
61 u64 tcp_packets; /* TCP headers processed */
62 u64 udp_packets; /* UDP headers processed */
63 u64 sctp_packets; /* SCTP headers processed */
64 u64 nfs_packets; /* NFS headers processe */
65 u64 other_packets;
66};
67
68struct igc_ring_container {
69 struct igc_ring *ring; /* pointer to linked list of rings */
70 unsigned int total_bytes; /* total bytes processed this int */
71 unsigned int total_packets; /* total packets processed this int */
72 u16 work_limit; /* total work allowed per interrupt */
73 u8 count; /* total number of rings in vector */
74 u8 itr; /* current ITR setting for ring */
75};
76
77struct igc_ring {
78 struct igc_q_vector *q_vector; /* backlink to q_vector */
79 struct net_device *netdev; /* back pointer to net_device */
80 struct device *dev; /* device for dma mapping */
81 union { /* array of buffer info structs */
82 struct igc_tx_buffer *tx_buffer_info;
83 struct igc_rx_buffer *rx_buffer_info;
84 };
85 void *desc; /* descriptor ring memory */
86 unsigned long flags; /* ring specific flags */
87 void __iomem *tail; /* pointer to ring tail register */
88 dma_addr_t dma; /* phys address of the ring */
89 unsigned int size; /* length of desc. ring in bytes */
90
91 u16 count; /* number of desc. in the ring */
92 u8 queue_index; /* logical index of the ring*/
93 u8 reg_idx; /* physical index of the ring */
94 bool launchtime_enable; /* true if LaunchTime is enabled */
95
96 u32 start_time;
97 u32 end_time;
98
99 /* everything past this point are written often */
100 u16 next_to_clean;
101 u16 next_to_use;
102 u16 next_to_alloc;
103
104 union {
105 /* TX */
106 struct {
107 struct igc_tx_queue_stats tx_stats;
108 struct u64_stats_sync tx_syncp;
109 struct u64_stats_sync tx_syncp2;
110 };
111 /* RX */
112 struct {
113 struct igc_rx_queue_stats rx_stats;
114 struct igc_rx_packet_stats pkt_stats;
115 struct u64_stats_sync rx_syncp;
116 struct sk_buff *skb;
117 };
118 };
119
120 struct xdp_rxq_info xdp_rxq;
121 struct xsk_buff_pool *xsk_pool;
122} ____cacheline_internodealigned_in_smp;
123
124/* Board specific private data structure */
125struct igc_adapter {
126 struct net_device *netdev;
127
128 struct ethtool_eee eee;
129 u16 eee_advert;
130
131 unsigned long state;
132 unsigned int flags;
133 unsigned int num_q_vectors;
134
135 struct msix_entry *msix_entries;
136
137 /* TX */
138 u16 tx_work_limit;
139 u32 tx_timeout_count;
140 int num_tx_queues;
141 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
142
143 /* RX */
144 int num_rx_queues;
145 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
146
147 struct timer_list watchdog_timer;
148 struct timer_list dma_err_timer;
149 struct timer_list phy_info_timer;
150
151 u32 wol;
152 u32 en_mng_pt;
153 u16 link_speed;
154 u16 link_duplex;
155
156 u8 port_num;
157
158 u8 __iomem *io_addr;
159 /* Interrupt Throttle Rate */
160 u32 rx_itr_setting;
161 u32 tx_itr_setting;
162
163 struct work_struct reset_task;
164 struct work_struct watchdog_task;
165 struct work_struct dma_err_task;
166 bool fc_autoneg;
167
168 u8 tx_timeout_factor;
169
170 int msg_enable;
171 u32 max_frame_size;
172 u32 min_frame_size;
173
174 ktime_t base_time;
175 ktime_t cycle_time;
176
177 /* OS defined structs */
178 struct pci_dev *pdev;
179 /* lock for statistics */
180 spinlock_t stats64_lock;
181 struct rtnl_link_stats64 stats64;
182
183 /* structs defined in igc_hw.h */
184 struct igc_hw hw;
185 struct igc_hw_stats stats;
186
187 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
188 u32 eims_enable_mask;
189 u32 eims_other;
190
191 u16 tx_ring_count;
192 u16 rx_ring_count;
193
194 u32 tx_hwtstamp_timeouts;
195 u32 tx_hwtstamp_skipped;
196 u32 rx_hwtstamp_cleared;
197
198 u32 rss_queues;
199 u32 rss_indir_tbl_init;
200
201 /* Any access to elements in nfc_rule_list is protected by the
202 * nfc_rule_lock.
203 */
204 struct mutex nfc_rule_lock;
205 struct list_head nfc_rule_list;
206 unsigned int nfc_rule_count;
207
208 u8 rss_indir_tbl[IGC_RETA_SIZE];
209
210 unsigned long link_check_timeout;
211 struct igc_info ei;
212
213 u32 test_icr;
214
215 struct ptp_clock *ptp_clock;
216 struct ptp_clock_info ptp_caps;
217 struct work_struct ptp_tx_work;
218 struct sk_buff *ptp_tx_skb;
219 struct hwtstamp_config tstamp_config;
220 unsigned long ptp_tx_start;
221 unsigned int ptp_flags;
222 /* System time value lock */
223 spinlock_t tmreg_lock;
224 struct cyclecounter cc;
225 struct timecounter tc;
226 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
227 ktime_t ptp_reset_start; /* Reset time in clock mono */
228
229 char fw_version[32];
230
231 struct bpf_prog *xdp_prog;
232
233 bool pps_sys_wrap_on;
234
235 struct ptp_pin_desc sdp_config[IGC_N_SDP];
236 struct {
237 struct timespec64 start;
238 struct timespec64 period;
239 } perout[IGC_N_PEROUT];
240};
241
242void igc_up(struct igc_adapter *adapter);
243void igc_down(struct igc_adapter *adapter);
244int igc_open(struct net_device *netdev);
245int igc_close(struct net_device *netdev);
246int igc_setup_tx_resources(struct igc_ring *ring);
247int igc_setup_rx_resources(struct igc_ring *ring);
248void igc_free_tx_resources(struct igc_ring *ring);
249void igc_free_rx_resources(struct igc_ring *ring);
250unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
251void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
252 const u32 max_rss_queues);
253int igc_reinit_queues(struct igc_adapter *adapter);
254void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
255bool igc_has_link(struct igc_adapter *adapter);
256void igc_reset(struct igc_adapter *adapter);
257int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
258void igc_update_stats(struct igc_adapter *adapter);
259void igc_disable_rx_ring(struct igc_ring *ring);
260void igc_enable_rx_ring(struct igc_ring *ring);
261void igc_disable_tx_ring(struct igc_ring *ring);
262void igc_enable_tx_ring(struct igc_ring *ring);
263int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
264
265/* igc_dump declarations */
266void igc_rings_dump(struct igc_adapter *adapter);
267void igc_regs_dump(struct igc_adapter *adapter);
268
269extern char igc_driver_name[];
270
271#define IGC_REGS_LEN 740
272
273/* flags controlling PTP/1588 function */
274#define IGC_PTP_ENABLED BIT(0)
275
276/* Flags definitions */
277#define IGC_FLAG_HAS_MSI BIT(0)
278#define IGC_FLAG_QUEUE_PAIRS BIT(3)
279#define IGC_FLAG_DMAC BIT(4)
280#define IGC_FLAG_PTP BIT(8)
281#define IGC_FLAG_WOL_SUPPORTED BIT(8)
282#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
283#define IGC_FLAG_MEDIA_RESET BIT(10)
284#define IGC_FLAG_MAS_ENABLE BIT(12)
285#define IGC_FLAG_HAS_MSIX BIT(13)
286#define IGC_FLAG_EEE BIT(14)
287#define IGC_FLAG_VLAN_PROMISC BIT(15)
288#define IGC_FLAG_RX_LEGACY BIT(16)
289#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
290
291#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
292#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
293
294#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
295#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
296#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
297
298/* Interrupt defines */
299#define IGC_START_ITR 648 /* ~6000 ints/sec */
300#define IGC_4K_ITR 980
301#define IGC_20K_ITR 196
302#define IGC_70K_ITR 56
303
304#define IGC_DEFAULT_ITR 3 /* dynamic */
305#define IGC_MAX_ITR_USECS 10000
306#define IGC_MIN_ITR_USECS 10
307#define NON_Q_VECTORS 1
308#define MAX_MSIX_ENTRIES 10
309
310/* TX/RX descriptor defines */
311#define IGC_DEFAULT_TXD 256
312#define IGC_DEFAULT_TX_WORK 128
313#define IGC_MIN_TXD 80
314#define IGC_MAX_TXD 4096
315
316#define IGC_DEFAULT_RXD 256
317#define IGC_MIN_RXD 80
318#define IGC_MAX_RXD 4096
319
320/* Supported Rx Buffer Sizes */
321#define IGC_RXBUFFER_256 256
322#define IGC_RXBUFFER_2048 2048
323#define IGC_RXBUFFER_3072 3072
324
325#define AUTO_ALL_MODES 0
326#define IGC_RX_HDR_LEN IGC_RXBUFFER_256
327
328/* Transmit and receive latency (for PTP timestamps) */
329#define IGC_I225_TX_LATENCY_10 240
330#define IGC_I225_TX_LATENCY_100 58
331#define IGC_I225_TX_LATENCY_1000 80
332#define IGC_I225_TX_LATENCY_2500 1325
333#define IGC_I225_RX_LATENCY_10 6450
334#define IGC_I225_RX_LATENCY_100 185
335#define IGC_I225_RX_LATENCY_1000 300
336#define IGC_I225_RX_LATENCY_2500 1485
337
338/* RX and TX descriptor control thresholds.
339 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
340 * descriptors available in its onboard memory.
341 * Setting this to 0 disables RX descriptor prefetch.
342 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
343 * available in host memory.
344 * If PTHRESH is 0, this should also be 0.
345 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
346 * descriptors until either it has this many to write back, or the
347 * ITR timer expires.
348 */
349#define IGC_RX_PTHRESH 8
350#define IGC_RX_HTHRESH 8
351#define IGC_TX_PTHRESH 8
352#define IGC_TX_HTHRESH 1
353#define IGC_RX_WTHRESH 4
354#define IGC_TX_WTHRESH 16
355
356#define IGC_RX_DMA_ATTR \
357 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
358
359#define IGC_TS_HDR_LEN 16
360
361#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
362
363#if (PAGE_SIZE < 8192)
364#define IGC_MAX_FRAME_BUILD_SKB \
365 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
366#else
367#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
368#endif
369
370/* How many Rx Buffers do we bundle into one write to the hardware ? */
371#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
372
373/* VLAN info */
374#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
375#define IGC_TX_FLAGS_VLAN_SHIFT 16
376
377/* igc_test_staterr - tests bits within Rx descriptor status and error fields */
378static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
379 const u32 stat_err_bits)
380{
381 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
382}
383
384enum igc_state_t {
385 __IGC_TESTING,
386 __IGC_RESETTING,
387 __IGC_DOWN,
388 __IGC_PTP_TX_IN_PROGRESS,
389};
390
391enum igc_tx_flags {
392 /* cmd_type flags */
393 IGC_TX_FLAGS_VLAN = 0x01,
394 IGC_TX_FLAGS_TSO = 0x02,
395 IGC_TX_FLAGS_TSTAMP = 0x04,
396
397 /* olinfo flags */
398 IGC_TX_FLAGS_IPV4 = 0x10,
399 IGC_TX_FLAGS_CSUM = 0x20,
400};
401
402enum igc_boards {
403 board_base,
404};
405
406/* The largest size we can write to the descriptor is 65535. In order to
407 * maintain a power of two alignment we have to limit ourselves to 32K.
408 */
409#define IGC_MAX_TXD_PWR 15
410#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
411
412/* Tx Descriptors needed, worst case */
413#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
414#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
415
416enum igc_tx_buffer_type {
417 IGC_TX_BUFFER_TYPE_SKB,
418 IGC_TX_BUFFER_TYPE_XDP,
419 IGC_TX_BUFFER_TYPE_XSK,
420};
421
422/* wrapper around a pointer to a socket buffer,
423 * so a DMA handle can be stored along with the buffer
424 */
425struct igc_tx_buffer {
426 union igc_adv_tx_desc *next_to_watch;
427 unsigned long time_stamp;
428 enum igc_tx_buffer_type type;
429 union {
430 struct sk_buff *skb;
431 struct xdp_frame *xdpf;
432 };
433 unsigned int bytecount;
434 u16 gso_segs;
435 __be16 protocol;
436
437 DEFINE_DMA_UNMAP_ADDR(dma);
438 DEFINE_DMA_UNMAP_LEN(len);
439 u32 tx_flags;
440};
441
442struct igc_rx_buffer {
443 union {
444 struct {
445 dma_addr_t dma;
446 struct page *page;
447#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
448 __u32 page_offset;
449#else
450 __u16 page_offset;
451#endif
452 __u16 pagecnt_bias;
453 };
454 struct xdp_buff *xdp;
455 };
456};
457
458struct igc_q_vector {
459 struct igc_adapter *adapter; /* backlink */
460 void __iomem *itr_register;
461 u32 eims_value; /* EIMS mask value */
462
463 u16 itr_val;
464 u8 set_itr;
465
466 struct igc_ring_container rx, tx;
467
468 struct napi_struct napi;
469
470 struct rcu_head rcu; /* to avoid race with update stats on free */
471 char name[IFNAMSIZ + 9];
472 struct net_device poll_dev;
473
474 /* for dynamic allocation of rings associated with this q_vector */
475 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
476};
477
478enum igc_filter_match_flags {
479 IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
480 IGC_FILTER_FLAG_VLAN_TCI = 0x2,
481 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
482 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
483};
484
485struct igc_nfc_filter {
486 u8 match_flags;
487 u16 etype;
488 u16 vlan_tci;
489 u8 src_addr[ETH_ALEN];
490 u8 dst_addr[ETH_ALEN];
491};
492
493struct igc_nfc_rule {
494 struct list_head list;
495 struct igc_nfc_filter filter;
496 u32 location;
497 u16 action;
498};
499
500/* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
501 * based, and 8 ethertype based.
502 */
503#define IGC_MAX_RXNFC_RULES 32
504
505/* igc_desc_unused - calculate if we have unused descriptors */
506static inline u16 igc_desc_unused(const struct igc_ring *ring)
507{
508 u16 ntc = ring->next_to_clean;
509 u16 ntu = ring->next_to_use;
510
511 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
512}
513
514static inline s32 igc_get_phy_info(struct igc_hw *hw)
515{
516 if (hw->phy.ops.get_phy_info)
517 return hw->phy.ops.get_phy_info(hw);
518
519 return 0;
520}
521
522static inline s32 igc_reset_phy(struct igc_hw *hw)
523{
524 if (hw->phy.ops.reset)
525 return hw->phy.ops.reset(hw);
526
527 return 0;
528}
529
530static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
531{
532 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
533}
534
535enum igc_ring_flags_t {
536 IGC_RING_FLAG_RX_3K_BUFFER,
537 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
538 IGC_RING_FLAG_RX_SCTP_CSUM,
539 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
540 IGC_RING_FLAG_TX_CTX_IDX,
541 IGC_RING_FLAG_TX_DETECT_HANG,
542 IGC_RING_FLAG_AF_XDP_ZC,
543};
544
545#define ring_uses_large_buffer(ring) \
546 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
547#define set_ring_uses_large_buffer(ring) \
548 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
549#define clear_ring_uses_large_buffer(ring) \
550 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
551
552#define ring_uses_build_skb(ring) \
553 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
554
555static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
556{
557#if (PAGE_SIZE < 8192)
558 if (ring_uses_large_buffer(ring))
559 return IGC_RXBUFFER_3072;
560
561 if (ring_uses_build_skb(ring))
562 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
563#endif
564 return IGC_RXBUFFER_2048;
565}
566
567static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
568{
569#if (PAGE_SIZE < 8192)
570 if (ring_uses_large_buffer(ring))
571 return 1;
572#endif
573 return 0;
574}
575
576static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
577{
578 if (hw->phy.ops.read_reg)
579 return hw->phy.ops.read_reg(hw, offset, data);
580
581 return -EOPNOTSUPP;
582}
583
584void igc_reinit_locked(struct igc_adapter *);
585struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
586 u32 location);
587int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
588void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
589
590void igc_ptp_init(struct igc_adapter *adapter);
591void igc_ptp_reset(struct igc_adapter *adapter);
592void igc_ptp_suspend(struct igc_adapter *adapter);
593void igc_ptp_stop(struct igc_adapter *adapter);
594ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
595int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
596int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
597void igc_ptp_tx_hang(struct igc_adapter *adapter);
598void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
599
600#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
601
602#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
603
604#define IGC_RX_DESC(R, i) \
605 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
606#define IGC_TX_DESC(R, i) \
607 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
608#define IGC_TX_CTXTDESC(R, i) \
609 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
610
611#endif /* _IGC_H_ */