Loading...
1/*
2 * CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
13 * written by:
14 * Copyright
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
17 *
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
22 *
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/netdevice.h>
33#include <linux/if_arp.h>
34#include <linux/if_ether.h>
35#include <linux/list.h>
36#include <linux/io.h>
37#include <linux/pm_runtime.h>
38#include <linux/pinctrl/consumer.h>
39
40#include <linux/can.h>
41#include <linux/can/dev.h>
42#include <linux/can/error.h>
43
44#include "c_can.h"
45
46/* Number of interface registers */
47#define IF_ENUM_REG_LEN 11
48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
49
50/* control extension register D_CAN specific */
51#define CONTROL_EX_PDR BIT(8)
52
53/* control register */
54#define CONTROL_SWR BIT(15)
55#define CONTROL_TEST BIT(7)
56#define CONTROL_CCE BIT(6)
57#define CONTROL_DISABLE_AR BIT(5)
58#define CONTROL_ENABLE_AR (0 << 5)
59#define CONTROL_EIE BIT(3)
60#define CONTROL_SIE BIT(2)
61#define CONTROL_IE BIT(1)
62#define CONTROL_INIT BIT(0)
63
64#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
65
66/* test register */
67#define TEST_RX BIT(7)
68#define TEST_TX1 BIT(6)
69#define TEST_TX2 BIT(5)
70#define TEST_LBACK BIT(4)
71#define TEST_SILENT BIT(3)
72#define TEST_BASIC BIT(2)
73
74/* status register */
75#define STATUS_PDA BIT(10)
76#define STATUS_BOFF BIT(7)
77#define STATUS_EWARN BIT(6)
78#define STATUS_EPASS BIT(5)
79#define STATUS_RXOK BIT(4)
80#define STATUS_TXOK BIT(3)
81
82/* error counter register */
83#define ERR_CNT_TEC_MASK 0xff
84#define ERR_CNT_TEC_SHIFT 0
85#define ERR_CNT_REC_SHIFT 8
86#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
87#define ERR_CNT_RP_SHIFT 15
88#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
89
90/* bit-timing register */
91#define BTR_BRP_MASK 0x3f
92#define BTR_BRP_SHIFT 0
93#define BTR_SJW_SHIFT 6
94#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
95#define BTR_TSEG1_SHIFT 8
96#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
97#define BTR_TSEG2_SHIFT 12
98#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
99
100/* interrupt register */
101#define INT_STS_PENDING 0x8000
102
103/* brp extension register */
104#define BRP_EXT_BRPE_MASK 0x0f
105#define BRP_EXT_BRPE_SHIFT 0
106
107/* IFx command request */
108#define IF_COMR_BUSY BIT(15)
109
110/* IFx command mask */
111#define IF_COMM_WR BIT(7)
112#define IF_COMM_MASK BIT(6)
113#define IF_COMM_ARB BIT(5)
114#define IF_COMM_CONTROL BIT(4)
115#define IF_COMM_CLR_INT_PND BIT(3)
116#define IF_COMM_TXRQST BIT(2)
117#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
118#define IF_COMM_DATAA BIT(1)
119#define IF_COMM_DATAB BIT(0)
120
121/* TX buffer setup */
122#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
123 IF_COMM_TXRQST | \
124 IF_COMM_DATAA | IF_COMM_DATAB)
125
126/* For the low buffers we clear the interrupt bit, but keep newdat */
127#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
128 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
129 IF_COMM_DATAA | IF_COMM_DATAB)
130
131/* For the high buffers we clear the interrupt bit and newdat */
132#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
133
134/* Receive setup of message objects */
135#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
136
137/* Invalidation of message objects */
138#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
139
140/* IFx arbitration */
141#define IF_ARB_MSGVAL BIT(31)
142#define IF_ARB_MSGXTD BIT(30)
143#define IF_ARB_TRANSMIT BIT(29)
144
145/* IFx message control */
146#define IF_MCONT_NEWDAT BIT(15)
147#define IF_MCONT_MSGLST BIT(14)
148#define IF_MCONT_INTPND BIT(13)
149#define IF_MCONT_UMASK BIT(12)
150#define IF_MCONT_TXIE BIT(11)
151#define IF_MCONT_RXIE BIT(10)
152#define IF_MCONT_RMTEN BIT(9)
153#define IF_MCONT_TXRQST BIT(8)
154#define IF_MCONT_EOB BIT(7)
155#define IF_MCONT_DLC_MASK 0xf
156
157#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
158#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
159
160#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
161
162/* Use IF1 in NAPI path and IF2 in TX path */
163#define IF_NAPI 0
164#define IF_TX 1
165
166/* minimum timeout for checking BUSY status */
167#define MIN_TIMEOUT_VALUE 6
168
169/* Wait for ~1 sec for INIT bit */
170#define INIT_WAIT_MS 1000
171
172/* c_can lec values */
173enum c_can_lec_type {
174 LEC_NO_ERROR = 0,
175 LEC_STUFF_ERROR,
176 LEC_FORM_ERROR,
177 LEC_ACK_ERROR,
178 LEC_BIT1_ERROR,
179 LEC_BIT0_ERROR,
180 LEC_CRC_ERROR,
181 LEC_UNUSED,
182 LEC_MASK = LEC_UNUSED,
183};
184
185/* c_can error types:
186 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
187 */
188enum c_can_bus_error_types {
189 C_CAN_NO_ERROR = 0,
190 C_CAN_BUS_OFF,
191 C_CAN_ERROR_WARNING,
192 C_CAN_ERROR_PASSIVE,
193};
194
195static const struct can_bittiming_const c_can_bittiming_const = {
196 .name = KBUILD_MODNAME,
197 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
198 .tseg1_max = 16,
199 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
200 .tseg2_max = 8,
201 .sjw_max = 4,
202 .brp_min = 1,
203 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
204 .brp_inc = 1,
205};
206
207static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
208{
209 if (priv->device)
210 pm_runtime_get_sync(priv->device);
211}
212
213static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
214{
215 if (priv->device)
216 pm_runtime_put_sync(priv->device);
217}
218
219static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
220{
221 if (priv->raminit)
222 priv->raminit(priv, enable);
223}
224
225static void c_can_irq_control(struct c_can_priv *priv, bool enable)
226{
227 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
228
229 if (enable)
230 ctrl |= CONTROL_IRQMSK;
231
232 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
233}
234
235static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
236{
237 struct c_can_priv *priv = netdev_priv(dev);
238 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
239
240 priv->write_reg32(priv, reg, (cmd << 16) | obj);
241
242 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
243 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
244 return;
245 udelay(1);
246 }
247 netdev_err(dev, "Updating object timed out\n");
248}
249
250static inline void c_can_object_get(struct net_device *dev, int iface,
251 u32 obj, u32 cmd)
252{
253 c_can_obj_update(dev, iface, cmd, obj);
254}
255
256static inline void c_can_object_put(struct net_device *dev, int iface,
257 u32 obj, u32 cmd)
258{
259 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
260}
261
262/* Note: According to documentation clearing TXIE while MSGVAL is set
263 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
264 * load significantly.
265 */
266static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
267{
268 struct c_can_priv *priv = netdev_priv(dev);
269
270 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
271 c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
272}
273
274static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
275{
276 struct c_can_priv *priv = netdev_priv(dev);
277
278 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
279 c_can_inval_tx_object(dev, iface, obj);
280}
281
282static void c_can_setup_tx_object(struct net_device *dev, int iface,
283 struct can_frame *frame, int idx)
284{
285 struct c_can_priv *priv = netdev_priv(dev);
286 u16 ctrl = IF_MCONT_TX | frame->len;
287 bool rtr = frame->can_id & CAN_RTR_FLAG;
288 u32 arb = IF_ARB_MSGVAL;
289 int i;
290
291 if (frame->can_id & CAN_EFF_FLAG) {
292 arb |= frame->can_id & CAN_EFF_MASK;
293 arb |= IF_ARB_MSGXTD;
294 } else {
295 arb |= (frame->can_id & CAN_SFF_MASK) << 18;
296 }
297
298 if (!rtr)
299 arb |= IF_ARB_TRANSMIT;
300
301 /* If we change the DIR bit, we need to invalidate the buffer
302 * first, i.e. clear the MSGVAL flag in the arbiter.
303 */
304 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
305 u32 obj = idx + priv->msg_obj_tx_first;
306
307 c_can_inval_msg_object(dev, iface, obj);
308 change_bit(idx, &priv->tx_dir);
309 }
310
311 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
312
313 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
314
315 if (priv->type == BOSCH_D_CAN) {
316 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface);
317
318 for (i = 0; i < frame->len; i += 4, dreg += 2) {
319 data = (u32)frame->data[i];
320 data |= (u32)frame->data[i + 1] << 8;
321 data |= (u32)frame->data[i + 2] << 16;
322 data |= (u32)frame->data[i + 3] << 24;
323 priv->write_reg32(priv, dreg, data);
324 }
325 } else {
326 for (i = 0; i < frame->len; i += 2) {
327 priv->write_reg(priv,
328 C_CAN_IFACE(DATA1_REG, iface) + i / 2,
329 frame->data[i] |
330 (frame->data[i + 1] << 8));
331 }
332 }
333}
334
335static int c_can_handle_lost_msg_obj(struct net_device *dev,
336 int iface, int objno, u32 ctrl)
337{
338 struct net_device_stats *stats = &dev->stats;
339 struct c_can_priv *priv = netdev_priv(dev);
340 struct can_frame *frame;
341 struct sk_buff *skb;
342
343 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
344 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
345 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
346
347 stats->rx_errors++;
348 stats->rx_over_errors++;
349
350 /* create an error msg */
351 skb = alloc_can_err_skb(dev, &frame);
352 if (unlikely(!skb))
353 return 0;
354
355 frame->can_id |= CAN_ERR_CRTL;
356 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
357
358 netif_receive_skb(skb);
359 return 1;
360}
361
362static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
363{
364 struct net_device_stats *stats = &dev->stats;
365 struct c_can_priv *priv = netdev_priv(dev);
366 struct can_frame *frame;
367 struct sk_buff *skb;
368 u32 arb, data;
369
370 skb = alloc_can_skb(dev, &frame);
371 if (!skb) {
372 stats->rx_dropped++;
373 return -ENOMEM;
374 }
375
376 frame->len = can_cc_dlc2len(ctrl & 0x0F);
377
378 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
379
380 if (arb & IF_ARB_MSGXTD)
381 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
382 else
383 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
384
385 if (arb & IF_ARB_TRANSMIT) {
386 frame->can_id |= CAN_RTR_FLAG;
387 } else {
388 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
389
390 if (priv->type == BOSCH_D_CAN) {
391 for (i = 0; i < frame->len; i += 4, dreg += 2) {
392 data = priv->read_reg32(priv, dreg);
393 frame->data[i] = data;
394 frame->data[i + 1] = data >> 8;
395 frame->data[i + 2] = data >> 16;
396 frame->data[i + 3] = data >> 24;
397 }
398 } else {
399 for (i = 0; i < frame->len; i += 2, dreg++) {
400 data = priv->read_reg(priv, dreg);
401 frame->data[i] = data;
402 frame->data[i + 1] = data >> 8;
403 }
404 }
405
406 stats->rx_bytes += frame->len;
407 }
408 stats->rx_packets++;
409
410 netif_receive_skb(skb);
411 return 0;
412}
413
414static void c_can_setup_receive_object(struct net_device *dev, int iface,
415 u32 obj, u32 mask, u32 id, u32 mcont)
416{
417 struct c_can_priv *priv = netdev_priv(dev);
418
419 mask |= BIT(29);
420 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
421
422 id |= IF_ARB_MSGVAL;
423 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
424
425 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
426 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
427}
428
429static bool c_can_tx_busy(const struct c_can_priv *priv,
430 const struct c_can_tx_ring *tx_ring)
431{
432 if (c_can_get_tx_free(priv, tx_ring) > 0)
433 return false;
434
435 netif_stop_queue(priv->dev);
436
437 /* Memory barrier before checking tx_free (head and tail) */
438 smp_mb();
439
440 if (c_can_get_tx_free(priv, tx_ring) == 0) {
441 netdev_dbg(priv->dev,
442 "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n",
443 tx_ring->head, tx_ring->tail,
444 tx_ring->head - tx_ring->tail);
445 return true;
446 }
447
448 netif_start_queue(priv->dev);
449 return false;
450}
451
452static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
453 struct net_device *dev)
454{
455 struct can_frame *frame = (struct can_frame *)skb->data;
456 struct c_can_priv *priv = netdev_priv(dev);
457 struct c_can_tx_ring *tx_ring = &priv->tx;
458 u32 idx, obj, cmd = IF_COMM_TX;
459
460 if (can_dev_dropped_skb(dev, skb))
461 return NETDEV_TX_OK;
462
463 if (c_can_tx_busy(priv, tx_ring))
464 return NETDEV_TX_BUSY;
465
466 idx = c_can_get_tx_head(tx_ring);
467 tx_ring->head++;
468 if (c_can_get_tx_free(priv, tx_ring) == 0)
469 netif_stop_queue(dev);
470
471 if (idx < c_can_get_tx_tail(tx_ring))
472 cmd &= ~IF_COMM_TXRQST; /* Cache the message */
473
474 /* Store the message in the interface so we can call
475 * can_put_echo_skb(). We must do this before we enable
476 * transmit as we might race against do_tx().
477 */
478 c_can_setup_tx_object(dev, IF_TX, frame, idx);
479 can_put_echo_skb(skb, dev, idx, 0);
480 obj = idx + priv->msg_obj_tx_first;
481 c_can_object_put(dev, IF_TX, obj, cmd);
482
483 return NETDEV_TX_OK;
484}
485
486static int c_can_wait_for_ctrl_init(struct net_device *dev,
487 struct c_can_priv *priv, u32 init)
488{
489 int retry = 0;
490
491 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
492 udelay(10);
493 if (retry++ > 1000) {
494 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
495 return -EIO;
496 }
497 }
498 return 0;
499}
500
501static int c_can_set_bittiming(struct net_device *dev)
502{
503 unsigned int reg_btr, reg_brpe, ctrl_save;
504 u8 brp, brpe, sjw, tseg1, tseg2;
505 u32 ten_bit_brp;
506 struct c_can_priv *priv = netdev_priv(dev);
507 const struct can_bittiming *bt = &priv->can.bittiming;
508 int res;
509
510 /* c_can provides a 6-bit brp and 4-bit brpe fields */
511 ten_bit_brp = bt->brp - 1;
512 brp = ten_bit_brp & BTR_BRP_MASK;
513 brpe = ten_bit_brp >> 6;
514
515 sjw = bt->sjw - 1;
516 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
517 tseg2 = bt->phase_seg2 - 1;
518 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
519 (tseg2 << BTR_TSEG2_SHIFT);
520 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
521
522 netdev_info(dev,
523 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
524
525 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
526 ctrl_save &= ~CONTROL_INIT;
527 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
528 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
529 if (res)
530 return res;
531
532 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
533 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
534 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
535
536 return c_can_wait_for_ctrl_init(dev, priv, 0);
537}
538
539/* Configure C_CAN message objects for Tx and Rx purposes:
540 * C_CAN provides a total of 32 message objects that can be configured
541 * either for Tx or Rx purposes. Here the first 16 message objects are used as
542 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
543 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
544 * See user guide document for further details on configuring message
545 * objects.
546 */
547static void c_can_configure_msg_objects(struct net_device *dev)
548{
549 struct c_can_priv *priv = netdev_priv(dev);
550 int i;
551
552 /* first invalidate all message objects */
553 for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++)
554 c_can_inval_msg_object(dev, IF_NAPI, i);
555
556 /* setup receive message objects */
557 for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++)
558 c_can_setup_receive_object(dev, IF_NAPI, i, 0, 0, IF_MCONT_RCV);
559
560 c_can_setup_receive_object(dev, IF_NAPI, priv->msg_obj_rx_last, 0, 0,
561 IF_MCONT_RCV_EOB);
562}
563
564static int c_can_software_reset(struct net_device *dev)
565{
566 struct c_can_priv *priv = netdev_priv(dev);
567 int retry = 0;
568
569 if (priv->type != BOSCH_D_CAN)
570 return 0;
571
572 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT);
573 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) {
574 msleep(20);
575 if (retry++ > 100) {
576 netdev_err(dev, "CCTRL: software reset failed\n");
577 return -EIO;
578 }
579 }
580
581 return 0;
582}
583
584/* Configure C_CAN chip:
585 * - enable/disable auto-retransmission
586 * - set operating mode
587 * - configure message objects
588 */
589static int c_can_chip_config(struct net_device *dev)
590{
591 struct c_can_priv *priv = netdev_priv(dev);
592 struct c_can_tx_ring *tx_ring = &priv->tx;
593 int err;
594
595 err = c_can_software_reset(dev);
596 if (err)
597 return err;
598
599 /* enable automatic retransmission */
600 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
601
602 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
603 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
604 /* loopback + silent mode : useful for hot self-test */
605 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
606 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
607 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
608 /* loopback mode : useful for self-test function */
609 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
610 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
611 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
612 /* silent mode : bus-monitoring mode */
613 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
614 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
615 }
616
617 /* configure message objects */
618 c_can_configure_msg_objects(dev);
619
620 /* set a `lec` value so that we can check for updates later */
621 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
622
623 /* Clear all internal status */
624 tx_ring->head = 0;
625 tx_ring->tail = 0;
626 priv->tx_dir = 0;
627
628 /* set bittiming params */
629 return c_can_set_bittiming(dev);
630}
631
632static int c_can_start(struct net_device *dev)
633{
634 struct c_can_priv *priv = netdev_priv(dev);
635 int err;
636 struct pinctrl *p;
637
638 /* basic c_can configuration */
639 err = c_can_chip_config(dev);
640 if (err)
641 return err;
642
643 /* Setup the command for new messages */
644 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
645 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
646
647 priv->can.state = CAN_STATE_ERROR_ACTIVE;
648
649 /* Attempt to use "active" if available else use "default" */
650 p = pinctrl_get_select(priv->device, "active");
651 if (!IS_ERR(p))
652 pinctrl_put(p);
653 else
654 pinctrl_pm_select_default_state(priv->device);
655
656 return 0;
657}
658
659static void c_can_stop(struct net_device *dev)
660{
661 struct c_can_priv *priv = netdev_priv(dev);
662
663 c_can_irq_control(priv, false);
664
665 /* put ctrl to init on stop to end ongoing transmission */
666 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT);
667
668 /* deactivate pins */
669 pinctrl_pm_select_sleep_state(dev->dev.parent);
670 priv->can.state = CAN_STATE_STOPPED;
671}
672
673static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
674{
675 struct c_can_priv *priv = netdev_priv(dev);
676 int err;
677
678 switch (mode) {
679 case CAN_MODE_START:
680 err = c_can_start(dev);
681 if (err)
682 return err;
683 netif_wake_queue(dev);
684 c_can_irq_control(priv, true);
685 break;
686 default:
687 return -EOPNOTSUPP;
688 }
689
690 return 0;
691}
692
693static int __c_can_get_berr_counter(const struct net_device *dev,
694 struct can_berr_counter *bec)
695{
696 unsigned int reg_err_counter;
697 struct c_can_priv *priv = netdev_priv(dev);
698
699 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
700 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
701 ERR_CNT_REC_SHIFT;
702 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
703
704 return 0;
705}
706
707static int c_can_get_berr_counter(const struct net_device *dev,
708 struct can_berr_counter *bec)
709{
710 struct c_can_priv *priv = netdev_priv(dev);
711 int err;
712
713 c_can_pm_runtime_get_sync(priv);
714 err = __c_can_get_berr_counter(dev, bec);
715 c_can_pm_runtime_put_sync(priv);
716
717 return err;
718}
719
720static void c_can_do_tx(struct net_device *dev)
721{
722 struct c_can_priv *priv = netdev_priv(dev);
723 struct c_can_tx_ring *tx_ring = &priv->tx;
724 struct net_device_stats *stats = &dev->stats;
725 u32 idx, obj, pkts = 0, bytes = 0, pend;
726 u8 tail;
727
728 if (priv->msg_obj_tx_last > 32)
729 pend = priv->read_reg32(priv, C_CAN_INTPND3_REG);
730 else
731 pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
732
733 while ((idx = ffs(pend))) {
734 idx--;
735 pend &= ~BIT(idx);
736 obj = idx + priv->msg_obj_tx_first;
737
738 /* We use IF_NAPI interface instead of IF_TX because we
739 * are called from c_can_poll(), which runs inside
740 * NAPI. We are not transmitting.
741 */
742 c_can_inval_tx_object(dev, IF_NAPI, obj);
743 bytes += can_get_echo_skb(dev, idx, NULL);
744 pkts++;
745 }
746
747 if (!pkts)
748 return;
749
750 tx_ring->tail += pkts;
751 if (c_can_get_tx_free(priv, tx_ring)) {
752 /* Make sure that anybody stopping the queue after
753 * this sees the new tx_ring->tail.
754 */
755 smp_mb();
756 netif_wake_queue(priv->dev);
757 }
758
759 stats->tx_bytes += bytes;
760 stats->tx_packets += pkts;
761
762 tail = c_can_get_tx_tail(tx_ring);
763 if (priv->type == BOSCH_D_CAN && tail == 0) {
764 u8 head = c_can_get_tx_head(tx_ring);
765
766 /* Start transmission for all cached messages */
767 for (idx = tail; idx < head; idx++) {
768 obj = idx + priv->msg_obj_tx_first;
769 c_can_object_put(dev, IF_NAPI, obj, IF_COMM_TXRQST);
770 }
771 }
772}
773
774/* If we have a gap in the pending bits, that means we either
775 * raced with the hardware or failed to readout all upper
776 * objects in the last run due to quota limit.
777 */
778static u32 c_can_adjust_pending(u32 pend, u32 rx_mask)
779{
780 u32 weight, lasts;
781
782 if (pend == rx_mask)
783 return pend;
784
785 /* If the last set bit is larger than the number of pending
786 * bits we have a gap.
787 */
788 weight = hweight32(pend);
789 lasts = fls(pend);
790
791 /* If the bits are linear, nothing to do */
792 if (lasts == weight)
793 return pend;
794
795 /* Find the first set bit after the gap. We walk backwards
796 * from the last set bit.
797 */
798 for (lasts--; pend & BIT(lasts - 1); lasts--)
799 ;
800
801 return pend & ~GENMASK(lasts - 1, 0);
802}
803
804static inline void c_can_rx_object_get(struct net_device *dev,
805 struct c_can_priv *priv, u32 obj)
806{
807 c_can_object_get(dev, IF_NAPI, obj, priv->comm_rcv_high);
808}
809
810static inline void c_can_rx_finalize(struct net_device *dev,
811 struct c_can_priv *priv, u32 obj)
812{
813 if (priv->type != BOSCH_D_CAN)
814 c_can_object_get(dev, IF_NAPI, obj, IF_COMM_CLR_NEWDAT);
815}
816
817static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
818 u32 pend, int quota)
819{
820 u32 pkts = 0, ctrl, obj;
821
822 while ((obj = ffs(pend)) && quota > 0) {
823 pend &= ~BIT(obj - 1);
824
825 c_can_rx_object_get(dev, priv, obj);
826 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_NAPI));
827
828 if (ctrl & IF_MCONT_MSGLST) {
829 int n;
830
831 n = c_can_handle_lost_msg_obj(dev, IF_NAPI, obj, ctrl);
832
833 pkts += n;
834 quota -= n;
835 continue;
836 }
837
838 /* This really should not happen, but this covers some
839 * odd HW behaviour. Do not remove that unless you
840 * want to brick your machine.
841 */
842 if (!(ctrl & IF_MCONT_NEWDAT))
843 continue;
844
845 /* read the data from the message object */
846 c_can_read_msg_object(dev, IF_NAPI, ctrl);
847
848 c_can_rx_finalize(dev, priv, obj);
849
850 pkts++;
851 quota--;
852 }
853
854 return pkts;
855}
856
857static inline u32 c_can_get_pending(struct c_can_priv *priv)
858{
859 u32 pend;
860
861 if (priv->msg_obj_rx_last > 16)
862 pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG);
863 else
864 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
865
866 return pend;
867}
868
869/* theory of operation:
870 *
871 * c_can core saves a received CAN message into the first free message
872 * object it finds free (starting with the lowest). Bits NEWDAT and
873 * INTPND are set for this message object indicating that a new message
874 * has arrived.
875 *
876 * We clear the newdat bit right away.
877 *
878 * This can result in packet reordering when the readout is slow.
879 */
880static int c_can_do_rx_poll(struct net_device *dev, int quota)
881{
882 struct c_can_priv *priv = netdev_priv(dev);
883 u32 pkts = 0, pend = 0, toread, n;
884
885 while (quota > 0) {
886 if (!pend) {
887 pend = c_can_get_pending(priv);
888 if (!pend)
889 break;
890 /* If the pending field has a gap, handle the
891 * bits above the gap first.
892 */
893 toread = c_can_adjust_pending(pend,
894 priv->msg_obj_rx_mask);
895 } else {
896 toread = pend;
897 }
898 /* Remove the bits from pend */
899 pend &= ~toread;
900 /* Read the objects */
901 n = c_can_read_objects(dev, priv, toread, quota);
902 pkts += n;
903 quota -= n;
904 }
905
906 return pkts;
907}
908
909static int c_can_handle_state_change(struct net_device *dev,
910 enum c_can_bus_error_types error_type)
911{
912 unsigned int reg_err_counter;
913 unsigned int rx_err_passive;
914 struct c_can_priv *priv = netdev_priv(dev);
915 struct can_frame *cf;
916 struct sk_buff *skb;
917 struct can_berr_counter bec;
918
919 switch (error_type) {
920 case C_CAN_NO_ERROR:
921 priv->can.state = CAN_STATE_ERROR_ACTIVE;
922 break;
923 case C_CAN_ERROR_WARNING:
924 /* error warning state */
925 priv->can.can_stats.error_warning++;
926 priv->can.state = CAN_STATE_ERROR_WARNING;
927 break;
928 case C_CAN_ERROR_PASSIVE:
929 /* error passive state */
930 priv->can.can_stats.error_passive++;
931 priv->can.state = CAN_STATE_ERROR_PASSIVE;
932 break;
933 case C_CAN_BUS_OFF:
934 /* bus-off state */
935 priv->can.state = CAN_STATE_BUS_OFF;
936 priv->can.can_stats.bus_off++;
937 break;
938 default:
939 break;
940 }
941
942 /* propagate the error condition to the CAN stack */
943 skb = alloc_can_err_skb(dev, &cf);
944 if (unlikely(!skb))
945 return 0;
946
947 __c_can_get_berr_counter(dev, &bec);
948 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
949 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
950 ERR_CNT_RP_SHIFT;
951
952 switch (error_type) {
953 case C_CAN_NO_ERROR:
954 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
955 cf->data[1] = CAN_ERR_CRTL_ACTIVE;
956 cf->data[6] = bec.txerr;
957 cf->data[7] = bec.rxerr;
958 break;
959 case C_CAN_ERROR_WARNING:
960 /* error warning state */
961 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
962 cf->data[1] = (bec.txerr > bec.rxerr) ?
963 CAN_ERR_CRTL_TX_WARNING :
964 CAN_ERR_CRTL_RX_WARNING;
965 cf->data[6] = bec.txerr;
966 cf->data[7] = bec.rxerr;
967
968 break;
969 case C_CAN_ERROR_PASSIVE:
970 /* error passive state */
971 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
972 if (rx_err_passive)
973 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
974 if (bec.txerr > 127)
975 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
976
977 cf->data[6] = bec.txerr;
978 cf->data[7] = bec.rxerr;
979 break;
980 case C_CAN_BUS_OFF:
981 /* bus-off state */
982 cf->can_id |= CAN_ERR_BUSOFF;
983 can_bus_off(dev);
984 break;
985 default:
986 break;
987 }
988
989 netif_receive_skb(skb);
990
991 return 1;
992}
993
994static int c_can_handle_bus_err(struct net_device *dev,
995 enum c_can_lec_type lec_type)
996{
997 struct c_can_priv *priv = netdev_priv(dev);
998 struct net_device_stats *stats = &dev->stats;
999 struct can_frame *cf;
1000 struct sk_buff *skb;
1001
1002 /* early exit if no lec update or no error.
1003 * no lec update means that no CAN bus event has been detected
1004 * since CPU wrote 0x7 value to status reg.
1005 */
1006 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
1007 return 0;
1008
1009 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1010 return 0;
1011
1012 /* common for all type of bus errors */
1013 priv->can.can_stats.bus_error++;
1014
1015 /* propagate the error condition to the CAN stack */
1016 skb = alloc_can_err_skb(dev, &cf);
1017
1018 /* check for 'last error code' which tells us the
1019 * type of the last error to occur on the CAN bus
1020 */
1021 if (likely(skb))
1022 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1023
1024 switch (lec_type) {
1025 case LEC_STUFF_ERROR:
1026 netdev_dbg(dev, "stuff error\n");
1027 if (likely(skb))
1028 cf->data[2] |= CAN_ERR_PROT_STUFF;
1029 stats->rx_errors++;
1030 break;
1031 case LEC_FORM_ERROR:
1032 netdev_dbg(dev, "form error\n");
1033 if (likely(skb))
1034 cf->data[2] |= CAN_ERR_PROT_FORM;
1035 stats->rx_errors++;
1036 break;
1037 case LEC_ACK_ERROR:
1038 netdev_dbg(dev, "ack error\n");
1039 if (likely(skb))
1040 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1041 stats->tx_errors++;
1042 break;
1043 case LEC_BIT1_ERROR:
1044 netdev_dbg(dev, "bit1 error\n");
1045 if (likely(skb))
1046 cf->data[2] |= CAN_ERR_PROT_BIT1;
1047 stats->tx_errors++;
1048 break;
1049 case LEC_BIT0_ERROR:
1050 netdev_dbg(dev, "bit0 error\n");
1051 if (likely(skb))
1052 cf->data[2] |= CAN_ERR_PROT_BIT0;
1053 stats->tx_errors++;
1054 break;
1055 case LEC_CRC_ERROR:
1056 netdev_dbg(dev, "CRC error\n");
1057 if (likely(skb))
1058 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1059 stats->rx_errors++;
1060 break;
1061 default:
1062 break;
1063 }
1064
1065 if (unlikely(!skb))
1066 return 0;
1067
1068 netif_receive_skb(skb);
1069 return 1;
1070}
1071
1072static int c_can_poll(struct napi_struct *napi, int quota)
1073{
1074 struct net_device *dev = napi->dev;
1075 struct c_can_priv *priv = netdev_priv(dev);
1076 u16 curr, last = priv->last_status;
1077 int work_done = 0;
1078
1079 /* Only read the status register if a status interrupt was pending */
1080 if (atomic_xchg(&priv->sie_pending, 0)) {
1081 priv->last_status = priv->read_reg(priv, C_CAN_STS_REG);
1082 curr = priv->last_status;
1083 /* Ack status on C_CAN. D_CAN is self clearing */
1084 if (priv->type != BOSCH_D_CAN)
1085 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1086 } else {
1087 /* no change detected ... */
1088 curr = last;
1089 }
1090
1091 /* handle state changes */
1092 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1093 netdev_dbg(dev, "entered error warning state\n");
1094 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1095 }
1096
1097 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1098 netdev_dbg(dev, "entered error passive state\n");
1099 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1100 }
1101
1102 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1103 netdev_dbg(dev, "entered bus off state\n");
1104 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1105 goto end;
1106 }
1107
1108 /* handle bus recovery events */
1109 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1110 netdev_dbg(dev, "left bus off state\n");
1111 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1112 }
1113
1114 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1115 netdev_dbg(dev, "left error passive state\n");
1116 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1117 }
1118
1119 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) {
1120 netdev_dbg(dev, "left error warning state\n");
1121 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR);
1122 }
1123
1124 /* handle lec errors on the bus */
1125 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1126
1127 /* Handle Tx/Rx events. We do this unconditionally */
1128 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1129 c_can_do_tx(dev);
1130
1131end:
1132 if (work_done < quota) {
1133 napi_complete_done(napi, work_done);
1134 /* enable all IRQs if we are not in bus off state */
1135 if (priv->can.state != CAN_STATE_BUS_OFF)
1136 c_can_irq_control(priv, true);
1137 }
1138
1139 return work_done;
1140}
1141
1142static irqreturn_t c_can_isr(int irq, void *dev_id)
1143{
1144 struct net_device *dev = (struct net_device *)dev_id;
1145 struct c_can_priv *priv = netdev_priv(dev);
1146 int reg_int;
1147
1148 reg_int = priv->read_reg(priv, C_CAN_INT_REG);
1149 if (!reg_int)
1150 return IRQ_NONE;
1151
1152 /* save for later use */
1153 if (reg_int & INT_STS_PENDING)
1154 atomic_set(&priv->sie_pending, 1);
1155
1156 /* disable all interrupts and schedule the NAPI */
1157 c_can_irq_control(priv, false);
1158 napi_schedule(&priv->napi);
1159
1160 return IRQ_HANDLED;
1161}
1162
1163static int c_can_open(struct net_device *dev)
1164{
1165 int err;
1166 struct c_can_priv *priv = netdev_priv(dev);
1167
1168 c_can_pm_runtime_get_sync(priv);
1169 c_can_reset_ram(priv, true);
1170
1171 /* open the can device */
1172 err = open_candev(dev);
1173 if (err) {
1174 netdev_err(dev, "failed to open can device\n");
1175 goto exit_open_fail;
1176 }
1177
1178 /* register interrupt handler */
1179 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1180 dev);
1181 if (err < 0) {
1182 netdev_err(dev, "failed to request interrupt\n");
1183 goto exit_irq_fail;
1184 }
1185
1186 /* start the c_can controller */
1187 err = c_can_start(dev);
1188 if (err)
1189 goto exit_start_fail;
1190
1191 napi_enable(&priv->napi);
1192 /* enable status change, error and module interrupts */
1193 c_can_irq_control(priv, true);
1194 netif_start_queue(dev);
1195
1196 return 0;
1197
1198exit_start_fail:
1199 free_irq(dev->irq, dev);
1200exit_irq_fail:
1201 close_candev(dev);
1202exit_open_fail:
1203 c_can_reset_ram(priv, false);
1204 c_can_pm_runtime_put_sync(priv);
1205 return err;
1206}
1207
1208static int c_can_close(struct net_device *dev)
1209{
1210 struct c_can_priv *priv = netdev_priv(dev);
1211
1212 netif_stop_queue(dev);
1213 napi_disable(&priv->napi);
1214 c_can_stop(dev);
1215 free_irq(dev->irq, dev);
1216 close_candev(dev);
1217
1218 c_can_reset_ram(priv, false);
1219 c_can_pm_runtime_put_sync(priv);
1220
1221 return 0;
1222}
1223
1224struct net_device *alloc_c_can_dev(int msg_obj_num)
1225{
1226 struct net_device *dev;
1227 struct c_can_priv *priv;
1228 int msg_obj_tx_num = msg_obj_num / 2;
1229
1230 dev = alloc_candev(sizeof(*priv), msg_obj_tx_num);
1231 if (!dev)
1232 return NULL;
1233
1234 priv = netdev_priv(dev);
1235 priv->msg_obj_num = msg_obj_num;
1236 priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num;
1237 priv->msg_obj_rx_first = 1;
1238 priv->msg_obj_rx_last =
1239 priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1;
1240 priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0);
1241
1242 priv->msg_obj_tx_num = msg_obj_tx_num;
1243 priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1;
1244 priv->msg_obj_tx_last =
1245 priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1;
1246
1247 priv->tx.head = 0;
1248 priv->tx.tail = 0;
1249 priv->tx.obj_num = msg_obj_tx_num;
1250
1251 netif_napi_add_weight(dev, &priv->napi, c_can_poll,
1252 priv->msg_obj_rx_num);
1253
1254 priv->dev = dev;
1255 priv->can.bittiming_const = &c_can_bittiming_const;
1256 priv->can.do_set_mode = c_can_set_mode;
1257 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1258 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1259 CAN_CTRLMODE_LISTENONLY |
1260 CAN_CTRLMODE_BERR_REPORTING;
1261
1262 return dev;
1263}
1264EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1265
1266#ifdef CONFIG_PM
1267int c_can_power_down(struct net_device *dev)
1268{
1269 u32 val;
1270 unsigned long time_out;
1271 struct c_can_priv *priv = netdev_priv(dev);
1272
1273 if (!(dev->flags & IFF_UP))
1274 return 0;
1275
1276 WARN_ON(priv->type != BOSCH_D_CAN);
1277
1278 /* set PDR value so the device goes to power down mode */
1279 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1280 val |= CONTROL_EX_PDR;
1281 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1282
1283 /* Wait for the PDA bit to get set */
1284 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1285 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1286 time_after(time_out, jiffies))
1287 cpu_relax();
1288
1289 if (time_after(jiffies, time_out))
1290 return -ETIMEDOUT;
1291
1292 c_can_stop(dev);
1293
1294 c_can_reset_ram(priv, false);
1295 c_can_pm_runtime_put_sync(priv);
1296
1297 return 0;
1298}
1299EXPORT_SYMBOL_GPL(c_can_power_down);
1300
1301int c_can_power_up(struct net_device *dev)
1302{
1303 u32 val;
1304 unsigned long time_out;
1305 struct c_can_priv *priv = netdev_priv(dev);
1306 int ret;
1307
1308 if (!(dev->flags & IFF_UP))
1309 return 0;
1310
1311 WARN_ON(priv->type != BOSCH_D_CAN);
1312
1313 c_can_pm_runtime_get_sync(priv);
1314 c_can_reset_ram(priv, true);
1315
1316 /* Clear PDR and INIT bits */
1317 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1318 val &= ~CONTROL_EX_PDR;
1319 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1320 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1321 val &= ~CONTROL_INIT;
1322 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1323
1324 /* Wait for the PDA bit to get clear */
1325 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1326 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1327 time_after(time_out, jiffies))
1328 cpu_relax();
1329
1330 if (time_after(jiffies, time_out)) {
1331 ret = -ETIMEDOUT;
1332 goto err_out;
1333 }
1334
1335 ret = c_can_start(dev);
1336 if (ret)
1337 goto err_out;
1338
1339 c_can_irq_control(priv, true);
1340
1341 return 0;
1342
1343err_out:
1344 c_can_reset_ram(priv, false);
1345 c_can_pm_runtime_put_sync(priv);
1346
1347 return ret;
1348}
1349EXPORT_SYMBOL_GPL(c_can_power_up);
1350#endif
1351
1352void free_c_can_dev(struct net_device *dev)
1353{
1354 struct c_can_priv *priv = netdev_priv(dev);
1355
1356 netif_napi_del(&priv->napi);
1357 free_candev(dev);
1358}
1359EXPORT_SYMBOL_GPL(free_c_can_dev);
1360
1361static const struct net_device_ops c_can_netdev_ops = {
1362 .ndo_open = c_can_open,
1363 .ndo_stop = c_can_close,
1364 .ndo_start_xmit = c_can_start_xmit,
1365 .ndo_change_mtu = can_change_mtu,
1366};
1367
1368int register_c_can_dev(struct net_device *dev)
1369{
1370 /* Deactivate pins to prevent DRA7 DCAN IP from being
1371 * stuck in transition when module is disabled.
1372 * Pins are activated in c_can_start() and deactivated
1373 * in c_can_stop()
1374 */
1375 pinctrl_pm_select_sleep_state(dev->dev.parent);
1376
1377 dev->flags |= IFF_ECHO; /* we support local echo */
1378 dev->netdev_ops = &c_can_netdev_ops;
1379 dev->ethtool_ops = &c_can_ethtool_ops;
1380
1381 return register_candev(dev);
1382}
1383EXPORT_SYMBOL_GPL(register_c_can_dev);
1384
1385void unregister_c_can_dev(struct net_device *dev)
1386{
1387 unregister_candev(dev);
1388}
1389EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1390
1391MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1392MODULE_LICENSE("GPL v2");
1393MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");
1/*
2 * CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
13 * written by:
14 * Copyright
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
17 *
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
22 *
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/netdevice.h>
33#include <linux/if_arp.h>
34#include <linux/if_ether.h>
35#include <linux/list.h>
36#include <linux/io.h>
37#include <linux/pm_runtime.h>
38#include <linux/pinctrl/consumer.h>
39
40#include <linux/can.h>
41#include <linux/can/dev.h>
42#include <linux/can/error.h>
43#include <linux/can/led.h>
44
45#include "c_can.h"
46
47/* Number of interface registers */
48#define IF_ENUM_REG_LEN 11
49#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
50
51/* control extension register D_CAN specific */
52#define CONTROL_EX_PDR BIT(8)
53
54/* control register */
55#define CONTROL_SWR BIT(15)
56#define CONTROL_TEST BIT(7)
57#define CONTROL_CCE BIT(6)
58#define CONTROL_DISABLE_AR BIT(5)
59#define CONTROL_ENABLE_AR (0 << 5)
60#define CONTROL_EIE BIT(3)
61#define CONTROL_SIE BIT(2)
62#define CONTROL_IE BIT(1)
63#define CONTROL_INIT BIT(0)
64
65#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
66
67/* test register */
68#define TEST_RX BIT(7)
69#define TEST_TX1 BIT(6)
70#define TEST_TX2 BIT(5)
71#define TEST_LBACK BIT(4)
72#define TEST_SILENT BIT(3)
73#define TEST_BASIC BIT(2)
74
75/* status register */
76#define STATUS_PDA BIT(10)
77#define STATUS_BOFF BIT(7)
78#define STATUS_EWARN BIT(6)
79#define STATUS_EPASS BIT(5)
80#define STATUS_RXOK BIT(4)
81#define STATUS_TXOK BIT(3)
82
83/* error counter register */
84#define ERR_CNT_TEC_MASK 0xff
85#define ERR_CNT_TEC_SHIFT 0
86#define ERR_CNT_REC_SHIFT 8
87#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
88#define ERR_CNT_RP_SHIFT 15
89#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
90
91/* bit-timing register */
92#define BTR_BRP_MASK 0x3f
93#define BTR_BRP_SHIFT 0
94#define BTR_SJW_SHIFT 6
95#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
96#define BTR_TSEG1_SHIFT 8
97#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
98#define BTR_TSEG2_SHIFT 12
99#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
100
101/* interrupt register */
102#define INT_STS_PENDING 0x8000
103
104/* brp extension register */
105#define BRP_EXT_BRPE_MASK 0x0f
106#define BRP_EXT_BRPE_SHIFT 0
107
108/* IFx command request */
109#define IF_COMR_BUSY BIT(15)
110
111/* IFx command mask */
112#define IF_COMM_WR BIT(7)
113#define IF_COMM_MASK BIT(6)
114#define IF_COMM_ARB BIT(5)
115#define IF_COMM_CONTROL BIT(4)
116#define IF_COMM_CLR_INT_PND BIT(3)
117#define IF_COMM_TXRQST BIT(2)
118#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
119#define IF_COMM_DATAA BIT(1)
120#define IF_COMM_DATAB BIT(0)
121
122/* TX buffer setup */
123#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
124 IF_COMM_TXRQST | \
125 IF_COMM_DATAA | IF_COMM_DATAB)
126
127/* For the low buffers we clear the interrupt bit, but keep newdat */
128#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
129 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
130 IF_COMM_DATAA | IF_COMM_DATAB)
131
132/* For the high buffers we clear the interrupt bit and newdat */
133#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
134
135/* Receive setup of message objects */
136#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
137
138/* Invalidation of message objects */
139#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
140
141/* IFx arbitration */
142#define IF_ARB_MSGVAL BIT(31)
143#define IF_ARB_MSGXTD BIT(30)
144#define IF_ARB_TRANSMIT BIT(29)
145
146/* IFx message control */
147#define IF_MCONT_NEWDAT BIT(15)
148#define IF_MCONT_MSGLST BIT(14)
149#define IF_MCONT_INTPND BIT(13)
150#define IF_MCONT_UMASK BIT(12)
151#define IF_MCONT_TXIE BIT(11)
152#define IF_MCONT_RXIE BIT(10)
153#define IF_MCONT_RMTEN BIT(9)
154#define IF_MCONT_TXRQST BIT(8)
155#define IF_MCONT_EOB BIT(7)
156#define IF_MCONT_DLC_MASK 0xf
157
158#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
159#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
160
161#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
162
163/* Use IF1 for RX and IF2 for TX */
164#define IF_RX 0
165#define IF_TX 1
166
167/* minimum timeout for checking BUSY status */
168#define MIN_TIMEOUT_VALUE 6
169
170/* Wait for ~1 sec for INIT bit */
171#define INIT_WAIT_MS 1000
172
173/* c_can lec values */
174enum c_can_lec_type {
175 LEC_NO_ERROR = 0,
176 LEC_STUFF_ERROR,
177 LEC_FORM_ERROR,
178 LEC_ACK_ERROR,
179 LEC_BIT1_ERROR,
180 LEC_BIT0_ERROR,
181 LEC_CRC_ERROR,
182 LEC_UNUSED,
183 LEC_MASK = LEC_UNUSED,
184};
185
186/* c_can error types:
187 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
188 */
189enum c_can_bus_error_types {
190 C_CAN_NO_ERROR = 0,
191 C_CAN_BUS_OFF,
192 C_CAN_ERROR_WARNING,
193 C_CAN_ERROR_PASSIVE,
194};
195
196static const struct can_bittiming_const c_can_bittiming_const = {
197 .name = KBUILD_MODNAME,
198 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
199 .tseg1_max = 16,
200 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
201 .tseg2_max = 8,
202 .sjw_max = 4,
203 .brp_min = 1,
204 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
205 .brp_inc = 1,
206};
207
208static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
209{
210 if (priv->device)
211 pm_runtime_get_sync(priv->device);
212}
213
214static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
215{
216 if (priv->device)
217 pm_runtime_put_sync(priv->device);
218}
219
220static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
221{
222 if (priv->raminit)
223 priv->raminit(priv, enable);
224}
225
226static void c_can_irq_control(struct c_can_priv *priv, bool enable)
227{
228 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
229
230 if (enable)
231 ctrl |= CONTROL_IRQMSK;
232
233 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
234}
235
236static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
237{
238 struct c_can_priv *priv = netdev_priv(dev);
239 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
240
241 priv->write_reg32(priv, reg, (cmd << 16) | obj);
242
243 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
244 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
245 return;
246 udelay(1);
247 }
248 netdev_err(dev, "Updating object timed out\n");
249}
250
251static inline void c_can_object_get(struct net_device *dev, int iface,
252 u32 obj, u32 cmd)
253{
254 c_can_obj_update(dev, iface, cmd, obj);
255}
256
257static inline void c_can_object_put(struct net_device *dev, int iface,
258 u32 obj, u32 cmd)
259{
260 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
261}
262
263/* Note: According to documentation clearing TXIE while MSGVAL is set
264 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
265 * load significantly.
266 */
267static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
268{
269 struct c_can_priv *priv = netdev_priv(dev);
270
271 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
272 c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
273}
274
275static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
276{
277 struct c_can_priv *priv = netdev_priv(dev);
278
279 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
280 c_can_inval_tx_object(dev, iface, obj);
281}
282
283static void c_can_setup_tx_object(struct net_device *dev, int iface,
284 struct can_frame *frame, int idx)
285{
286 struct c_can_priv *priv = netdev_priv(dev);
287 u16 ctrl = IF_MCONT_TX | frame->len;
288 bool rtr = frame->can_id & CAN_RTR_FLAG;
289 u32 arb = IF_ARB_MSGVAL;
290 int i;
291
292 if (frame->can_id & CAN_EFF_FLAG) {
293 arb |= frame->can_id & CAN_EFF_MASK;
294 arb |= IF_ARB_MSGXTD;
295 } else {
296 arb |= (frame->can_id & CAN_SFF_MASK) << 18;
297 }
298
299 if (!rtr)
300 arb |= IF_ARB_TRANSMIT;
301
302 /* If we change the DIR bit, we need to invalidate the buffer
303 * first, i.e. clear the MSGVAL flag in the arbiter.
304 */
305 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
306 u32 obj = idx + priv->msg_obj_tx_first;
307
308 c_can_inval_msg_object(dev, iface, obj);
309 change_bit(idx, &priv->tx_dir);
310 }
311
312 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
313
314 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
315
316 if (priv->type == BOSCH_D_CAN) {
317 u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface);
318
319 for (i = 0; i < frame->len; i += 4, dreg += 2) {
320 data = (u32)frame->data[i];
321 data |= (u32)frame->data[i + 1] << 8;
322 data |= (u32)frame->data[i + 2] << 16;
323 data |= (u32)frame->data[i + 3] << 24;
324 priv->write_reg32(priv, dreg, data);
325 }
326 } else {
327 for (i = 0; i < frame->len; i += 2) {
328 priv->write_reg(priv,
329 C_CAN_IFACE(DATA1_REG, iface) + i / 2,
330 frame->data[i] |
331 (frame->data[i + 1] << 8));
332 }
333 }
334}
335
336static int c_can_handle_lost_msg_obj(struct net_device *dev,
337 int iface, int objno, u32 ctrl)
338{
339 struct net_device_stats *stats = &dev->stats;
340 struct c_can_priv *priv = netdev_priv(dev);
341 struct can_frame *frame;
342 struct sk_buff *skb;
343
344 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
345 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
346 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
347
348 stats->rx_errors++;
349 stats->rx_over_errors++;
350
351 /* create an error msg */
352 skb = alloc_can_err_skb(dev, &frame);
353 if (unlikely(!skb))
354 return 0;
355
356 frame->can_id |= CAN_ERR_CRTL;
357 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
358
359 netif_receive_skb(skb);
360 return 1;
361}
362
363static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
364{
365 struct net_device_stats *stats = &dev->stats;
366 struct c_can_priv *priv = netdev_priv(dev);
367 struct can_frame *frame;
368 struct sk_buff *skb;
369 u32 arb, data;
370
371 skb = alloc_can_skb(dev, &frame);
372 if (!skb) {
373 stats->rx_dropped++;
374 return -ENOMEM;
375 }
376
377 frame->len = can_cc_dlc2len(ctrl & 0x0F);
378
379 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
380
381 if (arb & IF_ARB_MSGXTD)
382 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
383 else
384 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
385
386 if (arb & IF_ARB_TRANSMIT) {
387 frame->can_id |= CAN_RTR_FLAG;
388 } else {
389 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
390
391 if (priv->type == BOSCH_D_CAN) {
392 for (i = 0; i < frame->len; i += 4, dreg += 2) {
393 data = priv->read_reg32(priv, dreg);
394 frame->data[i] = data;
395 frame->data[i + 1] = data >> 8;
396 frame->data[i + 2] = data >> 16;
397 frame->data[i + 3] = data >> 24;
398 }
399 } else {
400 for (i = 0; i < frame->len; i += 2, dreg++) {
401 data = priv->read_reg(priv, dreg);
402 frame->data[i] = data;
403 frame->data[i + 1] = data >> 8;
404 }
405 }
406 }
407
408 stats->rx_packets++;
409 stats->rx_bytes += frame->len;
410
411 netif_receive_skb(skb);
412 return 0;
413}
414
415static void c_can_setup_receive_object(struct net_device *dev, int iface,
416 u32 obj, u32 mask, u32 id, u32 mcont)
417{
418 struct c_can_priv *priv = netdev_priv(dev);
419
420 mask |= BIT(29);
421 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
422
423 id |= IF_ARB_MSGVAL;
424 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
425
426 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
427 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
428}
429
430static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
431 struct net_device *dev)
432{
433 struct can_frame *frame = (struct can_frame *)skb->data;
434 struct c_can_priv *priv = netdev_priv(dev);
435 u32 idx, obj;
436
437 if (can_dropped_invalid_skb(dev, skb))
438 return NETDEV_TX_OK;
439 /* This is not a FIFO. C/D_CAN sends out the buffers
440 * prioritized. The lowest buffer number wins.
441 */
442 idx = fls(atomic_read(&priv->tx_active));
443 obj = idx + priv->msg_obj_tx_first;
444
445 /* If this is the last buffer, stop the xmit queue */
446 if (idx == priv->msg_obj_tx_num - 1)
447 netif_stop_queue(dev);
448 /* Store the message in the interface so we can call
449 * can_put_echo_skb(). We must do this before we enable
450 * transmit as we might race against do_tx().
451 */
452 c_can_setup_tx_object(dev, IF_TX, frame, idx);
453 priv->dlc[idx] = frame->len;
454 can_put_echo_skb(skb, dev, idx, 0);
455
456 /* Update the active bits */
457 atomic_add(BIT(idx), &priv->tx_active);
458 /* Start transmission */
459 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX);
460
461 return NETDEV_TX_OK;
462}
463
464static int c_can_wait_for_ctrl_init(struct net_device *dev,
465 struct c_can_priv *priv, u32 init)
466{
467 int retry = 0;
468
469 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
470 udelay(10);
471 if (retry++ > 1000) {
472 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
473 return -EIO;
474 }
475 }
476 return 0;
477}
478
479static int c_can_set_bittiming(struct net_device *dev)
480{
481 unsigned int reg_btr, reg_brpe, ctrl_save;
482 u8 brp, brpe, sjw, tseg1, tseg2;
483 u32 ten_bit_brp;
484 struct c_can_priv *priv = netdev_priv(dev);
485 const struct can_bittiming *bt = &priv->can.bittiming;
486 int res;
487
488 /* c_can provides a 6-bit brp and 4-bit brpe fields */
489 ten_bit_brp = bt->brp - 1;
490 brp = ten_bit_brp & BTR_BRP_MASK;
491 brpe = ten_bit_brp >> 6;
492
493 sjw = bt->sjw - 1;
494 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
495 tseg2 = bt->phase_seg2 - 1;
496 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
497 (tseg2 << BTR_TSEG2_SHIFT);
498 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
499
500 netdev_info(dev,
501 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
502
503 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
504 ctrl_save &= ~CONTROL_INIT;
505 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
506 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
507 if (res)
508 return res;
509
510 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
511 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
512 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
513
514 return c_can_wait_for_ctrl_init(dev, priv, 0);
515}
516
517/* Configure C_CAN message objects for Tx and Rx purposes:
518 * C_CAN provides a total of 32 message objects that can be configured
519 * either for Tx or Rx purposes. Here the first 16 message objects are used as
520 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
521 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
522 * See user guide document for further details on configuring message
523 * objects.
524 */
525static void c_can_configure_msg_objects(struct net_device *dev)
526{
527 struct c_can_priv *priv = netdev_priv(dev);
528 int i;
529
530 /* first invalidate all message objects */
531 for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++)
532 c_can_inval_msg_object(dev, IF_RX, i);
533
534 /* setup receive message objects */
535 for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++)
536 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV);
537
538 c_can_setup_receive_object(dev, IF_RX, priv->msg_obj_rx_last, 0, 0,
539 IF_MCONT_RCV_EOB);
540}
541
542static int c_can_software_reset(struct net_device *dev)
543{
544 struct c_can_priv *priv = netdev_priv(dev);
545 int retry = 0;
546
547 if (priv->type != BOSCH_D_CAN)
548 return 0;
549
550 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT);
551 while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) {
552 msleep(20);
553 if (retry++ > 100) {
554 netdev_err(dev, "CCTRL: software reset failed\n");
555 return -EIO;
556 }
557 }
558
559 return 0;
560}
561
562/* Configure C_CAN chip:
563 * - enable/disable auto-retransmission
564 * - set operating mode
565 * - configure message objects
566 */
567static int c_can_chip_config(struct net_device *dev)
568{
569 struct c_can_priv *priv = netdev_priv(dev);
570 int err;
571
572 err = c_can_software_reset(dev);
573 if (err)
574 return err;
575
576 /* enable automatic retransmission */
577 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
578
579 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
580 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
581 /* loopback + silent mode : useful for hot self-test */
582 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
583 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
584 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
585 /* loopback mode : useful for self-test function */
586 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
587 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
588 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
589 /* silent mode : bus-monitoring mode */
590 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
591 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
592 }
593
594 /* configure message objects */
595 c_can_configure_msg_objects(dev);
596
597 /* set a `lec` value so that we can check for updates later */
598 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
599
600 /* Clear all internal status */
601 atomic_set(&priv->tx_active, 0);
602 priv->tx_dir = 0;
603
604 /* set bittiming params */
605 return c_can_set_bittiming(dev);
606}
607
608static int c_can_start(struct net_device *dev)
609{
610 struct c_can_priv *priv = netdev_priv(dev);
611 int err;
612 struct pinctrl *p;
613
614 /* basic c_can configuration */
615 err = c_can_chip_config(dev);
616 if (err)
617 return err;
618
619 /* Setup the command for new messages */
620 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
621 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
622
623 priv->can.state = CAN_STATE_ERROR_ACTIVE;
624
625 /* Attempt to use "active" if available else use "default" */
626 p = pinctrl_get_select(priv->device, "active");
627 if (!IS_ERR(p))
628 pinctrl_put(p);
629 else
630 pinctrl_pm_select_default_state(priv->device);
631
632 return 0;
633}
634
635static void c_can_stop(struct net_device *dev)
636{
637 struct c_can_priv *priv = netdev_priv(dev);
638
639 c_can_irq_control(priv, false);
640
641 /* put ctrl to init on stop to end ongoing transmission */
642 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT);
643
644 /* deactivate pins */
645 pinctrl_pm_select_sleep_state(dev->dev.parent);
646 priv->can.state = CAN_STATE_STOPPED;
647}
648
649static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
650{
651 struct c_can_priv *priv = netdev_priv(dev);
652 int err;
653
654 switch (mode) {
655 case CAN_MODE_START:
656 err = c_can_start(dev);
657 if (err)
658 return err;
659 netif_wake_queue(dev);
660 c_can_irq_control(priv, true);
661 break;
662 default:
663 return -EOPNOTSUPP;
664 }
665
666 return 0;
667}
668
669static int __c_can_get_berr_counter(const struct net_device *dev,
670 struct can_berr_counter *bec)
671{
672 unsigned int reg_err_counter;
673 struct c_can_priv *priv = netdev_priv(dev);
674
675 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
676 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
677 ERR_CNT_REC_SHIFT;
678 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
679
680 return 0;
681}
682
683static int c_can_get_berr_counter(const struct net_device *dev,
684 struct can_berr_counter *bec)
685{
686 struct c_can_priv *priv = netdev_priv(dev);
687 int err;
688
689 c_can_pm_runtime_get_sync(priv);
690 err = __c_can_get_berr_counter(dev, bec);
691 c_can_pm_runtime_put_sync(priv);
692
693 return err;
694}
695
696static void c_can_do_tx(struct net_device *dev)
697{
698 struct c_can_priv *priv = netdev_priv(dev);
699 struct net_device_stats *stats = &dev->stats;
700 u32 idx, obj, pkts = 0, bytes = 0, pend, clr;
701
702 if (priv->msg_obj_tx_last > 32)
703 pend = priv->read_reg32(priv, C_CAN_INTPND3_REG);
704 else
705 pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
706 clr = pend;
707
708 while ((idx = ffs(pend))) {
709 idx--;
710 pend &= ~BIT(idx);
711 obj = idx + priv->msg_obj_tx_first;
712
713 /* We use IF_RX interface instead of IF_TX because we
714 * are called from c_can_poll(), which runs inside
715 * NAPI. We are not trasmitting.
716 */
717 c_can_inval_tx_object(dev, IF_RX, obj);
718 can_get_echo_skb(dev, idx, NULL);
719 bytes += priv->dlc[idx];
720 pkts++;
721 }
722
723 /* Clear the bits in the tx_active mask */
724 atomic_sub(clr, &priv->tx_active);
725
726 if (clr & BIT(priv->msg_obj_tx_num - 1))
727 netif_wake_queue(dev);
728
729 if (pkts) {
730 stats->tx_bytes += bytes;
731 stats->tx_packets += pkts;
732 can_led_event(dev, CAN_LED_EVENT_TX);
733 }
734}
735
736/* If we have a gap in the pending bits, that means we either
737 * raced with the hardware or failed to readout all upper
738 * objects in the last run due to quota limit.
739 */
740static u32 c_can_adjust_pending(u32 pend, u32 rx_mask)
741{
742 u32 weight, lasts;
743
744 if (pend == rx_mask)
745 return pend;
746
747 /* If the last set bit is larger than the number of pending
748 * bits we have a gap.
749 */
750 weight = hweight32(pend);
751 lasts = fls(pend);
752
753 /* If the bits are linear, nothing to do */
754 if (lasts == weight)
755 return pend;
756
757 /* Find the first set bit after the gap. We walk backwards
758 * from the last set bit.
759 */
760 for (lasts--; pend & BIT(lasts - 1); lasts--)
761 ;
762
763 return pend & ~GENMASK(lasts - 1, 0);
764}
765
766static inline void c_can_rx_object_get(struct net_device *dev,
767 struct c_can_priv *priv, u32 obj)
768{
769 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high);
770}
771
772static inline void c_can_rx_finalize(struct net_device *dev,
773 struct c_can_priv *priv, u32 obj)
774{
775 if (priv->type != BOSCH_D_CAN)
776 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT);
777}
778
779static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
780 u32 pend, int quota)
781{
782 u32 pkts = 0, ctrl, obj;
783
784 while ((obj = ffs(pend)) && quota > 0) {
785 pend &= ~BIT(obj - 1);
786
787 c_can_rx_object_get(dev, priv, obj);
788 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
789
790 if (ctrl & IF_MCONT_MSGLST) {
791 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
792
793 pkts += n;
794 quota -= n;
795 continue;
796 }
797
798 /* This really should not happen, but this covers some
799 * odd HW behaviour. Do not remove that unless you
800 * want to brick your machine.
801 */
802 if (!(ctrl & IF_MCONT_NEWDAT))
803 continue;
804
805 /* read the data from the message object */
806 c_can_read_msg_object(dev, IF_RX, ctrl);
807
808 c_can_rx_finalize(dev, priv, obj);
809
810 pkts++;
811 quota--;
812 }
813
814 return pkts;
815}
816
817static inline u32 c_can_get_pending(struct c_can_priv *priv)
818{
819 u32 pend;
820
821 if (priv->msg_obj_rx_last > 16)
822 pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG);
823 else
824 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
825
826 return pend;
827}
828
829/* theory of operation:
830 *
831 * c_can core saves a received CAN message into the first free message
832 * object it finds free (starting with the lowest). Bits NEWDAT and
833 * INTPND are set for this message object indicating that a new message
834 * has arrived.
835 *
836 * We clear the newdat bit right away.
837 *
838 * This can result in packet reordering when the readout is slow.
839 */
840static int c_can_do_rx_poll(struct net_device *dev, int quota)
841{
842 struct c_can_priv *priv = netdev_priv(dev);
843 u32 pkts = 0, pend = 0, toread, n;
844
845 while (quota > 0) {
846 if (!pend) {
847 pend = c_can_get_pending(priv);
848 if (!pend)
849 break;
850 /* If the pending field has a gap, handle the
851 * bits above the gap first.
852 */
853 toread = c_can_adjust_pending(pend,
854 priv->msg_obj_rx_mask);
855 } else {
856 toread = pend;
857 }
858 /* Remove the bits from pend */
859 pend &= ~toread;
860 /* Read the objects */
861 n = c_can_read_objects(dev, priv, toread, quota);
862 pkts += n;
863 quota -= n;
864 }
865
866 if (pkts)
867 can_led_event(dev, CAN_LED_EVENT_RX);
868
869 return pkts;
870}
871
872static int c_can_handle_state_change(struct net_device *dev,
873 enum c_can_bus_error_types error_type)
874{
875 unsigned int reg_err_counter;
876 unsigned int rx_err_passive;
877 struct c_can_priv *priv = netdev_priv(dev);
878 struct net_device_stats *stats = &dev->stats;
879 struct can_frame *cf;
880 struct sk_buff *skb;
881 struct can_berr_counter bec;
882
883 switch (error_type) {
884 case C_CAN_NO_ERROR:
885 priv->can.state = CAN_STATE_ERROR_ACTIVE;
886 break;
887 case C_CAN_ERROR_WARNING:
888 /* error warning state */
889 priv->can.can_stats.error_warning++;
890 priv->can.state = CAN_STATE_ERROR_WARNING;
891 break;
892 case C_CAN_ERROR_PASSIVE:
893 /* error passive state */
894 priv->can.can_stats.error_passive++;
895 priv->can.state = CAN_STATE_ERROR_PASSIVE;
896 break;
897 case C_CAN_BUS_OFF:
898 /* bus-off state */
899 priv->can.state = CAN_STATE_BUS_OFF;
900 priv->can.can_stats.bus_off++;
901 break;
902 default:
903 break;
904 }
905
906 /* propagate the error condition to the CAN stack */
907 skb = alloc_can_err_skb(dev, &cf);
908 if (unlikely(!skb))
909 return 0;
910
911 __c_can_get_berr_counter(dev, &bec);
912 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
913 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
914 ERR_CNT_RP_SHIFT;
915
916 switch (error_type) {
917 case C_CAN_NO_ERROR:
918 /* error warning state */
919 cf->can_id |= CAN_ERR_CRTL;
920 cf->data[1] = CAN_ERR_CRTL_ACTIVE;
921 cf->data[6] = bec.txerr;
922 cf->data[7] = bec.rxerr;
923 break;
924 case C_CAN_ERROR_WARNING:
925 /* error warning state */
926 cf->can_id |= CAN_ERR_CRTL;
927 cf->data[1] = (bec.txerr > bec.rxerr) ?
928 CAN_ERR_CRTL_TX_WARNING :
929 CAN_ERR_CRTL_RX_WARNING;
930 cf->data[6] = bec.txerr;
931 cf->data[7] = bec.rxerr;
932
933 break;
934 case C_CAN_ERROR_PASSIVE:
935 /* error passive state */
936 cf->can_id |= CAN_ERR_CRTL;
937 if (rx_err_passive)
938 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
939 if (bec.txerr > 127)
940 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
941
942 cf->data[6] = bec.txerr;
943 cf->data[7] = bec.rxerr;
944 break;
945 case C_CAN_BUS_OFF:
946 /* bus-off state */
947 cf->can_id |= CAN_ERR_BUSOFF;
948 can_bus_off(dev);
949 break;
950 default:
951 break;
952 }
953
954 stats->rx_packets++;
955 stats->rx_bytes += cf->len;
956 netif_receive_skb(skb);
957
958 return 1;
959}
960
961static int c_can_handle_bus_err(struct net_device *dev,
962 enum c_can_lec_type lec_type)
963{
964 struct c_can_priv *priv = netdev_priv(dev);
965 struct net_device_stats *stats = &dev->stats;
966 struct can_frame *cf;
967 struct sk_buff *skb;
968
969 /* early exit if no lec update or no error.
970 * no lec update means that no CAN bus event has been detected
971 * since CPU wrote 0x7 value to status reg.
972 */
973 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
974 return 0;
975
976 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
977 return 0;
978
979 /* common for all type of bus errors */
980 priv->can.can_stats.bus_error++;
981 stats->rx_errors++;
982
983 /* propagate the error condition to the CAN stack */
984 skb = alloc_can_err_skb(dev, &cf);
985 if (unlikely(!skb))
986 return 0;
987
988 /* check for 'last error code' which tells us the
989 * type of the last error to occur on the CAN bus
990 */
991 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
992
993 switch (lec_type) {
994 case LEC_STUFF_ERROR:
995 netdev_dbg(dev, "stuff error\n");
996 cf->data[2] |= CAN_ERR_PROT_STUFF;
997 break;
998 case LEC_FORM_ERROR:
999 netdev_dbg(dev, "form error\n");
1000 cf->data[2] |= CAN_ERR_PROT_FORM;
1001 break;
1002 case LEC_ACK_ERROR:
1003 netdev_dbg(dev, "ack error\n");
1004 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1005 break;
1006 case LEC_BIT1_ERROR:
1007 netdev_dbg(dev, "bit1 error\n");
1008 cf->data[2] |= CAN_ERR_PROT_BIT1;
1009 break;
1010 case LEC_BIT0_ERROR:
1011 netdev_dbg(dev, "bit0 error\n");
1012 cf->data[2] |= CAN_ERR_PROT_BIT0;
1013 break;
1014 case LEC_CRC_ERROR:
1015 netdev_dbg(dev, "CRC error\n");
1016 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1017 break;
1018 default:
1019 break;
1020 }
1021
1022 stats->rx_packets++;
1023 stats->rx_bytes += cf->len;
1024 netif_receive_skb(skb);
1025 return 1;
1026}
1027
1028static int c_can_poll(struct napi_struct *napi, int quota)
1029{
1030 struct net_device *dev = napi->dev;
1031 struct c_can_priv *priv = netdev_priv(dev);
1032 u16 curr, last = priv->last_status;
1033 int work_done = 0;
1034
1035 /* Only read the status register if a status interrupt was pending */
1036 if (atomic_xchg(&priv->sie_pending, 0)) {
1037 priv->last_status = priv->read_reg(priv, C_CAN_STS_REG);
1038 curr = priv->last_status;
1039 /* Ack status on C_CAN. D_CAN is self clearing */
1040 if (priv->type != BOSCH_D_CAN)
1041 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1042 } else {
1043 /* no change detected ... */
1044 curr = last;
1045 }
1046
1047 /* handle state changes */
1048 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1049 netdev_dbg(dev, "entered error warning state\n");
1050 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1051 }
1052
1053 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1054 netdev_dbg(dev, "entered error passive state\n");
1055 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1056 }
1057
1058 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1059 netdev_dbg(dev, "entered bus off state\n");
1060 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1061 goto end;
1062 }
1063
1064 /* handle bus recovery events */
1065 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1066 netdev_dbg(dev, "left bus off state\n");
1067 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1068 }
1069
1070 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1071 netdev_dbg(dev, "left error passive state\n");
1072 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1073 }
1074
1075 if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) {
1076 netdev_dbg(dev, "left error warning state\n");
1077 work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR);
1078 }
1079
1080 /* handle lec errors on the bus */
1081 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1082
1083 /* Handle Tx/Rx events. We do this unconditionally */
1084 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1085 c_can_do_tx(dev);
1086
1087end:
1088 if (work_done < quota) {
1089 napi_complete_done(napi, work_done);
1090 /* enable all IRQs if we are not in bus off state */
1091 if (priv->can.state != CAN_STATE_BUS_OFF)
1092 c_can_irq_control(priv, true);
1093 }
1094
1095 return work_done;
1096}
1097
1098static irqreturn_t c_can_isr(int irq, void *dev_id)
1099{
1100 struct net_device *dev = (struct net_device *)dev_id;
1101 struct c_can_priv *priv = netdev_priv(dev);
1102 int reg_int;
1103
1104 reg_int = priv->read_reg(priv, C_CAN_INT_REG);
1105 if (!reg_int)
1106 return IRQ_NONE;
1107
1108 /* save for later use */
1109 if (reg_int & INT_STS_PENDING)
1110 atomic_set(&priv->sie_pending, 1);
1111
1112 /* disable all interrupts and schedule the NAPI */
1113 c_can_irq_control(priv, false);
1114 napi_schedule(&priv->napi);
1115
1116 return IRQ_HANDLED;
1117}
1118
1119static int c_can_open(struct net_device *dev)
1120{
1121 int err;
1122 struct c_can_priv *priv = netdev_priv(dev);
1123
1124 c_can_pm_runtime_get_sync(priv);
1125 c_can_reset_ram(priv, true);
1126
1127 /* open the can device */
1128 err = open_candev(dev);
1129 if (err) {
1130 netdev_err(dev, "failed to open can device\n");
1131 goto exit_open_fail;
1132 }
1133
1134 /* register interrupt handler */
1135 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1136 dev);
1137 if (err < 0) {
1138 netdev_err(dev, "failed to request interrupt\n");
1139 goto exit_irq_fail;
1140 }
1141
1142 /* start the c_can controller */
1143 err = c_can_start(dev);
1144 if (err)
1145 goto exit_start_fail;
1146
1147 can_led_event(dev, CAN_LED_EVENT_OPEN);
1148
1149 napi_enable(&priv->napi);
1150 /* enable status change, error and module interrupts */
1151 c_can_irq_control(priv, true);
1152 netif_start_queue(dev);
1153
1154 return 0;
1155
1156exit_start_fail:
1157 free_irq(dev->irq, dev);
1158exit_irq_fail:
1159 close_candev(dev);
1160exit_open_fail:
1161 c_can_reset_ram(priv, false);
1162 c_can_pm_runtime_put_sync(priv);
1163 return err;
1164}
1165
1166static int c_can_close(struct net_device *dev)
1167{
1168 struct c_can_priv *priv = netdev_priv(dev);
1169
1170 netif_stop_queue(dev);
1171 napi_disable(&priv->napi);
1172 c_can_stop(dev);
1173 free_irq(dev->irq, dev);
1174 close_candev(dev);
1175
1176 c_can_reset_ram(priv, false);
1177 c_can_pm_runtime_put_sync(priv);
1178
1179 can_led_event(dev, CAN_LED_EVENT_STOP);
1180
1181 return 0;
1182}
1183
1184struct net_device *alloc_c_can_dev(int msg_obj_num)
1185{
1186 struct net_device *dev;
1187 struct c_can_priv *priv;
1188 int msg_obj_tx_num = msg_obj_num / 2;
1189
1190 dev = alloc_candev(struct_size(priv, dlc, msg_obj_tx_num),
1191 msg_obj_tx_num);
1192 if (!dev)
1193 return NULL;
1194
1195 priv = netdev_priv(dev);
1196 priv->msg_obj_num = msg_obj_num;
1197 priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num;
1198 priv->msg_obj_rx_first = 1;
1199 priv->msg_obj_rx_last =
1200 priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1;
1201 priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0);
1202
1203 priv->msg_obj_tx_num = msg_obj_tx_num;
1204 priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1;
1205 priv->msg_obj_tx_last =
1206 priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1;
1207
1208 netif_napi_add(dev, &priv->napi, c_can_poll, priv->msg_obj_rx_num);
1209
1210 priv->dev = dev;
1211 priv->can.bittiming_const = &c_can_bittiming_const;
1212 priv->can.do_set_mode = c_can_set_mode;
1213 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1214 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1215 CAN_CTRLMODE_LISTENONLY |
1216 CAN_CTRLMODE_BERR_REPORTING;
1217
1218 return dev;
1219}
1220EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1221
1222#ifdef CONFIG_PM
1223int c_can_power_down(struct net_device *dev)
1224{
1225 u32 val;
1226 unsigned long time_out;
1227 struct c_can_priv *priv = netdev_priv(dev);
1228
1229 if (!(dev->flags & IFF_UP))
1230 return 0;
1231
1232 WARN_ON(priv->type != BOSCH_D_CAN);
1233
1234 /* set PDR value so the device goes to power down mode */
1235 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1236 val |= CONTROL_EX_PDR;
1237 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1238
1239 /* Wait for the PDA bit to get set */
1240 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1241 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1242 time_after(time_out, jiffies))
1243 cpu_relax();
1244
1245 if (time_after(jiffies, time_out))
1246 return -ETIMEDOUT;
1247
1248 c_can_stop(dev);
1249
1250 c_can_reset_ram(priv, false);
1251 c_can_pm_runtime_put_sync(priv);
1252
1253 return 0;
1254}
1255EXPORT_SYMBOL_GPL(c_can_power_down);
1256
1257int c_can_power_up(struct net_device *dev)
1258{
1259 u32 val;
1260 unsigned long time_out;
1261 struct c_can_priv *priv = netdev_priv(dev);
1262 int ret;
1263
1264 if (!(dev->flags & IFF_UP))
1265 return 0;
1266
1267 WARN_ON(priv->type != BOSCH_D_CAN);
1268
1269 c_can_pm_runtime_get_sync(priv);
1270 c_can_reset_ram(priv, true);
1271
1272 /* Clear PDR and INIT bits */
1273 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1274 val &= ~CONTROL_EX_PDR;
1275 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1276 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1277 val &= ~CONTROL_INIT;
1278 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1279
1280 /* Wait for the PDA bit to get clear */
1281 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1282 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1283 time_after(time_out, jiffies))
1284 cpu_relax();
1285
1286 if (time_after(jiffies, time_out)) {
1287 ret = -ETIMEDOUT;
1288 goto err_out;
1289 }
1290
1291 ret = c_can_start(dev);
1292 if (ret)
1293 goto err_out;
1294
1295 c_can_irq_control(priv, true);
1296
1297 return 0;
1298
1299err_out:
1300 c_can_reset_ram(priv, false);
1301 c_can_pm_runtime_put_sync(priv);
1302
1303 return ret;
1304}
1305EXPORT_SYMBOL_GPL(c_can_power_up);
1306#endif
1307
1308void free_c_can_dev(struct net_device *dev)
1309{
1310 struct c_can_priv *priv = netdev_priv(dev);
1311
1312 netif_napi_del(&priv->napi);
1313 free_candev(dev);
1314}
1315EXPORT_SYMBOL_GPL(free_c_can_dev);
1316
1317static const struct net_device_ops c_can_netdev_ops = {
1318 .ndo_open = c_can_open,
1319 .ndo_stop = c_can_close,
1320 .ndo_start_xmit = c_can_start_xmit,
1321 .ndo_change_mtu = can_change_mtu,
1322};
1323
1324int register_c_can_dev(struct net_device *dev)
1325{
1326 int err;
1327
1328 /* Deactivate pins to prevent DRA7 DCAN IP from being
1329 * stuck in transition when module is disabled.
1330 * Pins are activated in c_can_start() and deactivated
1331 * in c_can_stop()
1332 */
1333 pinctrl_pm_select_sleep_state(dev->dev.parent);
1334
1335 dev->flags |= IFF_ECHO; /* we support local echo */
1336 dev->netdev_ops = &c_can_netdev_ops;
1337 c_can_set_ethtool_ops(dev);
1338
1339 err = register_candev(dev);
1340 if (!err)
1341 devm_can_led_init(dev);
1342 return err;
1343}
1344EXPORT_SYMBOL_GPL(register_c_can_dev);
1345
1346void unregister_c_can_dev(struct net_device *dev)
1347{
1348 unregister_candev(dev);
1349}
1350EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1351
1352MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1353MODULE_LICENSE("GPL v2");
1354MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");