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1/*
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <linux/aperture.h>
33#include <linux/compat.h>
34#include <linux/module.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
37#include <linux/mmu_notifier.h>
38#include <linux/pci.h>
39
40#include <drm/drm_client_setup.h>
41#include <drm/drm_drv.h>
42#include <drm/drm_file.h>
43#include <drm/drm_fourcc.h>
44#include <drm/drm_gem.h>
45#include <drm/drm_ioctl.h>
46#include <drm/drm_pciids.h>
47#include <drm/drm_probe_helper.h>
48#include <drm/drm_vblank.h>
49#include <drm/radeon_drm.h>
50
51#include "radeon_drv.h"
52#include "radeon.h"
53#include "radeon_kms.h"
54#include "radeon_ttm.h"
55#include "radeon_device.h"
56#include "radeon_prime.h"
57
58/*
59 * KMS wrapper.
60 * - 2.0.0 - initial interface
61 * - 2.1.0 - add square tiling interface
62 * - 2.2.0 - add r6xx/r7xx const buffer support
63 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
64 * - 2.4.0 - add crtc id query
65 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
66 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
67 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
68 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
69 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
70 * 2.10.0 - fusion 2D tiling
71 * 2.11.0 - backend map, initial compute support for the CS checker
72 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
73 * 2.13.0 - virtual memory support, streamout
74 * 2.14.0 - add evergreen tiling informations
75 * 2.15.0 - add max_pipes query
76 * 2.16.0 - fix evergreen 2D tiled surface calculation
77 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
78 * 2.18.0 - r600-eg: allow "invalid" DB formats
79 * 2.19.0 - r600-eg: MSAA textures
80 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
81 * 2.21.0 - r600-r700: FMASK and CMASK
82 * 2.22.0 - r600 only: RESOLVE_BOX allowed
83 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
84 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
85 * 2.25.0 - eg+: new info request for num SE and num SH
86 * 2.26.0 - r600-eg: fix htile size computation
87 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
88 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
89 * 2.29.0 - R500 FP16 color clear registers
90 * 2.30.0 - fix for FMASK texturing
91 * 2.31.0 - Add fastfb support for rs690
92 * 2.32.0 - new info request for rings working
93 * 2.33.0 - Add SI tiling mode array query
94 * 2.34.0 - Add CIK tiling mode array query
95 * 2.35.0 - Add CIK macrotile mode array query
96 * 2.36.0 - Fix CIK DCE tiling setup
97 * 2.37.0 - allow GS ring setup on r6xx/r7xx
98 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
99 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
100 * 2.39.0 - Add INFO query for number of active CUs
101 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
102 * CS to GPU on >= r600
103 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
104 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
105 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
106 * 2.44.0 - SET_APPEND_CNT packet3 support
107 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
108 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
109 * 2.47.0 - Add UVD_NO_OP register support
110 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
111 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
112 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
113 */
114#define KMS_DRIVER_MAJOR 2
115#define KMS_DRIVER_MINOR 50
116#define KMS_DRIVER_PATCHLEVEL 0
117
118int radeon_no_wb;
119int radeon_modeset = -1;
120int radeon_dynclks = -1;
121int radeon_r4xx_atom;
122int radeon_agpmode = -1;
123int radeon_vram_limit;
124int radeon_gart_size = -1; /* auto */
125int radeon_benchmarking;
126int radeon_testing;
127int radeon_connector_table;
128int radeon_tv = 1;
129int radeon_audio = -1;
130int radeon_disp_priority;
131int radeon_hw_i2c;
132int radeon_pcie_gen2 = -1;
133int radeon_msi = -1;
134int radeon_lockup_timeout = 10000;
135int radeon_fastfb;
136int radeon_dpm = -1;
137int radeon_aspm = -1;
138int radeon_runtime_pm = -1;
139int radeon_hard_reset;
140int radeon_vm_size = 8;
141int radeon_vm_block_size = -1;
142int radeon_deep_color;
143int radeon_use_pflipirq = 2;
144int radeon_bapm = -1;
145int radeon_backlight = -1;
146int radeon_auxch = -1;
147int radeon_uvd = 1;
148int radeon_vce = 1;
149
150MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
151module_param_named(no_wb, radeon_no_wb, int, 0444);
152
153MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
154module_param_named(modeset, radeon_modeset, int, 0400);
155
156MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
157module_param_named(dynclks, radeon_dynclks, int, 0444);
158
159MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
160module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
161
162MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
163module_param_named(vramlimit, radeon_vram_limit, int, 0600);
164
165MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
166module_param_named(agpmode, radeon_agpmode, int, 0444);
167
168MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
169module_param_named(gartsize, radeon_gart_size, int, 0600);
170
171MODULE_PARM_DESC(benchmark, "Run benchmark");
172module_param_named(benchmark, radeon_benchmarking, int, 0444);
173
174MODULE_PARM_DESC(test, "Run tests");
175module_param_named(test, radeon_testing, int, 0444);
176
177MODULE_PARM_DESC(connector_table, "Force connector table");
178module_param_named(connector_table, radeon_connector_table, int, 0444);
179
180MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
181module_param_named(tv, radeon_tv, int, 0444);
182
183MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
184module_param_named(audio, radeon_audio, int, 0444);
185
186MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
187module_param_named(disp_priority, radeon_disp_priority, int, 0444);
188
189MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
190module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
191
192MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
193module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
194
195MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
196module_param_named(msi, radeon_msi, int, 0444);
197
198MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
199module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
200
201MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
202module_param_named(fastfb, radeon_fastfb, int, 0444);
203
204MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
205module_param_named(dpm, radeon_dpm, int, 0444);
206
207MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
208module_param_named(aspm, radeon_aspm, int, 0444);
209
210MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
211module_param_named(runpm, radeon_runtime_pm, int, 0444);
212
213MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
214module_param_named(hard_reset, radeon_hard_reset, int, 0444);
215
216MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
217module_param_named(vm_size, radeon_vm_size, int, 0444);
218
219MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
220module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
221
222MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
223module_param_named(deep_color, radeon_deep_color, int, 0444);
224
225MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
226module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
227
228MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
229module_param_named(bapm, radeon_bapm, int, 0444);
230
231MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
232module_param_named(backlight, radeon_backlight, int, 0444);
233
234MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
235module_param_named(auxch, radeon_auxch, int, 0444);
236
237MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
238module_param_named(uvd, radeon_uvd, int, 0444);
239
240MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
241module_param_named(vce, radeon_vce, int, 0444);
242
243int radeon_si_support = 1;
244MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
245module_param_named(si_support, radeon_si_support, int, 0444);
246
247int radeon_cik_support = 1;
248MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
249module_param_named(cik_support, radeon_cik_support, int, 0444);
250
251static const struct pci_device_id pciidlist[] = {
252 radeon_PCI_IDS
253};
254MODULE_DEVICE_TABLE(pci, pciidlist);
255
256static const struct drm_driver kms_driver;
257
258static int radeon_pci_probe(struct pci_dev *pdev,
259 const struct pci_device_id *ent)
260{
261 unsigned long flags = 0;
262 struct drm_device *ddev;
263 struct radeon_device *rdev;
264 const struct drm_format_info *format;
265 int ret;
266
267 if (!ent)
268 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
269
270 flags = ent->driver_data;
271
272 if (!radeon_si_support) {
273 switch (flags & RADEON_FAMILY_MASK) {
274 case CHIP_TAHITI:
275 case CHIP_PITCAIRN:
276 case CHIP_VERDE:
277 case CHIP_OLAND:
278 case CHIP_HAINAN:
279 dev_info(&pdev->dev,
280 "SI support disabled by module param\n");
281 return -ENODEV;
282 }
283 }
284 if (!radeon_cik_support) {
285 switch (flags & RADEON_FAMILY_MASK) {
286 case CHIP_KAVERI:
287 case CHIP_BONAIRE:
288 case CHIP_HAWAII:
289 case CHIP_KABINI:
290 case CHIP_MULLINS:
291 dev_info(&pdev->dev,
292 "CIK support disabled by module param\n");
293 return -ENODEV;
294 }
295 }
296
297 if (vga_switcheroo_client_probe_defer(pdev))
298 return -EPROBE_DEFER;
299
300 /* Get rid of things like offb */
301 ret = aperture_remove_conflicting_pci_devices(pdev, kms_driver.name);
302 if (ret)
303 return ret;
304
305 rdev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*rdev), ddev);
306 if (IS_ERR(rdev))
307 return PTR_ERR(rdev);
308
309 rdev->dev = &pdev->dev;
310 rdev->pdev = pdev;
311 ddev = rdev_to_drm(rdev);
312 ddev->dev_private = rdev;
313
314 ret = pci_enable_device(pdev);
315 if (ret)
316 goto err_free;
317
318 pci_set_drvdata(pdev, ddev);
319
320 ret = radeon_driver_load_kms(ddev, flags);
321 if (ret)
322 goto err_agp;
323
324 ret = drm_dev_register(ddev, flags);
325 if (ret)
326 goto err_agp;
327
328 if (rdev->mc.real_vram_size <= (8 * 1024 * 1024))
329 format = drm_format_info(DRM_FORMAT_C8);
330 else if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32 * 1024 * 1024))
331 format = drm_format_info(DRM_FORMAT_RGB565);
332 else
333 format = NULL;
334
335 drm_client_setup(ddev, format);
336
337 return 0;
338
339err_agp:
340 pci_disable_device(pdev);
341err_free:
342 drm_dev_put(ddev);
343 return ret;
344}
345
346static void
347radeon_pci_remove(struct pci_dev *pdev)
348{
349 struct drm_device *dev = pci_get_drvdata(pdev);
350
351 drm_put_dev(dev);
352}
353
354static void
355radeon_pci_shutdown(struct pci_dev *pdev)
356{
357 /* if we are running in a VM, make sure the device
358 * torn down properly on reboot/shutdown
359 */
360 if (radeon_device_is_virtual())
361 radeon_pci_remove(pdev);
362
363#if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
364 /*
365 * Some adapters need to be suspended before a
366 * shutdown occurs in order to prevent an error
367 * during kexec, shutdown or reboot.
368 * Make this power and Loongson specific because
369 * it breaks some other boards.
370 */
371 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
372#endif
373}
374
375static int radeon_pmops_suspend(struct device *dev)
376{
377 struct drm_device *drm_dev = dev_get_drvdata(dev);
378
379 return radeon_suspend_kms(drm_dev, true, true, false);
380}
381
382static int radeon_pmops_resume(struct device *dev)
383{
384 struct drm_device *drm_dev = dev_get_drvdata(dev);
385
386 /* GPU comes up enabled by the bios on resume */
387 if (radeon_is_px(drm_dev)) {
388 pm_runtime_disable(dev);
389 pm_runtime_set_active(dev);
390 pm_runtime_enable(dev);
391 }
392
393 return radeon_resume_kms(drm_dev, true, true);
394}
395
396static int radeon_pmops_freeze(struct device *dev)
397{
398 struct drm_device *drm_dev = dev_get_drvdata(dev);
399
400 return radeon_suspend_kms(drm_dev, false, true, true);
401}
402
403static int radeon_pmops_thaw(struct device *dev)
404{
405 struct drm_device *drm_dev = dev_get_drvdata(dev);
406
407 return radeon_resume_kms(drm_dev, false, true);
408}
409
410static int radeon_pmops_runtime_suspend(struct device *dev)
411{
412 struct pci_dev *pdev = to_pci_dev(dev);
413 struct drm_device *drm_dev = pci_get_drvdata(pdev);
414
415 if (!radeon_is_px(drm_dev)) {
416 pm_runtime_forbid(dev);
417 return -EBUSY;
418 }
419
420 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
421 drm_kms_helper_poll_disable(drm_dev);
422
423 radeon_suspend_kms(drm_dev, false, false, false);
424 pci_save_state(pdev);
425 pci_disable_device(pdev);
426 pci_ignore_hotplug(pdev);
427 if (radeon_is_atpx_hybrid())
428 pci_set_power_state(pdev, PCI_D3cold);
429 else if (!radeon_has_atpx_dgpu_power_cntl())
430 pci_set_power_state(pdev, PCI_D3hot);
431 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
432
433 return 0;
434}
435
436static int radeon_pmops_runtime_resume(struct device *dev)
437{
438 struct pci_dev *pdev = to_pci_dev(dev);
439 struct drm_device *drm_dev = pci_get_drvdata(pdev);
440 int ret;
441
442 if (!radeon_is_px(drm_dev))
443 return -EINVAL;
444
445 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
446
447 if (radeon_is_atpx_hybrid() ||
448 !radeon_has_atpx_dgpu_power_cntl())
449 pci_set_power_state(pdev, PCI_D0);
450 pci_restore_state(pdev);
451 ret = pci_enable_device(pdev);
452 if (ret)
453 return ret;
454 pci_set_master(pdev);
455
456 ret = radeon_resume_kms(drm_dev, false, false);
457 drm_kms_helper_poll_enable(drm_dev);
458 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
459 return 0;
460}
461
462static int radeon_pmops_runtime_idle(struct device *dev)
463{
464 struct drm_device *drm_dev = dev_get_drvdata(dev);
465 struct drm_crtc *crtc;
466
467 if (!radeon_is_px(drm_dev)) {
468 pm_runtime_forbid(dev);
469 return -EBUSY;
470 }
471
472 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
473 if (crtc->enabled) {
474 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
475 return -EBUSY;
476 }
477 }
478
479 pm_runtime_mark_last_busy(dev);
480 pm_runtime_autosuspend(dev);
481 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
482 return 1;
483}
484
485long radeon_drm_ioctl(struct file *filp,
486 unsigned int cmd, unsigned long arg)
487{
488 struct drm_file *file_priv = filp->private_data;
489 struct drm_device *dev;
490 long ret;
491
492 dev = file_priv->minor->dev;
493 ret = pm_runtime_get_sync(dev->dev);
494 if (ret < 0) {
495 pm_runtime_put_autosuspend(dev->dev);
496 return ret;
497 }
498
499 ret = drm_ioctl(filp, cmd, arg);
500
501 pm_runtime_mark_last_busy(dev->dev);
502 pm_runtime_put_autosuspend(dev->dev);
503 return ret;
504}
505
506#ifdef CONFIG_COMPAT
507static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
508{
509 unsigned int nr = DRM_IOCTL_NR(cmd);
510
511 if (nr < DRM_COMMAND_BASE)
512 return drm_compat_ioctl(filp, cmd, arg);
513
514 return radeon_drm_ioctl(filp, cmd, arg);
515}
516#endif
517
518static const struct dev_pm_ops radeon_pm_ops = {
519 .suspend = radeon_pmops_suspend,
520 .resume = radeon_pmops_resume,
521 .freeze = radeon_pmops_freeze,
522 .thaw = radeon_pmops_thaw,
523 .poweroff = radeon_pmops_freeze,
524 .restore = radeon_pmops_resume,
525 .runtime_suspend = radeon_pmops_runtime_suspend,
526 .runtime_resume = radeon_pmops_runtime_resume,
527 .runtime_idle = radeon_pmops_runtime_idle,
528};
529
530static const struct file_operations radeon_driver_kms_fops = {
531 .owner = THIS_MODULE,
532 .open = drm_open,
533 .release = drm_release,
534 .unlocked_ioctl = radeon_drm_ioctl,
535 .mmap = drm_gem_mmap,
536 .poll = drm_poll,
537 .read = drm_read,
538#ifdef CONFIG_COMPAT
539 .compat_ioctl = radeon_kms_compat_ioctl,
540#endif
541 .fop_flags = FOP_UNSIGNED_OFFSET,
542};
543
544static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
545 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
546 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
547 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
548 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
549 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
550 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
551 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
552 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
553 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
554 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
555 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
556 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
557 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
558 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
559 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
560 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
561 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
562 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
563 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
564 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
565 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
566 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
567 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
568 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
569 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
570 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
571 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
572 /* KMS */
573 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
574 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
575 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
576 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
577 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
578 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
579 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
580 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
581 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
582 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
583 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
584 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
585 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
586};
587
588static const struct drm_driver kms_driver = {
589 .driver_features =
590 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
591 .open = radeon_driver_open_kms,
592 .postclose = radeon_driver_postclose_kms,
593 .unload = radeon_driver_unload_kms,
594 .ioctls = radeon_ioctls_kms,
595 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
596 .dumb_create = radeon_mode_dumb_create,
597 .dumb_map_offset = radeon_mode_dumb_mmap,
598 .fops = &radeon_driver_kms_fops,
599
600 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
601
602 RADEON_FBDEV_DRIVER_OPS,
603
604 .name = DRIVER_NAME,
605 .desc = DRIVER_DESC,
606 .date = DRIVER_DATE,
607 .major = KMS_DRIVER_MAJOR,
608 .minor = KMS_DRIVER_MINOR,
609 .patchlevel = KMS_DRIVER_PATCHLEVEL,
610};
611
612static struct pci_driver radeon_kms_pci_driver = {
613 .name = DRIVER_NAME,
614 .id_table = pciidlist,
615 .probe = radeon_pci_probe,
616 .remove = radeon_pci_remove,
617 .shutdown = radeon_pci_shutdown,
618 .driver.pm = &radeon_pm_ops,
619};
620
621static int __init radeon_module_init(void)
622{
623 if (drm_firmware_drivers_only() && radeon_modeset == -1)
624 radeon_modeset = 0;
625
626 if (radeon_modeset == 0)
627 return -EINVAL;
628
629 DRM_INFO("radeon kernel modesetting enabled.\n");
630 radeon_register_atpx_handler();
631
632 return pci_register_driver(&radeon_kms_pci_driver);
633}
634
635static void __exit radeon_module_exit(void)
636{
637 pci_unregister_driver(&radeon_kms_pci_driver);
638 radeon_unregister_atpx_handler();
639 mmu_notifier_synchronize();
640}
641
642module_init(radeon_module_init);
643module_exit(radeon_module_exit);
644
645MODULE_AUTHOR(DRIVER_AUTHOR);
646MODULE_DESCRIPTION(DRIVER_DESC);
647MODULE_LICENSE("GPL and additional rights");
1/*
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32
33#include <linux/compat.h>
34#include <linux/console.h>
35#include <linux/module.h>
36#include <linux/pm_runtime.h>
37#include <linux/vga_switcheroo.h>
38#include <linux/mmu_notifier.h>
39#include <linux/pci.h>
40
41#include <drm/drm_aperture.h>
42#include <drm/drm_crtc_helper.h>
43#include <drm/drm_drv.h>
44#include <drm/drm_fb_helper.h>
45#include <drm/drm_file.h>
46#include <drm/drm_gem.h>
47#include <drm/drm_ioctl.h>
48#include <drm/drm_pciids.h>
49#include <drm/drm_probe_helper.h>
50#include <drm/drm_vblank.h>
51#include <drm/radeon_drm.h>
52
53#include "radeon_drv.h"
54#include "radeon.h"
55#include "radeon_kms.h"
56#include "radeon_ttm.h"
57#include "radeon_device.h"
58#include "radeon_prime.h"
59
60/*
61 * KMS wrapper.
62 * - 2.0.0 - initial interface
63 * - 2.1.0 - add square tiling interface
64 * - 2.2.0 - add r6xx/r7xx const buffer support
65 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
66 * - 2.4.0 - add crtc id query
67 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
68 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
69 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
70 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
71 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
72 * 2.10.0 - fusion 2D tiling
73 * 2.11.0 - backend map, initial compute support for the CS checker
74 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
75 * 2.13.0 - virtual memory support, streamout
76 * 2.14.0 - add evergreen tiling informations
77 * 2.15.0 - add max_pipes query
78 * 2.16.0 - fix evergreen 2D tiled surface calculation
79 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
80 * 2.18.0 - r600-eg: allow "invalid" DB formats
81 * 2.19.0 - r600-eg: MSAA textures
82 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
83 * 2.21.0 - r600-r700: FMASK and CMASK
84 * 2.22.0 - r600 only: RESOLVE_BOX allowed
85 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
86 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
87 * 2.25.0 - eg+: new info request for num SE and num SH
88 * 2.26.0 - r600-eg: fix htile size computation
89 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
90 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
91 * 2.29.0 - R500 FP16 color clear registers
92 * 2.30.0 - fix for FMASK texturing
93 * 2.31.0 - Add fastfb support for rs690
94 * 2.32.0 - new info request for rings working
95 * 2.33.0 - Add SI tiling mode array query
96 * 2.34.0 - Add CIK tiling mode array query
97 * 2.35.0 - Add CIK macrotile mode array query
98 * 2.36.0 - Fix CIK DCE tiling setup
99 * 2.37.0 - allow GS ring setup on r6xx/r7xx
100 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
101 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
102 * 2.39.0 - Add INFO query for number of active CUs
103 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
104 * CS to GPU on >= r600
105 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
106 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
107 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
108 * 2.44.0 - SET_APPEND_CNT packet3 support
109 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
110 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
111 * 2.47.0 - Add UVD_NO_OP register support
112 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
113 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
114 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
115 */
116#define KMS_DRIVER_MAJOR 2
117#define KMS_DRIVER_MINOR 50
118#define KMS_DRIVER_PATCHLEVEL 0
119int radeon_suspend_kms(struct drm_device *dev, bool suspend,
120 bool fbcon, bool freeze);
121int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
122extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
123 unsigned int flags, int *vpos, int *hpos,
124 ktime_t *stime, ktime_t *etime,
125 const struct drm_display_mode *mode);
126extern bool radeon_is_px(struct drm_device *dev);
127int radeon_mode_dumb_mmap(struct drm_file *filp,
128 struct drm_device *dev,
129 uint32_t handle, uint64_t *offset_p);
130int radeon_mode_dumb_create(struct drm_file *file_priv,
131 struct drm_device *dev,
132 struct drm_mode_create_dumb *args);
133
134/* atpx handler */
135#if defined(CONFIG_VGA_SWITCHEROO)
136void radeon_register_atpx_handler(void);
137void radeon_unregister_atpx_handler(void);
138bool radeon_has_atpx_dgpu_power_cntl(void);
139bool radeon_is_atpx_hybrid(void);
140#else
141static inline void radeon_register_atpx_handler(void) {}
142static inline void radeon_unregister_atpx_handler(void) {}
143static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
144static inline bool radeon_is_atpx_hybrid(void) { return false; }
145#endif
146
147int radeon_no_wb;
148int radeon_modeset = -1;
149int radeon_dynclks = -1;
150int radeon_r4xx_atom = 0;
151int radeon_agpmode = -1;
152int radeon_vram_limit = 0;
153int radeon_gart_size = -1; /* auto */
154int radeon_benchmarking = 0;
155int radeon_testing = 0;
156int radeon_connector_table = 0;
157int radeon_tv = 1;
158int radeon_audio = -1;
159int radeon_disp_priority = 0;
160int radeon_hw_i2c = 0;
161int radeon_pcie_gen2 = -1;
162int radeon_msi = -1;
163int radeon_lockup_timeout = 10000;
164int radeon_fastfb = 0;
165int radeon_dpm = -1;
166int radeon_aspm = -1;
167int radeon_runtime_pm = -1;
168int radeon_hard_reset = 0;
169int radeon_vm_size = 8;
170int radeon_vm_block_size = -1;
171int radeon_deep_color = 0;
172int radeon_use_pflipirq = 2;
173int radeon_bapm = -1;
174int radeon_backlight = -1;
175int radeon_auxch = -1;
176int radeon_mst = 0;
177int radeon_uvd = 1;
178int radeon_vce = 1;
179
180MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
181module_param_named(no_wb, radeon_no_wb, int, 0444);
182
183MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
184module_param_named(modeset, radeon_modeset, int, 0400);
185
186MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
187module_param_named(dynclks, radeon_dynclks, int, 0444);
188
189MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
190module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
191
192MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
193module_param_named(vramlimit, radeon_vram_limit, int, 0600);
194
195MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
196module_param_named(agpmode, radeon_agpmode, int, 0444);
197
198MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
199module_param_named(gartsize, radeon_gart_size, int, 0600);
200
201MODULE_PARM_DESC(benchmark, "Run benchmark");
202module_param_named(benchmark, radeon_benchmarking, int, 0444);
203
204MODULE_PARM_DESC(test, "Run tests");
205module_param_named(test, radeon_testing, int, 0444);
206
207MODULE_PARM_DESC(connector_table, "Force connector table");
208module_param_named(connector_table, radeon_connector_table, int, 0444);
209
210MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
211module_param_named(tv, radeon_tv, int, 0444);
212
213MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
214module_param_named(audio, radeon_audio, int, 0444);
215
216MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
217module_param_named(disp_priority, radeon_disp_priority, int, 0444);
218
219MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
220module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
221
222MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
223module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
224
225MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
226module_param_named(msi, radeon_msi, int, 0444);
227
228MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
229module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
230
231MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
232module_param_named(fastfb, radeon_fastfb, int, 0444);
233
234MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
235module_param_named(dpm, radeon_dpm, int, 0444);
236
237MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
238module_param_named(aspm, radeon_aspm, int, 0444);
239
240MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
241module_param_named(runpm, radeon_runtime_pm, int, 0444);
242
243MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
244module_param_named(hard_reset, radeon_hard_reset, int, 0444);
245
246MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
247module_param_named(vm_size, radeon_vm_size, int, 0444);
248
249MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
250module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
251
252MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
253module_param_named(deep_color, radeon_deep_color, int, 0444);
254
255MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
256module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
257
258MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
259module_param_named(bapm, radeon_bapm, int, 0444);
260
261MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
262module_param_named(backlight, radeon_backlight, int, 0444);
263
264MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
265module_param_named(auxch, radeon_auxch, int, 0444);
266
267MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
268module_param_named(mst, radeon_mst, int, 0444);
269
270MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
271module_param_named(uvd, radeon_uvd, int, 0444);
272
273MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
274module_param_named(vce, radeon_vce, int, 0444);
275
276int radeon_si_support = 1;
277MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
278module_param_named(si_support, radeon_si_support, int, 0444);
279
280int radeon_cik_support = 1;
281MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
282module_param_named(cik_support, radeon_cik_support, int, 0444);
283
284static struct pci_device_id pciidlist[] = {
285 radeon_PCI_IDS
286};
287
288MODULE_DEVICE_TABLE(pci, pciidlist);
289
290static const struct drm_driver kms_driver;
291
292static int radeon_pci_probe(struct pci_dev *pdev,
293 const struct pci_device_id *ent)
294{
295 unsigned long flags = 0;
296 struct drm_device *dev;
297 int ret;
298
299 if (!ent)
300 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
301
302 flags = ent->driver_data;
303
304 if (!radeon_si_support) {
305 switch (flags & RADEON_FAMILY_MASK) {
306 case CHIP_TAHITI:
307 case CHIP_PITCAIRN:
308 case CHIP_VERDE:
309 case CHIP_OLAND:
310 case CHIP_HAINAN:
311 dev_info(&pdev->dev,
312 "SI support disabled by module param\n");
313 return -ENODEV;
314 }
315 }
316 if (!radeon_cik_support) {
317 switch (flags & RADEON_FAMILY_MASK) {
318 case CHIP_KAVERI:
319 case CHIP_BONAIRE:
320 case CHIP_HAWAII:
321 case CHIP_KABINI:
322 case CHIP_MULLINS:
323 dev_info(&pdev->dev,
324 "CIK support disabled by module param\n");
325 return -ENODEV;
326 }
327 }
328
329 if (vga_switcheroo_client_probe_defer(pdev))
330 return -EPROBE_DEFER;
331
332 /* Get rid of things like offb */
333 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb");
334 if (ret)
335 return ret;
336
337 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
338 if (IS_ERR(dev))
339 return PTR_ERR(dev);
340
341 ret = pci_enable_device(pdev);
342 if (ret)
343 goto err_free;
344
345 pci_set_drvdata(pdev, dev);
346
347 ret = drm_dev_register(dev, ent->driver_data);
348 if (ret)
349 goto err_agp;
350
351 return 0;
352
353err_agp:
354 pci_disable_device(pdev);
355err_free:
356 drm_dev_put(dev);
357 return ret;
358}
359
360static void
361radeon_pci_remove(struct pci_dev *pdev)
362{
363 struct drm_device *dev = pci_get_drvdata(pdev);
364
365 drm_put_dev(dev);
366}
367
368static void
369radeon_pci_shutdown(struct pci_dev *pdev)
370{
371 /* if we are running in a VM, make sure the device
372 * torn down properly on reboot/shutdown
373 */
374 if (radeon_device_is_virtual())
375 radeon_pci_remove(pdev);
376
377#if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
378 /*
379 * Some adapters need to be suspended before a
380 * shutdown occurs in order to prevent an error
381 * during kexec, shutdown or reboot.
382 * Make this power and Loongson specific because
383 * it breaks some other boards.
384 */
385 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
386#endif
387}
388
389static int radeon_pmops_suspend(struct device *dev)
390{
391 struct drm_device *drm_dev = dev_get_drvdata(dev);
392 return radeon_suspend_kms(drm_dev, true, true, false);
393}
394
395static int radeon_pmops_resume(struct device *dev)
396{
397 struct drm_device *drm_dev = dev_get_drvdata(dev);
398
399 /* GPU comes up enabled by the bios on resume */
400 if (radeon_is_px(drm_dev)) {
401 pm_runtime_disable(dev);
402 pm_runtime_set_active(dev);
403 pm_runtime_enable(dev);
404 }
405
406 return radeon_resume_kms(drm_dev, true, true);
407}
408
409static int radeon_pmops_freeze(struct device *dev)
410{
411 struct drm_device *drm_dev = dev_get_drvdata(dev);
412 return radeon_suspend_kms(drm_dev, false, true, true);
413}
414
415static int radeon_pmops_thaw(struct device *dev)
416{
417 struct drm_device *drm_dev = dev_get_drvdata(dev);
418 return radeon_resume_kms(drm_dev, false, true);
419}
420
421static int radeon_pmops_runtime_suspend(struct device *dev)
422{
423 struct pci_dev *pdev = to_pci_dev(dev);
424 struct drm_device *drm_dev = pci_get_drvdata(pdev);
425
426 if (!radeon_is_px(drm_dev)) {
427 pm_runtime_forbid(dev);
428 return -EBUSY;
429 }
430
431 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
432 drm_kms_helper_poll_disable(drm_dev);
433
434 radeon_suspend_kms(drm_dev, false, false, false);
435 pci_save_state(pdev);
436 pci_disable_device(pdev);
437 pci_ignore_hotplug(pdev);
438 if (radeon_is_atpx_hybrid())
439 pci_set_power_state(pdev, PCI_D3cold);
440 else if (!radeon_has_atpx_dgpu_power_cntl())
441 pci_set_power_state(pdev, PCI_D3hot);
442 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
443
444 return 0;
445}
446
447static int radeon_pmops_runtime_resume(struct device *dev)
448{
449 struct pci_dev *pdev = to_pci_dev(dev);
450 struct drm_device *drm_dev = pci_get_drvdata(pdev);
451 int ret;
452
453 if (!radeon_is_px(drm_dev))
454 return -EINVAL;
455
456 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
457
458 if (radeon_is_atpx_hybrid() ||
459 !radeon_has_atpx_dgpu_power_cntl())
460 pci_set_power_state(pdev, PCI_D0);
461 pci_restore_state(pdev);
462 ret = pci_enable_device(pdev);
463 if (ret)
464 return ret;
465 pci_set_master(pdev);
466
467 ret = radeon_resume_kms(drm_dev, false, false);
468 drm_kms_helper_poll_enable(drm_dev);
469 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
470 return 0;
471}
472
473static int radeon_pmops_runtime_idle(struct device *dev)
474{
475 struct drm_device *drm_dev = dev_get_drvdata(dev);
476 struct drm_crtc *crtc;
477
478 if (!radeon_is_px(drm_dev)) {
479 pm_runtime_forbid(dev);
480 return -EBUSY;
481 }
482
483 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
484 if (crtc->enabled) {
485 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
486 return -EBUSY;
487 }
488 }
489
490 pm_runtime_mark_last_busy(dev);
491 pm_runtime_autosuspend(dev);
492 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
493 return 1;
494}
495
496long radeon_drm_ioctl(struct file *filp,
497 unsigned int cmd, unsigned long arg)
498{
499 struct drm_file *file_priv = filp->private_data;
500 struct drm_device *dev;
501 long ret;
502 dev = file_priv->minor->dev;
503 ret = pm_runtime_get_sync(dev->dev);
504 if (ret < 0) {
505 pm_runtime_put_autosuspend(dev->dev);
506 return ret;
507 }
508
509 ret = drm_ioctl(filp, cmd, arg);
510
511 pm_runtime_mark_last_busy(dev->dev);
512 pm_runtime_put_autosuspend(dev->dev);
513 return ret;
514}
515
516#ifdef CONFIG_COMPAT
517static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
518{
519 unsigned int nr = DRM_IOCTL_NR(cmd);
520 int ret;
521
522 if (nr < DRM_COMMAND_BASE)
523 return drm_compat_ioctl(filp, cmd, arg);
524
525 ret = radeon_drm_ioctl(filp, cmd, arg);
526
527 return ret;
528}
529#endif
530
531static const struct dev_pm_ops radeon_pm_ops = {
532 .suspend = radeon_pmops_suspend,
533 .resume = radeon_pmops_resume,
534 .freeze = radeon_pmops_freeze,
535 .thaw = radeon_pmops_thaw,
536 .poweroff = radeon_pmops_freeze,
537 .restore = radeon_pmops_resume,
538 .runtime_suspend = radeon_pmops_runtime_suspend,
539 .runtime_resume = radeon_pmops_runtime_resume,
540 .runtime_idle = radeon_pmops_runtime_idle,
541};
542
543static const struct file_operations radeon_driver_kms_fops = {
544 .owner = THIS_MODULE,
545 .open = drm_open,
546 .release = drm_release,
547 .unlocked_ioctl = radeon_drm_ioctl,
548 .mmap = drm_gem_mmap,
549 .poll = drm_poll,
550 .read = drm_read,
551#ifdef CONFIG_COMPAT
552 .compat_ioctl = radeon_kms_compat_ioctl,
553#endif
554};
555
556static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
557 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
558 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
559 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
560 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
561 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
562 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
563 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
564 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
565 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
566 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
567 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
568 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
569 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
570 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
571 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
572 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
573 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
574 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
575 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
576 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
577 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
578 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
579 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
580 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
581 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
582 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
583 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
584 /* KMS */
585 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
586 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
587 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
588 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
589 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
590 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
591 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
592 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
593 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
594 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
595 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
596 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
597 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
598 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
599 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
600};
601
602static const struct drm_driver kms_driver = {
603 .driver_features =
604 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
605 .load = radeon_driver_load_kms,
606 .open = radeon_driver_open_kms,
607 .postclose = radeon_driver_postclose_kms,
608 .lastclose = radeon_driver_lastclose_kms,
609 .unload = radeon_driver_unload_kms,
610 .irq_preinstall = radeon_driver_irq_preinstall_kms,
611 .irq_postinstall = radeon_driver_irq_postinstall_kms,
612 .irq_uninstall = radeon_driver_irq_uninstall_kms,
613 .irq_handler = radeon_driver_irq_handler_kms,
614 .ioctls = radeon_ioctls_kms,
615 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
616 .dumb_create = radeon_mode_dumb_create,
617 .dumb_map_offset = radeon_mode_dumb_mmap,
618 .fops = &radeon_driver_kms_fops,
619
620 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
621 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
622 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
623 .gem_prime_mmap = drm_gem_prime_mmap,
624
625 .name = DRIVER_NAME,
626 .desc = DRIVER_DESC,
627 .date = DRIVER_DATE,
628 .major = KMS_DRIVER_MAJOR,
629 .minor = KMS_DRIVER_MINOR,
630 .patchlevel = KMS_DRIVER_PATCHLEVEL,
631};
632
633static struct pci_driver radeon_kms_pci_driver = {
634 .name = DRIVER_NAME,
635 .id_table = pciidlist,
636 .probe = radeon_pci_probe,
637 .remove = radeon_pci_remove,
638 .shutdown = radeon_pci_shutdown,
639 .driver.pm = &radeon_pm_ops,
640};
641
642static int __init radeon_module_init(void)
643{
644 if (vgacon_text_force() && radeon_modeset == -1) {
645 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
646 radeon_modeset = 0;
647 }
648
649 if (radeon_modeset == 0) {
650 DRM_ERROR("No UMS support in radeon module!\n");
651 return -EINVAL;
652 }
653
654 DRM_INFO("radeon kernel modesetting enabled.\n");
655 radeon_register_atpx_handler();
656
657 return pci_register_driver(&radeon_kms_pci_driver);
658}
659
660static void __exit radeon_module_exit(void)
661{
662 pci_unregister_driver(&radeon_kms_pci_driver);
663 radeon_unregister_atpx_handler();
664 mmu_notifier_synchronize();
665}
666
667module_init(radeon_module_init);
668module_exit(radeon_module_exit);
669
670MODULE_AUTHOR(DRIVER_AUTHOR);
671MODULE_DESCRIPTION(DRIVER_DESC);
672MODULE_LICENSE("GPL and additional rights");