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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/pci.h>
31
32#include <drm/drm_print.h>
33
34#include "ast_dram_tables.h"
35#include "ast_drv.h"
36
37static void ast_post_chip_2300(struct ast_device *ast);
38static void ast_post_chip_2500(struct ast_device *ast);
39
40static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
42
43static void ast_set_def_ext_reg(struct ast_device *ast)
44{
45 u8 i, index, reg;
46 const u8 *ext_reg_info;
47
48 /* reset scratch */
49 for (i = 0x81; i <= 0x9f; i++)
50 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
51
52 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
53 ext_reg_info = extreginfo_ast2300;
54 else
55 ext_reg_info = extreginfo;
56
57 index = 0xa0;
58 while (*ext_reg_info != 0xff) {
59 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
60 index++;
61 ext_reg_info++;
62 }
63
64 /* disable standard IO/MEM decode if secondary */
65 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
66
67 /* Set Ext. Default */
68 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
69 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
70
71 /* Enable RAMDAC for A1 */
72 reg = 0x04;
73 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
74 reg |= 0x20;
75 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
76}
77
78static u32 __ast_mindwm(void __iomem *regs, u32 r)
79{
80 u32 data;
81
82 __ast_write32(regs, 0xf004, r & 0xffff0000);
83 __ast_write32(regs, 0xf000, 0x1);
84
85 do {
86 data = __ast_read32(regs, 0xf004) & 0xffff0000;
87 } while (data != (r & 0xffff0000));
88
89 return __ast_read32(regs, 0x10000 + (r & 0x0000ffff));
90}
91
92static void __ast_moutdwm(void __iomem *regs, u32 r, u32 v)
93{
94 u32 data;
95
96 __ast_write32(regs, 0xf004, r & 0xffff0000);
97 __ast_write32(regs, 0xf000, 0x1);
98
99 do {
100 data = __ast_read32(regs, 0xf004) & 0xffff0000;
101 } while (data != (r & 0xffff0000));
102
103 __ast_write32(regs, 0x10000 + (r & 0x0000ffff), v);
104}
105
106u32 ast_mindwm(struct ast_device *ast, u32 r)
107{
108 return __ast_mindwm(ast->regs, r);
109}
110
111void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
112{
113 __ast_moutdwm(ast->regs, r, v);
114}
115
116/*
117 * AST2100/2150 DLL CBR Setting
118 */
119#define CBR_SIZE_AST2150 ((16 << 10) - 1)
120#define CBR_PASSNUM_AST2150 5
121#define CBR_THRESHOLD_AST2150 10
122#define CBR_THRESHOLD2_AST2150 10
123#define TIMEOUT_AST2150 5000000
124
125#define CBR_PATNUM_AST2150 8
126
127static const u32 pattern_AST2150[14] = {
128 0xFF00FF00,
129 0xCC33CC33,
130 0xAA55AA55,
131 0xFFFE0001,
132 0x683501FE,
133 0x0F1929B0,
134 0x2D0B4346,
135 0x60767F02,
136 0x6FBE36A6,
137 0x3A253035,
138 0x3019686D,
139 0x41C6167E,
140 0x620152BF,
141 0x20F050E0
142};
143
144static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
145{
146 u32 data, timeout;
147
148 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
149 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
150 timeout = 0;
151 do {
152 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
153 if (++timeout > TIMEOUT_AST2150) {
154 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
155 return 0xffffffff;
156 }
157 } while (!data);
158 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
159 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
160 timeout = 0;
161 do {
162 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
163 if (++timeout > TIMEOUT_AST2150) {
164 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
165 return 0xffffffff;
166 }
167 } while (!data);
168 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
170 return data;
171}
172
173#if 0 /* unused in DDX driver - here for completeness */
174static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
175{
176 u32 data, timeout;
177
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
180 timeout = 0;
181 do {
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
183 if (++timeout > TIMEOUT_AST2150) {
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
185 return 0xffffffff;
186 }
187 } while (!data);
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
190 return data;
191}
192#endif
193
194static int cbrtest_ast2150(struct ast_device *ast)
195{
196 int i;
197
198 for (i = 0; i < 8; i++)
199 if (mmctestburst2_ast2150(ast, i))
200 return 0;
201 return 1;
202}
203
204static int cbrscan_ast2150(struct ast_device *ast, int busw)
205{
206 u32 patcnt, loop;
207
208 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
209 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
210 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
211 if (cbrtest_ast2150(ast))
212 break;
213 }
214 if (loop == CBR_PASSNUM_AST2150)
215 return 0;
216 }
217 return 1;
218}
219
220
221static void cbrdlli_ast2150(struct ast_device *ast, int busw)
222{
223 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
224
225cbr_start:
226 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
227 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
228 passcnt = 0;
229
230 for (dlli = 0; dlli < 100; dlli++) {
231 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
232 data = cbrscan_ast2150(ast, busw);
233 if (data != 0) {
234 if (data & 0x1) {
235 if (dll_min[0] > dlli)
236 dll_min[0] = dlli;
237 if (dll_max[0] < dlli)
238 dll_max[0] = dlli;
239 }
240 passcnt++;
241 } else if (passcnt >= CBR_THRESHOLD_AST2150)
242 goto cbr_start;
243 }
244 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
245 goto cbr_start;
246
247 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
248 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
249}
250
251
252
253static void ast_init_dram_reg(struct ast_device *ast)
254{
255 u8 j;
256 u32 data, temp, i;
257 const struct ast_dramstruct *dram_reg_info;
258
259 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
260
261 if ((j & 0x80) == 0) { /* VGA only */
262 if (IS_AST_GEN1(ast)) {
263 dram_reg_info = ast2000_dram_table_data;
264 ast_write32(ast, 0xf004, 0x1e6e0000);
265 ast_write32(ast, 0xf000, 0x1);
266 ast_write32(ast, 0x10100, 0xa8);
267
268 do {
269 ;
270 } while (ast_read32(ast, 0x10100) != 0xa8);
271 } else { /* GEN2/GEN3 */
272 if (ast->chip == AST2100 || ast->chip == AST2200)
273 dram_reg_info = ast2100_dram_table_data;
274 else
275 dram_reg_info = ast1100_dram_table_data;
276
277 ast_write32(ast, 0xf004, 0x1e6e0000);
278 ast_write32(ast, 0xf000, 0x1);
279 ast_write32(ast, 0x12000, 0x1688A8A8);
280 do {
281 ;
282 } while (ast_read32(ast, 0x12000) != 0x01);
283
284 ast_write32(ast, 0x10000, 0xfc600309);
285 do {
286 ;
287 } while (ast_read32(ast, 0x10000) != 0x01);
288 }
289
290 while (dram_reg_info->index != 0xffff) {
291 if (dram_reg_info->index == 0xff00) {/* delay fn */
292 for (i = 0; i < 15; i++)
293 udelay(dram_reg_info->data);
294 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
295 data = dram_reg_info->data;
296 if (ast->dram_type == AST_DRAM_1Gx16)
297 data = 0x00000d89;
298 else if (ast->dram_type == AST_DRAM_1Gx32)
299 data = 0x00000c8d;
300
301 temp = ast_read32(ast, 0x12070);
302 temp &= 0xc;
303 temp <<= 2;
304 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
305 } else
306 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
307 dram_reg_info++;
308 }
309
310 /* AST 2100/2150 DRAM calibration */
311 data = ast_read32(ast, 0x10120);
312 if (data == 0x5061) { /* 266Mhz */
313 data = ast_read32(ast, 0x10004);
314 if (data & 0x40)
315 cbrdlli_ast2150(ast, 16); /* 16 bits */
316 else
317 cbrdlli_ast2150(ast, 32); /* 32 bits */
318 }
319
320 switch (AST_GEN(ast)) {
321 case 1:
322 temp = ast_read32(ast, 0x10140);
323 ast_write32(ast, 0x10140, temp | 0x40);
324 break;
325 case 2:
326 case 3:
327 temp = ast_read32(ast, 0x1200c);
328 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
329 temp = ast_read32(ast, 0x12040);
330 ast_write32(ast, 0x12040, temp | 0x40);
331 break;
332 default:
333 break;
334 }
335 }
336
337 /* wait ready */
338 do {
339 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
340 } while ((j & 0x40) == 0);
341}
342
343void ast_post_gpu(struct ast_device *ast)
344{
345 ast_set_def_ext_reg(ast);
346
347 if (IS_AST_GEN7(ast)) {
348 if (ast->tx_chip == AST_TX_ASTDP)
349 ast_dp_launch(ast);
350 } else if (ast->config_mode == ast_use_p2a) {
351 if (IS_AST_GEN6(ast))
352 ast_post_chip_2500(ast);
353 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
354 ast_post_chip_2300(ast);
355 else
356 ast_init_dram_reg(ast);
357
358 ast_init_3rdtx(ast);
359 } else {
360 if (ast->tx_chip == AST_TX_SIL164)
361 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */
362 }
363}
364
365/* AST 2300 DRAM settings */
366#define AST_DDR3 0
367#define AST_DDR2 1
368
369struct ast2300_dram_param {
370 u32 dram_type;
371 u32 dram_chipid;
372 u32 dram_freq;
373 u32 vram_size;
374 u32 odt;
375 u32 wodt;
376 u32 rodt;
377 u32 dram_config;
378 u32 reg_PERIOD;
379 u32 reg_MADJ;
380 u32 reg_SADJ;
381 u32 reg_MRS;
382 u32 reg_EMRS;
383 u32 reg_AC1;
384 u32 reg_AC2;
385 u32 reg_DQSIC;
386 u32 reg_DRV;
387 u32 reg_IOZ;
388 u32 reg_DQIDLY;
389 u32 reg_FREQ;
390 u32 madj_max;
391 u32 dll2_finetune_step;
392};
393
394/*
395 * DQSI DLL CBR Setting
396 */
397#define CBR_SIZE0 ((1 << 10) - 1)
398#define CBR_SIZE1 ((4 << 10) - 1)
399#define CBR_SIZE2 ((64 << 10) - 1)
400#define CBR_PASSNUM 5
401#define CBR_PASSNUM2 5
402#define CBR_THRESHOLD 10
403#define CBR_THRESHOLD2 10
404#define TIMEOUT 5000000
405#define CBR_PATNUM 8
406
407static const u32 pattern[8] = {
408 0xFF00FF00,
409 0xCC33CC33,
410 0xAA55AA55,
411 0x88778877,
412 0x92CC4D6E,
413 0x543D3CDE,
414 0xF1E843C7,
415 0x7C61D253
416};
417
418static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
419{
420 u32 data, timeout;
421
422 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
423 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
424 timeout = 0;
425 do {
426 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
427 if (data & 0x2000)
428 return false;
429 if (++timeout > TIMEOUT) {
430 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
431 return false;
432 }
433 } while (!data);
434 ast_moutdwm(ast, 0x1e6e0070, 0x0);
435 return true;
436}
437
438static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
439{
440 u32 data, timeout;
441
442 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
443 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
444 timeout = 0;
445 do {
446 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
447 if (++timeout > TIMEOUT) {
448 ast_moutdwm(ast, 0x1e6e0070, 0x0);
449 return 0xffffffff;
450 }
451 } while (!data);
452 data = ast_mindwm(ast, 0x1e6e0078);
453 data = (data | (data >> 16)) & 0xffff;
454 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
455 return data;
456}
457
458
459static bool mmc_test_burst(struct ast_device *ast, u32 datagen)
460{
461 return mmc_test(ast, datagen, 0xc1);
462}
463
464static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
465{
466 return mmc_test2(ast, datagen, 0x41);
467}
468
469static bool mmc_test_single(struct ast_device *ast, u32 datagen)
470{
471 return mmc_test(ast, datagen, 0xc5);
472}
473
474static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
475{
476 return mmc_test2(ast, datagen, 0x05);
477}
478
479static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
480{
481 return mmc_test(ast, datagen, 0x85);
482}
483
484static int cbr_test(struct ast_device *ast)
485{
486 u32 data;
487 int i;
488 data = mmc_test_single2(ast, 0);
489 if ((data & 0xff) && (data & 0xff00))
490 return 0;
491 for (i = 0; i < 8; i++) {
492 data = mmc_test_burst2(ast, i);
493 if ((data & 0xff) && (data & 0xff00))
494 return 0;
495 }
496 if (!data)
497 return 3;
498 else if (data & 0xff)
499 return 2;
500 return 1;
501}
502
503static int cbr_scan(struct ast_device *ast)
504{
505 u32 data, data2, patcnt, loop;
506
507 data2 = 3;
508 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
509 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
510 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
511 if ((data = cbr_test(ast)) != 0) {
512 data2 &= data;
513 if (!data2)
514 return 0;
515 break;
516 }
517 }
518 if (loop == CBR_PASSNUM2)
519 return 0;
520 }
521 return data2;
522}
523
524static u32 cbr_test2(struct ast_device *ast)
525{
526 u32 data;
527
528 data = mmc_test_burst2(ast, 0);
529 if (data == 0xffff)
530 return 0;
531 data |= mmc_test_single2(ast, 0);
532 if (data == 0xffff)
533 return 0;
534
535 return ~data & 0xffff;
536}
537
538static u32 cbr_scan2(struct ast_device *ast)
539{
540 u32 data, data2, patcnt, loop;
541
542 data2 = 0xffff;
543 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
544 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
545 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
546 if ((data = cbr_test2(ast)) != 0) {
547 data2 &= data;
548 if (!data2)
549 return 0;
550 break;
551 }
552 }
553 if (loop == CBR_PASSNUM2)
554 return 0;
555 }
556 return data2;
557}
558
559static bool cbr_test3(struct ast_device *ast)
560{
561 if (!mmc_test_burst(ast, 0))
562 return false;
563 if (!mmc_test_single(ast, 0))
564 return false;
565 return true;
566}
567
568static bool cbr_scan3(struct ast_device *ast)
569{
570 u32 patcnt, loop;
571
572 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
573 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
574 for (loop = 0; loop < 2; loop++) {
575 if (cbr_test3(ast))
576 break;
577 }
578 if (loop == 2)
579 return false;
580 }
581 return true;
582}
583
584static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
585{
586 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
587 bool status = false;
588FINETUNE_START:
589 for (cnt = 0; cnt < 16; cnt++) {
590 dllmin[cnt] = 0xff;
591 dllmax[cnt] = 0x0;
592 }
593 passcnt = 0;
594 for (dlli = 0; dlli < 76; dlli++) {
595 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
596 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
597 data = cbr_scan2(ast);
598 if (data != 0) {
599 mask = 0x00010001;
600 for (cnt = 0; cnt < 16; cnt++) {
601 if (data & mask) {
602 if (dllmin[cnt] > dlli) {
603 dllmin[cnt] = dlli;
604 }
605 if (dllmax[cnt] < dlli) {
606 dllmax[cnt] = dlli;
607 }
608 }
609 mask <<= 1;
610 }
611 passcnt++;
612 } else if (passcnt >= CBR_THRESHOLD2) {
613 break;
614 }
615 }
616 gold_sadj[0] = 0x0;
617 passcnt = 0;
618 for (cnt = 0; cnt < 16; cnt++) {
619 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
620 gold_sadj[0] += dllmin[cnt];
621 passcnt++;
622 }
623 }
624 if (retry++ > 10)
625 goto FINETUNE_DONE;
626 if (passcnt != 16) {
627 goto FINETUNE_START;
628 }
629 status = true;
630FINETUNE_DONE:
631 gold_sadj[0] = gold_sadj[0] >> 4;
632 gold_sadj[1] = gold_sadj[0];
633
634 data = 0;
635 for (cnt = 0; cnt < 8; cnt++) {
636 data >>= 3;
637 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
638 dlli = dllmin[cnt];
639 if (gold_sadj[0] >= dlli) {
640 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
641 if (dlli > 3) {
642 dlli = 3;
643 }
644 } else {
645 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
646 if (dlli > 4) {
647 dlli = 4;
648 }
649 dlli = (8 - dlli) & 0x7;
650 }
651 data |= dlli << 21;
652 }
653 }
654 ast_moutdwm(ast, 0x1E6E0080, data);
655
656 data = 0;
657 for (cnt = 8; cnt < 16; cnt++) {
658 data >>= 3;
659 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
660 dlli = dllmin[cnt];
661 if (gold_sadj[1] >= dlli) {
662 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
663 if (dlli > 3) {
664 dlli = 3;
665 } else {
666 dlli = (dlli - 1) & 0x7;
667 }
668 } else {
669 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
670 dlli += 1;
671 if (dlli > 4) {
672 dlli = 4;
673 }
674 dlli = (8 - dlli) & 0x7;
675 }
676 data |= dlli << 21;
677 }
678 }
679 ast_moutdwm(ast, 0x1E6E0084, data);
680 return status;
681} /* finetuneDQI_L */
682
683static void finetuneDQSI(struct ast_device *ast)
684{
685 u32 dlli, dqsip, dqidly;
686 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
687 u32 g_dqidly, g_dqsip, g_margin, g_side;
688 u16 pass[32][2][2];
689 char tag[2][76];
690
691 /* Disable DQI CBR */
692 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
693 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
694 reg_mcr18 &= 0x0000ffff;
695 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
696
697 for (dlli = 0; dlli < 76; dlli++) {
698 tag[0][dlli] = 0x0;
699 tag[1][dlli] = 0x0;
700 }
701 for (dqidly = 0; dqidly < 32; dqidly++) {
702 pass[dqidly][0][0] = 0xff;
703 pass[dqidly][0][1] = 0x0;
704 pass[dqidly][1][0] = 0xff;
705 pass[dqidly][1][1] = 0x0;
706 }
707 for (dqidly = 0; dqidly < 32; dqidly++) {
708 passcnt[0] = passcnt[1] = 0;
709 for (dqsip = 0; dqsip < 2; dqsip++) {
710 ast_moutdwm(ast, 0x1E6E000C, 0);
711 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
712 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
713 for (dlli = 0; dlli < 76; dlli++) {
714 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
715 ast_moutdwm(ast, 0x1E6E0070, 0);
716 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
717 if (cbr_scan3(ast)) {
718 if (dlli == 0)
719 break;
720 passcnt[dqsip]++;
721 tag[dqsip][dlli] = 'P';
722 if (dlli < pass[dqidly][dqsip][0])
723 pass[dqidly][dqsip][0] = (u16) dlli;
724 if (dlli > pass[dqidly][dqsip][1])
725 pass[dqidly][dqsip][1] = (u16) dlli;
726 } else if (passcnt[dqsip] >= 5)
727 break;
728 else {
729 pass[dqidly][dqsip][0] = 0xff;
730 pass[dqidly][dqsip][1] = 0x0;
731 }
732 }
733 }
734 if (passcnt[0] == 0 && passcnt[1] == 0)
735 dqidly++;
736 }
737 /* Search margin */
738 g_dqidly = g_dqsip = g_margin = g_side = 0;
739
740 for (dqidly = 0; dqidly < 32; dqidly++) {
741 for (dqsip = 0; dqsip < 2; dqsip++) {
742 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
743 continue;
744 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
745 if ((diff+2) < g_margin)
746 continue;
747 passcnt[0] = passcnt[1] = 0;
748 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
749 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
750 if (passcnt[0] > passcnt[1])
751 passcnt[0] = passcnt[1];
752 passcnt[1] = 0;
753 if (passcnt[0] > g_side)
754 passcnt[1] = passcnt[0] - g_side;
755 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
756 g_margin = diff;
757 g_dqidly = dqidly;
758 g_dqsip = dqsip;
759 g_side = passcnt[0];
760 } else if (passcnt[1] > 1 && g_side < 8) {
761 if (diff > g_margin)
762 g_margin = diff;
763 g_dqidly = dqidly;
764 g_dqsip = dqsip;
765 g_side = passcnt[0];
766 }
767 }
768 }
769 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
770 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
771
772}
773static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
774{
775 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
776 bool status = false;
777
778 finetuneDQSI(ast);
779 if (finetuneDQI_L(ast, param) == false)
780 return status;
781
782CBR_START2:
783 dllmin[0] = dllmin[1] = 0xff;
784 dllmax[0] = dllmax[1] = 0x0;
785 passcnt = 0;
786 for (dlli = 0; dlli < 76; dlli++) {
787 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
788 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
789 data = cbr_scan(ast);
790 if (data != 0) {
791 if (data & 0x1) {
792 if (dllmin[0] > dlli) {
793 dllmin[0] = dlli;
794 }
795 if (dllmax[0] < dlli) {
796 dllmax[0] = dlli;
797 }
798 }
799 if (data & 0x2) {
800 if (dllmin[1] > dlli) {
801 dllmin[1] = dlli;
802 }
803 if (dllmax[1] < dlli) {
804 dllmax[1] = dlli;
805 }
806 }
807 passcnt++;
808 } else if (passcnt >= CBR_THRESHOLD) {
809 break;
810 }
811 }
812 if (retry++ > 10)
813 goto CBR_DONE2;
814 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
815 goto CBR_START2;
816 }
817 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
818 goto CBR_START2;
819 }
820 status = true;
821CBR_DONE2:
822 dlli = (dllmin[1] + dllmax[1]) >> 1;
823 dlli <<= 8;
824 dlli += (dllmin[0] + dllmax[0]) >> 1;
825 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
826 return status;
827} /* CBRDLL2 */
828
829static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
830{
831 u32 trap, trap_AC2, trap_MRS;
832
833 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
834
835 /* Ger trap info */
836 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
837 trap_AC2 = 0x00020000 + (trap << 16);
838 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
839 trap_MRS = 0x00000010 + (trap << 4);
840 trap_MRS |= ((trap & 0x2) << 18);
841
842 param->reg_MADJ = 0x00034C4C;
843 param->reg_SADJ = 0x00001800;
844 param->reg_DRV = 0x000000F0;
845 param->reg_PERIOD = param->dram_freq;
846 param->rodt = 0;
847
848 switch (param->dram_freq) {
849 case 336:
850 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
851 param->wodt = 0;
852 param->reg_AC1 = 0x22202725;
853 param->reg_AC2 = 0xAA007613 | trap_AC2;
854 param->reg_DQSIC = 0x000000BA;
855 param->reg_MRS = 0x04001400 | trap_MRS;
856 param->reg_EMRS = 0x00000000;
857 param->reg_IOZ = 0x00000023;
858 param->reg_DQIDLY = 0x00000074;
859 param->reg_FREQ = 0x00004DC0;
860 param->madj_max = 96;
861 param->dll2_finetune_step = 3;
862 switch (param->dram_chipid) {
863 default:
864 case AST_DRAM_512Mx16:
865 case AST_DRAM_1Gx16:
866 param->reg_AC2 = 0xAA007613 | trap_AC2;
867 break;
868 case AST_DRAM_2Gx16:
869 param->reg_AC2 = 0xAA00761C | trap_AC2;
870 break;
871 case AST_DRAM_4Gx16:
872 param->reg_AC2 = 0xAA007636 | trap_AC2;
873 break;
874 }
875 break;
876 default:
877 case 396:
878 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
879 param->wodt = 1;
880 param->reg_AC1 = 0x33302825;
881 param->reg_AC2 = 0xCC009617 | trap_AC2;
882 param->reg_DQSIC = 0x000000E2;
883 param->reg_MRS = 0x04001600 | trap_MRS;
884 param->reg_EMRS = 0x00000000;
885 param->reg_IOZ = 0x00000034;
886 param->reg_DRV = 0x000000FA;
887 param->reg_DQIDLY = 0x00000089;
888 param->reg_FREQ = 0x00005040;
889 param->madj_max = 96;
890 param->dll2_finetune_step = 4;
891
892 switch (param->dram_chipid) {
893 default:
894 case AST_DRAM_512Mx16:
895 case AST_DRAM_1Gx16:
896 param->reg_AC2 = 0xCC009617 | trap_AC2;
897 break;
898 case AST_DRAM_2Gx16:
899 param->reg_AC2 = 0xCC009622 | trap_AC2;
900 break;
901 case AST_DRAM_4Gx16:
902 param->reg_AC2 = 0xCC00963F | trap_AC2;
903 break;
904 }
905 break;
906
907 case 408:
908 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
909 param->wodt = 1;
910 param->reg_AC1 = 0x33302825;
911 param->reg_AC2 = 0xCC009617 | trap_AC2;
912 param->reg_DQSIC = 0x000000E2;
913 param->reg_MRS = 0x04001600 | trap_MRS;
914 param->reg_EMRS = 0x00000000;
915 param->reg_IOZ = 0x00000023;
916 param->reg_DRV = 0x000000FA;
917 param->reg_DQIDLY = 0x00000089;
918 param->reg_FREQ = 0x000050C0;
919 param->madj_max = 96;
920 param->dll2_finetune_step = 4;
921
922 switch (param->dram_chipid) {
923 default:
924 case AST_DRAM_512Mx16:
925 case AST_DRAM_1Gx16:
926 param->reg_AC2 = 0xCC009617 | trap_AC2;
927 break;
928 case AST_DRAM_2Gx16:
929 param->reg_AC2 = 0xCC009622 | trap_AC2;
930 break;
931 case AST_DRAM_4Gx16:
932 param->reg_AC2 = 0xCC00963F | trap_AC2;
933 break;
934 }
935
936 break;
937 case 456:
938 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
939 param->wodt = 0;
940 param->reg_AC1 = 0x33302926;
941 param->reg_AC2 = 0xCD44961A;
942 param->reg_DQSIC = 0x000000FC;
943 param->reg_MRS = 0x00081830;
944 param->reg_EMRS = 0x00000000;
945 param->reg_IOZ = 0x00000045;
946 param->reg_DQIDLY = 0x00000097;
947 param->reg_FREQ = 0x000052C0;
948 param->madj_max = 88;
949 param->dll2_finetune_step = 4;
950 break;
951 case 504:
952 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
953 param->wodt = 1;
954 param->reg_AC1 = 0x33302926;
955 param->reg_AC2 = 0xDE44A61D;
956 param->reg_DQSIC = 0x00000117;
957 param->reg_MRS = 0x00081A30;
958 param->reg_EMRS = 0x00000000;
959 param->reg_IOZ = 0x070000BB;
960 param->reg_DQIDLY = 0x000000A0;
961 param->reg_FREQ = 0x000054C0;
962 param->madj_max = 79;
963 param->dll2_finetune_step = 4;
964 break;
965 case 528:
966 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
967 param->wodt = 1;
968 param->rodt = 1;
969 param->reg_AC1 = 0x33302926;
970 param->reg_AC2 = 0xEF44B61E;
971 param->reg_DQSIC = 0x00000125;
972 param->reg_MRS = 0x00081A30;
973 param->reg_EMRS = 0x00000040;
974 param->reg_DRV = 0x000000F5;
975 param->reg_IOZ = 0x00000023;
976 param->reg_DQIDLY = 0x00000088;
977 param->reg_FREQ = 0x000055C0;
978 param->madj_max = 76;
979 param->dll2_finetune_step = 3;
980 break;
981 case 576:
982 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
983 param->reg_MADJ = 0x00136868;
984 param->reg_SADJ = 0x00004534;
985 param->wodt = 1;
986 param->rodt = 1;
987 param->reg_AC1 = 0x33302A37;
988 param->reg_AC2 = 0xEF56B61E;
989 param->reg_DQSIC = 0x0000013F;
990 param->reg_MRS = 0x00101A50;
991 param->reg_EMRS = 0x00000040;
992 param->reg_DRV = 0x000000FA;
993 param->reg_IOZ = 0x00000023;
994 param->reg_DQIDLY = 0x00000078;
995 param->reg_FREQ = 0x000057C0;
996 param->madj_max = 136;
997 param->dll2_finetune_step = 3;
998 break;
999 case 600:
1000 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1001 param->reg_MADJ = 0x00136868;
1002 param->reg_SADJ = 0x00004534;
1003 param->wodt = 1;
1004 param->rodt = 1;
1005 param->reg_AC1 = 0x32302A37;
1006 param->reg_AC2 = 0xDF56B61F;
1007 param->reg_DQSIC = 0x0000014D;
1008 param->reg_MRS = 0x00101A50;
1009 param->reg_EMRS = 0x00000004;
1010 param->reg_DRV = 0x000000F5;
1011 param->reg_IOZ = 0x00000023;
1012 param->reg_DQIDLY = 0x00000078;
1013 param->reg_FREQ = 0x000058C0;
1014 param->madj_max = 132;
1015 param->dll2_finetune_step = 3;
1016 break;
1017 case 624:
1018 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1019 param->reg_MADJ = 0x00136868;
1020 param->reg_SADJ = 0x00004534;
1021 param->wodt = 1;
1022 param->rodt = 1;
1023 param->reg_AC1 = 0x32302A37;
1024 param->reg_AC2 = 0xEF56B621;
1025 param->reg_DQSIC = 0x0000015A;
1026 param->reg_MRS = 0x02101A50;
1027 param->reg_EMRS = 0x00000004;
1028 param->reg_DRV = 0x000000F5;
1029 param->reg_IOZ = 0x00000034;
1030 param->reg_DQIDLY = 0x00000078;
1031 param->reg_FREQ = 0x000059C0;
1032 param->madj_max = 128;
1033 param->dll2_finetune_step = 3;
1034 break;
1035 } /* switch freq */
1036
1037 switch (param->dram_chipid) {
1038 case AST_DRAM_512Mx16:
1039 param->dram_config = 0x130;
1040 break;
1041 default:
1042 case AST_DRAM_1Gx16:
1043 param->dram_config = 0x131;
1044 break;
1045 case AST_DRAM_2Gx16:
1046 param->dram_config = 0x132;
1047 break;
1048 case AST_DRAM_4Gx16:
1049 param->dram_config = 0x133;
1050 break;
1051 } /* switch size */
1052
1053 switch (param->vram_size) {
1054 default:
1055 case AST_VIDMEM_SIZE_8M:
1056 param->dram_config |= 0x00;
1057 break;
1058 case AST_VIDMEM_SIZE_16M:
1059 param->dram_config |= 0x04;
1060 break;
1061 case AST_VIDMEM_SIZE_32M:
1062 param->dram_config |= 0x08;
1063 break;
1064 case AST_VIDMEM_SIZE_64M:
1065 param->dram_config |= 0x0c;
1066 break;
1067 }
1068
1069}
1070
1071static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1072{
1073 u32 data, data2, retry = 0;
1074
1075ddr3_init_start:
1076 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1077 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1078 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1079 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1080 udelay(10);
1081 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1082 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1083 udelay(10);
1084 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1085 udelay(10);
1086
1087 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1088 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1089 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1090 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1091 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1092 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1093 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1094 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1095 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1096 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1097 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1098 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1099 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1100 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1101 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1102 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1103 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1104 ast_moutdwm(ast, 0x1E6E0054, 0);
1105 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1106 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1107 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1108 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1109 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1110 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1111 /* Wait MCLK2X lock to MCLK */
1112 do {
1113 data = ast_mindwm(ast, 0x1E6E001C);
1114 } while (!(data & 0x08000000));
1115 data = ast_mindwm(ast, 0x1E6E001C);
1116 data = (data >> 8) & 0xff;
1117 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1118 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1119 if ((data2 & 0xff) > param->madj_max) {
1120 break;
1121 }
1122 ast_moutdwm(ast, 0x1E6E0064, data2);
1123 if (data2 & 0x00100000) {
1124 data2 = ((data2 & 0xff) >> 3) + 3;
1125 } else {
1126 data2 = ((data2 & 0xff) >> 2) + 5;
1127 }
1128 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1129 data2 += data & 0xff;
1130 data = data | (data2 << 8);
1131 ast_moutdwm(ast, 0x1E6E0068, data);
1132 udelay(10);
1133 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1134 udelay(10);
1135 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1136 ast_moutdwm(ast, 0x1E6E0018, data);
1137 data = data | 0x200;
1138 ast_moutdwm(ast, 0x1E6E0018, data);
1139 do {
1140 data = ast_mindwm(ast, 0x1E6E001C);
1141 } while (!(data & 0x08000000));
1142
1143 data = ast_mindwm(ast, 0x1E6E001C);
1144 data = (data >> 8) & 0xff;
1145 }
1146 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1147 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1148 ast_moutdwm(ast, 0x1E6E0018, data);
1149
1150 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1151 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1152 udelay(50);
1153 /* Mode Register Setting */
1154 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1155 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1156 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1157 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1158 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1159 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1160 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1161 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1162 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1163
1164 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1165 data = 0;
1166 if (param->wodt) {
1167 data = 0x300;
1168 }
1169 if (param->rodt) {
1170 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1171 }
1172 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1173
1174 /* Calibrate the DQSI delay */
1175 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1176 goto ddr3_init_start;
1177
1178 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1179 /* ECC Memory Initialization */
1180#ifdef ECC
1181 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1182 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1183 do {
1184 data = ast_mindwm(ast, 0x1E6E0070);
1185 } while (!(data & 0x00001000));
1186 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1187 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1188 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1189#endif
1190
1191
1192}
1193
1194static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1195{
1196 u32 trap, trap_AC2, trap_MRS;
1197
1198 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1199
1200 /* Ger trap info */
1201 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1202 trap_AC2 = (trap << 20) | (trap << 16);
1203 trap_AC2 += 0x00110000;
1204 trap_MRS = 0x00000040 | (trap << 4);
1205
1206
1207 param->reg_MADJ = 0x00034C4C;
1208 param->reg_SADJ = 0x00001800;
1209 param->reg_DRV = 0x000000F0;
1210 param->reg_PERIOD = param->dram_freq;
1211 param->rodt = 0;
1212
1213 switch (param->dram_freq) {
1214 case 264:
1215 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1216 param->wodt = 0;
1217 param->reg_AC1 = 0x11101513;
1218 param->reg_AC2 = 0x78117011;
1219 param->reg_DQSIC = 0x00000092;
1220 param->reg_MRS = 0x00000842;
1221 param->reg_EMRS = 0x00000000;
1222 param->reg_DRV = 0x000000F0;
1223 param->reg_IOZ = 0x00000034;
1224 param->reg_DQIDLY = 0x0000005A;
1225 param->reg_FREQ = 0x00004AC0;
1226 param->madj_max = 138;
1227 param->dll2_finetune_step = 3;
1228 break;
1229 case 336:
1230 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1231 param->wodt = 1;
1232 param->reg_AC1 = 0x22202613;
1233 param->reg_AC2 = 0xAA009016 | trap_AC2;
1234 param->reg_DQSIC = 0x000000BA;
1235 param->reg_MRS = 0x00000A02 | trap_MRS;
1236 param->reg_EMRS = 0x00000040;
1237 param->reg_DRV = 0x000000FA;
1238 param->reg_IOZ = 0x00000034;
1239 param->reg_DQIDLY = 0x00000074;
1240 param->reg_FREQ = 0x00004DC0;
1241 param->madj_max = 96;
1242 param->dll2_finetune_step = 3;
1243 switch (param->dram_chipid) {
1244 default:
1245 case AST_DRAM_512Mx16:
1246 param->reg_AC2 = 0xAA009012 | trap_AC2;
1247 break;
1248 case AST_DRAM_1Gx16:
1249 param->reg_AC2 = 0xAA009016 | trap_AC2;
1250 break;
1251 case AST_DRAM_2Gx16:
1252 param->reg_AC2 = 0xAA009023 | trap_AC2;
1253 break;
1254 case AST_DRAM_4Gx16:
1255 param->reg_AC2 = 0xAA00903B | trap_AC2;
1256 break;
1257 }
1258 break;
1259 default:
1260 case 396:
1261 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1262 param->wodt = 1;
1263 param->rodt = 0;
1264 param->reg_AC1 = 0x33302714;
1265 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1266 param->reg_DQSIC = 0x000000E2;
1267 param->reg_MRS = 0x00000C02 | trap_MRS;
1268 param->reg_EMRS = 0x00000040;
1269 param->reg_DRV = 0x000000FA;
1270 param->reg_IOZ = 0x00000034;
1271 param->reg_DQIDLY = 0x00000089;
1272 param->reg_FREQ = 0x00005040;
1273 param->madj_max = 96;
1274 param->dll2_finetune_step = 4;
1275
1276 switch (param->dram_chipid) {
1277 case AST_DRAM_512Mx16:
1278 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1279 break;
1280 default:
1281 case AST_DRAM_1Gx16:
1282 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1283 break;
1284 case AST_DRAM_2Gx16:
1285 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1286 break;
1287 case AST_DRAM_4Gx16:
1288 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1289 break;
1290 }
1291
1292 break;
1293
1294 case 408:
1295 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1296 param->wodt = 1;
1297 param->rodt = 0;
1298 param->reg_AC1 = 0x33302714;
1299 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1300 param->reg_DQSIC = 0x000000E2;
1301 param->reg_MRS = 0x00000C02 | trap_MRS;
1302 param->reg_EMRS = 0x00000040;
1303 param->reg_DRV = 0x000000FA;
1304 param->reg_IOZ = 0x00000034;
1305 param->reg_DQIDLY = 0x00000089;
1306 param->reg_FREQ = 0x000050C0;
1307 param->madj_max = 96;
1308 param->dll2_finetune_step = 4;
1309
1310 switch (param->dram_chipid) {
1311 case AST_DRAM_512Mx16:
1312 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1313 break;
1314 default:
1315 case AST_DRAM_1Gx16:
1316 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1317 break;
1318 case AST_DRAM_2Gx16:
1319 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1320 break;
1321 case AST_DRAM_4Gx16:
1322 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1323 break;
1324 }
1325
1326 break;
1327 case 456:
1328 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1329 param->wodt = 0;
1330 param->reg_AC1 = 0x33302815;
1331 param->reg_AC2 = 0xCD44B01E;
1332 param->reg_DQSIC = 0x000000FC;
1333 param->reg_MRS = 0x00000E72;
1334 param->reg_EMRS = 0x00000000;
1335 param->reg_DRV = 0x00000000;
1336 param->reg_IOZ = 0x00000034;
1337 param->reg_DQIDLY = 0x00000097;
1338 param->reg_FREQ = 0x000052C0;
1339 param->madj_max = 88;
1340 param->dll2_finetune_step = 3;
1341 break;
1342 case 504:
1343 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1344 param->wodt = 1;
1345 param->rodt = 1;
1346 param->reg_AC1 = 0x33302815;
1347 param->reg_AC2 = 0xDE44C022;
1348 param->reg_DQSIC = 0x00000117;
1349 param->reg_MRS = 0x00000E72;
1350 param->reg_EMRS = 0x00000040;
1351 param->reg_DRV = 0x0000000A;
1352 param->reg_IOZ = 0x00000045;
1353 param->reg_DQIDLY = 0x000000A0;
1354 param->reg_FREQ = 0x000054C0;
1355 param->madj_max = 79;
1356 param->dll2_finetune_step = 3;
1357 break;
1358 case 528:
1359 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1360 param->wodt = 1;
1361 param->rodt = 1;
1362 param->reg_AC1 = 0x33302815;
1363 param->reg_AC2 = 0xEF44D024;
1364 param->reg_DQSIC = 0x00000125;
1365 param->reg_MRS = 0x00000E72;
1366 param->reg_EMRS = 0x00000004;
1367 param->reg_DRV = 0x000000F9;
1368 param->reg_IOZ = 0x00000045;
1369 param->reg_DQIDLY = 0x000000A7;
1370 param->reg_FREQ = 0x000055C0;
1371 param->madj_max = 76;
1372 param->dll2_finetune_step = 3;
1373 break;
1374 case 552:
1375 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1376 param->wodt = 1;
1377 param->rodt = 1;
1378 param->reg_AC1 = 0x43402915;
1379 param->reg_AC2 = 0xFF44E025;
1380 param->reg_DQSIC = 0x00000132;
1381 param->reg_MRS = 0x00000E72;
1382 param->reg_EMRS = 0x00000040;
1383 param->reg_DRV = 0x0000000A;
1384 param->reg_IOZ = 0x00000045;
1385 param->reg_DQIDLY = 0x000000AD;
1386 param->reg_FREQ = 0x000056C0;
1387 param->madj_max = 76;
1388 param->dll2_finetune_step = 3;
1389 break;
1390 case 576:
1391 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1392 param->wodt = 1;
1393 param->rodt = 1;
1394 param->reg_AC1 = 0x43402915;
1395 param->reg_AC2 = 0xFF44E027;
1396 param->reg_DQSIC = 0x0000013F;
1397 param->reg_MRS = 0x00000E72;
1398 param->reg_EMRS = 0x00000004;
1399 param->reg_DRV = 0x000000F5;
1400 param->reg_IOZ = 0x00000045;
1401 param->reg_DQIDLY = 0x000000B3;
1402 param->reg_FREQ = 0x000057C0;
1403 param->madj_max = 76;
1404 param->dll2_finetune_step = 3;
1405 break;
1406 }
1407
1408 switch (param->dram_chipid) {
1409 case AST_DRAM_512Mx16:
1410 param->dram_config = 0x100;
1411 break;
1412 default:
1413 case AST_DRAM_1Gx16:
1414 param->dram_config = 0x121;
1415 break;
1416 case AST_DRAM_2Gx16:
1417 param->dram_config = 0x122;
1418 break;
1419 case AST_DRAM_4Gx16:
1420 param->dram_config = 0x123;
1421 break;
1422 } /* switch size */
1423
1424 switch (param->vram_size) {
1425 default:
1426 case AST_VIDMEM_SIZE_8M:
1427 param->dram_config |= 0x00;
1428 break;
1429 case AST_VIDMEM_SIZE_16M:
1430 param->dram_config |= 0x04;
1431 break;
1432 case AST_VIDMEM_SIZE_32M:
1433 param->dram_config |= 0x08;
1434 break;
1435 case AST_VIDMEM_SIZE_64M:
1436 param->dram_config |= 0x0c;
1437 break;
1438 }
1439}
1440
1441static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1442{
1443 u32 data, data2, retry = 0;
1444
1445ddr2_init_start:
1446 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1447 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1448 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1449 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1450 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1451 udelay(10);
1452 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1453 udelay(10);
1454
1455 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1456 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1457 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1458 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1459 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1460 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1461 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1462 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1463 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1464 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1465 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1466 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1467 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1468 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1469 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1470 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1471 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1472 ast_moutdwm(ast, 0x1E6E0054, 0);
1473 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1474 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1475 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1476 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1477 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1478 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1479
1480 /* Wait MCLK2X lock to MCLK */
1481 do {
1482 data = ast_mindwm(ast, 0x1E6E001C);
1483 } while (!(data & 0x08000000));
1484 data = ast_mindwm(ast, 0x1E6E001C);
1485 data = (data >> 8) & 0xff;
1486 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1487 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1488 if ((data2 & 0xff) > param->madj_max) {
1489 break;
1490 }
1491 ast_moutdwm(ast, 0x1E6E0064, data2);
1492 if (data2 & 0x00100000) {
1493 data2 = ((data2 & 0xff) >> 3) + 3;
1494 } else {
1495 data2 = ((data2 & 0xff) >> 2) + 5;
1496 }
1497 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1498 data2 += data & 0xff;
1499 data = data | (data2 << 8);
1500 ast_moutdwm(ast, 0x1E6E0068, data);
1501 udelay(10);
1502 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1503 udelay(10);
1504 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1505 ast_moutdwm(ast, 0x1E6E0018, data);
1506 data = data | 0x200;
1507 ast_moutdwm(ast, 0x1E6E0018, data);
1508 do {
1509 data = ast_mindwm(ast, 0x1E6E001C);
1510 } while (!(data & 0x08000000));
1511
1512 data = ast_mindwm(ast, 0x1E6E001C);
1513 data = (data >> 8) & 0xff;
1514 }
1515 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1516 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1517 ast_moutdwm(ast, 0x1E6E0018, data);
1518
1519 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1520 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1521 udelay(50);
1522 /* Mode Register Setting */
1523 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1524 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1525 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1526 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1527 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1528 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1529
1530 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1531 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1532 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1533 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1534 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1535 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1536 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1537
1538 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1539 data = 0;
1540 if (param->wodt) {
1541 data = 0x500;
1542 }
1543 if (param->rodt) {
1544 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1545 }
1546 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1547 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1548
1549 /* Calibrate the DQSI delay */
1550 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1551 goto ddr2_init_start;
1552
1553 /* ECC Memory Initialization */
1554#ifdef ECC
1555 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1556 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1557 do {
1558 data = ast_mindwm(ast, 0x1E6E0070);
1559 } while (!(data & 0x00001000));
1560 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1561 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1562 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1563#endif
1564
1565}
1566
1567static void ast_post_chip_2300(struct ast_device *ast)
1568{
1569 struct ast2300_dram_param param;
1570 u32 temp;
1571 u8 reg;
1572
1573 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1574 if ((reg & 0x80) == 0) {/* vga only */
1575 ast_write32(ast, 0xf004, 0x1e6e0000);
1576 ast_write32(ast, 0xf000, 0x1);
1577 ast_write32(ast, 0x12000, 0x1688a8a8);
1578 do {
1579 ;
1580 } while (ast_read32(ast, 0x12000) != 0x1);
1581
1582 ast_write32(ast, 0x10000, 0xfc600309);
1583 do {
1584 ;
1585 } while (ast_read32(ast, 0x10000) != 0x1);
1586
1587 /* Slow down CPU/AHB CLK in VGA only mode */
1588 temp = ast_read32(ast, 0x12008);
1589 temp |= 0x73;
1590 ast_write32(ast, 0x12008, temp);
1591
1592 param.dram_freq = 396;
1593 param.dram_type = AST_DDR3;
1594 temp = ast_mindwm(ast, 0x1e6e2070);
1595 if (temp & 0x01000000)
1596 param.dram_type = AST_DDR2;
1597 switch (temp & 0x18000000) {
1598 case 0:
1599 param.dram_chipid = AST_DRAM_512Mx16;
1600 break;
1601 default:
1602 case 0x08000000:
1603 param.dram_chipid = AST_DRAM_1Gx16;
1604 break;
1605 case 0x10000000:
1606 param.dram_chipid = AST_DRAM_2Gx16;
1607 break;
1608 case 0x18000000:
1609 param.dram_chipid = AST_DRAM_4Gx16;
1610 break;
1611 }
1612 switch (temp & 0x0c) {
1613 default:
1614 case 0x00:
1615 param.vram_size = AST_VIDMEM_SIZE_8M;
1616 break;
1617
1618 case 0x04:
1619 param.vram_size = AST_VIDMEM_SIZE_16M;
1620 break;
1621
1622 case 0x08:
1623 param.vram_size = AST_VIDMEM_SIZE_32M;
1624 break;
1625
1626 case 0x0c:
1627 param.vram_size = AST_VIDMEM_SIZE_64M;
1628 break;
1629 }
1630
1631 if (param.dram_type == AST_DDR3) {
1632 get_ddr3_info(ast, ¶m);
1633 ddr3_init(ast, ¶m);
1634 } else {
1635 get_ddr2_info(ast, ¶m);
1636 ddr2_init(ast, ¶m);
1637 }
1638
1639 temp = ast_mindwm(ast, 0x1e6e2040);
1640 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1641 }
1642
1643 /* wait ready */
1644 do {
1645 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1646 } while ((reg & 0x40) == 0);
1647}
1648
1649static bool cbr_test_2500(struct ast_device *ast)
1650{
1651 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1652 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1653 if (!mmc_test_burst(ast, 0))
1654 return false;
1655 if (!mmc_test_single_2500(ast, 0))
1656 return false;
1657 return true;
1658}
1659
1660static bool ddr_test_2500(struct ast_device *ast)
1661{
1662 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1663 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1664 if (!mmc_test_burst(ast, 0))
1665 return false;
1666 if (!mmc_test_burst(ast, 1))
1667 return false;
1668 if (!mmc_test_burst(ast, 2))
1669 return false;
1670 if (!mmc_test_burst(ast, 3))
1671 return false;
1672 if (!mmc_test_single_2500(ast, 0))
1673 return false;
1674 return true;
1675}
1676
1677static void ddr_init_common_2500(struct ast_device *ast)
1678{
1679 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1680 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1681 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1682 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1683 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1684 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1685 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1686 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1687 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1688 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1689 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1690 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1691 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1692 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1693 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1694 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1695 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1696 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1697 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1698}
1699
1700static void ddr_phy_init_2500(struct ast_device *ast)
1701{
1702 u32 data, pass, timecnt;
1703
1704 pass = 0;
1705 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1706 while (!pass) {
1707 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1708 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1709 if (!data)
1710 break;
1711 }
1712 if (timecnt != TIMEOUT) {
1713 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1714 if (!data)
1715 pass = 1;
1716 }
1717 if (!pass) {
1718 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1719 udelay(10); /* delay 10 us */
1720 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1721 }
1722 }
1723
1724 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1725}
1726
1727/*
1728 * Check DRAM Size
1729 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1730 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1731 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1732 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1733 */
1734static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1735{
1736 u32 reg_04, reg_14;
1737
1738 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1739 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1740
1741 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1742 ast_moutdwm(ast, 0x90100000, 0x35363738);
1743 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1744 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1745
1746 /* Check 8Gbit */
1747 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1748 reg_04 |= 0x03;
1749 reg_14 |= (tRFC >> 24) & 0xFF;
1750 /* Check 4Gbit */
1751 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1752 reg_04 |= 0x02;
1753 reg_14 |= (tRFC >> 16) & 0xFF;
1754 /* Check 2Gbit */
1755 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1756 reg_04 |= 0x01;
1757 reg_14 |= (tRFC >> 8) & 0xFF;
1758 } else {
1759 reg_14 |= tRFC & 0xFF;
1760 }
1761 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1762 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1763}
1764
1765static void enable_cache_2500(struct ast_device *ast)
1766{
1767 u32 reg_04, data;
1768
1769 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1770 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1771
1772 do
1773 data = ast_mindwm(ast, 0x1E6E0004);
1774 while (!(data & 0x80000));
1775 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1776}
1777
1778static void set_mpll_2500(struct ast_device *ast)
1779{
1780 u32 addr, data, param;
1781
1782 /* Reset MMC */
1783 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1784 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1785 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1786 ast_moutdwm(ast, addr, 0x0);
1787 addr += 4;
1788 }
1789 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1790
1791 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1792 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1793 if (data) {
1794 /* CLKIN = 25MHz */
1795 param = 0x930023E0;
1796 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1797 } else {
1798 /* CLKIN = 24MHz */
1799 param = 0x93002400;
1800 }
1801 ast_moutdwm(ast, 0x1E6E2020, param);
1802 udelay(100);
1803}
1804
1805static void reset_mmc_2500(struct ast_device *ast)
1806{
1807 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1808 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1809 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1810 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1811 mdelay(100);
1812 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1813 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1814}
1815
1816static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1817{
1818
1819 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1820 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1821 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1822 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1823 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1824 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1825 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1826 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1827
1828 /* DDR PHY Setting */
1829 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1830 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1831 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1832 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1833 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1834 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1835 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1836 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1837 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1838 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1839 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1840 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1841 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1842 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1843
1844 /* Controller Setting */
1845 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1846
1847 /* Wait DDR PHY init done */
1848 ddr_phy_init_2500(ast);
1849
1850 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1851 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1852 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1853
1854 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1855 enable_cache_2500(ast);
1856 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1857 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1858}
1859
1860static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1861{
1862 u32 data, data2, pass, retrycnt;
1863 u32 ddr_vref, phy_vref;
1864 u32 min_ddr_vref = 0, min_phy_vref = 0;
1865 u32 max_ddr_vref = 0, max_phy_vref = 0;
1866
1867 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1868 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1869 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1870 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1871 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1872 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1873 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1874 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1875
1876 /* DDR PHY Setting */
1877 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1878 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1879 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1880 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1881 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1882 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1883 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1884 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1885 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1886 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1887 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1888 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1889 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1890 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1891 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1892
1893 /* Controller Setting */
1894 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1895
1896 /* Train PHY Vref first */
1897 pass = 0;
1898
1899 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1900 max_phy_vref = 0x0;
1901 pass = 0;
1902 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1903 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1904 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1905 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1906 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1907 /* Fire DFI Init */
1908 ddr_phy_init_2500(ast);
1909 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1910 if (cbr_test_2500(ast)) {
1911 pass++;
1912 data = ast_mindwm(ast, 0x1E6E03D0);
1913 data2 = data >> 8;
1914 data = data & 0xff;
1915 if (data > data2)
1916 data = data2;
1917 if (max_phy_vref < data) {
1918 max_phy_vref = data;
1919 min_phy_vref = phy_vref;
1920 }
1921 } else if (pass > 0)
1922 break;
1923 }
1924 }
1925 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1926
1927 /* Train DDR Vref next */
1928 pass = 0;
1929
1930 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1931 min_ddr_vref = 0xFF;
1932 max_ddr_vref = 0x0;
1933 pass = 0;
1934 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1935 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1936 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1937 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1938 /* Fire DFI Init */
1939 ddr_phy_init_2500(ast);
1940 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1941 if (cbr_test_2500(ast)) {
1942 pass++;
1943 if (min_ddr_vref > ddr_vref)
1944 min_ddr_vref = ddr_vref;
1945 if (max_ddr_vref < ddr_vref)
1946 max_ddr_vref = ddr_vref;
1947 } else if (pass != 0)
1948 break;
1949 }
1950 }
1951
1952 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1953 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1954 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1955 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1956
1957 /* Wait DDR PHY init done */
1958 ddr_phy_init_2500(ast);
1959
1960 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1961 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1962 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1963
1964 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1965 enable_cache_2500(ast);
1966 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1967 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1968}
1969
1970static bool ast_dram_init_2500(struct ast_device *ast)
1971{
1972 u32 data;
1973 u32 max_tries = 5;
1974
1975 do {
1976 if (max_tries-- == 0)
1977 return false;
1978 set_mpll_2500(ast);
1979 reset_mmc_2500(ast);
1980 ddr_init_common_2500(ast);
1981
1982 data = ast_mindwm(ast, 0x1E6E2070);
1983 if (data & 0x01000000)
1984 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
1985 else
1986 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
1987 } while (!ddr_test_2500(ast));
1988
1989 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
1990
1991 /* Patch code */
1992 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
1993 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
1994
1995 return true;
1996}
1997
1998void ast_patch_ahb_2500(void __iomem *regs)
1999{
2000 u32 data;
2001
2002 /* Clear bus lock condition */
2003 __ast_moutdwm(regs, 0x1e600000, 0xAEED1A03);
2004 __ast_moutdwm(regs, 0x1e600084, 0x00010000);
2005 __ast_moutdwm(regs, 0x1e600088, 0x00000000);
2006 __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2007
2008 data = __ast_mindwm(regs, 0x1e6e2070);
2009 if (data & 0x08000000) { /* check fast reset */
2010 /*
2011 * If "Fast restet" is enabled for ARM-ICE debugger,
2012 * then WDT needs to enable, that
2013 * WDT04 is WDT#1 Reload reg.
2014 * WDT08 is WDT#1 counter restart reg to avoid system deadlock
2015 * WDT0C is WDT#1 control reg
2016 * [6:5]:= 01:Full chip
2017 * [4]:= 1:1MHz clock source
2018 * [1]:= 1:WDT will be cleeared and disabled after timeout occurs
2019 * [0]:= 1:WDT enable
2020 */
2021 __ast_moutdwm(regs, 0x1E785004, 0x00000010);
2022 __ast_moutdwm(regs, 0x1E785008, 0x00004755);
2023 __ast_moutdwm(regs, 0x1E78500c, 0x00000033);
2024 udelay(1000);
2025 }
2026
2027 do {
2028 __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2029 data = __ast_mindwm(regs, 0x1e6e2000);
2030 } while (data != 1);
2031
2032 __ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */
2033}
2034
2035void ast_post_chip_2500(struct ast_device *ast)
2036{
2037 struct drm_device *dev = &ast->base;
2038 u32 temp;
2039 u8 reg;
2040
2041 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2042 if ((reg & AST_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
2043 /* Clear bus lock condition */
2044 ast_patch_ahb_2500(ast->regs);
2045
2046 /* Disable watchdog */
2047 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2048 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2049
2050 /*
2051 * Reset USB port to patch USB unknown device issue
2052 * SCU90 is Multi-function Pin Control #5
2053 * [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
2054 * port).
2055 * SCU94 is Multi-function Pin Control #6
2056 * [14:13]:= 1x:USB2.0 Host2 controller
2057 * SCU70 is Hardware Strap reg
2058 * [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
2059 * [18]: 0(24)/1(48) MHz)
2060 * SCU7C is Write clear reg to SCU70
2061 * [23]:= write 1 and then SCU70[23] will be clear as 0b.
2062 */
2063 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2064 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2065 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2066 ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2067 mdelay(100);
2068 ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2069 }
2070 /* Modify eSPI reset pin */
2071 temp = ast_mindwm(ast, 0x1E6E2070);
2072 if (temp & 0x02000000)
2073 ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2074
2075 /* Slow down CPU/AHB CLK in VGA only mode */
2076 temp = ast_read32(ast, 0x12008);
2077 temp |= 0x73;
2078 ast_write32(ast, 0x12008, temp);
2079
2080 if (!ast_dram_init_2500(ast))
2081 drm_err(dev, "DRAM init failed !\n");
2082
2083 temp = ast_mindwm(ast, 0x1e6e2040);
2084 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2085 }
2086
2087 /* wait ready */
2088 do {
2089 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2090 } while ((reg & 0x40) == 0);
2091}
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/pci.h>
31
32#include <drm/drm_print.h>
33
34#include "ast_dram_tables.h"
35#include "ast_drv.h"
36
37static void ast_post_chip_2300(struct drm_device *dev);
38static void ast_post_chip_2500(struct drm_device *dev);
39
40void ast_enable_vga(struct drm_device *dev)
41{
42 struct ast_private *ast = to_ast_private(dev);
43
44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
46}
47
48void ast_enable_mmio(struct drm_device *dev)
49{
50 struct ast_private *ast = to_ast_private(dev);
51
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
53}
54
55
56bool ast_is_vga_enabled(struct drm_device *dev)
57{
58 struct ast_private *ast = to_ast_private(dev);
59 u8 ch;
60
61 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
62
63 return !!(ch & 0x01);
64}
65
66static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
67static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
68static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
69
70static void
71ast_set_def_ext_reg(struct drm_device *dev)
72{
73 struct ast_private *ast = to_ast_private(dev);
74 struct pci_dev *pdev = to_pci_dev(dev->dev);
75 u8 i, index, reg;
76 const u8 *ext_reg_info;
77
78 /* reset scratch */
79 for (i = 0x81; i <= 0x9f; i++)
80 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
81
82 if (ast->chip == AST2300 || ast->chip == AST2400 ||
83 ast->chip == AST2500) {
84 if (pdev->revision >= 0x20)
85 ext_reg_info = extreginfo_ast2300;
86 else
87 ext_reg_info = extreginfo_ast2300a0;
88 } else
89 ext_reg_info = extreginfo;
90
91 index = 0xa0;
92 while (*ext_reg_info != 0xff) {
93 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
94 index++;
95 ext_reg_info++;
96 }
97
98 /* disable standard IO/MEM decode if secondary */
99 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
100
101 /* Set Ext. Default */
102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
103 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
104
105 /* Enable RAMDAC for A1 */
106 reg = 0x04;
107 if (ast->chip == AST2300 || ast->chip == AST2400 ||
108 ast->chip == AST2500)
109 reg |= 0x20;
110 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
111}
112
113u32 ast_mindwm(struct ast_private *ast, u32 r)
114{
115 uint32_t data;
116
117 ast_write32(ast, 0xf004, r & 0xffff0000);
118 ast_write32(ast, 0xf000, 0x1);
119
120 do {
121 data = ast_read32(ast, 0xf004) & 0xffff0000;
122 } while (data != (r & 0xffff0000));
123 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
124}
125
126void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
127{
128 uint32_t data;
129 ast_write32(ast, 0xf004, r & 0xffff0000);
130 ast_write32(ast, 0xf000, 0x1);
131 do {
132 data = ast_read32(ast, 0xf004) & 0xffff0000;
133 } while (data != (r & 0xffff0000));
134 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
135}
136
137/*
138 * AST2100/2150 DLL CBR Setting
139 */
140#define CBR_SIZE_AST2150 ((16 << 10) - 1)
141#define CBR_PASSNUM_AST2150 5
142#define CBR_THRESHOLD_AST2150 10
143#define CBR_THRESHOLD2_AST2150 10
144#define TIMEOUT_AST2150 5000000
145
146#define CBR_PATNUM_AST2150 8
147
148static const u32 pattern_AST2150[14] = {
149 0xFF00FF00,
150 0xCC33CC33,
151 0xAA55AA55,
152 0xFFFE0001,
153 0x683501FE,
154 0x0F1929B0,
155 0x2D0B4346,
156 0x60767F02,
157 0x6FBE36A6,
158 0x3A253035,
159 0x3019686D,
160 0x41C6167E,
161 0x620152BF,
162 0x20F050E0
163};
164
165static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
166{
167 u32 data, timeout;
168
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
170 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
171 timeout = 0;
172 do {
173 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
174 if (++timeout > TIMEOUT_AST2150) {
175 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
176 return 0xffffffff;
177 }
178 } while (!data);
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
180 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
181 timeout = 0;
182 do {
183 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
184 if (++timeout > TIMEOUT_AST2150) {
185 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
186 return 0xffffffff;
187 }
188 } while (!data);
189 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
190 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
191 return data;
192}
193
194#if 0 /* unused in DDX driver - here for completeness */
195static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
196{
197 u32 data, timeout;
198
199 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
200 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
201 timeout = 0;
202 do {
203 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
204 if (++timeout > TIMEOUT_AST2150) {
205 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
206 return 0xffffffff;
207 }
208 } while (!data);
209 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
210 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
211 return data;
212}
213#endif
214
215static int cbrtest_ast2150(struct ast_private *ast)
216{
217 int i;
218
219 for (i = 0; i < 8; i++)
220 if (mmctestburst2_ast2150(ast, i))
221 return 0;
222 return 1;
223}
224
225static int cbrscan_ast2150(struct ast_private *ast, int busw)
226{
227 u32 patcnt, loop;
228
229 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
230 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
231 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
232 if (cbrtest_ast2150(ast))
233 break;
234 }
235 if (loop == CBR_PASSNUM_AST2150)
236 return 0;
237 }
238 return 1;
239}
240
241
242static void cbrdlli_ast2150(struct ast_private *ast, int busw)
243{
244 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
245
246cbr_start:
247 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
248 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
249 passcnt = 0;
250
251 for (dlli = 0; dlli < 100; dlli++) {
252 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
253 data = cbrscan_ast2150(ast, busw);
254 if (data != 0) {
255 if (data & 0x1) {
256 if (dll_min[0] > dlli)
257 dll_min[0] = dlli;
258 if (dll_max[0] < dlli)
259 dll_max[0] = dlli;
260 }
261 passcnt++;
262 } else if (passcnt >= CBR_THRESHOLD_AST2150)
263 goto cbr_start;
264 }
265 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
266 goto cbr_start;
267
268 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
269 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
270}
271
272
273
274static void ast_init_dram_reg(struct drm_device *dev)
275{
276 struct ast_private *ast = to_ast_private(dev);
277 u8 j;
278 u32 data, temp, i;
279 const struct ast_dramstruct *dram_reg_info;
280
281 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
282
283 if ((j & 0x80) == 0) { /* VGA only */
284 if (ast->chip == AST2000) {
285 dram_reg_info = ast2000_dram_table_data;
286 ast_write32(ast, 0xf004, 0x1e6e0000);
287 ast_write32(ast, 0xf000, 0x1);
288 ast_write32(ast, 0x10100, 0xa8);
289
290 do {
291 ;
292 } while (ast_read32(ast, 0x10100) != 0xa8);
293 } else {/* AST2100/1100 */
294 if (ast->chip == AST2100 || ast->chip == 2200)
295 dram_reg_info = ast2100_dram_table_data;
296 else
297 dram_reg_info = ast1100_dram_table_data;
298
299 ast_write32(ast, 0xf004, 0x1e6e0000);
300 ast_write32(ast, 0xf000, 0x1);
301 ast_write32(ast, 0x12000, 0x1688A8A8);
302 do {
303 ;
304 } while (ast_read32(ast, 0x12000) != 0x01);
305
306 ast_write32(ast, 0x10000, 0xfc600309);
307 do {
308 ;
309 } while (ast_read32(ast, 0x10000) != 0x01);
310 }
311
312 while (dram_reg_info->index != 0xffff) {
313 if (dram_reg_info->index == 0xff00) {/* delay fn */
314 for (i = 0; i < 15; i++)
315 udelay(dram_reg_info->data);
316 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
317 data = dram_reg_info->data;
318 if (ast->dram_type == AST_DRAM_1Gx16)
319 data = 0x00000d89;
320 else if (ast->dram_type == AST_DRAM_1Gx32)
321 data = 0x00000c8d;
322
323 temp = ast_read32(ast, 0x12070);
324 temp &= 0xc;
325 temp <<= 2;
326 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
327 } else
328 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
329 dram_reg_info++;
330 }
331
332 /* AST 2100/2150 DRAM calibration */
333 data = ast_read32(ast, 0x10120);
334 if (data == 0x5061) { /* 266Mhz */
335 data = ast_read32(ast, 0x10004);
336 if (data & 0x40)
337 cbrdlli_ast2150(ast, 16); /* 16 bits */
338 else
339 cbrdlli_ast2150(ast, 32); /* 32 bits */
340 }
341
342 switch (ast->chip) {
343 case AST2000:
344 temp = ast_read32(ast, 0x10140);
345 ast_write32(ast, 0x10140, temp | 0x40);
346 break;
347 case AST1100:
348 case AST2100:
349 case AST2200:
350 case AST2150:
351 temp = ast_read32(ast, 0x1200c);
352 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
353 temp = ast_read32(ast, 0x12040);
354 ast_write32(ast, 0x12040, temp | 0x40);
355 break;
356 default:
357 break;
358 }
359 }
360
361 /* wait ready */
362 do {
363 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
364 } while ((j & 0x40) == 0);
365}
366
367void ast_post_gpu(struct drm_device *dev)
368{
369 struct ast_private *ast = to_ast_private(dev);
370 struct pci_dev *pdev = to_pci_dev(dev->dev);
371 u32 reg;
372
373 pci_read_config_dword(pdev, 0x04, ®);
374 reg |= 0x3;
375 pci_write_config_dword(pdev, 0x04, reg);
376
377 ast_enable_vga(dev);
378 ast_open_key(ast);
379 ast_enable_mmio(dev);
380 ast_set_def_ext_reg(dev);
381
382 if (ast->config_mode == ast_use_p2a) {
383 if (ast->chip == AST2500)
384 ast_post_chip_2500(dev);
385 else if (ast->chip == AST2300 || ast->chip == AST2400)
386 ast_post_chip_2300(dev);
387 else
388 ast_init_dram_reg(dev);
389
390 ast_init_3rdtx(dev);
391 } else {
392 if (ast->tx_chip_type != AST_TX_NONE)
393 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
394 }
395}
396
397/* AST 2300 DRAM settings */
398#define AST_DDR3 0
399#define AST_DDR2 1
400
401struct ast2300_dram_param {
402 u32 dram_type;
403 u32 dram_chipid;
404 u32 dram_freq;
405 u32 vram_size;
406 u32 odt;
407 u32 wodt;
408 u32 rodt;
409 u32 dram_config;
410 u32 reg_PERIOD;
411 u32 reg_MADJ;
412 u32 reg_SADJ;
413 u32 reg_MRS;
414 u32 reg_EMRS;
415 u32 reg_AC1;
416 u32 reg_AC2;
417 u32 reg_DQSIC;
418 u32 reg_DRV;
419 u32 reg_IOZ;
420 u32 reg_DQIDLY;
421 u32 reg_FREQ;
422 u32 madj_max;
423 u32 dll2_finetune_step;
424};
425
426/*
427 * DQSI DLL CBR Setting
428 */
429#define CBR_SIZE0 ((1 << 10) - 1)
430#define CBR_SIZE1 ((4 << 10) - 1)
431#define CBR_SIZE2 ((64 << 10) - 1)
432#define CBR_PASSNUM 5
433#define CBR_PASSNUM2 5
434#define CBR_THRESHOLD 10
435#define CBR_THRESHOLD2 10
436#define TIMEOUT 5000000
437#define CBR_PATNUM 8
438
439static const u32 pattern[8] = {
440 0xFF00FF00,
441 0xCC33CC33,
442 0xAA55AA55,
443 0x88778877,
444 0x92CC4D6E,
445 0x543D3CDE,
446 0xF1E843C7,
447 0x7C61D253
448};
449
450static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
451{
452 u32 data, timeout;
453
454 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
455 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
456 timeout = 0;
457 do {
458 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
459 if (data & 0x2000)
460 return false;
461 if (++timeout > TIMEOUT) {
462 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
463 return false;
464 }
465 } while (!data);
466 ast_moutdwm(ast, 0x1e6e0070, 0x0);
467 return true;
468}
469
470static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
471{
472 u32 data, timeout;
473
474 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
475 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
476 timeout = 0;
477 do {
478 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
479 if (++timeout > TIMEOUT) {
480 ast_moutdwm(ast, 0x1e6e0070, 0x0);
481 return 0xffffffff;
482 }
483 } while (!data);
484 data = ast_mindwm(ast, 0x1e6e0078);
485 data = (data | (data >> 16)) & 0xffff;
486 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
487 return data;
488}
489
490
491static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
492{
493 return mmc_test(ast, datagen, 0xc1);
494}
495
496static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
497{
498 return mmc_test2(ast, datagen, 0x41);
499}
500
501static bool mmc_test_single(struct ast_private *ast, u32 datagen)
502{
503 return mmc_test(ast, datagen, 0xc5);
504}
505
506static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
507{
508 return mmc_test2(ast, datagen, 0x05);
509}
510
511static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
512{
513 return mmc_test(ast, datagen, 0x85);
514}
515
516static int cbr_test(struct ast_private *ast)
517{
518 u32 data;
519 int i;
520 data = mmc_test_single2(ast, 0);
521 if ((data & 0xff) && (data & 0xff00))
522 return 0;
523 for (i = 0; i < 8; i++) {
524 data = mmc_test_burst2(ast, i);
525 if ((data & 0xff) && (data & 0xff00))
526 return 0;
527 }
528 if (!data)
529 return 3;
530 else if (data & 0xff)
531 return 2;
532 return 1;
533}
534
535static int cbr_scan(struct ast_private *ast)
536{
537 u32 data, data2, patcnt, loop;
538
539 data2 = 3;
540 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
541 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
542 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
543 if ((data = cbr_test(ast)) != 0) {
544 data2 &= data;
545 if (!data2)
546 return 0;
547 break;
548 }
549 }
550 if (loop == CBR_PASSNUM2)
551 return 0;
552 }
553 return data2;
554}
555
556static u32 cbr_test2(struct ast_private *ast)
557{
558 u32 data;
559
560 data = mmc_test_burst2(ast, 0);
561 if (data == 0xffff)
562 return 0;
563 data |= mmc_test_single2(ast, 0);
564 if (data == 0xffff)
565 return 0;
566
567 return ~data & 0xffff;
568}
569
570static u32 cbr_scan2(struct ast_private *ast)
571{
572 u32 data, data2, patcnt, loop;
573
574 data2 = 0xffff;
575 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
576 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
577 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
578 if ((data = cbr_test2(ast)) != 0) {
579 data2 &= data;
580 if (!data2)
581 return 0;
582 break;
583 }
584 }
585 if (loop == CBR_PASSNUM2)
586 return 0;
587 }
588 return data2;
589}
590
591static bool cbr_test3(struct ast_private *ast)
592{
593 if (!mmc_test_burst(ast, 0))
594 return false;
595 if (!mmc_test_single(ast, 0))
596 return false;
597 return true;
598}
599
600static bool cbr_scan3(struct ast_private *ast)
601{
602 u32 patcnt, loop;
603
604 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
605 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
606 for (loop = 0; loop < 2; loop++) {
607 if (cbr_test3(ast))
608 break;
609 }
610 if (loop == 2)
611 return false;
612 }
613 return true;
614}
615
616static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
617{
618 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
619 bool status = false;
620FINETUNE_START:
621 for (cnt = 0; cnt < 16; cnt++) {
622 dllmin[cnt] = 0xff;
623 dllmax[cnt] = 0x0;
624 }
625 passcnt = 0;
626 for (dlli = 0; dlli < 76; dlli++) {
627 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
628 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
629 data = cbr_scan2(ast);
630 if (data != 0) {
631 mask = 0x00010001;
632 for (cnt = 0; cnt < 16; cnt++) {
633 if (data & mask) {
634 if (dllmin[cnt] > dlli) {
635 dllmin[cnt] = dlli;
636 }
637 if (dllmax[cnt] < dlli) {
638 dllmax[cnt] = dlli;
639 }
640 }
641 mask <<= 1;
642 }
643 passcnt++;
644 } else if (passcnt >= CBR_THRESHOLD2) {
645 break;
646 }
647 }
648 gold_sadj[0] = 0x0;
649 passcnt = 0;
650 for (cnt = 0; cnt < 16; cnt++) {
651 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
652 gold_sadj[0] += dllmin[cnt];
653 passcnt++;
654 }
655 }
656 if (retry++ > 10)
657 goto FINETUNE_DONE;
658 if (passcnt != 16) {
659 goto FINETUNE_START;
660 }
661 status = true;
662FINETUNE_DONE:
663 gold_sadj[0] = gold_sadj[0] >> 4;
664 gold_sadj[1] = gold_sadj[0];
665
666 data = 0;
667 for (cnt = 0; cnt < 8; cnt++) {
668 data >>= 3;
669 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
670 dlli = dllmin[cnt];
671 if (gold_sadj[0] >= dlli) {
672 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
673 if (dlli > 3) {
674 dlli = 3;
675 }
676 } else {
677 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
678 if (dlli > 4) {
679 dlli = 4;
680 }
681 dlli = (8 - dlli) & 0x7;
682 }
683 data |= dlli << 21;
684 }
685 }
686 ast_moutdwm(ast, 0x1E6E0080, data);
687
688 data = 0;
689 for (cnt = 8; cnt < 16; cnt++) {
690 data >>= 3;
691 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
692 dlli = dllmin[cnt];
693 if (gold_sadj[1] >= dlli) {
694 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
695 if (dlli > 3) {
696 dlli = 3;
697 } else {
698 dlli = (dlli - 1) & 0x7;
699 }
700 } else {
701 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
702 dlli += 1;
703 if (dlli > 4) {
704 dlli = 4;
705 }
706 dlli = (8 - dlli) & 0x7;
707 }
708 data |= dlli << 21;
709 }
710 }
711 ast_moutdwm(ast, 0x1E6E0084, data);
712 return status;
713} /* finetuneDQI_L */
714
715static void finetuneDQSI(struct ast_private *ast)
716{
717 u32 dlli, dqsip, dqidly;
718 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
719 u32 g_dqidly, g_dqsip, g_margin, g_side;
720 u16 pass[32][2][2];
721 char tag[2][76];
722
723 /* Disable DQI CBR */
724 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
725 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
726 reg_mcr18 &= 0x0000ffff;
727 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
728
729 for (dlli = 0; dlli < 76; dlli++) {
730 tag[0][dlli] = 0x0;
731 tag[1][dlli] = 0x0;
732 }
733 for (dqidly = 0; dqidly < 32; dqidly++) {
734 pass[dqidly][0][0] = 0xff;
735 pass[dqidly][0][1] = 0x0;
736 pass[dqidly][1][0] = 0xff;
737 pass[dqidly][1][1] = 0x0;
738 }
739 for (dqidly = 0; dqidly < 32; dqidly++) {
740 passcnt[0] = passcnt[1] = 0;
741 for (dqsip = 0; dqsip < 2; dqsip++) {
742 ast_moutdwm(ast, 0x1E6E000C, 0);
743 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
744 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
745 for (dlli = 0; dlli < 76; dlli++) {
746 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
747 ast_moutdwm(ast, 0x1E6E0070, 0);
748 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
749 if (cbr_scan3(ast)) {
750 if (dlli == 0)
751 break;
752 passcnt[dqsip]++;
753 tag[dqsip][dlli] = 'P';
754 if (dlli < pass[dqidly][dqsip][0])
755 pass[dqidly][dqsip][0] = (u16) dlli;
756 if (dlli > pass[dqidly][dqsip][1])
757 pass[dqidly][dqsip][1] = (u16) dlli;
758 } else if (passcnt[dqsip] >= 5)
759 break;
760 else {
761 pass[dqidly][dqsip][0] = 0xff;
762 pass[dqidly][dqsip][1] = 0x0;
763 }
764 }
765 }
766 if (passcnt[0] == 0 && passcnt[1] == 0)
767 dqidly++;
768 }
769 /* Search margin */
770 g_dqidly = g_dqsip = g_margin = g_side = 0;
771
772 for (dqidly = 0; dqidly < 32; dqidly++) {
773 for (dqsip = 0; dqsip < 2; dqsip++) {
774 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
775 continue;
776 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
777 if ((diff+2) < g_margin)
778 continue;
779 passcnt[0] = passcnt[1] = 0;
780 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
781 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
782 if (passcnt[0] > passcnt[1])
783 passcnt[0] = passcnt[1];
784 passcnt[1] = 0;
785 if (passcnt[0] > g_side)
786 passcnt[1] = passcnt[0] - g_side;
787 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
788 g_margin = diff;
789 g_dqidly = dqidly;
790 g_dqsip = dqsip;
791 g_side = passcnt[0];
792 } else if (passcnt[1] > 1 && g_side < 8) {
793 if (diff > g_margin)
794 g_margin = diff;
795 g_dqidly = dqidly;
796 g_dqsip = dqsip;
797 g_side = passcnt[0];
798 }
799 }
800 }
801 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
802 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
803
804}
805static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
806{
807 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
808 bool status = false;
809
810 finetuneDQSI(ast);
811 if (finetuneDQI_L(ast, param) == false)
812 return status;
813
814CBR_START2:
815 dllmin[0] = dllmin[1] = 0xff;
816 dllmax[0] = dllmax[1] = 0x0;
817 passcnt = 0;
818 for (dlli = 0; dlli < 76; dlli++) {
819 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
820 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
821 data = cbr_scan(ast);
822 if (data != 0) {
823 if (data & 0x1) {
824 if (dllmin[0] > dlli) {
825 dllmin[0] = dlli;
826 }
827 if (dllmax[0] < dlli) {
828 dllmax[0] = dlli;
829 }
830 }
831 if (data & 0x2) {
832 if (dllmin[1] > dlli) {
833 dllmin[1] = dlli;
834 }
835 if (dllmax[1] < dlli) {
836 dllmax[1] = dlli;
837 }
838 }
839 passcnt++;
840 } else if (passcnt >= CBR_THRESHOLD) {
841 break;
842 }
843 }
844 if (retry++ > 10)
845 goto CBR_DONE2;
846 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
847 goto CBR_START2;
848 }
849 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
850 goto CBR_START2;
851 }
852 status = true;
853CBR_DONE2:
854 dlli = (dllmin[1] + dllmax[1]) >> 1;
855 dlli <<= 8;
856 dlli += (dllmin[0] + dllmax[0]) >> 1;
857 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
858 return status;
859} /* CBRDLL2 */
860
861static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
862{
863 u32 trap, trap_AC2, trap_MRS;
864
865 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
866
867 /* Ger trap info */
868 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
869 trap_AC2 = 0x00020000 + (trap << 16);
870 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
871 trap_MRS = 0x00000010 + (trap << 4);
872 trap_MRS |= ((trap & 0x2) << 18);
873
874 param->reg_MADJ = 0x00034C4C;
875 param->reg_SADJ = 0x00001800;
876 param->reg_DRV = 0x000000F0;
877 param->reg_PERIOD = param->dram_freq;
878 param->rodt = 0;
879
880 switch (param->dram_freq) {
881 case 336:
882 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
883 param->wodt = 0;
884 param->reg_AC1 = 0x22202725;
885 param->reg_AC2 = 0xAA007613 | trap_AC2;
886 param->reg_DQSIC = 0x000000BA;
887 param->reg_MRS = 0x04001400 | trap_MRS;
888 param->reg_EMRS = 0x00000000;
889 param->reg_IOZ = 0x00000023;
890 param->reg_DQIDLY = 0x00000074;
891 param->reg_FREQ = 0x00004DC0;
892 param->madj_max = 96;
893 param->dll2_finetune_step = 3;
894 switch (param->dram_chipid) {
895 default:
896 case AST_DRAM_512Mx16:
897 case AST_DRAM_1Gx16:
898 param->reg_AC2 = 0xAA007613 | trap_AC2;
899 break;
900 case AST_DRAM_2Gx16:
901 param->reg_AC2 = 0xAA00761C | trap_AC2;
902 break;
903 case AST_DRAM_4Gx16:
904 param->reg_AC2 = 0xAA007636 | trap_AC2;
905 break;
906 }
907 break;
908 default:
909 case 396:
910 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
911 param->wodt = 1;
912 param->reg_AC1 = 0x33302825;
913 param->reg_AC2 = 0xCC009617 | trap_AC2;
914 param->reg_DQSIC = 0x000000E2;
915 param->reg_MRS = 0x04001600 | trap_MRS;
916 param->reg_EMRS = 0x00000000;
917 param->reg_IOZ = 0x00000034;
918 param->reg_DRV = 0x000000FA;
919 param->reg_DQIDLY = 0x00000089;
920 param->reg_FREQ = 0x00005040;
921 param->madj_max = 96;
922 param->dll2_finetune_step = 4;
923
924 switch (param->dram_chipid) {
925 default:
926 case AST_DRAM_512Mx16:
927 case AST_DRAM_1Gx16:
928 param->reg_AC2 = 0xCC009617 | trap_AC2;
929 break;
930 case AST_DRAM_2Gx16:
931 param->reg_AC2 = 0xCC009622 | trap_AC2;
932 break;
933 case AST_DRAM_4Gx16:
934 param->reg_AC2 = 0xCC00963F | trap_AC2;
935 break;
936 }
937 break;
938
939 case 408:
940 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
941 param->wodt = 1;
942 param->reg_AC1 = 0x33302825;
943 param->reg_AC2 = 0xCC009617 | trap_AC2;
944 param->reg_DQSIC = 0x000000E2;
945 param->reg_MRS = 0x04001600 | trap_MRS;
946 param->reg_EMRS = 0x00000000;
947 param->reg_IOZ = 0x00000023;
948 param->reg_DRV = 0x000000FA;
949 param->reg_DQIDLY = 0x00000089;
950 param->reg_FREQ = 0x000050C0;
951 param->madj_max = 96;
952 param->dll2_finetune_step = 4;
953
954 switch (param->dram_chipid) {
955 default:
956 case AST_DRAM_512Mx16:
957 case AST_DRAM_1Gx16:
958 param->reg_AC2 = 0xCC009617 | trap_AC2;
959 break;
960 case AST_DRAM_2Gx16:
961 param->reg_AC2 = 0xCC009622 | trap_AC2;
962 break;
963 case AST_DRAM_4Gx16:
964 param->reg_AC2 = 0xCC00963F | trap_AC2;
965 break;
966 }
967
968 break;
969 case 456:
970 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
971 param->wodt = 0;
972 param->reg_AC1 = 0x33302926;
973 param->reg_AC2 = 0xCD44961A;
974 param->reg_DQSIC = 0x000000FC;
975 param->reg_MRS = 0x00081830;
976 param->reg_EMRS = 0x00000000;
977 param->reg_IOZ = 0x00000045;
978 param->reg_DQIDLY = 0x00000097;
979 param->reg_FREQ = 0x000052C0;
980 param->madj_max = 88;
981 param->dll2_finetune_step = 4;
982 break;
983 case 504:
984 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
985 param->wodt = 1;
986 param->reg_AC1 = 0x33302926;
987 param->reg_AC2 = 0xDE44A61D;
988 param->reg_DQSIC = 0x00000117;
989 param->reg_MRS = 0x00081A30;
990 param->reg_EMRS = 0x00000000;
991 param->reg_IOZ = 0x070000BB;
992 param->reg_DQIDLY = 0x000000A0;
993 param->reg_FREQ = 0x000054C0;
994 param->madj_max = 79;
995 param->dll2_finetune_step = 4;
996 break;
997 case 528:
998 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
999 param->wodt = 1;
1000 param->rodt = 1;
1001 param->reg_AC1 = 0x33302926;
1002 param->reg_AC2 = 0xEF44B61E;
1003 param->reg_DQSIC = 0x00000125;
1004 param->reg_MRS = 0x00081A30;
1005 param->reg_EMRS = 0x00000040;
1006 param->reg_DRV = 0x000000F5;
1007 param->reg_IOZ = 0x00000023;
1008 param->reg_DQIDLY = 0x00000088;
1009 param->reg_FREQ = 0x000055C0;
1010 param->madj_max = 76;
1011 param->dll2_finetune_step = 3;
1012 break;
1013 case 576:
1014 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1015 param->reg_MADJ = 0x00136868;
1016 param->reg_SADJ = 0x00004534;
1017 param->wodt = 1;
1018 param->rodt = 1;
1019 param->reg_AC1 = 0x33302A37;
1020 param->reg_AC2 = 0xEF56B61E;
1021 param->reg_DQSIC = 0x0000013F;
1022 param->reg_MRS = 0x00101A50;
1023 param->reg_EMRS = 0x00000040;
1024 param->reg_DRV = 0x000000FA;
1025 param->reg_IOZ = 0x00000023;
1026 param->reg_DQIDLY = 0x00000078;
1027 param->reg_FREQ = 0x000057C0;
1028 param->madj_max = 136;
1029 param->dll2_finetune_step = 3;
1030 break;
1031 case 600:
1032 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1033 param->reg_MADJ = 0x00136868;
1034 param->reg_SADJ = 0x00004534;
1035 param->wodt = 1;
1036 param->rodt = 1;
1037 param->reg_AC1 = 0x32302A37;
1038 param->reg_AC2 = 0xDF56B61F;
1039 param->reg_DQSIC = 0x0000014D;
1040 param->reg_MRS = 0x00101A50;
1041 param->reg_EMRS = 0x00000004;
1042 param->reg_DRV = 0x000000F5;
1043 param->reg_IOZ = 0x00000023;
1044 param->reg_DQIDLY = 0x00000078;
1045 param->reg_FREQ = 0x000058C0;
1046 param->madj_max = 132;
1047 param->dll2_finetune_step = 3;
1048 break;
1049 case 624:
1050 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1051 param->reg_MADJ = 0x00136868;
1052 param->reg_SADJ = 0x00004534;
1053 param->wodt = 1;
1054 param->rodt = 1;
1055 param->reg_AC1 = 0x32302A37;
1056 param->reg_AC2 = 0xEF56B621;
1057 param->reg_DQSIC = 0x0000015A;
1058 param->reg_MRS = 0x02101A50;
1059 param->reg_EMRS = 0x00000004;
1060 param->reg_DRV = 0x000000F5;
1061 param->reg_IOZ = 0x00000034;
1062 param->reg_DQIDLY = 0x00000078;
1063 param->reg_FREQ = 0x000059C0;
1064 param->madj_max = 128;
1065 param->dll2_finetune_step = 3;
1066 break;
1067 } /* switch freq */
1068
1069 switch (param->dram_chipid) {
1070 case AST_DRAM_512Mx16:
1071 param->dram_config = 0x130;
1072 break;
1073 default:
1074 case AST_DRAM_1Gx16:
1075 param->dram_config = 0x131;
1076 break;
1077 case AST_DRAM_2Gx16:
1078 param->dram_config = 0x132;
1079 break;
1080 case AST_DRAM_4Gx16:
1081 param->dram_config = 0x133;
1082 break;
1083 } /* switch size */
1084
1085 switch (param->vram_size) {
1086 default:
1087 case AST_VIDMEM_SIZE_8M:
1088 param->dram_config |= 0x00;
1089 break;
1090 case AST_VIDMEM_SIZE_16M:
1091 param->dram_config |= 0x04;
1092 break;
1093 case AST_VIDMEM_SIZE_32M:
1094 param->dram_config |= 0x08;
1095 break;
1096 case AST_VIDMEM_SIZE_64M:
1097 param->dram_config |= 0x0c;
1098 break;
1099 }
1100
1101}
1102
1103static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1104{
1105 u32 data, data2, retry = 0;
1106
1107ddr3_init_start:
1108 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1109 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1110 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1111 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1112 udelay(10);
1113 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1114 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1115 udelay(10);
1116 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1117 udelay(10);
1118
1119 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1120 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1121 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1122 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1123 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1124 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1125 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1126 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1127 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1128 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1129 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1130 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1131 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1132 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1133 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1134 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1135 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1136 ast_moutdwm(ast, 0x1E6E0054, 0);
1137 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1138 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1139 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1140 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1141 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1142 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1143 /* Wait MCLK2X lock to MCLK */
1144 do {
1145 data = ast_mindwm(ast, 0x1E6E001C);
1146 } while (!(data & 0x08000000));
1147 data = ast_mindwm(ast, 0x1E6E001C);
1148 data = (data >> 8) & 0xff;
1149 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1150 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1151 if ((data2 & 0xff) > param->madj_max) {
1152 break;
1153 }
1154 ast_moutdwm(ast, 0x1E6E0064, data2);
1155 if (data2 & 0x00100000) {
1156 data2 = ((data2 & 0xff) >> 3) + 3;
1157 } else {
1158 data2 = ((data2 & 0xff) >> 2) + 5;
1159 }
1160 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1161 data2 += data & 0xff;
1162 data = data | (data2 << 8);
1163 ast_moutdwm(ast, 0x1E6E0068, data);
1164 udelay(10);
1165 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1166 udelay(10);
1167 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1168 ast_moutdwm(ast, 0x1E6E0018, data);
1169 data = data | 0x200;
1170 ast_moutdwm(ast, 0x1E6E0018, data);
1171 do {
1172 data = ast_mindwm(ast, 0x1E6E001C);
1173 } while (!(data & 0x08000000));
1174
1175 data = ast_mindwm(ast, 0x1E6E001C);
1176 data = (data >> 8) & 0xff;
1177 }
1178 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1179 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1180 ast_moutdwm(ast, 0x1E6E0018, data);
1181
1182 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1183 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1184 udelay(50);
1185 /* Mode Register Setting */
1186 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1187 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1188 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1189 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1190 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1191 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1192 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1193 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1194 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1195
1196 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1197 data = 0;
1198 if (param->wodt) {
1199 data = 0x300;
1200 }
1201 if (param->rodt) {
1202 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1203 }
1204 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1205
1206 /* Calibrate the DQSI delay */
1207 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1208 goto ddr3_init_start;
1209
1210 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1211 /* ECC Memory Initialization */
1212#ifdef ECC
1213 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1214 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1215 do {
1216 data = ast_mindwm(ast, 0x1E6E0070);
1217 } while (!(data & 0x00001000));
1218 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1219 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1220 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1221#endif
1222
1223
1224}
1225
1226static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1227{
1228 u32 trap, trap_AC2, trap_MRS;
1229
1230 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1231
1232 /* Ger trap info */
1233 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1234 trap_AC2 = (trap << 20) | (trap << 16);
1235 trap_AC2 += 0x00110000;
1236 trap_MRS = 0x00000040 | (trap << 4);
1237
1238
1239 param->reg_MADJ = 0x00034C4C;
1240 param->reg_SADJ = 0x00001800;
1241 param->reg_DRV = 0x000000F0;
1242 param->reg_PERIOD = param->dram_freq;
1243 param->rodt = 0;
1244
1245 switch (param->dram_freq) {
1246 case 264:
1247 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1248 param->wodt = 0;
1249 param->reg_AC1 = 0x11101513;
1250 param->reg_AC2 = 0x78117011;
1251 param->reg_DQSIC = 0x00000092;
1252 param->reg_MRS = 0x00000842;
1253 param->reg_EMRS = 0x00000000;
1254 param->reg_DRV = 0x000000F0;
1255 param->reg_IOZ = 0x00000034;
1256 param->reg_DQIDLY = 0x0000005A;
1257 param->reg_FREQ = 0x00004AC0;
1258 param->madj_max = 138;
1259 param->dll2_finetune_step = 3;
1260 break;
1261 case 336:
1262 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1263 param->wodt = 1;
1264 param->reg_AC1 = 0x22202613;
1265 param->reg_AC2 = 0xAA009016 | trap_AC2;
1266 param->reg_DQSIC = 0x000000BA;
1267 param->reg_MRS = 0x00000A02 | trap_MRS;
1268 param->reg_EMRS = 0x00000040;
1269 param->reg_DRV = 0x000000FA;
1270 param->reg_IOZ = 0x00000034;
1271 param->reg_DQIDLY = 0x00000074;
1272 param->reg_FREQ = 0x00004DC0;
1273 param->madj_max = 96;
1274 param->dll2_finetune_step = 3;
1275 switch (param->dram_chipid) {
1276 default:
1277 case AST_DRAM_512Mx16:
1278 param->reg_AC2 = 0xAA009012 | trap_AC2;
1279 break;
1280 case AST_DRAM_1Gx16:
1281 param->reg_AC2 = 0xAA009016 | trap_AC2;
1282 break;
1283 case AST_DRAM_2Gx16:
1284 param->reg_AC2 = 0xAA009023 | trap_AC2;
1285 break;
1286 case AST_DRAM_4Gx16:
1287 param->reg_AC2 = 0xAA00903B | trap_AC2;
1288 break;
1289 }
1290 break;
1291 default:
1292 case 396:
1293 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1294 param->wodt = 1;
1295 param->rodt = 0;
1296 param->reg_AC1 = 0x33302714;
1297 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1298 param->reg_DQSIC = 0x000000E2;
1299 param->reg_MRS = 0x00000C02 | trap_MRS;
1300 param->reg_EMRS = 0x00000040;
1301 param->reg_DRV = 0x000000FA;
1302 param->reg_IOZ = 0x00000034;
1303 param->reg_DQIDLY = 0x00000089;
1304 param->reg_FREQ = 0x00005040;
1305 param->madj_max = 96;
1306 param->dll2_finetune_step = 4;
1307
1308 switch (param->dram_chipid) {
1309 case AST_DRAM_512Mx16:
1310 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1311 break;
1312 default:
1313 case AST_DRAM_1Gx16:
1314 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1315 break;
1316 case AST_DRAM_2Gx16:
1317 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1318 break;
1319 case AST_DRAM_4Gx16:
1320 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1321 break;
1322 }
1323
1324 break;
1325
1326 case 408:
1327 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1328 param->wodt = 1;
1329 param->rodt = 0;
1330 param->reg_AC1 = 0x33302714;
1331 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1332 param->reg_DQSIC = 0x000000E2;
1333 param->reg_MRS = 0x00000C02 | trap_MRS;
1334 param->reg_EMRS = 0x00000040;
1335 param->reg_DRV = 0x000000FA;
1336 param->reg_IOZ = 0x00000034;
1337 param->reg_DQIDLY = 0x00000089;
1338 param->reg_FREQ = 0x000050C0;
1339 param->madj_max = 96;
1340 param->dll2_finetune_step = 4;
1341
1342 switch (param->dram_chipid) {
1343 case AST_DRAM_512Mx16:
1344 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1345 break;
1346 default:
1347 case AST_DRAM_1Gx16:
1348 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1349 break;
1350 case AST_DRAM_2Gx16:
1351 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1352 break;
1353 case AST_DRAM_4Gx16:
1354 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1355 break;
1356 }
1357
1358 break;
1359 case 456:
1360 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1361 param->wodt = 0;
1362 param->reg_AC1 = 0x33302815;
1363 param->reg_AC2 = 0xCD44B01E;
1364 param->reg_DQSIC = 0x000000FC;
1365 param->reg_MRS = 0x00000E72;
1366 param->reg_EMRS = 0x00000000;
1367 param->reg_DRV = 0x00000000;
1368 param->reg_IOZ = 0x00000034;
1369 param->reg_DQIDLY = 0x00000097;
1370 param->reg_FREQ = 0x000052C0;
1371 param->madj_max = 88;
1372 param->dll2_finetune_step = 3;
1373 break;
1374 case 504:
1375 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1376 param->wodt = 1;
1377 param->rodt = 1;
1378 param->reg_AC1 = 0x33302815;
1379 param->reg_AC2 = 0xDE44C022;
1380 param->reg_DQSIC = 0x00000117;
1381 param->reg_MRS = 0x00000E72;
1382 param->reg_EMRS = 0x00000040;
1383 param->reg_DRV = 0x0000000A;
1384 param->reg_IOZ = 0x00000045;
1385 param->reg_DQIDLY = 0x000000A0;
1386 param->reg_FREQ = 0x000054C0;
1387 param->madj_max = 79;
1388 param->dll2_finetune_step = 3;
1389 break;
1390 case 528:
1391 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1392 param->wodt = 1;
1393 param->rodt = 1;
1394 param->reg_AC1 = 0x33302815;
1395 param->reg_AC2 = 0xEF44D024;
1396 param->reg_DQSIC = 0x00000125;
1397 param->reg_MRS = 0x00000E72;
1398 param->reg_EMRS = 0x00000004;
1399 param->reg_DRV = 0x000000F9;
1400 param->reg_IOZ = 0x00000045;
1401 param->reg_DQIDLY = 0x000000A7;
1402 param->reg_FREQ = 0x000055C0;
1403 param->madj_max = 76;
1404 param->dll2_finetune_step = 3;
1405 break;
1406 case 552:
1407 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1408 param->wodt = 1;
1409 param->rodt = 1;
1410 param->reg_AC1 = 0x43402915;
1411 param->reg_AC2 = 0xFF44E025;
1412 param->reg_DQSIC = 0x00000132;
1413 param->reg_MRS = 0x00000E72;
1414 param->reg_EMRS = 0x00000040;
1415 param->reg_DRV = 0x0000000A;
1416 param->reg_IOZ = 0x00000045;
1417 param->reg_DQIDLY = 0x000000AD;
1418 param->reg_FREQ = 0x000056C0;
1419 param->madj_max = 76;
1420 param->dll2_finetune_step = 3;
1421 break;
1422 case 576:
1423 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1424 param->wodt = 1;
1425 param->rodt = 1;
1426 param->reg_AC1 = 0x43402915;
1427 param->reg_AC2 = 0xFF44E027;
1428 param->reg_DQSIC = 0x0000013F;
1429 param->reg_MRS = 0x00000E72;
1430 param->reg_EMRS = 0x00000004;
1431 param->reg_DRV = 0x000000F5;
1432 param->reg_IOZ = 0x00000045;
1433 param->reg_DQIDLY = 0x000000B3;
1434 param->reg_FREQ = 0x000057C0;
1435 param->madj_max = 76;
1436 param->dll2_finetune_step = 3;
1437 break;
1438 }
1439
1440 switch (param->dram_chipid) {
1441 case AST_DRAM_512Mx16:
1442 param->dram_config = 0x100;
1443 break;
1444 default:
1445 case AST_DRAM_1Gx16:
1446 param->dram_config = 0x121;
1447 break;
1448 case AST_DRAM_2Gx16:
1449 param->dram_config = 0x122;
1450 break;
1451 case AST_DRAM_4Gx16:
1452 param->dram_config = 0x123;
1453 break;
1454 } /* switch size */
1455
1456 switch (param->vram_size) {
1457 default:
1458 case AST_VIDMEM_SIZE_8M:
1459 param->dram_config |= 0x00;
1460 break;
1461 case AST_VIDMEM_SIZE_16M:
1462 param->dram_config |= 0x04;
1463 break;
1464 case AST_VIDMEM_SIZE_32M:
1465 param->dram_config |= 0x08;
1466 break;
1467 case AST_VIDMEM_SIZE_64M:
1468 param->dram_config |= 0x0c;
1469 break;
1470 }
1471}
1472
1473static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1474{
1475 u32 data, data2, retry = 0;
1476
1477ddr2_init_start:
1478 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1479 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1480 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1481 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1482 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1483 udelay(10);
1484 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1485 udelay(10);
1486
1487 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1488 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1489 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1490 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1491 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1492 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1493 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1494 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1495 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1496 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1497 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1498 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1499 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1500 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1501 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1502 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1503 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1504 ast_moutdwm(ast, 0x1E6E0054, 0);
1505 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1506 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1507 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1508 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1509 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1510 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1511
1512 /* Wait MCLK2X lock to MCLK */
1513 do {
1514 data = ast_mindwm(ast, 0x1E6E001C);
1515 } while (!(data & 0x08000000));
1516 data = ast_mindwm(ast, 0x1E6E001C);
1517 data = (data >> 8) & 0xff;
1518 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1519 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1520 if ((data2 & 0xff) > param->madj_max) {
1521 break;
1522 }
1523 ast_moutdwm(ast, 0x1E6E0064, data2);
1524 if (data2 & 0x00100000) {
1525 data2 = ((data2 & 0xff) >> 3) + 3;
1526 } else {
1527 data2 = ((data2 & 0xff) >> 2) + 5;
1528 }
1529 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1530 data2 += data & 0xff;
1531 data = data | (data2 << 8);
1532 ast_moutdwm(ast, 0x1E6E0068, data);
1533 udelay(10);
1534 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1535 udelay(10);
1536 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1537 ast_moutdwm(ast, 0x1E6E0018, data);
1538 data = data | 0x200;
1539 ast_moutdwm(ast, 0x1E6E0018, data);
1540 do {
1541 data = ast_mindwm(ast, 0x1E6E001C);
1542 } while (!(data & 0x08000000));
1543
1544 data = ast_mindwm(ast, 0x1E6E001C);
1545 data = (data >> 8) & 0xff;
1546 }
1547 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1548 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1549 ast_moutdwm(ast, 0x1E6E0018, data);
1550
1551 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1552 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1553 udelay(50);
1554 /* Mode Register Setting */
1555 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1556 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1557 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1558 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1559 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1560 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1561
1562 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1563 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1564 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1565 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1567 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1568 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1569
1570 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1571 data = 0;
1572 if (param->wodt) {
1573 data = 0x500;
1574 }
1575 if (param->rodt) {
1576 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1577 }
1578 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1579 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1580
1581 /* Calibrate the DQSI delay */
1582 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1583 goto ddr2_init_start;
1584
1585 /* ECC Memory Initialization */
1586#ifdef ECC
1587 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1588 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1589 do {
1590 data = ast_mindwm(ast, 0x1E6E0070);
1591 } while (!(data & 0x00001000));
1592 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1593 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1594 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1595#endif
1596
1597}
1598
1599static void ast_post_chip_2300(struct drm_device *dev)
1600{
1601 struct ast_private *ast = to_ast_private(dev);
1602 struct ast2300_dram_param param;
1603 u32 temp;
1604 u8 reg;
1605
1606 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1607 if ((reg & 0x80) == 0) {/* vga only */
1608 ast_write32(ast, 0xf004, 0x1e6e0000);
1609 ast_write32(ast, 0xf000, 0x1);
1610 ast_write32(ast, 0x12000, 0x1688a8a8);
1611 do {
1612 ;
1613 } while (ast_read32(ast, 0x12000) != 0x1);
1614
1615 ast_write32(ast, 0x10000, 0xfc600309);
1616 do {
1617 ;
1618 } while (ast_read32(ast, 0x10000) != 0x1);
1619
1620 /* Slow down CPU/AHB CLK in VGA only mode */
1621 temp = ast_read32(ast, 0x12008);
1622 temp |= 0x73;
1623 ast_write32(ast, 0x12008, temp);
1624
1625 param.dram_freq = 396;
1626 param.dram_type = AST_DDR3;
1627 temp = ast_mindwm(ast, 0x1e6e2070);
1628 if (temp & 0x01000000)
1629 param.dram_type = AST_DDR2;
1630 switch (temp & 0x18000000) {
1631 case 0:
1632 param.dram_chipid = AST_DRAM_512Mx16;
1633 break;
1634 default:
1635 case 0x08000000:
1636 param.dram_chipid = AST_DRAM_1Gx16;
1637 break;
1638 case 0x10000000:
1639 param.dram_chipid = AST_DRAM_2Gx16;
1640 break;
1641 case 0x18000000:
1642 param.dram_chipid = AST_DRAM_4Gx16;
1643 break;
1644 }
1645 switch (temp & 0x0c) {
1646 default:
1647 case 0x00:
1648 param.vram_size = AST_VIDMEM_SIZE_8M;
1649 break;
1650
1651 case 0x04:
1652 param.vram_size = AST_VIDMEM_SIZE_16M;
1653 break;
1654
1655 case 0x08:
1656 param.vram_size = AST_VIDMEM_SIZE_32M;
1657 break;
1658
1659 case 0x0c:
1660 param.vram_size = AST_VIDMEM_SIZE_64M;
1661 break;
1662 }
1663
1664 if (param.dram_type == AST_DDR3) {
1665 get_ddr3_info(ast, ¶m);
1666 ddr3_init(ast, ¶m);
1667 } else {
1668 get_ddr2_info(ast, ¶m);
1669 ddr2_init(ast, ¶m);
1670 }
1671
1672 temp = ast_mindwm(ast, 0x1e6e2040);
1673 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1674 }
1675
1676 /* wait ready */
1677 do {
1678 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1679 } while ((reg & 0x40) == 0);
1680}
1681
1682static bool cbr_test_2500(struct ast_private *ast)
1683{
1684 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1685 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1686 if (!mmc_test_burst(ast, 0))
1687 return false;
1688 if (!mmc_test_single_2500(ast, 0))
1689 return false;
1690 return true;
1691}
1692
1693static bool ddr_test_2500(struct ast_private *ast)
1694{
1695 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1696 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1697 if (!mmc_test_burst(ast, 0))
1698 return false;
1699 if (!mmc_test_burst(ast, 1))
1700 return false;
1701 if (!mmc_test_burst(ast, 2))
1702 return false;
1703 if (!mmc_test_burst(ast, 3))
1704 return false;
1705 if (!mmc_test_single_2500(ast, 0))
1706 return false;
1707 return true;
1708}
1709
1710static void ddr_init_common_2500(struct ast_private *ast)
1711{
1712 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1713 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1714 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1715 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1716 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1717 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1718 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1719 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1720 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1721 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1722 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1723 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1724 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1725 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1726 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1727 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1728 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1729 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1730 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1731}
1732
1733static void ddr_phy_init_2500(struct ast_private *ast)
1734{
1735 u32 data, pass, timecnt;
1736
1737 pass = 0;
1738 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1739 while (!pass) {
1740 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1741 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1742 if (!data)
1743 break;
1744 }
1745 if (timecnt != TIMEOUT) {
1746 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1747 if (!data)
1748 pass = 1;
1749 }
1750 if (!pass) {
1751 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1752 udelay(10); /* delay 10 us */
1753 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1754 }
1755 }
1756
1757 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1758}
1759
1760/*
1761 * Check DRAM Size
1762 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1763 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1764 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1765 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1766 */
1767static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
1768{
1769 u32 reg_04, reg_14;
1770
1771 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1772 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1773
1774 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1775 ast_moutdwm(ast, 0x90100000, 0x35363738);
1776 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1777 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1778
1779 /* Check 8Gbit */
1780 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1781 reg_04 |= 0x03;
1782 reg_14 |= (tRFC >> 24) & 0xFF;
1783 /* Check 4Gbit */
1784 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1785 reg_04 |= 0x02;
1786 reg_14 |= (tRFC >> 16) & 0xFF;
1787 /* Check 2Gbit */
1788 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1789 reg_04 |= 0x01;
1790 reg_14 |= (tRFC >> 8) & 0xFF;
1791 } else {
1792 reg_14 |= tRFC & 0xFF;
1793 }
1794 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1795 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1796}
1797
1798static void enable_cache_2500(struct ast_private *ast)
1799{
1800 u32 reg_04, data;
1801
1802 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1803 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1804
1805 do
1806 data = ast_mindwm(ast, 0x1E6E0004);
1807 while (!(data & 0x80000));
1808 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1809}
1810
1811static void set_mpll_2500(struct ast_private *ast)
1812{
1813 u32 addr, data, param;
1814
1815 /* Reset MMC */
1816 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1817 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1818 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1819 ast_moutdwm(ast, addr, 0x0);
1820 addr += 4;
1821 }
1822 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1823
1824 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1825 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1826 if (data) {
1827 /* CLKIN = 25MHz */
1828 param = 0x930023E0;
1829 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1830 } else {
1831 /* CLKIN = 24MHz */
1832 param = 0x93002400;
1833 }
1834 ast_moutdwm(ast, 0x1E6E2020, param);
1835 udelay(100);
1836}
1837
1838static void reset_mmc_2500(struct ast_private *ast)
1839{
1840 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1841 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1842 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1843 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1844 mdelay(100);
1845 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1846 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1847}
1848
1849static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
1850{
1851
1852 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1853 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1854 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1855 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1856 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1857 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1858 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1859 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1860
1861 /* DDR PHY Setting */
1862 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1863 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1864 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1865 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1866 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1867 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1868 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1869 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1870 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1871 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1872 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1873 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1874 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1875 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1876
1877 /* Controller Setting */
1878 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1879
1880 /* Wait DDR PHY init done */
1881 ddr_phy_init_2500(ast);
1882
1883 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1884 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1885 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1886
1887 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1888 enable_cache_2500(ast);
1889 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1890 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1891}
1892
1893static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
1894{
1895 u32 data, data2, pass, retrycnt;
1896 u32 ddr_vref, phy_vref;
1897 u32 min_ddr_vref = 0, min_phy_vref = 0;
1898 u32 max_ddr_vref = 0, max_phy_vref = 0;
1899
1900 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1901 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1902 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1903 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1904 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1905 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1906 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1907 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1908
1909 /* DDR PHY Setting */
1910 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1911 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1912 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1913 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1914 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1915 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1916 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1917 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1918 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1919 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1920 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1921 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1922 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1923 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1924 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1925
1926 /* Controller Setting */
1927 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1928
1929 /* Train PHY Vref first */
1930 pass = 0;
1931
1932 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1933 max_phy_vref = 0x0;
1934 pass = 0;
1935 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1936 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1937 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1938 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1939 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1940 /* Fire DFI Init */
1941 ddr_phy_init_2500(ast);
1942 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1943 if (cbr_test_2500(ast)) {
1944 pass++;
1945 data = ast_mindwm(ast, 0x1E6E03D0);
1946 data2 = data >> 8;
1947 data = data & 0xff;
1948 if (data > data2)
1949 data = data2;
1950 if (max_phy_vref < data) {
1951 max_phy_vref = data;
1952 min_phy_vref = phy_vref;
1953 }
1954 } else if (pass > 0)
1955 break;
1956 }
1957 }
1958 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1959
1960 /* Train DDR Vref next */
1961 pass = 0;
1962
1963 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1964 min_ddr_vref = 0xFF;
1965 max_ddr_vref = 0x0;
1966 pass = 0;
1967 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1968 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1969 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1970 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1971 /* Fire DFI Init */
1972 ddr_phy_init_2500(ast);
1973 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1974 if (cbr_test_2500(ast)) {
1975 pass++;
1976 if (min_ddr_vref > ddr_vref)
1977 min_ddr_vref = ddr_vref;
1978 if (max_ddr_vref < ddr_vref)
1979 max_ddr_vref = ddr_vref;
1980 } else if (pass != 0)
1981 break;
1982 }
1983 }
1984
1985 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1986 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1987 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1988 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1989
1990 /* Wait DDR PHY init done */
1991 ddr_phy_init_2500(ast);
1992
1993 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1994 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1995 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1996
1997 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1998 enable_cache_2500(ast);
1999 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
2000 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
2001}
2002
2003static bool ast_dram_init_2500(struct ast_private *ast)
2004{
2005 u32 data;
2006 u32 max_tries = 5;
2007
2008 do {
2009 if (max_tries-- == 0)
2010 return false;
2011 set_mpll_2500(ast);
2012 reset_mmc_2500(ast);
2013 ddr_init_common_2500(ast);
2014
2015 data = ast_mindwm(ast, 0x1E6E2070);
2016 if (data & 0x01000000)
2017 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
2018 else
2019 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
2020 } while (!ddr_test_2500(ast));
2021
2022 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2023
2024 /* Patch code */
2025 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2026 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2027
2028 return true;
2029}
2030
2031void ast_patch_ahb_2500(struct ast_private *ast)
2032{
2033 u32 data;
2034
2035 /* Clear bus lock condition */
2036 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
2037 ast_moutdwm(ast, 0x1e600084, 0x00010000);
2038 ast_moutdwm(ast, 0x1e600088, 0x00000000);
2039 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2040 data = ast_mindwm(ast, 0x1e6e2070);
2041 if (data & 0x08000000) { /* check fast reset */
2042 /*
2043 * If "Fast restet" is enabled for ARM-ICE debugger,
2044 * then WDT needs to enable, that
2045 * WDT04 is WDT#1 Reload reg.
2046 * WDT08 is WDT#1 counter restart reg to avoid system deadlock
2047 * WDT0C is WDT#1 control reg
2048 * [6:5]:= 01:Full chip
2049 * [4]:= 1:1MHz clock source
2050 * [1]:= 1:WDT will be cleeared and disabled after timeout occurs
2051 * [0]:= 1:WDT enable
2052 */
2053 ast_moutdwm(ast, 0x1E785004, 0x00000010);
2054 ast_moutdwm(ast, 0x1E785008, 0x00004755);
2055 ast_moutdwm(ast, 0x1E78500c, 0x00000033);
2056 udelay(1000);
2057 }
2058 do {
2059 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2060 data = ast_mindwm(ast, 0x1e6e2000);
2061 } while (data != 1);
2062 ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */
2063}
2064
2065void ast_post_chip_2500(struct drm_device *dev)
2066{
2067 struct ast_private *ast = to_ast_private(dev);
2068 u32 temp;
2069 u8 reg;
2070
2071 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2072 if ((reg & AST_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
2073 /* Clear bus lock condition */
2074 ast_patch_ahb_2500(ast);
2075
2076 /* Disable watchdog */
2077 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2078 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2079
2080 /*
2081 * Reset USB port to patch USB unknown device issue
2082 * SCU90 is Multi-function Pin Control #5
2083 * [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
2084 * port).
2085 * SCU94 is Multi-function Pin Control #6
2086 * [14:13]:= 1x:USB2.0 Host2 controller
2087 * SCU70 is Hardware Strap reg
2088 * [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
2089 * [18]: 0(24)/1(48) MHz)
2090 * SCU7C is Write clear reg to SCU70
2091 * [23]:= write 1 and then SCU70[23] will be clear as 0b.
2092 */
2093 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2094 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2095 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2096 ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2097 mdelay(100);
2098 ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2099 }
2100 /* Modify eSPI reset pin */
2101 temp = ast_mindwm(ast, 0x1E6E2070);
2102 if (temp & 0x02000000)
2103 ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2104
2105 /* Slow down CPU/AHB CLK in VGA only mode */
2106 temp = ast_read32(ast, 0x12008);
2107 temp |= 0x73;
2108 ast_write32(ast, 0x12008, temp);
2109
2110 if (!ast_dram_init_2500(ast))
2111 drm_err(dev, "DRAM init failed !\n");
2112
2113 temp = ast_mindwm(ast, 0x1e6e2040);
2114 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2115 }
2116
2117 /* wait ready */
2118 do {
2119 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2120 } while ((reg & 0x40) == 0);
2121}