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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_net.h>
24#include <linux/nvmem-consumer.h>
25#include <linux/relay.h>
26#include <linux/dmi.h>
27#include <net/ieee80211_radiotap.h>
28
29#include "ath9k.h"
30
31struct ath9k_eeprom_ctx {
32 struct completion complete;
33 struct ath_hw *ah;
34};
35
36static char *dev_info = "ath9k";
37
38MODULE_AUTHOR("Atheros Communications");
39MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
40MODULE_LICENSE("Dual BSD/GPL");
41
42static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
43module_param_named(debug, ath9k_debug, uint, 0);
44MODULE_PARM_DESC(debug, "Debugging mask");
45
46int ath9k_modparam_nohwcrypt;
47module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
48MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
49
50int ath9k_led_blink;
51module_param_named(blink, ath9k_led_blink, int, 0444);
52MODULE_PARM_DESC(blink, "Enable LED blink on activity");
53
54static int ath9k_led_active_high = -1;
55module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
56MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
57
58static int ath9k_btcoex_enable;
59module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
60MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
61
62static int ath9k_bt_ant_diversity;
63module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
64MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
65
66static int ath9k_ps_enable;
67module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
68MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
69
70#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
71
72int ath9k_use_chanctx;
73module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
74MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
75
76#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
77
78int ath9k_use_msi;
79module_param_named(use_msi, ath9k_use_msi, int, 0444);
80MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible");
81
82bool is_ath9k_unloaded;
83
84#ifdef CONFIG_MAC80211_LEDS
85static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
86 { .throughput = 0 * 1024, .blink_time = 334 },
87 { .throughput = 1 * 1024, .blink_time = 260 },
88 { .throughput = 5 * 1024, .blink_time = 220 },
89 { .throughput = 10 * 1024, .blink_time = 190 },
90 { .throughput = 20 * 1024, .blink_time = 170 },
91 { .throughput = 50 * 1024, .blink_time = 150 },
92 { .throughput = 70 * 1024, .blink_time = 130 },
93 { .throughput = 100 * 1024, .blink_time = 110 },
94 { .throughput = 200 * 1024, .blink_time = 80 },
95 { .throughput = 300 * 1024, .blink_time = 50 },
96};
97#endif
98
99static int __init set_use_msi(const struct dmi_system_id *dmi)
100{
101 ath9k_use_msi = 1;
102 return 1;
103}
104
105static const struct dmi_system_id ath9k_quirks[] __initconst = {
106 {
107 .callback = set_use_msi,
108 .ident = "Dell Inspiron 24-3460",
109 .matches = {
110 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
111 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"),
112 },
113 },
114 {
115 .callback = set_use_msi,
116 .ident = "Dell Vostro 3262",
117 .matches = {
118 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
119 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"),
120 },
121 },
122 {
123 .callback = set_use_msi,
124 .ident = "Dell Inspiron 3472",
125 .matches = {
126 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
127 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"),
128 },
129 },
130 {
131 .callback = set_use_msi,
132 .ident = "Dell Vostro 15-3572",
133 .matches = {
134 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
135 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"),
136 },
137 },
138 {
139 .callback = set_use_msi,
140 .ident = "Dell Inspiron 14-3473",
141 .matches = {
142 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
143 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"),
144 },
145 },
146 {}
147};
148
149static void ath9k_deinit_softc(struct ath_softc *sc);
150
151static void ath9k_op_ps_wakeup(struct ath_common *common)
152{
153 ath9k_ps_wakeup(common->priv);
154}
155
156static void ath9k_op_ps_restore(struct ath_common *common)
157{
158 ath9k_ps_restore(common->priv);
159}
160
161static const struct ath_ps_ops ath9k_ps_ops = {
162 .wakeup = ath9k_op_ps_wakeup,
163 .restore = ath9k_op_ps_restore,
164};
165
166/*
167 * Read and write, they both share the same lock. We do this to serialize
168 * reads and writes on Atheros 802.11n PCI devices only. This is required
169 * as the FIFO on these devices can only accept sanely 2 requests.
170 */
171
172static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
173{
174 struct ath_hw *ah = hw_priv;
175 struct ath_common *common = ath9k_hw_common(ah);
176 struct ath_softc *sc = common->priv;
177
178 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
179 unsigned long flags;
180 spin_lock_irqsave(&sc->sc_serial_rw, flags);
181 iowrite32(val, sc->mem + reg_offset);
182 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
183 } else
184 iowrite32(val, sc->mem + reg_offset);
185}
186
187static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
188{
189 struct ath_hw *ah = hw_priv;
190 struct ath_common *common = ath9k_hw_common(ah);
191 struct ath_softc *sc = common->priv;
192 u32 val;
193
194 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
195 unsigned long flags;
196 spin_lock_irqsave(&sc->sc_serial_rw, flags);
197 val = ioread32(sc->mem + reg_offset);
198 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
199 } else
200 val = ioread32(sc->mem + reg_offset);
201 return val;
202}
203
204static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
205 u32 *val, u16 count)
206{
207 int i;
208
209 for (i = 0; i < count; i++)
210 val[i] = ath9k_ioread32(hw_priv, addr[i]);
211}
212
213
214static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
215 u32 set, u32 clr)
216{
217 u32 val;
218
219 val = ioread32(sc->mem + reg_offset);
220 val &= ~clr;
221 val |= set;
222 iowrite32(val, sc->mem + reg_offset);
223
224 return val;
225}
226
227static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
228{
229 struct ath_hw *ah = hw_priv;
230 struct ath_common *common = ath9k_hw_common(ah);
231 struct ath_softc *sc = common->priv;
232 unsigned long flags;
233 u32 val;
234
235 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
236 spin_lock_irqsave(&sc->sc_serial_rw, flags);
237 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
238 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
239 } else
240 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
241
242 return val;
243}
244
245/**************************/
246/* Initialization */
247/**************************/
248
249static void ath9k_reg_notifier(struct wiphy *wiphy,
250 struct regulatory_request *request)
251{
252 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
253 struct ath_softc *sc = hw->priv;
254 struct ath_hw *ah = sc->sc_ah;
255 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
256
257 ath_reg_notifier_apply(wiphy, request, reg);
258
259 /* synchronize DFS detector if regulatory domain changed */
260 if (sc->dfs_detector != NULL)
261 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
262 request->dfs_region);
263
264 /* Set tx power */
265 if (!ah->curchan)
266 return;
267
268 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
269 ath9k_ps_wakeup(sc);
270 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
271 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
272 sc->cur_chan->txpower,
273 &sc->cur_chan->cur_txpower);
274 ath9k_ps_restore(sc);
275}
276
277/*
278 * This function will allocate both the DMA descriptor structure, and the
279 * buffers it contains. These are used to contain the descriptors used
280 * by the system.
281*/
282int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
283 struct list_head *head, const char *name,
284 int nbuf, int ndesc, bool is_tx)
285{
286 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
287 u8 *ds;
288 int i, bsize, desc_len;
289
290 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
291 name, nbuf, ndesc);
292
293 INIT_LIST_HEAD(head);
294
295 if (is_tx)
296 desc_len = sc->sc_ah->caps.tx_desc_len;
297 else
298 desc_len = sizeof(struct ath_desc);
299
300 /* ath_desc must be a multiple of DWORDs */
301 if ((desc_len % 4) != 0) {
302 ath_err(common, "ath_desc not DWORD aligned\n");
303 BUG_ON((desc_len % 4) != 0);
304 return -ENOMEM;
305 }
306
307 dd->dd_desc_len = desc_len * nbuf * ndesc;
308
309 /*
310 * Need additional DMA memory because we can't use
311 * descriptors that cross the 4K page boundary. Assume
312 * one skipped descriptor per 4K page.
313 */
314 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
315 u32 ndesc_skipped =
316 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
317 u32 dma_len;
318
319 while (ndesc_skipped) {
320 dma_len = ndesc_skipped * desc_len;
321 dd->dd_desc_len += dma_len;
322
323 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
324 }
325 }
326
327 /* allocate descriptors */
328 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
329 &dd->dd_desc_paddr, GFP_KERNEL);
330 if (!dd->dd_desc)
331 return -ENOMEM;
332
333 ds = dd->dd_desc;
334 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
335 name, ds, (u32) dd->dd_desc_len,
336 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
337
338 /* allocate buffers */
339 if (is_tx) {
340 struct ath_buf *bf;
341
342 bsize = sizeof(struct ath_buf) * nbuf;
343 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
344 if (!bf)
345 return -ENOMEM;
346
347 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
348 bf->bf_desc = ds;
349 bf->bf_daddr = DS2PHYS(dd, ds);
350
351 if (!(sc->sc_ah->caps.hw_caps &
352 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
353 /*
354 * Skip descriptor addresses which can cause 4KB
355 * boundary crossing (addr + length) with a 32 dword
356 * descriptor fetch.
357 */
358 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
359 BUG_ON((caddr_t) bf->bf_desc >=
360 ((caddr_t) dd->dd_desc +
361 dd->dd_desc_len));
362
363 ds += (desc_len * ndesc);
364 bf->bf_desc = ds;
365 bf->bf_daddr = DS2PHYS(dd, ds);
366 }
367 }
368 list_add_tail(&bf->list, head);
369 }
370 } else {
371 struct ath_rxbuf *bf;
372
373 bsize = sizeof(struct ath_rxbuf) * nbuf;
374 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
375 if (!bf)
376 return -ENOMEM;
377
378 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
379 bf->bf_desc = ds;
380 bf->bf_daddr = DS2PHYS(dd, ds);
381
382 if (!(sc->sc_ah->caps.hw_caps &
383 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
384 /*
385 * Skip descriptor addresses which can cause 4KB
386 * boundary crossing (addr + length) with a 32 dword
387 * descriptor fetch.
388 */
389 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
390 BUG_ON((caddr_t) bf->bf_desc >=
391 ((caddr_t) dd->dd_desc +
392 dd->dd_desc_len));
393
394 ds += (desc_len * ndesc);
395 bf->bf_desc = ds;
396 bf->bf_daddr = DS2PHYS(dd, ds);
397 }
398 }
399 list_add_tail(&bf->list, head);
400 }
401 }
402 return 0;
403}
404
405static int ath9k_init_queues(struct ath_softc *sc)
406{
407 int i = 0;
408
409 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
410 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
411 ath_cabq_update(sc);
412
413 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
414
415 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
416 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
417 sc->tx.txq_map[i]->mac80211_qnum = i;
418 }
419 return 0;
420}
421
422static void ath9k_init_misc(struct ath_softc *sc)
423{
424 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
425 int i = 0;
426
427 timer_setup(&common->ani.timer, ath_ani_calibrate, 0);
428
429 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
430 eth_broadcast_addr(common->bssidmask);
431 sc->beacon.slottime = 9;
432
433 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
434 sc->beacon.bslot[i] = NULL;
435
436 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
437 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
438
439 sc->spec_priv.ah = sc->sc_ah;
440 sc->spec_priv.spec_config.enabled = 0;
441 sc->spec_priv.spec_config.short_repeat = true;
442 sc->spec_priv.spec_config.count = 8;
443 sc->spec_priv.spec_config.endless = false;
444 sc->spec_priv.spec_config.period = 0xFF;
445 sc->spec_priv.spec_config.fft_period = 0xF;
446}
447
448static void ath9k_init_pcoem_platform(struct ath_softc *sc)
449{
450 struct ath_hw *ah = sc->sc_ah;
451 struct ath9k_hw_capabilities *pCap = &ah->caps;
452 struct ath_common *common = ath9k_hw_common(ah);
453
454 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
455 return;
456
457 if (common->bus_ops->ath_bus_type != ATH_PCI)
458 return;
459
460 if (sc->driver_data & (ATH9K_PCI_CUS198 |
461 ATH9K_PCI_CUS230)) {
462 ah->config.xlna_gpio = 9;
463 ah->config.xatten_margin_cfg = true;
464 ah->config.alt_mingainidx = true;
465 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
466 sc->ant_comb.low_rssi_thresh = 20;
467 sc->ant_comb.fast_div_bias = 3;
468
469 ath_info(common, "Set parameters for %s\n",
470 (sc->driver_data & ATH9K_PCI_CUS198) ?
471 "CUS198" : "CUS230");
472 }
473
474 if (sc->driver_data & ATH9K_PCI_CUS217)
475 ath_info(common, "CUS217 card detected\n");
476
477 if (sc->driver_data & ATH9K_PCI_CUS252)
478 ath_info(common, "CUS252 card detected\n");
479
480 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
481 ath_info(common, "WB335 1-ANT card detected\n");
482
483 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
484 ath_info(common, "WB335 2-ANT card detected\n");
485
486 if (sc->driver_data & ATH9K_PCI_KILLER)
487 ath_info(common, "Killer Wireless card detected\n");
488
489 /*
490 * Some WB335 cards do not support antenna diversity. Since
491 * we use a hardcoded value for AR9565 instead of using the
492 * EEPROM/OTP data, remove the combining feature from
493 * the HW capabilities bitmap.
494 */
495 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
496 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
497 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
498 }
499
500 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
501 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
502 ath_info(common, "Set BT/WLAN RX diversity capability\n");
503 }
504
505 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
506 ah->config.pcie_waen = 0x0040473b;
507 ath_info(common, "Enable WAR for ASPM D3/L1\n");
508 }
509
510 /*
511 * The default value of pll_pwrsave is 1.
512 * For certain AR9485 cards, it is set to 0.
513 * For AR9462, AR9565 it's set to 7.
514 */
515 ah->config.pll_pwrsave = 1;
516
517 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
518 ah->config.pll_pwrsave = 0;
519 ath_info(common, "Disable PLL PowerSave\n");
520 }
521
522 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
523 ah->config.led_active_high = true;
524}
525
526static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
527 void *ctx)
528{
529 struct ath9k_eeprom_ctx *ec = ctx;
530
531 if (eeprom_blob)
532 ec->ah->eeprom_blob = eeprom_blob;
533
534 complete(&ec->complete);
535}
536
537static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
538{
539 struct ath9k_eeprom_ctx ec;
540 struct ath_hw *ah = sc->sc_ah;
541 int err;
542
543 /* try to load the EEPROM content asynchronously */
544 init_completion(&ec.complete);
545 ec.ah = sc->sc_ah;
546
547 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
548 &ec, ath9k_eeprom_request_cb);
549 if (err < 0) {
550 ath_err(ath9k_hw_common(ah),
551 "EEPROM request failed\n");
552 return err;
553 }
554
555 wait_for_completion(&ec.complete);
556
557 if (!ah->eeprom_blob) {
558 ath_err(ath9k_hw_common(ah),
559 "Unable to load EEPROM file %s\n", name);
560 return -EINVAL;
561 }
562
563 return 0;
564}
565
566static void ath9k_eeprom_release(struct ath_softc *sc)
567{
568 release_firmware(sc->sc_ah->eeprom_blob);
569}
570
571static int ath9k_nvmem_request_eeprom(struct ath_softc *sc)
572{
573 struct ath_hw *ah = sc->sc_ah;
574 struct nvmem_cell *cell;
575 void *buf;
576 size_t len;
577 int err;
578
579 cell = devm_nvmem_cell_get(sc->dev, "calibration");
580 if (IS_ERR(cell)) {
581 err = PTR_ERR(cell);
582
583 /* nvmem cell might not be defined, or the nvmem
584 * subsystem isn't included. In this case, follow
585 * the established "just return 0;" convention
586 * to say:
587 * "All good. Nothing to see here. Please go on."
588 */
589 if (err == -ENOENT || err == -EOPNOTSUPP)
590 return 0;
591
592 return err;
593 }
594
595 buf = nvmem_cell_read(cell, &len);
596 if (IS_ERR(buf))
597 return PTR_ERR(buf);
598
599 /* run basic sanity checks on the returned nvram cell length.
600 * That length has to be a multiple of a "u16" (i.e.: & 1).
601 * Furthermore, it has to be more than "let's say" 512 bytes
602 * but less than the maximum of AR9300_EEPROM_SIZE (16kb).
603 */
604 if ((len & 1) == 1 || len < 512 || len >= AR9300_EEPROM_SIZE) {
605 kfree(buf);
606 return -EINVAL;
607 }
608
609 /* devres manages the calibration values release on shutdown */
610 ah->nvmem_blob = devm_kmemdup(sc->dev, buf, len, GFP_KERNEL);
611 kfree(buf);
612 if (!ah->nvmem_blob)
613 return -ENOMEM;
614
615 ah->nvmem_blob_len = len;
616 ah->ah_flags &= ~AH_USE_EEPROM;
617 ah->ah_flags |= AH_NO_EEP_SWAP;
618
619 return 0;
620}
621
622static int ath9k_of_init(struct ath_softc *sc)
623{
624 struct device_node *np = sc->dev->of_node;
625 struct ath_hw *ah = sc->sc_ah;
626 struct ath_common *common = ath9k_hw_common(ah);
627 enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
628 char eeprom_name[100];
629 int ret;
630
631 if (!of_device_is_available(np))
632 return 0;
633
634 ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
635
636 if (of_property_read_bool(np, "qca,no-eeprom")) {
637 /* ath9k-eeprom-<bus>-<id>.bin */
638 scnprintf(eeprom_name, sizeof(eeprom_name),
639 "ath9k-eeprom-%s-%s.bin",
640 ath_bus_type_to_string(bus_type), dev_name(ah->dev));
641
642 ret = ath9k_eeprom_request(sc, eeprom_name);
643 if (ret)
644 return ret;
645
646 ah->ah_flags &= ~AH_USE_EEPROM;
647 ah->ah_flags |= AH_NO_EEP_SWAP;
648 }
649
650 of_get_mac_address(np, common->macaddr);
651
652 return 0;
653}
654
655static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
656 const struct ath_bus_ops *bus_ops)
657{
658 struct ath_hw *ah = NULL;
659 struct ath9k_hw_capabilities *pCap;
660 struct ath_common *common;
661 int ret = 0, i;
662 int csz = 0;
663
664 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
665 if (!ah)
666 return -ENOMEM;
667
668 ah->dev = sc->dev;
669 ah->hw = sc->hw;
670 ah->hw_version.devid = devid;
671 ah->ah_flags |= AH_USE_EEPROM;
672 ah->led_pin = -1;
673 ah->reg_ops.read = ath9k_ioread32;
674 ah->reg_ops.multi_read = ath9k_multi_ioread32;
675 ah->reg_ops.write = ath9k_iowrite32;
676 ah->reg_ops.rmw = ath9k_reg_rmw;
677 pCap = &ah->caps;
678
679 common = ath9k_hw_common(ah);
680
681 /* Will be cleared in ath9k_start() */
682 set_bit(ATH_OP_INVALID, &common->op_flags);
683
684 sc->sc_ah = ah;
685 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
686 sc->tx99_power = MAX_RATE_POWER + 1;
687 init_waitqueue_head(&sc->tx_wait);
688 sc->cur_chan = &sc->chanctx[0];
689 if (!ath9k_is_chanctx_enabled())
690 sc->cur_chan->hw_queue_base = 0;
691
692 common->ops = &ah->reg_ops;
693 common->bus_ops = bus_ops;
694 common->ps_ops = &ath9k_ps_ops;
695 common->ah = ah;
696 common->hw = sc->hw;
697 common->priv = sc;
698 common->debug_mask = ath9k_debug;
699 common->btcoex_enabled = ath9k_btcoex_enable == 1;
700 common->disable_ani = false;
701
702 /*
703 * Platform quirks.
704 */
705 ath9k_init_pcoem_platform(sc);
706
707 ret = ath9k_of_init(sc);
708 if (ret)
709 return ret;
710
711 ret = ath9k_nvmem_request_eeprom(sc);
712 if (ret)
713 return ret;
714
715 if (ath9k_led_active_high != -1)
716 ah->config.led_active_high = ath9k_led_active_high == 1;
717
718 /*
719 * Enable WLAN/BT RX Antenna diversity only when:
720 *
721 * - BTCOEX is disabled.
722 * - the user manually requests the feature.
723 * - the HW cap is set using the platform data.
724 */
725 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
726 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
727 common->bt_ant_diversity = 1;
728
729 spin_lock_init(&common->cc_lock);
730 spin_lock_init(&sc->intr_lock);
731 spin_lock_init(&sc->sc_serial_rw);
732 spin_lock_init(&sc->sc_pm_lock);
733 spin_lock_init(&sc->chan_lock);
734 mutex_init(&sc->mutex);
735 tasklet_setup(&sc->intr_tq, ath9k_tasklet);
736 tasklet_setup(&sc->bcon_tasklet, ath9k_beacon_tasklet);
737
738 timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0);
739 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
740 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
741 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
742 INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work);
743
744 ath9k_init_channel_context(sc);
745
746 /*
747 * Cache line size is used to size and align various
748 * structures used to communicate with the hardware.
749 */
750 ath_read_cachesize(common, &csz);
751 common->cachelsz = csz << 2; /* convert to bytes */
752
753 /* Initializes the hardware for all supported chipsets */
754 ret = ath9k_hw_init(ah);
755 if (ret)
756 goto err_hw;
757
758 ret = ath9k_init_queues(sc);
759 if (ret)
760 goto err_queues;
761
762 ret = ath9k_init_btcoex(sc);
763 if (ret)
764 goto err_btcoex;
765
766 ret = ath9k_cmn_init_channels_rates(common);
767 if (ret)
768 goto err_btcoex;
769
770 ret = ath9k_init_p2p(sc);
771 if (ret)
772 goto err_btcoex;
773
774 ath9k_cmn_init_crypto(sc->sc_ah);
775 ath9k_init_misc(sc);
776 ath_chanctx_init(sc);
777 ath9k_offchannel_init(sc);
778
779 if (common->bus_ops->aspm_init)
780 common->bus_ops->aspm_init(common);
781
782 return 0;
783
784err_btcoex:
785 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
786 if (ATH_TXQ_SETUP(sc, i))
787 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
788err_queues:
789 ath9k_hw_deinit(ah);
790err_hw:
791 ath9k_eeprom_release(sc);
792 dev_kfree_skb_any(sc->tx99_skb);
793 return ret;
794}
795
796static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
797{
798 struct ieee80211_supported_band *sband;
799 struct ieee80211_channel *chan;
800 struct ath_hw *ah = sc->sc_ah;
801 struct ath_common *common = ath9k_hw_common(ah);
802 struct cfg80211_chan_def chandef;
803 int i;
804
805 sband = &common->sbands[band];
806 for (i = 0; i < sband->n_channels; i++) {
807 chan = &sband->channels[i];
808 ah->curchan = &ah->channels[chan->hw_value];
809 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
810 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
811 ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true);
812 }
813}
814
815static void ath9k_init_txpower_limits(struct ath_softc *sc)
816{
817 struct ath_hw *ah = sc->sc_ah;
818 struct ath9k_channel *curchan = ah->curchan;
819
820 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
821 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
822 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
823 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
824
825 ah->curchan = curchan;
826}
827
828static const struct ieee80211_iface_limit if_limits[] = {
829 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
830 { .max = 8, .types =
831#ifdef CONFIG_MAC80211_MESH
832 BIT(NL80211_IFTYPE_MESH_POINT) |
833#endif
834 BIT(NL80211_IFTYPE_AP) },
835 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
836 BIT(NL80211_IFTYPE_P2P_GO) },
837};
838
839#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
840
841static const struct ieee80211_iface_limit if_limits_multi[] = {
842 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
843 BIT(NL80211_IFTYPE_AP) |
844 BIT(NL80211_IFTYPE_P2P_CLIENT) |
845 BIT(NL80211_IFTYPE_P2P_GO) },
846 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
847 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
848};
849
850static const struct ieee80211_iface_combination if_comb_multi[] = {
851 {
852 .limits = if_limits_multi,
853 .n_limits = ARRAY_SIZE(if_limits_multi),
854 .max_interfaces = 3,
855 .num_different_channels = 2,
856 .beacon_int_infra_match = true,
857 },
858};
859
860#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
861
862static const struct ieee80211_iface_combination if_comb[] = {
863 {
864 .limits = if_limits,
865 .n_limits = ARRAY_SIZE(if_limits),
866 .max_interfaces = 2048,
867 .num_different_channels = 1,
868 .beacon_int_infra_match = true,
869#ifdef CONFIG_ATH9K_DFS_CERTIFIED
870 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
871 BIT(NL80211_CHAN_WIDTH_20) |
872 BIT(NL80211_CHAN_WIDTH_40),
873#endif
874 },
875};
876
877#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
878static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
879{
880 struct ath_hw *ah = sc->sc_ah;
881 struct ath_common *common = ath9k_hw_common(ah);
882
883 if (!ath9k_is_chanctx_enabled())
884 return;
885
886 ieee80211_hw_set(hw, QUEUE_CONTROL);
887 hw->queues = ATH9K_NUM_TX_QUEUES;
888 hw->offchannel_tx_hw_queue = hw->queues - 1;
889 hw->wiphy->iface_combinations = if_comb_multi;
890 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
891 hw->wiphy->max_scan_ssids = 255;
892 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
893 hw->wiphy->max_remain_on_channel_duration = 10000;
894 hw->chanctx_data_size = sizeof(void *);
895 hw->extra_beacon_tailroom =
896 sizeof(struct ieee80211_p2p_noa_attr) + 9;
897
898 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
899}
900#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
901
902static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
903{
904 struct ath_hw *ah = sc->sc_ah;
905 struct ath_common *common = ath9k_hw_common(ah);
906
907 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
908 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
909 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
910 ieee80211_hw_set(hw, SPECTRUM_MGMT);
911 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
912 ieee80211_hw_set(hw, SIGNAL_DBM);
913 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
914 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
915 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
916 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
917
918 if (ath9k_ps_enable)
919 ieee80211_hw_set(hw, SUPPORTS_PS);
920
921 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
922 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
923
924 if (AR_SREV_9280_20_OR_LATER(ah))
925 hw->radiotap_mcs_details |=
926 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
927 }
928
929 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
930 ieee80211_hw_set(hw, MFP_CAPABLE);
931
932 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
933 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
934 NL80211_FEATURE_P2P_GO_CTWIN;
935
936 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {
937 hw->wiphy->interface_modes =
938 BIT(NL80211_IFTYPE_P2P_GO) |
939 BIT(NL80211_IFTYPE_P2P_CLIENT) |
940 BIT(NL80211_IFTYPE_AP) |
941 BIT(NL80211_IFTYPE_STATION) |
942 BIT(NL80211_IFTYPE_ADHOC) |
943 BIT(NL80211_IFTYPE_MESH_POINT) |
944 BIT(NL80211_IFTYPE_OCB);
945
946 if (ath9k_is_chanctx_enabled())
947 hw->wiphy->interface_modes |=
948 BIT(NL80211_IFTYPE_P2P_DEVICE);
949
950 hw->wiphy->iface_combinations = if_comb;
951 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
952 }
953
954 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
955
956 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
957 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
958 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
959 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
960 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
961 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
962
963 hw->queues = 4;
964 hw->max_rates = 4;
965 hw->max_listen_interval = 10;
966 hw->max_rate_tries = 10;
967 hw->sta_data_size = sizeof(struct ath_node);
968 hw->vif_data_size = sizeof(struct ath_vif);
969 hw->txq_data_size = sizeof(struct ath_atx_tid);
970 hw->extra_tx_headroom = 4;
971
972 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
973 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
974
975 /* single chain devices with rx diversity */
976 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
977 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
978
979 sc->ant_rx = hw->wiphy->available_antennas_rx;
980 sc->ant_tx = hw->wiphy->available_antennas_tx;
981
982 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
983 hw->wiphy->bands[NL80211_BAND_2GHZ] =
984 &common->sbands[NL80211_BAND_2GHZ];
985 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
986 hw->wiphy->bands[NL80211_BAND_5GHZ] =
987 &common->sbands[NL80211_BAND_5GHZ];
988
989#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
990 ath9k_set_mcc_capab(sc, hw);
991#endif
992 ath9k_init_wow(hw);
993 ath9k_cmn_reload_chainmask(ah);
994
995 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
996
997 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
998 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);
999 wiphy_ext_feature_set(hw->wiphy,
1000 NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS);
1001 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1002}
1003
1004int ath9k_init_device(u16 devid, struct ath_softc *sc,
1005 const struct ath_bus_ops *bus_ops)
1006{
1007 struct ieee80211_hw *hw = sc->hw;
1008 struct ath_common *common;
1009 struct ath_hw *ah;
1010 int error = 0;
1011 struct ath_regulatory *reg;
1012
1013 /* Bring up device */
1014 error = ath9k_init_softc(devid, sc, bus_ops);
1015 if (error)
1016 return error;
1017
1018 ah = sc->sc_ah;
1019 common = ath9k_hw_common(ah);
1020 ath9k_set_hw_capab(sc, hw);
1021
1022 /* Initialize regulatory */
1023 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1024 ath9k_reg_notifier);
1025 if (error)
1026 goto deinit;
1027
1028 reg = &common->regulatory;
1029
1030 /* Setup TX DMA */
1031 error = ath_tx_init(sc, ATH_TXBUF);
1032 if (error != 0)
1033 goto deinit;
1034
1035 /* Setup RX DMA */
1036 error = ath_rx_init(sc, ATH_RXBUF);
1037 if (error != 0)
1038 goto deinit;
1039
1040 ath9k_init_txpower_limits(sc);
1041
1042#ifdef CONFIG_MAC80211_LEDS
1043 /* must be initialized before ieee80211_register_hw */
1044 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1045 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1046 ARRAY_SIZE(ath9k_tpt_blink));
1047#endif
1048
1049 wiphy_read_of_freq_limits(hw->wiphy);
1050
1051 /* Register with mac80211 */
1052 error = ieee80211_register_hw(hw);
1053 if (error)
1054 goto rx_cleanup;
1055
1056 error = ath9k_init_debug(ah);
1057 if (error) {
1058 ath_err(common, "Unable to create debugfs files\n");
1059 goto unregister;
1060 }
1061
1062 /* Handle world regulatory */
1063 if (!ath_is_world_regd(reg)) {
1064 error = regulatory_hint(hw->wiphy, reg->alpha2);
1065 if (error)
1066 goto debug_cleanup;
1067 }
1068
1069 ath_init_leds(sc);
1070 ath_start_rfkill_poll(sc);
1071
1072 return 0;
1073
1074debug_cleanup:
1075 ath9k_deinit_debug(sc);
1076unregister:
1077 ieee80211_unregister_hw(hw);
1078rx_cleanup:
1079 ath_rx_cleanup(sc);
1080deinit:
1081 ath9k_deinit_softc(sc);
1082 return error;
1083}
1084
1085/*****************************/
1086/* De-Initialization */
1087/*****************************/
1088
1089static void ath9k_deinit_softc(struct ath_softc *sc)
1090{
1091 int i = 0;
1092
1093 ath9k_deinit_p2p(sc);
1094 ath9k_deinit_btcoex(sc);
1095
1096 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1097 if (ATH_TXQ_SETUP(sc, i))
1098 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1099
1100 del_timer_sync(&sc->sleep_timer);
1101 ath9k_hw_deinit(sc->sc_ah);
1102 if (sc->dfs_detector != NULL)
1103 sc->dfs_detector->exit(sc->dfs_detector);
1104
1105 ath9k_eeprom_release(sc);
1106}
1107
1108void ath9k_deinit_device(struct ath_softc *sc)
1109{
1110 struct ieee80211_hw *hw = sc->hw;
1111
1112 ath9k_ps_wakeup(sc);
1113
1114 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1115 ath_deinit_leds(sc);
1116
1117 ath9k_ps_restore(sc);
1118
1119 ath9k_deinit_debug(sc);
1120 ath9k_deinit_wow(hw);
1121 ieee80211_unregister_hw(hw);
1122 ath_rx_cleanup(sc);
1123 ath9k_deinit_softc(sc);
1124}
1125
1126/************************/
1127/* Module Hooks */
1128/************************/
1129
1130static int __init ath9k_init(void)
1131{
1132 int error;
1133
1134 error = ath_pci_init();
1135 if (error < 0) {
1136 pr_err("No PCI devices found, driver not installed\n");
1137 error = -ENODEV;
1138 goto err_out;
1139 }
1140
1141 error = ath_ahb_init();
1142 if (error < 0) {
1143 error = -ENODEV;
1144 goto err_pci_exit;
1145 }
1146
1147 dmi_check_system(ath9k_quirks);
1148
1149 return 0;
1150
1151 err_pci_exit:
1152 ath_pci_exit();
1153 err_out:
1154 return error;
1155}
1156module_init(ath9k_init);
1157
1158static void __exit ath9k_exit(void)
1159{
1160 is_ath9k_unloaded = true;
1161 ath_ahb_exit();
1162 ath_pci_exit();
1163 pr_info("%s: Driver unloaded\n", dev_info);
1164}
1165module_exit(ath9k_exit);
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/ath9k_platform.h>
22#include <linux/module.h>
23#include <linux/relay.h>
24#include <net/ieee80211_radiotap.h>
25
26#include "ath9k.h"
27
28struct ath9k_eeprom_ctx {
29 struct completion complete;
30 struct ath_hw *ah;
31};
32
33static char *dev_info = "ath9k";
34
35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
40static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41module_param_named(debug, ath9k_debug, uint, 0);
42MODULE_PARM_DESC(debug, "Debugging mask");
43
44int ath9k_modparam_nohwcrypt;
45module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
47
48int ath9k_led_blink;
49module_param_named(blink, ath9k_led_blink, int, 0444);
50MODULE_PARM_DESC(blink, "Enable LED blink on activity");
51
52static int ath9k_btcoex_enable;
53module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
54MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
55
56static int ath9k_bt_ant_diversity;
57module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
58MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
59
60static int ath9k_ps_enable;
61module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
62MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
63
64#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
65
66int ath9k_use_chanctx;
67module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
68MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
69
70#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
71
72bool is_ath9k_unloaded;
73
74#ifdef CONFIG_MAC80211_LEDS
75static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
76 { .throughput = 0 * 1024, .blink_time = 334 },
77 { .throughput = 1 * 1024, .blink_time = 260 },
78 { .throughput = 5 * 1024, .blink_time = 220 },
79 { .throughput = 10 * 1024, .blink_time = 190 },
80 { .throughput = 20 * 1024, .blink_time = 170 },
81 { .throughput = 50 * 1024, .blink_time = 150 },
82 { .throughput = 70 * 1024, .blink_time = 130 },
83 { .throughput = 100 * 1024, .blink_time = 110 },
84 { .throughput = 200 * 1024, .blink_time = 80 },
85 { .throughput = 300 * 1024, .blink_time = 50 },
86};
87#endif
88
89static void ath9k_deinit_softc(struct ath_softc *sc);
90
91static void ath9k_op_ps_wakeup(struct ath_common *common)
92{
93 ath9k_ps_wakeup((struct ath_softc *) common->priv);
94}
95
96static void ath9k_op_ps_restore(struct ath_common *common)
97{
98 ath9k_ps_restore((struct ath_softc *) common->priv);
99}
100
101static struct ath_ps_ops ath9k_ps_ops = {
102 .wakeup = ath9k_op_ps_wakeup,
103 .restore = ath9k_op_ps_restore,
104};
105
106/*
107 * Read and write, they both share the same lock. We do this to serialize
108 * reads and writes on Atheros 802.11n PCI devices only. This is required
109 * as the FIFO on these devices can only accept sanely 2 requests.
110 */
111
112static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
113{
114 struct ath_hw *ah = (struct ath_hw *) hw_priv;
115 struct ath_common *common = ath9k_hw_common(ah);
116 struct ath_softc *sc = (struct ath_softc *) common->priv;
117
118 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
119 unsigned long flags;
120 spin_lock_irqsave(&sc->sc_serial_rw, flags);
121 iowrite32(val, sc->mem + reg_offset);
122 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
123 } else
124 iowrite32(val, sc->mem + reg_offset);
125}
126
127static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
128{
129 struct ath_hw *ah = (struct ath_hw *) hw_priv;
130 struct ath_common *common = ath9k_hw_common(ah);
131 struct ath_softc *sc = (struct ath_softc *) common->priv;
132 u32 val;
133
134 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
135 unsigned long flags;
136 spin_lock_irqsave(&sc->sc_serial_rw, flags);
137 val = ioread32(sc->mem + reg_offset);
138 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
139 } else
140 val = ioread32(sc->mem + reg_offset);
141 return val;
142}
143
144static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
145 u32 *val, u16 count)
146{
147 int i;
148
149 for (i = 0; i < count; i++)
150 val[i] = ath9k_ioread32(hw_priv, addr[i]);
151}
152
153
154static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
155 u32 set, u32 clr)
156{
157 u32 val;
158
159 val = ioread32(sc->mem + reg_offset);
160 val &= ~clr;
161 val |= set;
162 iowrite32(val, sc->mem + reg_offset);
163
164 return val;
165}
166
167static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
168{
169 struct ath_hw *ah = (struct ath_hw *) hw_priv;
170 struct ath_common *common = ath9k_hw_common(ah);
171 struct ath_softc *sc = (struct ath_softc *) common->priv;
172 unsigned long uninitialized_var(flags);
173 u32 val;
174
175 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
176 spin_lock_irqsave(&sc->sc_serial_rw, flags);
177 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
178 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
179 } else
180 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
181
182 return val;
183}
184
185/**************************/
186/* Initialization */
187/**************************/
188
189static void ath9k_reg_notifier(struct wiphy *wiphy,
190 struct regulatory_request *request)
191{
192 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
193 struct ath_softc *sc = hw->priv;
194 struct ath_hw *ah = sc->sc_ah;
195 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
196
197 ath_reg_notifier_apply(wiphy, request, reg);
198
199 /* Set tx power */
200 if (!ah->curchan)
201 return;
202
203 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
204 ath9k_ps_wakeup(sc);
205 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
206 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
207 sc->cur_chan->txpower,
208 &sc->cur_chan->cur_txpower);
209 /* synchronize DFS detector if regulatory domain changed */
210 if (sc->dfs_detector != NULL)
211 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
212 request->dfs_region);
213 ath9k_ps_restore(sc);
214}
215
216/*
217 * This function will allocate both the DMA descriptor structure, and the
218 * buffers it contains. These are used to contain the descriptors used
219 * by the system.
220*/
221int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
222 struct list_head *head, const char *name,
223 int nbuf, int ndesc, bool is_tx)
224{
225 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
226 u8 *ds;
227 int i, bsize, desc_len;
228
229 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
230 name, nbuf, ndesc);
231
232 INIT_LIST_HEAD(head);
233
234 if (is_tx)
235 desc_len = sc->sc_ah->caps.tx_desc_len;
236 else
237 desc_len = sizeof(struct ath_desc);
238
239 /* ath_desc must be a multiple of DWORDs */
240 if ((desc_len % 4) != 0) {
241 ath_err(common, "ath_desc not DWORD aligned\n");
242 BUG_ON((desc_len % 4) != 0);
243 return -ENOMEM;
244 }
245
246 dd->dd_desc_len = desc_len * nbuf * ndesc;
247
248 /*
249 * Need additional DMA memory because we can't use
250 * descriptors that cross the 4K page boundary. Assume
251 * one skipped descriptor per 4K page.
252 */
253 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
254 u32 ndesc_skipped =
255 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
256 u32 dma_len;
257
258 while (ndesc_skipped) {
259 dma_len = ndesc_skipped * desc_len;
260 dd->dd_desc_len += dma_len;
261
262 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
263 }
264 }
265
266 /* allocate descriptors */
267 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
268 &dd->dd_desc_paddr, GFP_KERNEL);
269 if (!dd->dd_desc)
270 return -ENOMEM;
271
272 ds = (u8 *) dd->dd_desc;
273 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
274 name, ds, (u32) dd->dd_desc_len,
275 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
276
277 /* allocate buffers */
278 if (is_tx) {
279 struct ath_buf *bf;
280
281 bsize = sizeof(struct ath_buf) * nbuf;
282 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
283 if (!bf)
284 return -ENOMEM;
285
286 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
287 bf->bf_desc = ds;
288 bf->bf_daddr = DS2PHYS(dd, ds);
289
290 if (!(sc->sc_ah->caps.hw_caps &
291 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
292 /*
293 * Skip descriptor addresses which can cause 4KB
294 * boundary crossing (addr + length) with a 32 dword
295 * descriptor fetch.
296 */
297 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
298 BUG_ON((caddr_t) bf->bf_desc >=
299 ((caddr_t) dd->dd_desc +
300 dd->dd_desc_len));
301
302 ds += (desc_len * ndesc);
303 bf->bf_desc = ds;
304 bf->bf_daddr = DS2PHYS(dd, ds);
305 }
306 }
307 list_add_tail(&bf->list, head);
308 }
309 } else {
310 struct ath_rxbuf *bf;
311
312 bsize = sizeof(struct ath_rxbuf) * nbuf;
313 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
314 if (!bf)
315 return -ENOMEM;
316
317 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
318 bf->bf_desc = ds;
319 bf->bf_daddr = DS2PHYS(dd, ds);
320
321 if (!(sc->sc_ah->caps.hw_caps &
322 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
323 /*
324 * Skip descriptor addresses which can cause 4KB
325 * boundary crossing (addr + length) with a 32 dword
326 * descriptor fetch.
327 */
328 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
329 BUG_ON((caddr_t) bf->bf_desc >=
330 ((caddr_t) dd->dd_desc +
331 dd->dd_desc_len));
332
333 ds += (desc_len * ndesc);
334 bf->bf_desc = ds;
335 bf->bf_daddr = DS2PHYS(dd, ds);
336 }
337 }
338 list_add_tail(&bf->list, head);
339 }
340 }
341 return 0;
342}
343
344static int ath9k_init_queues(struct ath_softc *sc)
345{
346 int i = 0;
347
348 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
349 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
350 ath_cabq_update(sc);
351
352 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
353
354 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
355 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
356 sc->tx.txq_map[i]->mac80211_qnum = i;
357 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
358 }
359 return 0;
360}
361
362static void ath9k_init_misc(struct ath_softc *sc)
363{
364 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
365 int i = 0;
366
367 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
368
369 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
370 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
371 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
372
373 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
374 sc->beacon.bslot[i] = NULL;
375
376 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
377 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
378
379 sc->spec_priv.ah = sc->sc_ah;
380 sc->spec_priv.spec_config.enabled = 0;
381 sc->spec_priv.spec_config.short_repeat = true;
382 sc->spec_priv.spec_config.count = 8;
383 sc->spec_priv.spec_config.endless = false;
384 sc->spec_priv.spec_config.period = 0xFF;
385 sc->spec_priv.spec_config.fft_period = 0xF;
386}
387
388static void ath9k_init_pcoem_platform(struct ath_softc *sc)
389{
390 struct ath_hw *ah = sc->sc_ah;
391 struct ath9k_hw_capabilities *pCap = &ah->caps;
392 struct ath_common *common = ath9k_hw_common(ah);
393
394 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
395 return;
396
397 if (common->bus_ops->ath_bus_type != ATH_PCI)
398 return;
399
400 if (sc->driver_data & (ATH9K_PCI_CUS198 |
401 ATH9K_PCI_CUS230)) {
402 ah->config.xlna_gpio = 9;
403 ah->config.xatten_margin_cfg = true;
404 ah->config.alt_mingainidx = true;
405 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
406 sc->ant_comb.low_rssi_thresh = 20;
407 sc->ant_comb.fast_div_bias = 3;
408
409 ath_info(common, "Set parameters for %s\n",
410 (sc->driver_data & ATH9K_PCI_CUS198) ?
411 "CUS198" : "CUS230");
412 }
413
414 if (sc->driver_data & ATH9K_PCI_CUS217)
415 ath_info(common, "CUS217 card detected\n");
416
417 if (sc->driver_data & ATH9K_PCI_CUS252)
418 ath_info(common, "CUS252 card detected\n");
419
420 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
421 ath_info(common, "WB335 1-ANT card detected\n");
422
423 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
424 ath_info(common, "WB335 2-ANT card detected\n");
425
426 if (sc->driver_data & ATH9K_PCI_KILLER)
427 ath_info(common, "Killer Wireless card detected\n");
428
429 /*
430 * Some WB335 cards do not support antenna diversity. Since
431 * we use a hardcoded value for AR9565 instead of using the
432 * EEPROM/OTP data, remove the combining feature from
433 * the HW capabilities bitmap.
434 */
435 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
436 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
437 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
438 }
439
440 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
441 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
442 ath_info(common, "Set BT/WLAN RX diversity capability\n");
443 }
444
445 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
446 ah->config.pcie_waen = 0x0040473b;
447 ath_info(common, "Enable WAR for ASPM D3/L1\n");
448 }
449
450 /*
451 * The default value of pll_pwrsave is 1.
452 * For certain AR9485 cards, it is set to 0.
453 * For AR9462, AR9565 it's set to 7.
454 */
455 ah->config.pll_pwrsave = 1;
456
457 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
458 ah->config.pll_pwrsave = 0;
459 ath_info(common, "Disable PLL PowerSave\n");
460 }
461
462 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
463 ah->config.led_active_high = true;
464}
465
466static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
467 void *ctx)
468{
469 struct ath9k_eeprom_ctx *ec = ctx;
470
471 if (eeprom_blob)
472 ec->ah->eeprom_blob = eeprom_blob;
473
474 complete(&ec->complete);
475}
476
477static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
478{
479 struct ath9k_eeprom_ctx ec;
480 struct ath_hw *ah = ah = sc->sc_ah;
481 int err;
482
483 /* try to load the EEPROM content asynchronously */
484 init_completion(&ec.complete);
485 ec.ah = sc->sc_ah;
486
487 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
488 &ec, ath9k_eeprom_request_cb);
489 if (err < 0) {
490 ath_err(ath9k_hw_common(ah),
491 "EEPROM request failed\n");
492 return err;
493 }
494
495 wait_for_completion(&ec.complete);
496
497 if (!ah->eeprom_blob) {
498 ath_err(ath9k_hw_common(ah),
499 "Unable to load EEPROM file %s\n", name);
500 return -EINVAL;
501 }
502
503 return 0;
504}
505
506static void ath9k_eeprom_release(struct ath_softc *sc)
507{
508 release_firmware(sc->sc_ah->eeprom_blob);
509}
510
511static int ath9k_init_soc_platform(struct ath_softc *sc)
512{
513 struct ath9k_platform_data *pdata = sc->dev->platform_data;
514 struct ath_hw *ah = sc->sc_ah;
515 int ret = 0;
516
517 if (!pdata)
518 return 0;
519
520 if (pdata->eeprom_name) {
521 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
522 if (ret)
523 return ret;
524 }
525
526 if (pdata->tx_gain_buffalo)
527 ah->config.tx_gain_buffalo = true;
528
529 return ret;
530}
531
532static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
533 const struct ath_bus_ops *bus_ops)
534{
535 struct ath9k_platform_data *pdata = sc->dev->platform_data;
536 struct ath_hw *ah = NULL;
537 struct ath9k_hw_capabilities *pCap;
538 struct ath_common *common;
539 int ret = 0, i;
540 int csz = 0;
541
542 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
543 if (!ah)
544 return -ENOMEM;
545
546 ah->dev = sc->dev;
547 ah->hw = sc->hw;
548 ah->hw_version.devid = devid;
549 ah->reg_ops.read = ath9k_ioread32;
550 ah->reg_ops.multi_read = ath9k_multi_ioread32;
551 ah->reg_ops.write = ath9k_iowrite32;
552 ah->reg_ops.rmw = ath9k_reg_rmw;
553 pCap = &ah->caps;
554
555 common = ath9k_hw_common(ah);
556
557 /* Will be cleared in ath9k_start() */
558 set_bit(ATH_OP_INVALID, &common->op_flags);
559
560 sc->sc_ah = ah;
561 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
562 sc->tx99_power = MAX_RATE_POWER + 1;
563 init_waitqueue_head(&sc->tx_wait);
564 sc->cur_chan = &sc->chanctx[0];
565 if (!ath9k_is_chanctx_enabled())
566 sc->cur_chan->hw_queue_base = 0;
567
568 if (!pdata || pdata->use_eeprom) {
569 ah->ah_flags |= AH_USE_EEPROM;
570 sc->sc_ah->led_pin = -1;
571 } else {
572 sc->sc_ah->gpio_mask = pdata->gpio_mask;
573 sc->sc_ah->gpio_val = pdata->gpio_val;
574 sc->sc_ah->led_pin = pdata->led_pin;
575 ah->is_clk_25mhz = pdata->is_clk_25mhz;
576 ah->get_mac_revision = pdata->get_mac_revision;
577 ah->external_reset = pdata->external_reset;
578 ah->disable_2ghz = pdata->disable_2ghz;
579 ah->disable_5ghz = pdata->disable_5ghz;
580 if (!pdata->endian_check)
581 ah->ah_flags |= AH_NO_EEP_SWAP;
582 }
583
584 common->ops = &ah->reg_ops;
585 common->bus_ops = bus_ops;
586 common->ps_ops = &ath9k_ps_ops;
587 common->ah = ah;
588 common->hw = sc->hw;
589 common->priv = sc;
590 common->debug_mask = ath9k_debug;
591 common->btcoex_enabled = ath9k_btcoex_enable == 1;
592 common->disable_ani = false;
593
594 /*
595 * Platform quirks.
596 */
597 ath9k_init_pcoem_platform(sc);
598
599 ret = ath9k_init_soc_platform(sc);
600 if (ret)
601 return ret;
602
603 /*
604 * Enable WLAN/BT RX Antenna diversity only when:
605 *
606 * - BTCOEX is disabled.
607 * - the user manually requests the feature.
608 * - the HW cap is set using the platform data.
609 */
610 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
611 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
612 common->bt_ant_diversity = 1;
613
614 spin_lock_init(&common->cc_lock);
615 spin_lock_init(&sc->sc_serial_rw);
616 spin_lock_init(&sc->sc_pm_lock);
617 spin_lock_init(&sc->chan_lock);
618 mutex_init(&sc->mutex);
619 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
620 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
621 (unsigned long)sc);
622
623 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
624 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
625 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
626 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
627
628 ath9k_init_channel_context(sc);
629
630 /*
631 * Cache line size is used to size and align various
632 * structures used to communicate with the hardware.
633 */
634 ath_read_cachesize(common, &csz);
635 common->cachelsz = csz << 2; /* convert to bytes */
636
637 /* Initializes the hardware for all supported chipsets */
638 ret = ath9k_hw_init(ah);
639 if (ret)
640 goto err_hw;
641
642 if (pdata && pdata->macaddr)
643 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
644
645 ret = ath9k_init_queues(sc);
646 if (ret)
647 goto err_queues;
648
649 ret = ath9k_init_btcoex(sc);
650 if (ret)
651 goto err_btcoex;
652
653 ret = ath9k_cmn_init_channels_rates(common);
654 if (ret)
655 goto err_btcoex;
656
657 ret = ath9k_init_p2p(sc);
658 if (ret)
659 goto err_btcoex;
660
661 ath9k_cmn_init_crypto(sc->sc_ah);
662 ath9k_init_misc(sc);
663 ath_fill_led_pin(sc);
664 ath_chanctx_init(sc);
665 ath9k_offchannel_init(sc);
666
667 if (common->bus_ops->aspm_init)
668 common->bus_ops->aspm_init(common);
669
670 return 0;
671
672err_btcoex:
673 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
674 if (ATH_TXQ_SETUP(sc, i))
675 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
676err_queues:
677 ath9k_hw_deinit(ah);
678err_hw:
679 ath9k_eeprom_release(sc);
680 dev_kfree_skb_any(sc->tx99_skb);
681 return ret;
682}
683
684static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
685{
686 struct ieee80211_supported_band *sband;
687 struct ieee80211_channel *chan;
688 struct ath_hw *ah = sc->sc_ah;
689 struct ath_common *common = ath9k_hw_common(ah);
690 struct cfg80211_chan_def chandef;
691 int i;
692
693 sband = &common->sbands[band];
694 for (i = 0; i < sband->n_channels; i++) {
695 chan = &sband->channels[i];
696 ah->curchan = &ah->channels[chan->hw_value];
697 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
698 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
699 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
700 }
701}
702
703static void ath9k_init_txpower_limits(struct ath_softc *sc)
704{
705 struct ath_hw *ah = sc->sc_ah;
706 struct ath9k_channel *curchan = ah->curchan;
707
708 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
709 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
710 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
711 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
712
713 ah->curchan = curchan;
714}
715
716static const struct ieee80211_iface_limit if_limits[] = {
717 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
718 { .max = 8, .types =
719#ifdef CONFIG_MAC80211_MESH
720 BIT(NL80211_IFTYPE_MESH_POINT) |
721#endif
722 BIT(NL80211_IFTYPE_AP) },
723 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
724 BIT(NL80211_IFTYPE_P2P_GO) },
725};
726
727static const struct ieee80211_iface_limit wds_limits[] = {
728 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) },
729};
730
731#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
732
733static const struct ieee80211_iface_limit if_limits_multi[] = {
734 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
735 BIT(NL80211_IFTYPE_AP) |
736 BIT(NL80211_IFTYPE_P2P_CLIENT) |
737 BIT(NL80211_IFTYPE_P2P_GO) },
738 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
739 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
740};
741
742static const struct ieee80211_iface_combination if_comb_multi[] = {
743 {
744 .limits = if_limits_multi,
745 .n_limits = ARRAY_SIZE(if_limits_multi),
746 .max_interfaces = 3,
747 .num_different_channels = 2,
748 .beacon_int_infra_match = true,
749 },
750};
751
752#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
753
754static const struct ieee80211_iface_combination if_comb[] = {
755 {
756 .limits = if_limits,
757 .n_limits = ARRAY_SIZE(if_limits),
758 .max_interfaces = 2048,
759 .num_different_channels = 1,
760 .beacon_int_infra_match = true,
761#ifdef CONFIG_ATH9K_DFS_CERTIFIED
762 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
763 BIT(NL80211_CHAN_WIDTH_20) |
764 BIT(NL80211_CHAN_WIDTH_40),
765#endif
766 },
767 {
768 .limits = wds_limits,
769 .n_limits = ARRAY_SIZE(wds_limits),
770 .max_interfaces = 2048,
771 .num_different_channels = 1,
772 .beacon_int_infra_match = true,
773 },
774};
775
776#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
777static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
778{
779 struct ath_hw *ah = sc->sc_ah;
780 struct ath_common *common = ath9k_hw_common(ah);
781
782 if (!ath9k_is_chanctx_enabled())
783 return;
784
785 ieee80211_hw_set(hw, QUEUE_CONTROL);
786 hw->queues = ATH9K_NUM_TX_QUEUES;
787 hw->offchannel_tx_hw_queue = hw->queues - 1;
788 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
789 hw->wiphy->iface_combinations = if_comb_multi;
790 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
791 hw->wiphy->max_scan_ssids = 255;
792 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
793 hw->wiphy->max_remain_on_channel_duration = 10000;
794 hw->chanctx_data_size = sizeof(void *);
795 hw->extra_beacon_tailroom =
796 sizeof(struct ieee80211_p2p_noa_attr) + 9;
797
798 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
799}
800#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
801
802static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
803{
804 struct ath_hw *ah = sc->sc_ah;
805 struct ath_common *common = ath9k_hw_common(ah);
806
807 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
808 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
809 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
810 ieee80211_hw_set(hw, SPECTRUM_MGMT);
811 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
812 ieee80211_hw_set(hw, SIGNAL_DBM);
813 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
814 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
815 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
816 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
817
818 if (ath9k_ps_enable)
819 ieee80211_hw_set(hw, SUPPORTS_PS);
820
821 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
822 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
823
824 if (AR_SREV_9280_20_OR_LATER(ah))
825 hw->radiotap_mcs_details |=
826 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
827 }
828
829 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
830 ieee80211_hw_set(hw, MFP_CAPABLE);
831
832 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
833 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
834 NL80211_FEATURE_P2P_GO_CTWIN;
835
836 if (!config_enabled(CONFIG_ATH9K_TX99)) {
837 hw->wiphy->interface_modes =
838 BIT(NL80211_IFTYPE_P2P_GO) |
839 BIT(NL80211_IFTYPE_P2P_CLIENT) |
840 BIT(NL80211_IFTYPE_AP) |
841 BIT(NL80211_IFTYPE_STATION) |
842 BIT(NL80211_IFTYPE_ADHOC) |
843 BIT(NL80211_IFTYPE_MESH_POINT) |
844 BIT(NL80211_IFTYPE_WDS) |
845 BIT(NL80211_IFTYPE_OCB);
846
847 if (ath9k_is_chanctx_enabled())
848 hw->wiphy->interface_modes |=
849 BIT(NL80211_IFTYPE_P2P_DEVICE);
850
851 hw->wiphy->iface_combinations = if_comb;
852 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
853 }
854
855 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
856
857 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
858 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
859 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
860 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
861 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
862 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
863
864 hw->queues = 4;
865 hw->max_rates = 4;
866 hw->max_listen_interval = 10;
867 hw->max_rate_tries = 10;
868 hw->sta_data_size = sizeof(struct ath_node);
869 hw->vif_data_size = sizeof(struct ath_vif);
870 hw->extra_tx_headroom = 4;
871
872 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
873 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
874
875 /* single chain devices with rx diversity */
876 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
877 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
878
879 sc->ant_rx = hw->wiphy->available_antennas_rx;
880 sc->ant_tx = hw->wiphy->available_antennas_tx;
881
882 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
883 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
884 &common->sbands[IEEE80211_BAND_2GHZ];
885 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
886 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
887 &common->sbands[IEEE80211_BAND_5GHZ];
888
889#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
890 ath9k_set_mcc_capab(sc, hw);
891#endif
892 ath9k_init_wow(hw);
893 ath9k_cmn_reload_chainmask(ah);
894
895 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
896}
897
898int ath9k_init_device(u16 devid, struct ath_softc *sc,
899 const struct ath_bus_ops *bus_ops)
900{
901 struct ieee80211_hw *hw = sc->hw;
902 struct ath_common *common;
903 struct ath_hw *ah;
904 int error = 0;
905 struct ath_regulatory *reg;
906
907 /* Bring up device */
908 error = ath9k_init_softc(devid, sc, bus_ops);
909 if (error)
910 return error;
911
912 ah = sc->sc_ah;
913 common = ath9k_hw_common(ah);
914 ath9k_set_hw_capab(sc, hw);
915
916 /* Initialize regulatory */
917 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
918 ath9k_reg_notifier);
919 if (error)
920 goto deinit;
921
922 reg = &common->regulatory;
923
924 /* Setup TX DMA */
925 error = ath_tx_init(sc, ATH_TXBUF);
926 if (error != 0)
927 goto deinit;
928
929 /* Setup RX DMA */
930 error = ath_rx_init(sc, ATH_RXBUF);
931 if (error != 0)
932 goto deinit;
933
934 ath9k_init_txpower_limits(sc);
935
936#ifdef CONFIG_MAC80211_LEDS
937 /* must be initialized before ieee80211_register_hw */
938 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
939 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
940 ARRAY_SIZE(ath9k_tpt_blink));
941#endif
942
943 /* Register with mac80211 */
944 error = ieee80211_register_hw(hw);
945 if (error)
946 goto rx_cleanup;
947
948 error = ath9k_init_debug(ah);
949 if (error) {
950 ath_err(common, "Unable to create debugfs files\n");
951 goto unregister;
952 }
953
954 /* Handle world regulatory */
955 if (!ath_is_world_regd(reg)) {
956 error = regulatory_hint(hw->wiphy, reg->alpha2);
957 if (error)
958 goto debug_cleanup;
959 }
960
961 ath_init_leds(sc);
962 ath_start_rfkill_poll(sc);
963
964 return 0;
965
966debug_cleanup:
967 ath9k_deinit_debug(sc);
968unregister:
969 ieee80211_unregister_hw(hw);
970rx_cleanup:
971 ath_rx_cleanup(sc);
972deinit:
973 ath9k_deinit_softc(sc);
974 return error;
975}
976
977/*****************************/
978/* De-Initialization */
979/*****************************/
980
981static void ath9k_deinit_softc(struct ath_softc *sc)
982{
983 int i = 0;
984
985 ath9k_deinit_p2p(sc);
986 ath9k_deinit_btcoex(sc);
987
988 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
989 if (ATH_TXQ_SETUP(sc, i))
990 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
991
992 del_timer_sync(&sc->sleep_timer);
993 ath9k_hw_deinit(sc->sc_ah);
994 if (sc->dfs_detector != NULL)
995 sc->dfs_detector->exit(sc->dfs_detector);
996
997 ath9k_eeprom_release(sc);
998}
999
1000void ath9k_deinit_device(struct ath_softc *sc)
1001{
1002 struct ieee80211_hw *hw = sc->hw;
1003
1004 ath9k_ps_wakeup(sc);
1005
1006 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1007 ath_deinit_leds(sc);
1008
1009 ath9k_ps_restore(sc);
1010
1011 ath9k_deinit_debug(sc);
1012 ath9k_deinit_wow(hw);
1013 ieee80211_unregister_hw(hw);
1014 ath_rx_cleanup(sc);
1015 ath9k_deinit_softc(sc);
1016}
1017
1018/************************/
1019/* Module Hooks */
1020/************************/
1021
1022static int __init ath9k_init(void)
1023{
1024 int error;
1025
1026 error = ath_pci_init();
1027 if (error < 0) {
1028 pr_err("No PCI devices found, driver not installed\n");
1029 error = -ENODEV;
1030 goto err_out;
1031 }
1032
1033 error = ath_ahb_init();
1034 if (error < 0) {
1035 error = -ENODEV;
1036 goto err_pci_exit;
1037 }
1038
1039 return 0;
1040
1041 err_pci_exit:
1042 ath_pci_exit();
1043 err_out:
1044 return error;
1045}
1046module_init(ath9k_init);
1047
1048static void __exit ath9k_exit(void)
1049{
1050 is_ath9k_unloaded = true;
1051 ath_ahb_exit();
1052 ath_pci_exit();
1053 pr_info("%s: Driver unloaded\n", dev_info);
1054}
1055module_exit(ath9k_exit);