1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Marvell Octeon EP (EndPoint) Ethernet Driver
  3 *
  4 * Copyright (C) 2020 Marvell.
  5 *
  6 */
  7 #ifndef __OCTEP_CTRL_MBOX_H__
  8#define __OCTEP_CTRL_MBOX_H__
  9
 10/*              barmem structure
 11 * |===========================================|
 12 * |Info (16 + 120 + 120 = 256 bytes)          |
 13 * |-------------------------------------------|
 14 * |magic number (8 bytes)                     |
 15 * |bar memory size (4 bytes)                  |
 16 * |reserved (4 bytes)                         |
 17 * |-------------------------------------------|
 18 * |host version (8 bytes)                     |
 19 * |    low 32 bits                            |
 20 * |host status (8 bytes)                      |
 21 * |host reserved (104 bytes)                  |
 22 * |-------------------------------------------|
 23 * |fw version's (8 bytes)                     |
 24 * |    min=high 32 bits, max=low 32 bits      |
 25 * |fw status (8 bytes)                        |
 26 * |fw reserved (104 bytes)                    |
 27 * |===========================================|
 28 * |Host to Fw Queue info (16 bytes)           |
 29 * |-------------------------------------------|
 30 * |producer index (4 bytes)                   |
 31 * |consumer index (4 bytes)                   |
 32 * |max element size (4 bytes)                 |
 33 * |reserved (4 bytes)                         |
 34 * |===========================================|
 35 * |Fw to Host Queue info (16 bytes)           |
 36 * |-------------------------------------------|
 37 * |producer index (4 bytes)                   |
 38 * |consumer index (4 bytes)                   |
 39 * |max element size (4 bytes)                 |
 40 * |reserved (4 bytes)                         |
 41 * |===========================================|
 42 * |Host to Fw Queue ((total size-288/2) bytes)|
 43 * |-------------------------------------------|
 44 * |                                           |
 45 * |===========================================|
 46 * |===========================================|
 47 * |Fw to Host Queue ((total size-288/2) bytes)|
 48 * |-------------------------------------------|
 49 * |                                           |
 50 * |===========================================|
 51 */
 52
 53#define OCTEP_CTRL_MBOX_MAGIC_NUMBER			0xdeaddeadbeefbeefull
 54
 55/* Valid request message */
 56#define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_REQ		BIT(0)
 57/* Valid response message */
 58#define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_RESP		BIT(1)
 59/* Valid notification, no response required */
 60#define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_NOTIFY		BIT(2)
 61/* Valid custom message */
 62#define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_CUSTOM		BIT(3)
 63
 64#define OCTEP_CTRL_MBOX_MSG_DESC_MAX			4
 65
 66enum octep_ctrl_mbox_status {
 67	OCTEP_CTRL_MBOX_STATUS_INVALID = 0,
 68	OCTEP_CTRL_MBOX_STATUS_INIT,
 69	OCTEP_CTRL_MBOX_STATUS_READY,
 70	OCTEP_CTRL_MBOX_STATUS_UNINIT
 71};
 72
 73/* mbox message */
 74union octep_ctrl_mbox_msg_hdr {
 75	u64 words[2];
 76	struct {
 77		/* must be 0 */
 78		u16 reserved1:15;
 79		/* vf_idx is valid if 1 */
 80		u16 is_vf:1;
 81		/* sender vf index 0-(n-1), 0 if (is_vf==0) */
 82		u16 vf_idx;
 83		/* total size of message excluding header */
 84		u32 sz;
 85		/* OCTEP_CTRL_MBOX_MSG_HDR_FLAG_* */
 86		u32 flags;
 87		/* identifier to match responses */
 88		u16 msg_id;
 89		u16 reserved2;
 90	} s;
 91};
 92
 93/* mbox message buffer */
 94struct octep_ctrl_mbox_msg_buf {
 95	u32 reserved1;
 96	u16 reserved2;
 97	/* size of buffer */
 98	u16 sz;
 99	/* pointer to message buffer */
100	void *msg;
101};
102
103/* mbox message */
104struct octep_ctrl_mbox_msg {
105	/* mbox transaction header */
106	union octep_ctrl_mbox_msg_hdr hdr;
107	/* number of sg buffer's */
108	int sg_num;
109	/* message buffer's */
110	struct octep_ctrl_mbox_msg_buf sg_list[OCTEP_CTRL_MBOX_MSG_DESC_MAX];
111};
112
113/* Mbox queue */
114struct octep_ctrl_mbox_q {
115	/* size of queue buffer */
116	u32 sz;
117	/* producer address in bar mem */
118	u8 __iomem *hw_prod;
119	/* consumer address in bar mem */
120	u8 __iomem *hw_cons;
121	/* q base address in bar mem */
122	u8 __iomem *hw_q;
123};
124
125struct octep_ctrl_mbox {
126	/* control plane version */
127	u64 version;
128	/* size of bar memory */
129	u32 barmem_sz;
130	/* pointer to BAR memory */
131	u8 __iomem *barmem;
132	/* host-to-fw queue */
133	struct octep_ctrl_mbox_q h2fq;
134	/* fw-to-host queue */
135	struct octep_ctrl_mbox_q f2hq;
136	/* lock for h2fq */
137	struct mutex h2fq_lock;
138	/* lock for f2hq */
139	struct mutex f2hq_lock;
140	/* Min control plane version supported by firmware */
141	u32 min_fw_version;
142	/* Max control plane version supported by firmware */
143	u32 max_fw_version;
144};
145
146/* Initialize control mbox.
147 *
148 * @param mbox: non-null pointer to struct octep_ctrl_mbox.
149 *
150 * return value: 0 on success, -errno on failure.
151 */
152int octep_ctrl_mbox_init(struct octep_ctrl_mbox *mbox);
153
154/* Send mbox message.
155 *
156 * @param mbox: non-null pointer to struct octep_ctrl_mbox.
157 * @param msg:  non-null pointer to struct octep_ctrl_mbox_msg.
158 *              Caller should fill msg.sz and msg.desc.sz for each message.
159 *
160 * return value: 0 on success, -errno on failure.
161 */
162int octep_ctrl_mbox_send(struct octep_ctrl_mbox *mbox, struct octep_ctrl_mbox_msg *msg);
163
164/* Retrieve mbox message.
165 *
166 * @param mbox: non-null pointer to struct octep_ctrl_mbox.
167 * @param msg:  non-null pointer to struct octep_ctrl_mbox_msg.
168 *              Caller should fill msg.sz and msg.desc.sz for each message.
169 *
170 * return value: 0 on success, -errno on failure.
171 */
172int octep_ctrl_mbox_recv(struct octep_ctrl_mbox *mbox, struct octep_ctrl_mbox_msg *msg);
173
174/* Uninitialize control mbox.
175 *
176 * @param mbox: non-null pointer to struct octep_ctrl_mbox.
177 *
178 * return value: 0 on success, -errno on failure.
179 */
180int octep_ctrl_mbox_uninit(struct octep_ctrl_mbox *mbox);
181
182#endif /* __OCTEP_CTRL_MBOX_H__ */