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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#ifndef _IXGBEVF_H_
5#define _IXGBEVF_H_
6
7#include <linux/types.h>
8#include <linux/bitops.h>
9#include <linux/timer.h>
10#include <linux/io.h>
11#include <linux/netdevice.h>
12#include <linux/if_vlan.h>
13#include <linux/u64_stats_sync.h>
14#include <net/xdp.h>
15
16#include "vf.h"
17#include "ipsec.h"
18
19#define IXGBE_MAX_TXD_PWR 14
20#define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR)
21
22/* Tx Descriptors needed, worst case */
23#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
24#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
25
26/* wrapper around a pointer to a socket buffer,
27 * so a DMA handle can be stored along with the buffer
28 */
29struct ixgbevf_tx_buffer {
30 union ixgbe_adv_tx_desc *next_to_watch;
31 unsigned long time_stamp;
32 union {
33 struct sk_buff *skb;
34 /* XDP uses address ptr on irq_clean */
35 void *data;
36 };
37 unsigned int bytecount;
38 unsigned short gso_segs;
39 __be16 protocol;
40 DEFINE_DMA_UNMAP_ADDR(dma);
41 DEFINE_DMA_UNMAP_LEN(len);
42 u32 tx_flags;
43};
44
45struct ixgbevf_rx_buffer {
46 dma_addr_t dma;
47 struct page *page;
48#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
49 __u32 page_offset;
50#else
51 __u16 page_offset;
52#endif
53 __u16 pagecnt_bias;
54};
55
56struct ixgbevf_stats {
57 u64 packets;
58 u64 bytes;
59};
60
61struct ixgbevf_tx_queue_stats {
62 u64 restart_queue;
63 u64 tx_busy;
64 u64 tx_done_old;
65};
66
67struct ixgbevf_rx_queue_stats {
68 u64 alloc_rx_page_failed;
69 u64 alloc_rx_buff_failed;
70 u64 alloc_rx_page;
71 u64 csum_err;
72};
73
74enum ixgbevf_ring_state_t {
75 __IXGBEVF_RX_3K_BUFFER,
76 __IXGBEVF_RX_BUILD_SKB_ENABLED,
77 __IXGBEVF_TX_DETECT_HANG,
78 __IXGBEVF_HANG_CHECK_ARMED,
79 __IXGBEVF_TX_XDP_RING,
80 __IXGBEVF_TX_XDP_RING_PRIMED,
81};
82
83#define ring_is_xdp(ring) \
84 test_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
85#define set_ring_xdp(ring) \
86 set_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
87#define clear_ring_xdp(ring) \
88 clear_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
89
90struct ixgbevf_ring {
91 struct ixgbevf_ring *next;
92 struct ixgbevf_q_vector *q_vector; /* backpointer to q_vector */
93 struct net_device *netdev;
94 struct bpf_prog *xdp_prog;
95 struct device *dev;
96 void *desc; /* descriptor ring memory */
97 dma_addr_t dma; /* phys. address of descriptor ring */
98 unsigned int size; /* length in bytes */
99 u16 count; /* amount of descriptors */
100 u16 next_to_use;
101 u16 next_to_clean;
102 u16 next_to_alloc;
103
104 union {
105 struct ixgbevf_tx_buffer *tx_buffer_info;
106 struct ixgbevf_rx_buffer *rx_buffer_info;
107 };
108 unsigned long state;
109 struct ixgbevf_stats stats;
110 struct u64_stats_sync syncp;
111 union {
112 struct ixgbevf_tx_queue_stats tx_stats;
113 struct ixgbevf_rx_queue_stats rx_stats;
114 };
115 struct xdp_rxq_info xdp_rxq;
116 u64 hw_csum_rx_error;
117 u8 __iomem *tail;
118 struct sk_buff *skb;
119
120 /* holds the special value that gets the hardware register offset
121 * associated with this ring, which is different for DCB and RSS modes
122 */
123 u16 reg_idx;
124 int queue_index; /* needed for multiqueue queue management */
125} ____cacheline_internodealigned_in_smp;
126
127/* How many Rx Buffers do we bundle into one write to the hardware ? */
128#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
129
130#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
131#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
132#define MAX_XDP_QUEUES IXGBE_VF_MAX_TX_QUEUES
133#define IXGBEVF_MAX_RSS_QUEUES 2
134#define IXGBEVF_82599_RETA_SIZE 128 /* 128 entries */
135#define IXGBEVF_X550_VFRETA_SIZE 64 /* 64 entries */
136#define IXGBEVF_RSS_HASH_KEY_SIZE 40
137#define IXGBEVF_VFRSSRK_REGS 10 /* 10 registers for RSS key */
138
139#define IXGBEVF_DEFAULT_TXD 1024
140#define IXGBEVF_DEFAULT_RXD 512
141#define IXGBEVF_MAX_TXD 4096
142#define IXGBEVF_MIN_TXD 64
143#define IXGBEVF_MAX_RXD 4096
144#define IXGBEVF_MIN_RXD 64
145
146/* Supported Rx Buffer Sizes */
147#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
148#define IXGBEVF_RXBUFFER_2048 2048
149#define IXGBEVF_RXBUFFER_3072 3072
150
151#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
152
153#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
154
155#define IXGBEVF_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
156#if (PAGE_SIZE < 8192)
157#define IXGBEVF_MAX_FRAME_BUILD_SKB \
158 (SKB_WITH_OVERHEAD(IXGBEVF_RXBUFFER_2048) - IXGBEVF_SKB_PAD)
159#else
160#define IXGBEVF_MAX_FRAME_BUILD_SKB IXGBEVF_RXBUFFER_2048
161#endif
162
163#define IXGBE_TX_FLAGS_CSUM BIT(0)
164#define IXGBE_TX_FLAGS_VLAN BIT(1)
165#define IXGBE_TX_FLAGS_TSO BIT(2)
166#define IXGBE_TX_FLAGS_IPV4 BIT(3)
167#define IXGBE_TX_FLAGS_IPSEC BIT(4)
168#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
169#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
170#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
171
172#define ring_uses_large_buffer(ring) \
173 test_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
174#define set_ring_uses_large_buffer(ring) \
175 set_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
176#define clear_ring_uses_large_buffer(ring) \
177 clear_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
178
179#define ring_uses_build_skb(ring) \
180 test_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
181#define set_ring_build_skb_enabled(ring) \
182 set_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
183#define clear_ring_build_skb_enabled(ring) \
184 clear_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
185
186static inline unsigned int ixgbevf_rx_bufsz(struct ixgbevf_ring *ring)
187{
188#if (PAGE_SIZE < 8192)
189 if (ring_uses_large_buffer(ring))
190 return IXGBEVF_RXBUFFER_3072;
191
192 if (ring_uses_build_skb(ring))
193 return IXGBEVF_MAX_FRAME_BUILD_SKB;
194#endif
195 return IXGBEVF_RXBUFFER_2048;
196}
197
198static inline unsigned int ixgbevf_rx_pg_order(struct ixgbevf_ring *ring)
199{
200#if (PAGE_SIZE < 8192)
201 if (ring_uses_large_buffer(ring))
202 return 1;
203#endif
204 return 0;
205}
206
207#define ixgbevf_rx_pg_size(_ring) (PAGE_SIZE << ixgbevf_rx_pg_order(_ring))
208
209#define check_for_tx_hang(ring) \
210 test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
211#define set_check_for_tx_hang(ring) \
212 set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
213#define clear_check_for_tx_hang(ring) \
214 clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
215
216struct ixgbevf_ring_container {
217 struct ixgbevf_ring *ring; /* pointer to linked list of rings */
218 unsigned int total_bytes; /* total bytes processed this int */
219 unsigned int total_packets; /* total packets processed this int */
220 u8 count; /* total number of rings in vector */
221 u8 itr; /* current ITR setting for ring */
222};
223
224/* iterator for handling rings in ring container */
225#define ixgbevf_for_each_ring(pos, head) \
226 for (pos = (head).ring; pos != NULL; pos = pos->next)
227
228/* MAX_MSIX_Q_VECTORS of these are allocated,
229 * but we only use one per queue-specific vector.
230 */
231struct ixgbevf_q_vector {
232 struct ixgbevf_adapter *adapter;
233 /* index of q_vector within array, also used for finding the bit in
234 * EICR and friends that represents the vector for this ring
235 */
236 u16 v_idx;
237 u16 itr; /* Interrupt throttle rate written to EITR */
238 struct napi_struct napi;
239 struct ixgbevf_ring_container rx, tx;
240 struct rcu_head rcu; /* to avoid race with update stats on free */
241 char name[IFNAMSIZ + 9];
242
243 /* for dynamic allocation of rings associated with this q_vector */
244 struct ixgbevf_ring ring[0] ____cacheline_internodealigned_in_smp;
245#ifdef CONFIG_NET_RX_BUSY_POLL
246 unsigned int state;
247#define IXGBEVF_QV_STATE_IDLE 0
248#define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */
249#define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */
250#define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */
251#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
252#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
253#define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
254#define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
255#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \
256 IXGBEVF_QV_STATE_POLL_YIELD)
257#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \
258 IXGBEVF_QV_STATE_POLL_YIELD)
259 spinlock_t lock;
260#endif /* CONFIG_NET_RX_BUSY_POLL */
261};
262
263/* microsecond values for various ITR rates shifted by 2 to fit itr register
264 * with the first 3 bits reserved 0
265 */
266#define IXGBE_MIN_RSC_ITR 24
267#define IXGBE_100K_ITR 40
268#define IXGBE_20K_ITR 200
269#define IXGBE_12K_ITR 336
270
271/* Helper macros to switch between ints/sec and what the register uses.
272 * And yes, it's the same math going both ways. The lowest value
273 * supported by all of the ixgbe hardware is 8.
274 */
275#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
276 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
277#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
278
279/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
280static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
281 const u32 stat_err_bits)
282{
283 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
284}
285
286static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
287{
288 u16 ntc = ring->next_to_clean;
289 u16 ntu = ring->next_to_use;
290
291 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
292}
293
294static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
295{
296 writel(value, ring->tail);
297}
298
299#define IXGBEVF_RX_DESC(R, i) \
300 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
301#define IXGBEVF_TX_DESC(R, i) \
302 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
303#define IXGBEVF_TX_CTXTDESC(R, i) \
304 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
305
306#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
307
308#define OTHER_VECTOR 1
309#define NON_Q_VECTORS (OTHER_VECTOR)
310
311#define MAX_MSIX_Q_VECTORS 2
312
313#define MIN_MSIX_Q_VECTORS 1
314#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
315
316#define IXGBEVF_RX_DMA_ATTR \
317 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
318
319/* board specific private data structure */
320struct ixgbevf_adapter {
321 /* this field must be first, see ixgbevf_process_skb_fields */
322 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
323
324 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
325
326 /* Interrupt Throttle Rate */
327 u16 rx_itr_setting;
328 u16 tx_itr_setting;
329
330 /* interrupt masks */
331 u32 eims_enable_mask;
332 u32 eims_other;
333
334 /* XDP */
335 int num_xdp_queues;
336 struct ixgbevf_ring *xdp_ring[MAX_XDP_QUEUES];
337
338 /* TX */
339 int num_tx_queues;
340 struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */
341 u64 restart_queue;
342 u32 tx_timeout_count;
343 u64 tx_ipsec;
344
345 /* RX */
346 int num_rx_queues;
347 struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */
348 u64 hw_csum_rx_error;
349 u64 hw_rx_no_dma_resources;
350 int num_msix_vectors;
351 u64 alloc_rx_page_failed;
352 u64 alloc_rx_buff_failed;
353 u64 alloc_rx_page;
354 u64 rx_ipsec;
355
356 struct msix_entry *msix_entries;
357
358 /* OS defined structs */
359 struct net_device *netdev;
360 struct bpf_prog *xdp_prog;
361 struct pci_dev *pdev;
362
363 /* structs defined in ixgbe_vf.h */
364 struct ixgbe_hw hw;
365 u16 msg_enable;
366 /* Interrupt Throttle Rate */
367 u32 eitr_param;
368
369 struct ixgbevf_hw_stats stats;
370
371 unsigned long state;
372 u64 tx_busy;
373 unsigned int tx_ring_count;
374 unsigned int xdp_ring_count;
375 unsigned int rx_ring_count;
376
377 u8 __iomem *io_addr; /* Mainly for iounmap use */
378 u32 link_speed;
379 bool link_up;
380
381 struct timer_list service_timer;
382 struct work_struct service_task;
383
384 spinlock_t mbx_lock;
385 unsigned long last_reset;
386
387 u32 *rss_key;
388 u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
389 u32 flags;
390 bool link_state;
391
392#define IXGBEVF_FLAGS_LEGACY_RX BIT(1)
393
394#ifdef CONFIG_XFRM
395 struct ixgbevf_ipsec *ipsec;
396#endif /* CONFIG_XFRM */
397};
398
399enum ixbgevf_state_t {
400 __IXGBEVF_TESTING,
401 __IXGBEVF_RESETTING,
402 __IXGBEVF_DOWN,
403 __IXGBEVF_DISABLED,
404 __IXGBEVF_REMOVING,
405 __IXGBEVF_SERVICE_SCHED,
406 __IXGBEVF_SERVICE_INITED,
407 __IXGBEVF_RESET_REQUESTED,
408 __IXGBEVF_QUEUE_RESET_REQUESTED,
409};
410
411enum ixgbevf_boards {
412 board_82599_vf,
413 board_82599_vf_hv,
414 board_X540_vf,
415 board_X540_vf_hv,
416 board_X550_vf,
417 board_X550_vf_hv,
418 board_X550EM_x_vf,
419 board_X550EM_x_vf_hv,
420 board_x550em_a_vf,
421};
422
423enum ixgbevf_xcast_modes {
424 IXGBEVF_XCAST_MODE_NONE = 0,
425 IXGBEVF_XCAST_MODE_MULTI,
426 IXGBEVF_XCAST_MODE_ALLMULTI,
427 IXGBEVF_XCAST_MODE_PROMISC,
428};
429
430extern const struct ixgbevf_info ixgbevf_82599_vf_info;
431extern const struct ixgbevf_info ixgbevf_X540_vf_info;
432extern const struct ixgbevf_info ixgbevf_X550_vf_info;
433extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
434extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
435extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops_legacy;
436extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info;
437
438extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info;
439extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info;
440extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info;
441extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info;
442extern const struct ixgbe_mbx_operations ixgbevf_hv_mbx_ops;
443
444/* needed by ethtool.c */
445extern const char ixgbevf_driver_name[];
446
447int ixgbevf_open(struct net_device *netdev);
448int ixgbevf_close(struct net_device *netdev);
449void ixgbevf_up(struct ixgbevf_adapter *adapter);
450void ixgbevf_down(struct ixgbevf_adapter *adapter);
451void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
452void ixgbevf_reset(struct ixgbevf_adapter *adapter);
453void ixgbevf_set_ethtool_ops(struct net_device *netdev);
454int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
455 struct ixgbevf_ring *rx_ring);
456int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
457void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
458void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
459void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
460int ethtool_ioctl(struct ifreq *ifr);
461
462extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
463
464#ifdef CONFIG_IXGBEVF_IPSEC
465void ixgbevf_init_ipsec_offload(struct ixgbevf_adapter *adapter);
466void ixgbevf_stop_ipsec_offload(struct ixgbevf_adapter *adapter);
467void ixgbevf_ipsec_restore(struct ixgbevf_adapter *adapter);
468void ixgbevf_ipsec_rx(struct ixgbevf_ring *rx_ring,
469 union ixgbe_adv_rx_desc *rx_desc,
470 struct sk_buff *skb);
471int ixgbevf_ipsec_tx(struct ixgbevf_ring *tx_ring,
472 struct ixgbevf_tx_buffer *first,
473 struct ixgbevf_ipsec_tx_data *itd);
474#else
475static inline void ixgbevf_init_ipsec_offload(struct ixgbevf_adapter *adapter)
476{ }
477static inline void ixgbevf_stop_ipsec_offload(struct ixgbevf_adapter *adapter)
478{ }
479static inline void ixgbevf_ipsec_restore(struct ixgbevf_adapter *adapter) { }
480static inline void ixgbevf_ipsec_rx(struct ixgbevf_ring *rx_ring,
481 union ixgbe_adv_rx_desc *rx_desc,
482 struct sk_buff *skb) { }
483static inline int ixgbevf_ipsec_tx(struct ixgbevf_ring *tx_ring,
484 struct ixgbevf_tx_buffer *first,
485 struct ixgbevf_ipsec_tx_data *itd)
486{ return 0; }
487#endif /* CONFIG_IXGBEVF_IPSEC */
488
489#define ixgbevf_hw_to_netdev(hw) \
490 (((struct ixgbevf_adapter *)(hw)->back)->netdev)
491
492#define hw_dbg(hw, format, arg...) \
493 netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg)
494
495s32 ixgbevf_poll_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size);
496s32 ixgbevf_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size);
497
498#endif /* _IXGBEVF_H_ */
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2015 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
27#ifndef _IXGBEVF_H_
28#define _IXGBEVF_H_
29
30#include <linux/types.h>
31#include <linux/bitops.h>
32#include <linux/timer.h>
33#include <linux/io.h>
34#include <linux/netdevice.h>
35#include <linux/if_vlan.h>
36#include <linux/u64_stats_sync.h>
37
38#include "vf.h"
39
40#ifdef CONFIG_NET_RX_BUSY_POLL
41#include <net/busy_poll.h>
42#define BP_EXTENDED_STATS
43#endif
44
45#define IXGBE_MAX_TXD_PWR 14
46#define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR)
47
48/* Tx Descriptors needed, worst case */
49#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
50#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
51
52/* wrapper around a pointer to a socket buffer,
53 * so a DMA handle can be stored along with the buffer
54 */
55struct ixgbevf_tx_buffer {
56 union ixgbe_adv_tx_desc *next_to_watch;
57 unsigned long time_stamp;
58 struct sk_buff *skb;
59 unsigned int bytecount;
60 unsigned short gso_segs;
61 __be16 protocol;
62 DEFINE_DMA_UNMAP_ADDR(dma);
63 DEFINE_DMA_UNMAP_LEN(len);
64 u32 tx_flags;
65};
66
67struct ixgbevf_rx_buffer {
68 dma_addr_t dma;
69 struct page *page;
70 unsigned int page_offset;
71};
72
73struct ixgbevf_stats {
74 u64 packets;
75 u64 bytes;
76#ifdef BP_EXTENDED_STATS
77 u64 yields;
78 u64 misses;
79 u64 cleaned;
80#endif
81};
82
83struct ixgbevf_tx_queue_stats {
84 u64 restart_queue;
85 u64 tx_busy;
86 u64 tx_done_old;
87};
88
89struct ixgbevf_rx_queue_stats {
90 u64 alloc_rx_page_failed;
91 u64 alloc_rx_buff_failed;
92 u64 csum_err;
93};
94
95enum ixgbevf_ring_state_t {
96 __IXGBEVF_TX_DETECT_HANG,
97 __IXGBEVF_HANG_CHECK_ARMED,
98};
99
100#define check_for_tx_hang(ring) \
101 test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
102#define set_check_for_tx_hang(ring) \
103 set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
104#define clear_check_for_tx_hang(ring) \
105 clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
106
107struct ixgbevf_ring {
108 struct ixgbevf_ring *next;
109 struct net_device *netdev;
110 struct device *dev;
111 void *desc; /* descriptor ring memory */
112 dma_addr_t dma; /* phys. address of descriptor ring */
113 unsigned int size; /* length in bytes */
114 u16 count; /* amount of descriptors */
115 u16 next_to_use;
116 u16 next_to_clean;
117 u16 next_to_alloc;
118
119 union {
120 struct ixgbevf_tx_buffer *tx_buffer_info;
121 struct ixgbevf_rx_buffer *rx_buffer_info;
122 };
123 unsigned long state;
124 struct ixgbevf_stats stats;
125 struct u64_stats_sync syncp;
126 union {
127 struct ixgbevf_tx_queue_stats tx_stats;
128 struct ixgbevf_rx_queue_stats rx_stats;
129 };
130
131 u64 hw_csum_rx_error;
132 u8 __iomem *tail;
133 struct sk_buff *skb;
134
135 /* holds the special value that gets the hardware register offset
136 * associated with this ring, which is different for DCB and RSS modes
137 */
138 u16 reg_idx;
139 int queue_index; /* needed for multiqueue queue management */
140};
141
142/* How many Rx Buffers do we bundle into one write to the hardware ? */
143#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
144
145#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
146#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
147#define IXGBEVF_MAX_RSS_QUEUES 2
148#define IXGBEVF_82599_RETA_SIZE 128 /* 128 entries */
149#define IXGBEVF_X550_VFRETA_SIZE 64 /* 64 entries */
150#define IXGBEVF_RSS_HASH_KEY_SIZE 40
151#define IXGBEVF_VFRSSRK_REGS 10 /* 10 registers for RSS key */
152
153#define IXGBEVF_DEFAULT_TXD 1024
154#define IXGBEVF_DEFAULT_RXD 512
155#define IXGBEVF_MAX_TXD 4096
156#define IXGBEVF_MIN_TXD 64
157#define IXGBEVF_MAX_RXD 4096
158#define IXGBEVF_MIN_RXD 64
159
160/* Supported Rx Buffer Sizes */
161#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
162#define IXGBEVF_RXBUFFER_2048 2048
163
164#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
165#define IXGBEVF_RX_BUFSZ IXGBEVF_RXBUFFER_2048
166
167#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
168
169#define IXGBE_TX_FLAGS_CSUM (u32)(1)
170#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
171#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
172#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
173#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
174#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
175#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
176
177struct ixgbevf_ring_container {
178 struct ixgbevf_ring *ring; /* pointer to linked list of rings */
179 unsigned int total_bytes; /* total bytes processed this int */
180 unsigned int total_packets; /* total packets processed this int */
181 u8 count; /* total number of rings in vector */
182 u8 itr; /* current ITR setting for ring */
183};
184
185/* iterator for handling rings in ring container */
186#define ixgbevf_for_each_ring(pos, head) \
187 for (pos = (head).ring; pos != NULL; pos = pos->next)
188
189/* MAX_MSIX_Q_VECTORS of these are allocated,
190 * but we only use one per queue-specific vector.
191 */
192struct ixgbevf_q_vector {
193 struct ixgbevf_adapter *adapter;
194 /* index of q_vector within array, also used for finding the bit in
195 * EICR and friends that represents the vector for this ring
196 */
197 u16 v_idx;
198 u16 itr; /* Interrupt throttle rate written to EITR */
199 struct napi_struct napi;
200 struct ixgbevf_ring_container rx, tx;
201 char name[IFNAMSIZ + 9];
202#ifdef CONFIG_NET_RX_BUSY_POLL
203 unsigned int state;
204#define IXGBEVF_QV_STATE_IDLE 0
205#define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */
206#define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */
207#define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */
208#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
209#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
210#define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
211#define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
212#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \
213 IXGBEVF_QV_STATE_POLL_YIELD)
214#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \
215 IXGBEVF_QV_STATE_POLL_YIELD)
216 spinlock_t lock;
217#endif /* CONFIG_NET_RX_BUSY_POLL */
218};
219
220#ifdef CONFIG_NET_RX_BUSY_POLL
221static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
222{
223 spin_lock_init(&q_vector->lock);
224 q_vector->state = IXGBEVF_QV_STATE_IDLE;
225}
226
227/* called from the device poll routine to get ownership of a q_vector */
228static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
229{
230 int rc = true;
231
232 spin_lock_bh(&q_vector->lock);
233 if (q_vector->state & IXGBEVF_QV_LOCKED) {
234 WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
235 q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD;
236 rc = false;
237#ifdef BP_EXTENDED_STATS
238 q_vector->tx.ring->stats.yields++;
239#endif
240 } else {
241 /* we don't care if someone yielded */
242 q_vector->state = IXGBEVF_QV_STATE_NAPI;
243 }
244 spin_unlock_bh(&q_vector->lock);
245 return rc;
246}
247
248/* returns true is someone tried to get the qv while napi had it */
249static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
250{
251 int rc = false;
252
253 spin_lock_bh(&q_vector->lock);
254 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL |
255 IXGBEVF_QV_STATE_NAPI_YIELD));
256
257 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
258 rc = true;
259 /* reset state to idle, unless QV is disabled */
260 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
261 spin_unlock_bh(&q_vector->lock);
262 return rc;
263}
264
265/* called from ixgbevf_low_latency_poll() */
266static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
267{
268 int rc = true;
269
270 spin_lock_bh(&q_vector->lock);
271 if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
272 q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD;
273 rc = false;
274#ifdef BP_EXTENDED_STATS
275 q_vector->rx.ring->stats.yields++;
276#endif
277 } else {
278 /* preserve yield marks */
279 q_vector->state |= IXGBEVF_QV_STATE_POLL;
280 }
281 spin_unlock_bh(&q_vector->lock);
282 return rc;
283}
284
285/* returns true if someone tried to get the qv while it was locked */
286static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
287{
288 int rc = false;
289
290 spin_lock_bh(&q_vector->lock);
291 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));
292
293 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
294 rc = true;
295 /* reset state to idle, unless QV is disabled */
296 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
297 spin_unlock_bh(&q_vector->lock);
298 return rc;
299}
300
301/* true if a socket is polling, even if it did not get the lock */
302static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
303{
304 WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
305 return q_vector->state & IXGBEVF_QV_USER_PEND;
306}
307
308/* false if QV is currently owned */
309static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
310{
311 int rc = true;
312
313 spin_lock_bh(&q_vector->lock);
314 if (q_vector->state & IXGBEVF_QV_OWNED)
315 rc = false;
316 q_vector->state |= IXGBEVF_QV_STATE_DISABLED;
317 spin_unlock_bh(&q_vector->lock);
318 return rc;
319}
320
321#endif /* CONFIG_NET_RX_BUSY_POLL */
322
323/* microsecond values for various ITR rates shifted by 2 to fit itr register
324 * with the first 3 bits reserved 0
325 */
326#define IXGBE_MIN_RSC_ITR 24
327#define IXGBE_100K_ITR 40
328#define IXGBE_20K_ITR 200
329#define IXGBE_12K_ITR 336
330
331/* Helper macros to switch between ints/sec and what the register uses.
332 * And yes, it's the same math going both ways. The lowest value
333 * supported by all of the ixgbe hardware is 8.
334 */
335#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
336 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
337#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
338
339/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
340static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
341 const u32 stat_err_bits)
342{
343 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
344}
345
346static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
347{
348 u16 ntc = ring->next_to_clean;
349 u16 ntu = ring->next_to_use;
350
351 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
352}
353
354static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
355{
356 writel(value, ring->tail);
357}
358
359#define IXGBEVF_RX_DESC(R, i) \
360 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
361#define IXGBEVF_TX_DESC(R, i) \
362 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
363#define IXGBEVF_TX_CTXTDESC(R, i) \
364 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
365
366#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
367
368#define OTHER_VECTOR 1
369#define NON_Q_VECTORS (OTHER_VECTOR)
370
371#define MAX_MSIX_Q_VECTORS 2
372
373#define MIN_MSIX_Q_VECTORS 1
374#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
375
376/* board specific private data structure */
377struct ixgbevf_adapter {
378 /* this field must be first, see ixgbevf_process_skb_fields */
379 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
380
381 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
382
383 /* Interrupt Throttle Rate */
384 u16 rx_itr_setting;
385 u16 tx_itr_setting;
386
387 /* interrupt masks */
388 u32 eims_enable_mask;
389 u32 eims_other;
390
391 /* TX */
392 int num_tx_queues;
393 struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */
394 u64 restart_queue;
395 u32 tx_timeout_count;
396
397 /* RX */
398 int num_rx_queues;
399 struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */
400 u64 hw_csum_rx_error;
401 u64 hw_rx_no_dma_resources;
402 int num_msix_vectors;
403 u32 alloc_rx_page_failed;
404 u32 alloc_rx_buff_failed;
405
406 /* Some features need tri-state capability,
407 * thus the additional *_CAPABLE flags.
408 */
409 u32 flags;
410#define IXGBEVF_FLAG_RESET_REQUESTED (u32)(1)
411#define IXGBEVF_FLAG_QUEUE_RESET_REQUESTED (u32)(1 << 2)
412
413 struct msix_entry *msix_entries;
414
415 /* OS defined structs */
416 struct net_device *netdev;
417 struct pci_dev *pdev;
418
419 /* structs defined in ixgbe_vf.h */
420 struct ixgbe_hw hw;
421 u16 msg_enable;
422 /* Interrupt Throttle Rate */
423 u32 eitr_param;
424
425 struct ixgbevf_hw_stats stats;
426
427 unsigned long state;
428 u64 tx_busy;
429 unsigned int tx_ring_count;
430 unsigned int rx_ring_count;
431
432#ifdef BP_EXTENDED_STATS
433 u64 bp_rx_yields;
434 u64 bp_rx_cleaned;
435 u64 bp_rx_missed;
436
437 u64 bp_tx_yields;
438 u64 bp_tx_cleaned;
439 u64 bp_tx_missed;
440#endif
441
442 u8 __iomem *io_addr; /* Mainly for iounmap use */
443 u32 link_speed;
444 bool link_up;
445
446 struct timer_list service_timer;
447 struct work_struct service_task;
448
449 spinlock_t mbx_lock;
450 unsigned long last_reset;
451
452 u32 rss_key[IXGBEVF_VFRSSRK_REGS];
453 u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
454};
455
456enum ixbgevf_state_t {
457 __IXGBEVF_TESTING,
458 __IXGBEVF_RESETTING,
459 __IXGBEVF_DOWN,
460 __IXGBEVF_DISABLED,
461 __IXGBEVF_REMOVING,
462 __IXGBEVF_SERVICE_SCHED,
463 __IXGBEVF_SERVICE_INITED,
464};
465
466enum ixgbevf_boards {
467 board_82599_vf,
468 board_X540_vf,
469 board_X550_vf,
470 board_X550EM_x_vf,
471};
472
473enum ixgbevf_xcast_modes {
474 IXGBEVF_XCAST_MODE_NONE = 0,
475 IXGBEVF_XCAST_MODE_MULTI,
476 IXGBEVF_XCAST_MODE_ALLMULTI,
477};
478
479extern const struct ixgbevf_info ixgbevf_82599_vf_info;
480extern const struct ixgbevf_info ixgbevf_X540_vf_info;
481extern const struct ixgbevf_info ixgbevf_X550_vf_info;
482extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
483extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
484
485/* needed by ethtool.c */
486extern const char ixgbevf_driver_name[];
487extern const char ixgbevf_driver_version[];
488
489int ixgbevf_open(struct net_device *netdev);
490int ixgbevf_close(struct net_device *netdev);
491void ixgbevf_up(struct ixgbevf_adapter *adapter);
492void ixgbevf_down(struct ixgbevf_adapter *adapter);
493void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
494void ixgbevf_reset(struct ixgbevf_adapter *adapter);
495void ixgbevf_set_ethtool_ops(struct net_device *netdev);
496int ixgbevf_setup_rx_resources(struct ixgbevf_ring *);
497int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
498void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
499void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
500void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
501int ethtool_ioctl(struct ifreq *ifr);
502
503extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
504
505void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
506void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
507
508#ifdef DEBUG
509char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw);
510#define hw_dbg(hw, format, arg...) \
511 printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
512#else
513#define hw_dbg(hw, format, arg...) do {} while (0)
514#endif
515
516#endif /* _IXGBEVF_H_ */