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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4#include <linux/bitfield.h>
5#include <linux/delay.h>
6#include <linux/if_ether.h>
7#include "e1000_mac.h"
8#include "e1000_phy.h"
9
10static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
11static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
12 u16 *phy_ctrl);
13static s32 igb_wait_autoneg(struct e1000_hw *hw);
14static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
15
16/* Cable length tables */
17static const u16 e1000_m88_cable_length_table[] = {
18 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
19
20static const u16 e1000_igp_2_cable_length_table[] = {
21 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
22 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
23 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
24 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
25 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
26 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
27 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
28 104, 109, 114, 118, 121, 124};
29
30/**
31 * igb_check_reset_block - Check if PHY reset is blocked
32 * @hw: pointer to the HW structure
33 *
34 * Read the PHY management control register and check whether a PHY reset
35 * is blocked. If a reset is not blocked return 0, otherwise
36 * return E1000_BLK_PHY_RESET (12).
37 **/
38s32 igb_check_reset_block(struct e1000_hw *hw)
39{
40 u32 manc;
41
42 manc = rd32(E1000_MANC);
43
44 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
45}
46
47/**
48 * igb_get_phy_id - Retrieve the PHY ID and revision
49 * @hw: pointer to the HW structure
50 *
51 * Reads the PHY registers and stores the PHY ID and possibly the PHY
52 * revision in the hardware structure.
53 **/
54s32 igb_get_phy_id(struct e1000_hw *hw)
55{
56 struct e1000_phy_info *phy = &hw->phy;
57 s32 ret_val = 0;
58 u16 phy_id;
59
60 /* ensure PHY page selection to fix misconfigured i210 */
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
63
64 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
65 if (ret_val)
66 goto out;
67
68 phy->id = (u32)(phy_id << 16);
69 udelay(20);
70 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
71 if (ret_val)
72 goto out;
73
74 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
75 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
76
77out:
78 return ret_val;
79}
80
81/**
82 * igb_phy_reset_dsp - Reset PHY DSP
83 * @hw: pointer to the HW structure
84 *
85 * Reset the digital signal processor.
86 **/
87static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
88{
89 s32 ret_val = 0;
90
91 if (!(hw->phy.ops.write_reg))
92 goto out;
93
94 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
95 if (ret_val)
96 goto out;
97
98 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
99
100out:
101 return ret_val;
102}
103
104/**
105 * igb_read_phy_reg_mdic - Read MDI control register
106 * @hw: pointer to the HW structure
107 * @offset: register offset to be read
108 * @data: pointer to the read data
109 *
110 * Reads the MDI control register in the PHY at offset and stores the
111 * information read to data.
112 **/
113s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
114{
115 struct e1000_phy_info *phy = &hw->phy;
116 u32 i, mdic = 0;
117 s32 ret_val = 0;
118
119 if (offset > MAX_PHY_REG_ADDRESS) {
120 hw_dbg("PHY Address %d is out of range\n", offset);
121 ret_val = -E1000_ERR_PARAM;
122 goto out;
123 }
124
125 /* Set up Op-code, Phy Address, and register offset in the MDI
126 * Control register. The MAC will take care of interfacing with the
127 * PHY to retrieve the desired data.
128 */
129 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
130 (phy->addr << E1000_MDIC_PHY_SHIFT) |
131 (E1000_MDIC_OP_READ));
132
133 wr32(E1000_MDIC, mdic);
134
135 /* Poll the ready bit to see if the MDI read completed
136 * Increasing the time out as testing showed failures with
137 * the lower time out
138 */
139 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
140 udelay(50);
141 mdic = rd32(E1000_MDIC);
142 if (mdic & E1000_MDIC_READY)
143 break;
144 }
145 if (!(mdic & E1000_MDIC_READY)) {
146 hw_dbg("MDI Read did not complete\n");
147 ret_val = -E1000_ERR_PHY;
148 goto out;
149 }
150 if (mdic & E1000_MDIC_ERROR) {
151 hw_dbg("MDI Error\n");
152 ret_val = -E1000_ERR_PHY;
153 goto out;
154 }
155 *data = (u16) mdic;
156
157out:
158 return ret_val;
159}
160
161/**
162 * igb_write_phy_reg_mdic - Write MDI control register
163 * @hw: pointer to the HW structure
164 * @offset: register offset to write to
165 * @data: data to write to register at offset
166 *
167 * Writes data to MDI control register in the PHY at offset.
168 **/
169s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
170{
171 struct e1000_phy_info *phy = &hw->phy;
172 u32 i, mdic = 0;
173 s32 ret_val = 0;
174
175 if (offset > MAX_PHY_REG_ADDRESS) {
176 hw_dbg("PHY Address %d is out of range\n", offset);
177 ret_val = -E1000_ERR_PARAM;
178 goto out;
179 }
180
181 /* Set up Op-code, Phy Address, and register offset in the MDI
182 * Control register. The MAC will take care of interfacing with the
183 * PHY to retrieve the desired data.
184 */
185 mdic = (((u32)data) |
186 (offset << E1000_MDIC_REG_SHIFT) |
187 (phy->addr << E1000_MDIC_PHY_SHIFT) |
188 (E1000_MDIC_OP_WRITE));
189
190 wr32(E1000_MDIC, mdic);
191
192 /* Poll the ready bit to see if the MDI read completed
193 * Increasing the time out as testing showed failures with
194 * the lower time out
195 */
196 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
197 udelay(50);
198 mdic = rd32(E1000_MDIC);
199 if (mdic & E1000_MDIC_READY)
200 break;
201 }
202 if (!(mdic & E1000_MDIC_READY)) {
203 hw_dbg("MDI Write did not complete\n");
204 ret_val = -E1000_ERR_PHY;
205 goto out;
206 }
207 if (mdic & E1000_MDIC_ERROR) {
208 hw_dbg("MDI Error\n");
209 ret_val = -E1000_ERR_PHY;
210 goto out;
211 }
212
213out:
214 return ret_val;
215}
216
217/**
218 * igb_read_phy_reg_i2c - Read PHY register using i2c
219 * @hw: pointer to the HW structure
220 * @offset: register offset to be read
221 * @data: pointer to the read data
222 *
223 * Reads the PHY register at offset using the i2c interface and stores the
224 * retrieved information in data.
225 **/
226s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
227{
228 struct e1000_phy_info *phy = &hw->phy;
229 u32 i, i2ccmd = 0;
230
231 /* Set up Op-code, Phy Address, and register address in the I2CCMD
232 * register. The MAC will take care of interfacing with the
233 * PHY to retrieve the desired data.
234 */
235 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
236 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
237 (E1000_I2CCMD_OPCODE_READ));
238
239 wr32(E1000_I2CCMD, i2ccmd);
240
241 /* Poll the ready bit to see if the I2C read completed */
242 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
243 udelay(50);
244 i2ccmd = rd32(E1000_I2CCMD);
245 if (i2ccmd & E1000_I2CCMD_READY)
246 break;
247 }
248 if (!(i2ccmd & E1000_I2CCMD_READY)) {
249 hw_dbg("I2CCMD Read did not complete\n");
250 return -E1000_ERR_PHY;
251 }
252 if (i2ccmd & E1000_I2CCMD_ERROR) {
253 hw_dbg("I2CCMD Error bit set\n");
254 return -E1000_ERR_PHY;
255 }
256
257 /* Need to byte-swap the 16-bit value. */
258 *data = ((i2ccmd >> 8) & 0x00FF) | FIELD_PREP(0xFF00, i2ccmd);
259
260 return 0;
261}
262
263/**
264 * igb_write_phy_reg_i2c - Write PHY register using i2c
265 * @hw: pointer to the HW structure
266 * @offset: register offset to write to
267 * @data: data to write at register offset
268 *
269 * Writes the data to PHY register at the offset using the i2c interface.
270 **/
271s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
272{
273 struct e1000_phy_info *phy = &hw->phy;
274 u32 i, i2ccmd = 0;
275 u16 phy_data_swapped;
276
277 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
278 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
279 hw_dbg("PHY I2C Address %d is out of range.\n",
280 hw->phy.addr);
281 return -E1000_ERR_CONFIG;
282 }
283
284 /* Swap the data bytes for the I2C interface */
285 phy_data_swapped = ((data >> 8) & 0x00FF) | FIELD_PREP(0xFF00, data);
286
287 /* Set up Op-code, Phy Address, and register address in the I2CCMD
288 * register. The MAC will take care of interfacing with the
289 * PHY to retrieve the desired data.
290 */
291 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
292 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
293 E1000_I2CCMD_OPCODE_WRITE |
294 phy_data_swapped);
295
296 wr32(E1000_I2CCMD, i2ccmd);
297
298 /* Poll the ready bit to see if the I2C read completed */
299 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
300 udelay(50);
301 i2ccmd = rd32(E1000_I2CCMD);
302 if (i2ccmd & E1000_I2CCMD_READY)
303 break;
304 }
305 if (!(i2ccmd & E1000_I2CCMD_READY)) {
306 hw_dbg("I2CCMD Write did not complete\n");
307 return -E1000_ERR_PHY;
308 }
309 if (i2ccmd & E1000_I2CCMD_ERROR) {
310 hw_dbg("I2CCMD Error bit set\n");
311 return -E1000_ERR_PHY;
312 }
313
314 return 0;
315}
316
317/**
318 * igb_read_sfp_data_byte - Reads SFP module data.
319 * @hw: pointer to the HW structure
320 * @offset: byte location offset to be read
321 * @data: read data buffer pointer
322 *
323 * Reads one byte from SFP module data stored
324 * in SFP resided EEPROM memory or SFP diagnostic area.
325 * Function should be called with
326 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
327 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
328 * access
329 **/
330s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
331{
332 u32 i = 0;
333 u32 i2ccmd = 0;
334 u32 data_local = 0;
335
336 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
337 hw_dbg("I2CCMD command address exceeds upper limit\n");
338 return -E1000_ERR_PHY;
339 }
340
341 /* Set up Op-code, EEPROM Address,in the I2CCMD
342 * register. The MAC will take care of interfacing with the
343 * EEPROM to retrieve the desired data.
344 */
345 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
346 E1000_I2CCMD_OPCODE_READ);
347
348 wr32(E1000_I2CCMD, i2ccmd);
349
350 /* Poll the ready bit to see if the I2C read completed */
351 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
352 udelay(50);
353 data_local = rd32(E1000_I2CCMD);
354 if (data_local & E1000_I2CCMD_READY)
355 break;
356 }
357 if (!(data_local & E1000_I2CCMD_READY)) {
358 hw_dbg("I2CCMD Read did not complete\n");
359 return -E1000_ERR_PHY;
360 }
361 if (data_local & E1000_I2CCMD_ERROR) {
362 hw_dbg("I2CCMD Error bit set\n");
363 return -E1000_ERR_PHY;
364 }
365 *data = (u8) data_local & 0xFF;
366
367 return 0;
368}
369
370/**
371 * igb_read_phy_reg_igp - Read igp PHY register
372 * @hw: pointer to the HW structure
373 * @offset: register offset to be read
374 * @data: pointer to the read data
375 *
376 * Acquires semaphore, if necessary, then reads the PHY register at offset
377 * and storing the retrieved information in data. Release any acquired
378 * semaphores before exiting.
379 **/
380s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
381{
382 s32 ret_val = 0;
383
384 if (!(hw->phy.ops.acquire))
385 goto out;
386
387 ret_val = hw->phy.ops.acquire(hw);
388 if (ret_val)
389 goto out;
390
391 if (offset > MAX_PHY_MULTI_PAGE_REG) {
392 ret_val = igb_write_phy_reg_mdic(hw,
393 IGP01E1000_PHY_PAGE_SELECT,
394 (u16)offset);
395 if (ret_val) {
396 hw->phy.ops.release(hw);
397 goto out;
398 }
399 }
400
401 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
402 data);
403
404 hw->phy.ops.release(hw);
405
406out:
407 return ret_val;
408}
409
410/**
411 * igb_write_phy_reg_igp - Write igp PHY register
412 * @hw: pointer to the HW structure
413 * @offset: register offset to write to
414 * @data: data to write at register offset
415 *
416 * Acquires semaphore, if necessary, then writes the data to PHY register
417 * at the offset. Release any acquired semaphores before exiting.
418 **/
419s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
420{
421 s32 ret_val = 0;
422
423 if (!(hw->phy.ops.acquire))
424 goto out;
425
426 ret_val = hw->phy.ops.acquire(hw);
427 if (ret_val)
428 goto out;
429
430 if (offset > MAX_PHY_MULTI_PAGE_REG) {
431 ret_val = igb_write_phy_reg_mdic(hw,
432 IGP01E1000_PHY_PAGE_SELECT,
433 (u16)offset);
434 if (ret_val) {
435 hw->phy.ops.release(hw);
436 goto out;
437 }
438 }
439
440 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
441 data);
442
443 hw->phy.ops.release(hw);
444
445out:
446 return ret_val;
447}
448
449/**
450 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
451 * @hw: pointer to the HW structure
452 *
453 * Sets up Carrier-sense on Transmit and downshift values.
454 **/
455s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
456{
457 struct e1000_phy_info *phy = &hw->phy;
458 s32 ret_val;
459 u16 phy_data;
460
461 if (phy->reset_disable) {
462 ret_val = 0;
463 goto out;
464 }
465
466 if (phy->type == e1000_phy_82580) {
467 ret_val = hw->phy.ops.reset(hw);
468 if (ret_val) {
469 hw_dbg("Error resetting the PHY.\n");
470 goto out;
471 }
472 }
473
474 /* Enable CRS on TX. This must be set for half-duplex operation. */
475 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
476 if (ret_val)
477 goto out;
478
479 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
480
481 /* Enable downshift */
482 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
483
484 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
485 if (ret_val)
486 goto out;
487
488 /* Set MDI/MDIX mode */
489 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
490 if (ret_val)
491 goto out;
492 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
493 /* Options:
494 * 0 - Auto (default)
495 * 1 - MDI mode
496 * 2 - MDI-X mode
497 */
498 switch (hw->phy.mdix) {
499 case 1:
500 break;
501 case 2:
502 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
503 break;
504 case 0:
505 default:
506 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
507 break;
508 }
509 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
510
511out:
512 return ret_val;
513}
514
515/**
516 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
517 * @hw: pointer to the HW structure
518 *
519 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
520 * and downshift values are set also.
521 **/
522s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
523{
524 struct e1000_phy_info *phy = &hw->phy;
525 s32 ret_val;
526 u16 phy_data;
527
528 if (phy->reset_disable) {
529 ret_val = 0;
530 goto out;
531 }
532
533 /* Enable CRS on TX. This must be set for half-duplex operation. */
534 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
535 if (ret_val)
536 goto out;
537
538 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
539
540 /* Options:
541 * MDI/MDI-X = 0 (default)
542 * 0 - Auto for all speeds
543 * 1 - MDI mode
544 * 2 - MDI-X mode
545 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
546 */
547 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
548
549 switch (phy->mdix) {
550 case 1:
551 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
552 break;
553 case 2:
554 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
555 break;
556 case 3:
557 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
558 break;
559 case 0:
560 default:
561 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
562 break;
563 }
564
565 /* Options:
566 * disable_polarity_correction = 0 (default)
567 * Automatic Correction for Reversed Cable Polarity
568 * 0 - Disabled
569 * 1 - Enabled
570 */
571 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
572 if (phy->disable_polarity_correction == 1)
573 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
574
575 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
576 if (ret_val)
577 goto out;
578
579 if (phy->revision < E1000_REVISION_4) {
580 /* Force TX_CLK in the Extended PHY Specific Control Register
581 * to 25MHz clock.
582 */
583 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
584 &phy_data);
585 if (ret_val)
586 goto out;
587
588 phy_data |= M88E1000_EPSCR_TX_CLK_25;
589
590 if ((phy->revision == E1000_REVISION_2) &&
591 (phy->id == M88E1111_I_PHY_ID)) {
592 /* 82573L PHY - set the downshift counter to 5x. */
593 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
594 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
595 } else {
596 /* Configure Master and Slave downshift values */
597 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
598 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
599 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
600 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
601 }
602 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
603 phy_data);
604 if (ret_val)
605 goto out;
606 }
607
608 /* Commit the changes. */
609 ret_val = igb_phy_sw_reset(hw);
610 if (ret_val) {
611 hw_dbg("Error committing the PHY changes\n");
612 goto out;
613 }
614
615out:
616 return ret_val;
617}
618
619/**
620 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
621 * @hw: pointer to the HW structure
622 *
623 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
624 * Also enables and sets the downshift parameters.
625 **/
626s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
627{
628 struct e1000_phy_info *phy = &hw->phy;
629 s32 ret_val;
630 u16 phy_data;
631
632 if (phy->reset_disable)
633 return 0;
634
635 /* Enable CRS on Tx. This must be set for half-duplex operation. */
636 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
637 if (ret_val)
638 return ret_val;
639
640 /* Options:
641 * MDI/MDI-X = 0 (default)
642 * 0 - Auto for all speeds
643 * 1 - MDI mode
644 * 2 - MDI-X mode
645 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
646 */
647 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
648
649 switch (phy->mdix) {
650 case 1:
651 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
652 break;
653 case 2:
654 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
655 break;
656 case 3:
657 /* M88E1112 does not support this mode) */
658 if (phy->id != M88E1112_E_PHY_ID) {
659 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
660 break;
661 }
662 fallthrough;
663 case 0:
664 default:
665 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
666 break;
667 }
668
669 /* Options:
670 * disable_polarity_correction = 0 (default)
671 * Automatic Correction for Reversed Cable Polarity
672 * 0 - Disabled
673 * 1 - Enabled
674 */
675 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
676 if (phy->disable_polarity_correction == 1)
677 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
678
679 /* Enable downshift and setting it to X6 */
680 if (phy->id == M88E1543_E_PHY_ID) {
681 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
682 ret_val =
683 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
684 if (ret_val)
685 return ret_val;
686
687 ret_val = igb_phy_sw_reset(hw);
688 if (ret_val) {
689 hw_dbg("Error committing the PHY changes\n");
690 return ret_val;
691 }
692 }
693
694 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
695 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
696 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
697
698 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
699 if (ret_val)
700 return ret_val;
701
702 /* Commit the changes. */
703 ret_val = igb_phy_sw_reset(hw);
704 if (ret_val) {
705 hw_dbg("Error committing the PHY changes\n");
706 return ret_val;
707 }
708 ret_val = igb_set_master_slave_mode(hw);
709 if (ret_val)
710 return ret_val;
711
712 return 0;
713}
714
715/**
716 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
717 * @hw: pointer to the HW structure
718 *
719 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
720 * igp PHY's.
721 **/
722s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
723{
724 struct e1000_phy_info *phy = &hw->phy;
725 s32 ret_val;
726 u16 data;
727
728 if (phy->reset_disable) {
729 ret_val = 0;
730 goto out;
731 }
732
733 ret_val = phy->ops.reset(hw);
734 if (ret_val) {
735 hw_dbg("Error resetting the PHY.\n");
736 goto out;
737 }
738
739 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
740 * timeout issues when LFS is enabled.
741 */
742 msleep(100);
743
744 /* The NVM settings will configure LPLU in D3 for
745 * non-IGP1 PHYs.
746 */
747 if (phy->type == e1000_phy_igp) {
748 /* disable lplu d3 during driver init */
749 if (phy->ops.set_d3_lplu_state)
750 ret_val = phy->ops.set_d3_lplu_state(hw, false);
751 if (ret_val) {
752 hw_dbg("Error Disabling LPLU D3\n");
753 goto out;
754 }
755 }
756
757 /* disable lplu d0 during driver init */
758 ret_val = phy->ops.set_d0_lplu_state(hw, false);
759 if (ret_val) {
760 hw_dbg("Error Disabling LPLU D0\n");
761 goto out;
762 }
763 /* Configure mdi-mdix settings */
764 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
765 if (ret_val)
766 goto out;
767
768 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
769
770 switch (phy->mdix) {
771 case 1:
772 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
773 break;
774 case 2:
775 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
776 break;
777 case 0:
778 default:
779 data |= IGP01E1000_PSCR_AUTO_MDIX;
780 break;
781 }
782 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
783 if (ret_val)
784 goto out;
785
786 /* set auto-master slave resolution settings */
787 if (hw->mac.autoneg) {
788 /* when autonegotiation advertisement is only 1000Mbps then we
789 * should disable SmartSpeed and enable Auto MasterSlave
790 * resolution as hardware default.
791 */
792 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
793 /* Disable SmartSpeed */
794 ret_val = phy->ops.read_reg(hw,
795 IGP01E1000_PHY_PORT_CONFIG,
796 &data);
797 if (ret_val)
798 goto out;
799
800 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
801 ret_val = phy->ops.write_reg(hw,
802 IGP01E1000_PHY_PORT_CONFIG,
803 data);
804 if (ret_val)
805 goto out;
806
807 /* Set auto Master/Slave resolution process */
808 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
809 if (ret_val)
810 goto out;
811
812 data &= ~CR_1000T_MS_ENABLE;
813 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
814 if (ret_val)
815 goto out;
816 }
817
818 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
819 if (ret_val)
820 goto out;
821
822 /* load defaults for future use */
823 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
824 ((data & CR_1000T_MS_VALUE) ?
825 e1000_ms_force_master :
826 e1000_ms_force_slave) :
827 e1000_ms_auto;
828
829 switch (phy->ms_type) {
830 case e1000_ms_force_master:
831 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
832 break;
833 case e1000_ms_force_slave:
834 data |= CR_1000T_MS_ENABLE;
835 data &= ~(CR_1000T_MS_VALUE);
836 break;
837 case e1000_ms_auto:
838 data &= ~CR_1000T_MS_ENABLE;
839 break;
840 default:
841 break;
842 }
843 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
844 if (ret_val)
845 goto out;
846 }
847
848out:
849 return ret_val;
850}
851
852/**
853 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
854 * @hw: pointer to the HW structure
855 *
856 * Performs initial bounds checking on autoneg advertisement parameter, then
857 * configure to advertise the full capability. Setup the PHY to autoneg
858 * and restart the negotiation process between the link partner. If
859 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
860 **/
861static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
862{
863 struct e1000_phy_info *phy = &hw->phy;
864 s32 ret_val;
865 u16 phy_ctrl;
866
867 /* Perform some bounds checking on the autoneg advertisement
868 * parameter.
869 */
870 phy->autoneg_advertised &= phy->autoneg_mask;
871
872 /* If autoneg_advertised is zero, we assume it was not defaulted
873 * by the calling code so we set to advertise full capability.
874 */
875 if (phy->autoneg_advertised == 0)
876 phy->autoneg_advertised = phy->autoneg_mask;
877
878 hw_dbg("Reconfiguring auto-neg advertisement params\n");
879 ret_val = igb_phy_setup_autoneg(hw);
880 if (ret_val) {
881 hw_dbg("Error Setting up Auto-Negotiation\n");
882 goto out;
883 }
884 hw_dbg("Restarting Auto-Neg\n");
885
886 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
887 * the Auto Neg Restart bit in the PHY control register.
888 */
889 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
890 if (ret_val)
891 goto out;
892
893 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
894 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
895 if (ret_val)
896 goto out;
897
898 /* Does the user want to wait for Auto-Neg to complete here, or
899 * check at a later time (for example, callback routine).
900 */
901 if (phy->autoneg_wait_to_complete) {
902 ret_val = igb_wait_autoneg(hw);
903 if (ret_val) {
904 hw_dbg("Error while waiting for autoneg to complete\n");
905 goto out;
906 }
907 }
908
909 hw->mac.get_link_status = true;
910
911out:
912 return ret_val;
913}
914
915/**
916 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
917 * @hw: pointer to the HW structure
918 *
919 * Reads the MII auto-neg advertisement register and/or the 1000T control
920 * register and if the PHY is already setup for auto-negotiation, then
921 * return successful. Otherwise, setup advertisement and flow control to
922 * the appropriate values for the wanted auto-negotiation.
923 **/
924static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
925{
926 struct e1000_phy_info *phy = &hw->phy;
927 s32 ret_val;
928 u16 mii_autoneg_adv_reg;
929 u16 mii_1000t_ctrl_reg = 0;
930
931 phy->autoneg_advertised &= phy->autoneg_mask;
932
933 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
934 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
935 if (ret_val)
936 goto out;
937
938 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
939 /* Read the MII 1000Base-T Control Register (Address 9). */
940 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
941 &mii_1000t_ctrl_reg);
942 if (ret_val)
943 goto out;
944 }
945
946 /* Need to parse both autoneg_advertised and fc and set up
947 * the appropriate PHY registers. First we will parse for
948 * autoneg_advertised software override. Since we can advertise
949 * a plethora of combinations, we need to check each bit
950 * individually.
951 */
952
953 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
954 * Advertisement Register (Address 4) and the 1000 mb speed bits in
955 * the 1000Base-T Control Register (Address 9).
956 */
957 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
958 NWAY_AR_100TX_HD_CAPS |
959 NWAY_AR_10T_FD_CAPS |
960 NWAY_AR_10T_HD_CAPS);
961 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
962
963 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
964
965 /* Do we want to advertise 10 Mb Half Duplex? */
966 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
967 hw_dbg("Advertise 10mb Half duplex\n");
968 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
969 }
970
971 /* Do we want to advertise 10 Mb Full Duplex? */
972 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
973 hw_dbg("Advertise 10mb Full duplex\n");
974 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
975 }
976
977 /* Do we want to advertise 100 Mb Half Duplex? */
978 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
979 hw_dbg("Advertise 100mb Half duplex\n");
980 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
981 }
982
983 /* Do we want to advertise 100 Mb Full Duplex? */
984 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
985 hw_dbg("Advertise 100mb Full duplex\n");
986 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
987 }
988
989 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
990 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
991 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
992
993 /* Do we want to advertise 1000 Mb Full Duplex? */
994 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
995 hw_dbg("Advertise 1000mb Full duplex\n");
996 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
997 }
998
999 /* Check for a software override of the flow control settings, and
1000 * setup the PHY advertisement registers accordingly. If
1001 * auto-negotiation is enabled, then software will have to set the
1002 * "PAUSE" bits to the correct value in the Auto-Negotiation
1003 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1004 * negotiation.
1005 *
1006 * The possible values of the "fc" parameter are:
1007 * 0: Flow control is completely disabled
1008 * 1: Rx flow control is enabled (we can receive pause frames
1009 * but not send pause frames).
1010 * 2: Tx flow control is enabled (we can send pause frames
1011 * but we do not support receiving pause frames).
1012 * 3: Both Rx and TX flow control (symmetric) are enabled.
1013 * other: No software override. The flow control configuration
1014 * in the EEPROM is used.
1015 */
1016 switch (hw->fc.current_mode) {
1017 case e1000_fc_none:
1018 /* Flow control (RX & TX) is completely disabled by a
1019 * software over-ride.
1020 */
1021 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1022 break;
1023 case e1000_fc_rx_pause:
1024 /* RX Flow control is enabled, and TX Flow control is
1025 * disabled, by a software over-ride.
1026 *
1027 * Since there really isn't a way to advertise that we are
1028 * capable of RX Pause ONLY, we will advertise that we
1029 * support both symmetric and asymmetric RX PAUSE. Later
1030 * (in e1000_config_fc_after_link_up) we will disable the
1031 * hw's ability to send PAUSE frames.
1032 */
1033 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1034 break;
1035 case e1000_fc_tx_pause:
1036 /* TX Flow control is enabled, and RX Flow control is
1037 * disabled, by a software over-ride.
1038 */
1039 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1040 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1041 break;
1042 case e1000_fc_full:
1043 /* Flow control (both RX and TX) is enabled by a software
1044 * over-ride.
1045 */
1046 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1047 break;
1048 default:
1049 hw_dbg("Flow control param set incorrectly\n");
1050 ret_val = -E1000_ERR_CONFIG;
1051 goto out;
1052 }
1053
1054 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1055 if (ret_val)
1056 goto out;
1057
1058 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1059
1060 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1061 ret_val = phy->ops.write_reg(hw,
1062 PHY_1000T_CTRL,
1063 mii_1000t_ctrl_reg);
1064 if (ret_val)
1065 goto out;
1066 }
1067
1068out:
1069 return ret_val;
1070}
1071
1072/**
1073 * igb_setup_copper_link - Configure copper link settings
1074 * @hw: pointer to the HW structure
1075 *
1076 * Calls the appropriate function to configure the link for auto-neg or forced
1077 * speed and duplex. Then we check for link, once link is established calls
1078 * to configure collision distance and flow control are called. If link is
1079 * not established, we return -E1000_ERR_PHY (-2).
1080 **/
1081s32 igb_setup_copper_link(struct e1000_hw *hw)
1082{
1083 s32 ret_val;
1084 bool link;
1085
1086 if (hw->mac.autoneg) {
1087 /* Setup autoneg and flow control advertisement and perform
1088 * autonegotiation.
1089 */
1090 ret_val = igb_copper_link_autoneg(hw);
1091 if (ret_val)
1092 goto out;
1093 } else {
1094 /* PHY will be set to 10H, 10F, 100H or 100F
1095 * depending on user settings.
1096 */
1097 hw_dbg("Forcing Speed and Duplex\n");
1098 ret_val = hw->phy.ops.force_speed_duplex(hw);
1099 if (ret_val) {
1100 hw_dbg("Error Forcing Speed and Duplex\n");
1101 goto out;
1102 }
1103 }
1104
1105 /* Check link status. Wait up to 100 microseconds for link to become
1106 * valid.
1107 */
1108 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1109 if (ret_val)
1110 goto out;
1111
1112 if (link) {
1113 hw_dbg("Valid link established!!!\n");
1114 igb_config_collision_dist(hw);
1115 ret_val = igb_config_fc_after_link_up(hw);
1116 } else {
1117 hw_dbg("Unable to establish link!!!\n");
1118 }
1119
1120out:
1121 return ret_val;
1122}
1123
1124/**
1125 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1126 * @hw: pointer to the HW structure
1127 *
1128 * Calls the PHY setup function to force speed and duplex. Clears the
1129 * auto-crossover to force MDI manually. Waits for link and returns
1130 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1131 **/
1132s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1133{
1134 struct e1000_phy_info *phy = &hw->phy;
1135 s32 ret_val;
1136 u16 phy_data;
1137 bool link;
1138
1139 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1140 if (ret_val)
1141 goto out;
1142
1143 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1144
1145 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1146 if (ret_val)
1147 goto out;
1148
1149 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1150 * forced whenever speed and duplex are forced.
1151 */
1152 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1153 if (ret_val)
1154 goto out;
1155
1156 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1157 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1158
1159 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1160 if (ret_val)
1161 goto out;
1162
1163 hw_dbg("IGP PSCR: %X\n", phy_data);
1164
1165 udelay(1);
1166
1167 if (phy->autoneg_wait_to_complete) {
1168 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1169
1170 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1171 if (ret_val)
1172 goto out;
1173
1174 if (!link)
1175 hw_dbg("Link taking longer than expected.\n");
1176
1177 /* Try once more */
1178 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1179 if (ret_val)
1180 goto out;
1181 }
1182
1183out:
1184 return ret_val;
1185}
1186
1187/**
1188 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1189 * @hw: pointer to the HW structure
1190 *
1191 * Calls the PHY setup function to force speed and duplex. Clears the
1192 * auto-crossover to force MDI manually. Resets the PHY to commit the
1193 * changes. If time expires while waiting for link up, we reset the DSP.
1194 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1195 * successful completion, else return corresponding error code.
1196 **/
1197s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1198{
1199 struct e1000_phy_info *phy = &hw->phy;
1200 s32 ret_val;
1201 u16 phy_data;
1202 bool link;
1203
1204 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1205 if (phy->type != e1000_phy_i210) {
1206 /* Clear Auto-Crossover to force MDI manually. M88E1000
1207 * requires MDI forced whenever speed and duplex are forced.
1208 */
1209 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1210 &phy_data);
1211 if (ret_val)
1212 goto out;
1213
1214 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1215 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1216 phy_data);
1217 if (ret_val)
1218 goto out;
1219
1220 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1221 }
1222
1223 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1224 if (ret_val)
1225 goto out;
1226
1227 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1228
1229 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1230 if (ret_val)
1231 goto out;
1232
1233 /* Reset the phy to commit changes. */
1234 ret_val = igb_phy_sw_reset(hw);
1235 if (ret_val)
1236 goto out;
1237
1238 if (phy->autoneg_wait_to_complete) {
1239 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1240
1241 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1242 if (ret_val)
1243 goto out;
1244
1245 if (!link) {
1246 bool reset_dsp = true;
1247
1248 switch (hw->phy.id) {
1249 case I347AT4_E_PHY_ID:
1250 case M88E1112_E_PHY_ID:
1251 case M88E1543_E_PHY_ID:
1252 case M88E1512_E_PHY_ID:
1253 case I210_I_PHY_ID:
1254 reset_dsp = false;
1255 break;
1256 default:
1257 if (hw->phy.type != e1000_phy_m88)
1258 reset_dsp = false;
1259 break;
1260 }
1261 if (!reset_dsp) {
1262 hw_dbg("Link taking longer than expected.\n");
1263 } else {
1264 /* We didn't get link.
1265 * Reset the DSP and cross our fingers.
1266 */
1267 ret_val = phy->ops.write_reg(hw,
1268 M88E1000_PHY_PAGE_SELECT,
1269 0x001d);
1270 if (ret_val)
1271 goto out;
1272 ret_val = igb_phy_reset_dsp(hw);
1273 if (ret_val)
1274 goto out;
1275 }
1276 }
1277
1278 /* Try once more */
1279 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1280 100000, &link);
1281 if (ret_val)
1282 goto out;
1283 }
1284
1285 if (hw->phy.type != e1000_phy_m88 ||
1286 hw->phy.id == I347AT4_E_PHY_ID ||
1287 hw->phy.id == M88E1112_E_PHY_ID ||
1288 hw->phy.id == M88E1543_E_PHY_ID ||
1289 hw->phy.id == M88E1512_E_PHY_ID ||
1290 hw->phy.id == I210_I_PHY_ID)
1291 goto out;
1292
1293 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1294 if (ret_val)
1295 goto out;
1296
1297 /* Resetting the phy means we need to re-force TX_CLK in the
1298 * Extended PHY Specific Control Register to 25MHz clock from
1299 * the reset value of 2.5MHz.
1300 */
1301 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1302 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1303 if (ret_val)
1304 goto out;
1305
1306 /* In addition, we must re-enable CRS on Tx for both half and full
1307 * duplex.
1308 */
1309 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1310 if (ret_val)
1311 goto out;
1312
1313 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1314 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1315
1316out:
1317 return ret_val;
1318}
1319
1320/**
1321 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1322 * @hw: pointer to the HW structure
1323 * @phy_ctrl: pointer to current value of PHY_CONTROL
1324 *
1325 * Forces speed and duplex on the PHY by doing the following: disable flow
1326 * control, force speed/duplex on the MAC, disable auto speed detection,
1327 * disable auto-negotiation, configure duplex, configure speed, configure
1328 * the collision distance, write configuration to CTRL register. The
1329 * caller must write to the PHY_CONTROL register for these settings to
1330 * take affect.
1331 **/
1332static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1333 u16 *phy_ctrl)
1334{
1335 struct e1000_mac_info *mac = &hw->mac;
1336 u32 ctrl;
1337
1338 /* Turn off flow control when forcing speed/duplex */
1339 hw->fc.current_mode = e1000_fc_none;
1340
1341 /* Force speed/duplex on the mac */
1342 ctrl = rd32(E1000_CTRL);
1343 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1344 ctrl &= ~E1000_CTRL_SPD_SEL;
1345
1346 /* Disable Auto Speed Detection */
1347 ctrl &= ~E1000_CTRL_ASDE;
1348
1349 /* Disable autoneg on the phy */
1350 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1351
1352 /* Forcing Full or Half Duplex? */
1353 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1354 ctrl &= ~E1000_CTRL_FD;
1355 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1356 hw_dbg("Half Duplex\n");
1357 } else {
1358 ctrl |= E1000_CTRL_FD;
1359 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1360 hw_dbg("Full Duplex\n");
1361 }
1362
1363 /* Forcing 10mb or 100mb? */
1364 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1365 ctrl |= E1000_CTRL_SPD_100;
1366 *phy_ctrl |= MII_CR_SPEED_100;
1367 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1368 hw_dbg("Forcing 100mb\n");
1369 } else {
1370 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1371 *phy_ctrl |= MII_CR_SPEED_10;
1372 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1373 hw_dbg("Forcing 10mb\n");
1374 }
1375
1376 igb_config_collision_dist(hw);
1377
1378 wr32(E1000_CTRL, ctrl);
1379}
1380
1381/**
1382 * igb_set_d3_lplu_state - Sets low power link up state for D3
1383 * @hw: pointer to the HW structure
1384 * @active: boolean used to enable/disable lplu
1385 *
1386 * Success returns 0, Failure returns 1
1387 *
1388 * The low power link up (lplu) state is set to the power management level D3
1389 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1390 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1391 * is used during Dx states where the power conservation is most important.
1392 * During driver activity, SmartSpeed should be enabled so performance is
1393 * maintained.
1394 **/
1395s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1396{
1397 struct e1000_phy_info *phy = &hw->phy;
1398 s32 ret_val = 0;
1399 u16 data;
1400
1401 if (!(hw->phy.ops.read_reg))
1402 goto out;
1403
1404 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1405 if (ret_val)
1406 goto out;
1407
1408 if (!active) {
1409 data &= ~IGP02E1000_PM_D3_LPLU;
1410 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1411 data);
1412 if (ret_val)
1413 goto out;
1414 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1415 * during Dx states where the power conservation is most
1416 * important. During driver activity we should enable
1417 * SmartSpeed, so performance is maintained.
1418 */
1419 if (phy->smart_speed == e1000_smart_speed_on) {
1420 ret_val = phy->ops.read_reg(hw,
1421 IGP01E1000_PHY_PORT_CONFIG,
1422 &data);
1423 if (ret_val)
1424 goto out;
1425
1426 data |= IGP01E1000_PSCFR_SMART_SPEED;
1427 ret_val = phy->ops.write_reg(hw,
1428 IGP01E1000_PHY_PORT_CONFIG,
1429 data);
1430 if (ret_val)
1431 goto out;
1432 } else if (phy->smart_speed == e1000_smart_speed_off) {
1433 ret_val = phy->ops.read_reg(hw,
1434 IGP01E1000_PHY_PORT_CONFIG,
1435 &data);
1436 if (ret_val)
1437 goto out;
1438
1439 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1440 ret_val = phy->ops.write_reg(hw,
1441 IGP01E1000_PHY_PORT_CONFIG,
1442 data);
1443 if (ret_val)
1444 goto out;
1445 }
1446 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1447 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1448 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1449 data |= IGP02E1000_PM_D3_LPLU;
1450 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1451 data);
1452 if (ret_val)
1453 goto out;
1454
1455 /* When LPLU is enabled, we should disable SmartSpeed */
1456 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1457 &data);
1458 if (ret_val)
1459 goto out;
1460
1461 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1462 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1463 data);
1464 }
1465
1466out:
1467 return ret_val;
1468}
1469
1470/**
1471 * igb_check_downshift - Checks whether a downshift in speed occurred
1472 * @hw: pointer to the HW structure
1473 *
1474 * Success returns 0, Failure returns 1
1475 *
1476 * A downshift is detected by querying the PHY link health.
1477 **/
1478s32 igb_check_downshift(struct e1000_hw *hw)
1479{
1480 struct e1000_phy_info *phy = &hw->phy;
1481 s32 ret_val;
1482 u16 phy_data, offset, mask;
1483
1484 switch (phy->type) {
1485 case e1000_phy_i210:
1486 case e1000_phy_m88:
1487 case e1000_phy_gg82563:
1488 offset = M88E1000_PHY_SPEC_STATUS;
1489 mask = M88E1000_PSSR_DOWNSHIFT;
1490 break;
1491 case e1000_phy_igp_2:
1492 case e1000_phy_igp:
1493 case e1000_phy_igp_3:
1494 offset = IGP01E1000_PHY_LINK_HEALTH;
1495 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1496 break;
1497 default:
1498 /* speed downshift not supported */
1499 phy->speed_downgraded = false;
1500 ret_val = 0;
1501 goto out;
1502 }
1503
1504 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1505
1506 if (!ret_val)
1507 phy->speed_downgraded = (phy_data & mask) ? true : false;
1508
1509out:
1510 return ret_val;
1511}
1512
1513/**
1514 * igb_check_polarity_m88 - Checks the polarity.
1515 * @hw: pointer to the HW structure
1516 *
1517 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1518 *
1519 * Polarity is determined based on the PHY specific status register.
1520 **/
1521s32 igb_check_polarity_m88(struct e1000_hw *hw)
1522{
1523 struct e1000_phy_info *phy = &hw->phy;
1524 s32 ret_val;
1525 u16 data;
1526
1527 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1528
1529 if (!ret_val)
1530 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1531 ? e1000_rev_polarity_reversed
1532 : e1000_rev_polarity_normal;
1533
1534 return ret_val;
1535}
1536
1537/**
1538 * igb_check_polarity_igp - Checks the polarity.
1539 * @hw: pointer to the HW structure
1540 *
1541 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1542 *
1543 * Polarity is determined based on the PHY port status register, and the
1544 * current speed (since there is no polarity at 100Mbps).
1545 **/
1546static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1547{
1548 struct e1000_phy_info *phy = &hw->phy;
1549 s32 ret_val;
1550 u16 data, offset, mask;
1551
1552 /* Polarity is determined based on the speed of
1553 * our connection.
1554 */
1555 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1556 if (ret_val)
1557 goto out;
1558
1559 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1560 IGP01E1000_PSSR_SPEED_1000MBPS) {
1561 offset = IGP01E1000_PHY_PCS_INIT_REG;
1562 mask = IGP01E1000_PHY_POLARITY_MASK;
1563 } else {
1564 /* This really only applies to 10Mbps since
1565 * there is no polarity for 100Mbps (always 0).
1566 */
1567 offset = IGP01E1000_PHY_PORT_STATUS;
1568 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1569 }
1570
1571 ret_val = phy->ops.read_reg(hw, offset, &data);
1572
1573 if (!ret_val)
1574 phy->cable_polarity = (data & mask)
1575 ? e1000_rev_polarity_reversed
1576 : e1000_rev_polarity_normal;
1577
1578out:
1579 return ret_val;
1580}
1581
1582/**
1583 * igb_wait_autoneg - Wait for auto-neg completion
1584 * @hw: pointer to the HW structure
1585 *
1586 * Waits for auto-negotiation to complete or for the auto-negotiation time
1587 * limit to expire, which ever happens first.
1588 **/
1589static s32 igb_wait_autoneg(struct e1000_hw *hw)
1590{
1591 s32 ret_val = 0;
1592 u16 i, phy_status;
1593
1594 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1595 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1596 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1597 if (ret_val)
1598 break;
1599 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1600 if (ret_val)
1601 break;
1602 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1603 break;
1604 msleep(100);
1605 }
1606
1607 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1608 * has completed.
1609 */
1610 return ret_val;
1611}
1612
1613/**
1614 * igb_phy_has_link - Polls PHY for link
1615 * @hw: pointer to the HW structure
1616 * @iterations: number of times to poll for link
1617 * @usec_interval: delay between polling attempts
1618 * @success: pointer to whether polling was successful or not
1619 *
1620 * Polls the PHY status register for link, 'iterations' number of times.
1621 **/
1622s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1623 u32 usec_interval, bool *success)
1624{
1625 s32 ret_val = 0;
1626 u16 i, phy_status;
1627
1628 for (i = 0; i < iterations; i++) {
1629 /* Some PHYs require the PHY_STATUS register to be read
1630 * twice due to the link bit being sticky. No harm doing
1631 * it across the board.
1632 */
1633 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1634 if (ret_val && usec_interval > 0) {
1635 /* If the first read fails, another entity may have
1636 * ownership of the resources, wait and try again to
1637 * see if they have relinquished the resources yet.
1638 */
1639 if (usec_interval >= 1000)
1640 mdelay(usec_interval/1000);
1641 else
1642 udelay(usec_interval);
1643 }
1644 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1645 if (ret_val)
1646 break;
1647 if (phy_status & MII_SR_LINK_STATUS)
1648 break;
1649 if (usec_interval >= 1000)
1650 mdelay(usec_interval/1000);
1651 else
1652 udelay(usec_interval);
1653 }
1654
1655 *success = (i < iterations) ? true : false;
1656
1657 return ret_val;
1658}
1659
1660/**
1661 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1662 * @hw: pointer to the HW structure
1663 *
1664 * Reads the PHY specific status register to retrieve the cable length
1665 * information. The cable length is determined by averaging the minimum and
1666 * maximum values to get the "average" cable length. The m88 PHY has four
1667 * possible cable length values, which are:
1668 * Register Value Cable Length
1669 * 0 < 50 meters
1670 * 1 50 - 80 meters
1671 * 2 80 - 110 meters
1672 * 3 110 - 140 meters
1673 * 4 > 140 meters
1674 **/
1675s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1676{
1677 struct e1000_phy_info *phy = &hw->phy;
1678 s32 ret_val;
1679 u16 phy_data, index;
1680
1681 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1682 if (ret_val)
1683 goto out;
1684
1685 index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
1686 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1687 ret_val = -E1000_ERR_PHY;
1688 goto out;
1689 }
1690
1691 phy->min_cable_length = e1000_m88_cable_length_table[index];
1692 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1693
1694 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1695
1696out:
1697 return ret_val;
1698}
1699
1700s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1701{
1702 struct e1000_phy_info *phy = &hw->phy;
1703 s32 ret_val;
1704 u16 phy_data, phy_data2, index, default_page, is_cm;
1705 int len_tot = 0;
1706 u16 len_min;
1707 u16 len_max;
1708
1709 switch (hw->phy.id) {
1710 case M88E1543_E_PHY_ID:
1711 case M88E1512_E_PHY_ID:
1712 case I347AT4_E_PHY_ID:
1713 case I210_I_PHY_ID:
1714 /* Remember the original page select and set it to 7 */
1715 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1716 &default_page);
1717 if (ret_val)
1718 goto out;
1719
1720 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1721 if (ret_val)
1722 goto out;
1723
1724 /* Check if the unit of cable length is meters or cm */
1725 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1726 if (ret_val)
1727 goto out;
1728
1729 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1730
1731 /* Get cable length from Pair 0 length Regs */
1732 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL0, &phy_data);
1733 if (ret_val)
1734 goto out;
1735
1736 phy->pair_length[0] = phy_data / (is_cm ? 100 : 1);
1737 len_tot = phy->pair_length[0];
1738 len_min = phy->pair_length[0];
1739 len_max = phy->pair_length[0];
1740
1741 /* Get cable length from Pair 1 length Regs */
1742 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL1, &phy_data);
1743 if (ret_val)
1744 goto out;
1745
1746 phy->pair_length[1] = phy_data / (is_cm ? 100 : 1);
1747 len_tot += phy->pair_length[1];
1748 len_min = min(len_min, phy->pair_length[1]);
1749 len_max = max(len_max, phy->pair_length[1]);
1750
1751 /* Get cable length from Pair 2 length Regs */
1752 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL2, &phy_data);
1753 if (ret_val)
1754 goto out;
1755
1756 phy->pair_length[2] = phy_data / (is_cm ? 100 : 1);
1757 len_tot += phy->pair_length[2];
1758 len_min = min(len_min, phy->pair_length[2]);
1759 len_max = max(len_max, phy->pair_length[2]);
1760
1761 /* Get cable length from Pair 3 length Regs */
1762 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL3, &phy_data);
1763 if (ret_val)
1764 goto out;
1765
1766 phy->pair_length[3] = phy_data / (is_cm ? 100 : 1);
1767 len_tot += phy->pair_length[3];
1768 len_min = min(len_min, phy->pair_length[3]);
1769 len_max = max(len_max, phy->pair_length[3]);
1770
1771 /* Populate the phy structure with cable length in meters */
1772 phy->min_cable_length = len_min;
1773 phy->max_cable_length = len_max;
1774 phy->cable_length = len_tot / 4;
1775
1776 /* Reset the page selec to its original value */
1777 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1778 default_page);
1779 if (ret_val)
1780 goto out;
1781 break;
1782 case M88E1112_E_PHY_ID:
1783 /* Remember the original page select and set it to 5 */
1784 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1785 &default_page);
1786 if (ret_val)
1787 goto out;
1788
1789 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1790 if (ret_val)
1791 goto out;
1792
1793 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1794 &phy_data);
1795 if (ret_val)
1796 goto out;
1797
1798 index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
1799 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1800 ret_val = -E1000_ERR_PHY;
1801 goto out;
1802 }
1803
1804 phy->min_cable_length = e1000_m88_cable_length_table[index];
1805 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1806
1807 phy->cable_length = (phy->min_cable_length +
1808 phy->max_cable_length) / 2;
1809
1810 /* Reset the page select to its original value */
1811 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1812 default_page);
1813 if (ret_val)
1814 goto out;
1815
1816 break;
1817 default:
1818 ret_val = -E1000_ERR_PHY;
1819 goto out;
1820 }
1821
1822out:
1823 return ret_val;
1824}
1825
1826/**
1827 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1828 * @hw: pointer to the HW structure
1829 *
1830 * The automatic gain control (agc) normalizes the amplitude of the
1831 * received signal, adjusting for the attenuation produced by the
1832 * cable. By reading the AGC registers, which represent the
1833 * combination of coarse and fine gain value, the value can be put
1834 * into a lookup table to obtain the approximate cable length
1835 * for each channel.
1836 **/
1837s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1838{
1839 struct e1000_phy_info *phy = &hw->phy;
1840 s32 ret_val = 0;
1841 u16 phy_data, i, agc_value = 0;
1842 u16 cur_agc_index, max_agc_index = 0;
1843 u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1;
1844 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1845 IGP02E1000_PHY_AGC_A,
1846 IGP02E1000_PHY_AGC_B,
1847 IGP02E1000_PHY_AGC_C,
1848 IGP02E1000_PHY_AGC_D
1849 };
1850
1851 /* Read the AGC registers for all channels */
1852 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1853 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1854 if (ret_val)
1855 goto out;
1856
1857 /* Getting bits 15:9, which represent the combination of
1858 * coarse and fine gain values. The result is a number
1859 * that can be put into the lookup table to obtain the
1860 * approximate cable length.
1861 */
1862 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1863 IGP02E1000_AGC_LENGTH_MASK;
1864
1865 /* Array index bound check. */
1866 if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) ||
1867 (cur_agc_index == 0)) {
1868 ret_val = -E1000_ERR_PHY;
1869 goto out;
1870 }
1871
1872 /* Remove min & max AGC values from calculation. */
1873 if (e1000_igp_2_cable_length_table[min_agc_index] >
1874 e1000_igp_2_cable_length_table[cur_agc_index])
1875 min_agc_index = cur_agc_index;
1876 if (e1000_igp_2_cable_length_table[max_agc_index] <
1877 e1000_igp_2_cable_length_table[cur_agc_index])
1878 max_agc_index = cur_agc_index;
1879
1880 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1881 }
1882
1883 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1884 e1000_igp_2_cable_length_table[max_agc_index]);
1885 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1886
1887 /* Calculate cable length with the error range of +/- 10 meters. */
1888 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1889 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1890 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1891
1892 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1893
1894out:
1895 return ret_val;
1896}
1897
1898/**
1899 * igb_get_phy_info_m88 - Retrieve PHY information
1900 * @hw: pointer to the HW structure
1901 *
1902 * Valid for only copper links. Read the PHY status register (sticky read)
1903 * to verify that link is up. Read the PHY special control register to
1904 * determine the polarity and 10base-T extended distance. Read the PHY
1905 * special status register to determine MDI/MDIx and current speed. If
1906 * speed is 1000, then determine cable length, local and remote receiver.
1907 **/
1908s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1909{
1910 struct e1000_phy_info *phy = &hw->phy;
1911 s32 ret_val;
1912 u16 phy_data;
1913 bool link;
1914
1915 if (phy->media_type != e1000_media_type_copper) {
1916 hw_dbg("Phy info is only valid for copper media\n");
1917 ret_val = -E1000_ERR_CONFIG;
1918 goto out;
1919 }
1920
1921 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1922 if (ret_val)
1923 goto out;
1924
1925 if (!link) {
1926 hw_dbg("Phy info is only valid if link is up\n");
1927 ret_val = -E1000_ERR_CONFIG;
1928 goto out;
1929 }
1930
1931 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1932 if (ret_val)
1933 goto out;
1934
1935 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1936 ? true : false;
1937
1938 ret_val = igb_check_polarity_m88(hw);
1939 if (ret_val)
1940 goto out;
1941
1942 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1943 if (ret_val)
1944 goto out;
1945
1946 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1947
1948 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1949 ret_val = phy->ops.get_cable_length(hw);
1950 if (ret_val)
1951 goto out;
1952
1953 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1954 if (ret_val)
1955 goto out;
1956
1957 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1958 ? e1000_1000t_rx_status_ok
1959 : e1000_1000t_rx_status_not_ok;
1960
1961 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1962 ? e1000_1000t_rx_status_ok
1963 : e1000_1000t_rx_status_not_ok;
1964 } else {
1965 /* Set values to "undefined" */
1966 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1967 phy->local_rx = e1000_1000t_rx_status_undefined;
1968 phy->remote_rx = e1000_1000t_rx_status_undefined;
1969 }
1970
1971out:
1972 return ret_val;
1973}
1974
1975/**
1976 * igb_get_phy_info_igp - Retrieve igp PHY information
1977 * @hw: pointer to the HW structure
1978 *
1979 * Read PHY status to determine if link is up. If link is up, then
1980 * set/determine 10base-T extended distance and polarity correction. Read
1981 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1982 * determine on the cable length, local and remote receiver.
1983 **/
1984s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1985{
1986 struct e1000_phy_info *phy = &hw->phy;
1987 s32 ret_val;
1988 u16 data;
1989 bool link;
1990
1991 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1992 if (ret_val)
1993 goto out;
1994
1995 if (!link) {
1996 hw_dbg("Phy info is only valid if link is up\n");
1997 ret_val = -E1000_ERR_CONFIG;
1998 goto out;
1999 }
2000
2001 phy->polarity_correction = true;
2002
2003 ret_val = igb_check_polarity_igp(hw);
2004 if (ret_val)
2005 goto out;
2006
2007 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2008 if (ret_val)
2009 goto out;
2010
2011 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2012
2013 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2014 IGP01E1000_PSSR_SPEED_1000MBPS) {
2015 ret_val = phy->ops.get_cable_length(hw);
2016 if (ret_val)
2017 goto out;
2018
2019 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2020 if (ret_val)
2021 goto out;
2022
2023 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2024 ? e1000_1000t_rx_status_ok
2025 : e1000_1000t_rx_status_not_ok;
2026
2027 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2028 ? e1000_1000t_rx_status_ok
2029 : e1000_1000t_rx_status_not_ok;
2030 } else {
2031 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2032 phy->local_rx = e1000_1000t_rx_status_undefined;
2033 phy->remote_rx = e1000_1000t_rx_status_undefined;
2034 }
2035
2036out:
2037 return ret_val;
2038}
2039
2040/**
2041 * igb_phy_sw_reset - PHY software reset
2042 * @hw: pointer to the HW structure
2043 *
2044 * Does a software reset of the PHY by reading the PHY control register and
2045 * setting/write the control register reset bit to the PHY.
2046 **/
2047s32 igb_phy_sw_reset(struct e1000_hw *hw)
2048{
2049 s32 ret_val = 0;
2050 u16 phy_ctrl;
2051
2052 if (!(hw->phy.ops.read_reg))
2053 goto out;
2054
2055 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2056 if (ret_val)
2057 goto out;
2058
2059 phy_ctrl |= MII_CR_RESET;
2060 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2061 if (ret_val)
2062 goto out;
2063
2064 udelay(1);
2065
2066out:
2067 return ret_val;
2068}
2069
2070/**
2071 * igb_phy_hw_reset - PHY hardware reset
2072 * @hw: pointer to the HW structure
2073 *
2074 * Verify the reset block is not blocking us from resetting. Acquire
2075 * semaphore (if necessary) and read/set/write the device control reset
2076 * bit in the PHY. Wait the appropriate delay time for the device to
2077 * reset and release the semaphore (if necessary).
2078 **/
2079s32 igb_phy_hw_reset(struct e1000_hw *hw)
2080{
2081 struct e1000_phy_info *phy = &hw->phy;
2082 s32 ret_val;
2083 u32 ctrl;
2084
2085 ret_val = igb_check_reset_block(hw);
2086 if (ret_val) {
2087 ret_val = 0;
2088 goto out;
2089 }
2090
2091 ret_val = phy->ops.acquire(hw);
2092 if (ret_val)
2093 goto out;
2094
2095 ctrl = rd32(E1000_CTRL);
2096 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2097 wrfl();
2098
2099 udelay(phy->reset_delay_us);
2100
2101 wr32(E1000_CTRL, ctrl);
2102 wrfl();
2103
2104 udelay(150);
2105
2106 phy->ops.release(hw);
2107
2108 ret_val = phy->ops.get_cfg_done(hw);
2109
2110out:
2111 return ret_val;
2112}
2113
2114/**
2115 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2116 * @hw: pointer to the HW structure
2117 *
2118 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2119 **/
2120s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2121{
2122 hw_dbg("Running IGP 3 PHY init script\n");
2123
2124 /* PHY init IGP 3 */
2125 /* Enable rise/fall, 10-mode work in class-A */
2126 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2127 /* Remove all caps from Replica path filter */
2128 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2129 /* Bias trimming for ADC, AFE and Driver (Default) */
2130 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2131 /* Increase Hybrid poly bias */
2132 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2133 /* Add 4% to TX amplitude in Giga mode */
2134 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2135 /* Disable trimming (TTT) */
2136 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2137 /* Poly DC correction to 94.6% + 2% for all channels */
2138 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2139 /* ABS DC correction to 95.9% */
2140 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2141 /* BG temp curve trim */
2142 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2143 /* Increasing ADC OPAMP stage 1 currents to max */
2144 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2145 /* Force 1000 ( required for enabling PHY regs configuration) */
2146 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2147 /* Set upd_freq to 6 */
2148 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2149 /* Disable NPDFE */
2150 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2151 /* Disable adaptive fixed FFE (Default) */
2152 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2153 /* Enable FFE hysteresis */
2154 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2155 /* Fixed FFE for short cable lengths */
2156 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2157 /* Fixed FFE for medium cable lengths */
2158 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2159 /* Fixed FFE for long cable lengths */
2160 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2161 /* Enable Adaptive Clip Threshold */
2162 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2163 /* AHT reset limit to 1 */
2164 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2165 /* Set AHT master delay to 127 msec */
2166 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2167 /* Set scan bits for AHT */
2168 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2169 /* Set AHT Preset bits */
2170 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2171 /* Change integ_factor of channel A to 3 */
2172 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2173 /* Change prop_factor of channels BCD to 8 */
2174 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2175 /* Change cg_icount + enable integbp for channels BCD */
2176 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2177 /* Change cg_icount + enable integbp + change prop_factor_master
2178 * to 8 for channel A
2179 */
2180 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2181 /* Disable AHT in Slave mode on channel A */
2182 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2183 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2184 * Enable SPD+B2B
2185 */
2186 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2187 /* Enable restart AN on an1000_dis change */
2188 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2189 /* Enable wh_fifo read clock in 10/100 modes */
2190 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2191 /* Restart AN, Speed selection is 1000 */
2192 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2193
2194 return 0;
2195}
2196
2197/**
2198 * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY
2199 * @hw: pointer to the HW structure
2200 *
2201 * Initialize Marvel 1512 to work correctly with Avoton.
2202 **/
2203s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
2204{
2205 struct e1000_phy_info *phy = &hw->phy;
2206 s32 ret_val = 0;
2207
2208 /* Switch to PHY page 0xFF. */
2209 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2210 if (ret_val)
2211 goto out;
2212
2213 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2214 if (ret_val)
2215 goto out;
2216
2217 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2218 if (ret_val)
2219 goto out;
2220
2221 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2222 if (ret_val)
2223 goto out;
2224
2225 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2226 if (ret_val)
2227 goto out;
2228
2229 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2230 if (ret_val)
2231 goto out;
2232
2233 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2234 if (ret_val)
2235 goto out;
2236
2237 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2238 if (ret_val)
2239 goto out;
2240
2241 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2242 if (ret_val)
2243 goto out;
2244
2245 /* Switch to PHY page 0xFB. */
2246 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2247 if (ret_val)
2248 goto out;
2249
2250 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2251 if (ret_val)
2252 goto out;
2253
2254 /* Switch to PHY page 0x12. */
2255 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2256 if (ret_val)
2257 goto out;
2258
2259 /* Change mode to SGMII-to-Copper */
2260 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2261 if (ret_val)
2262 goto out;
2263
2264 /* Return the PHY to page 0. */
2265 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2266 if (ret_val)
2267 goto out;
2268
2269 ret_val = igb_phy_sw_reset(hw);
2270 if (ret_val) {
2271 hw_dbg("Error committing the PHY changes\n");
2272 return ret_val;
2273 }
2274
2275 /* msec_delay(1000); */
2276 usleep_range(1000, 2000);
2277out:
2278 return ret_val;
2279}
2280
2281/**
2282 * igb_initialize_M88E1543_phy - Initialize M88E1512 PHY
2283 * @hw: pointer to the HW structure
2284 *
2285 * Initialize Marvell 1543 to work correctly with Avoton.
2286 **/
2287s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw)
2288{
2289 struct e1000_phy_info *phy = &hw->phy;
2290 s32 ret_val = 0;
2291
2292 /* Switch to PHY page 0xFF. */
2293 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2294 if (ret_val)
2295 goto out;
2296
2297 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2298 if (ret_val)
2299 goto out;
2300
2301 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2302 if (ret_val)
2303 goto out;
2304
2305 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2306 if (ret_val)
2307 goto out;
2308
2309 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2310 if (ret_val)
2311 goto out;
2312
2313 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2314 if (ret_val)
2315 goto out;
2316
2317 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2318 if (ret_val)
2319 goto out;
2320
2321 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2322 if (ret_val)
2323 goto out;
2324
2325 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2326 if (ret_val)
2327 goto out;
2328
2329 /* Switch to PHY page 0xFB. */
2330 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2331 if (ret_val)
2332 goto out;
2333
2334 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D);
2335 if (ret_val)
2336 goto out;
2337
2338 /* Switch to PHY page 0x12. */
2339 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2340 if (ret_val)
2341 goto out;
2342
2343 /* Change mode to SGMII-to-Copper */
2344 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2345 if (ret_val)
2346 goto out;
2347
2348 /* Switch to PHY page 1. */
2349 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2350 if (ret_val)
2351 goto out;
2352
2353 /* Change mode to 1000BASE-X/SGMII and autoneg enable */
2354 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2355 if (ret_val)
2356 goto out;
2357
2358 /* Return the PHY to page 0. */
2359 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2360 if (ret_val)
2361 goto out;
2362
2363 ret_val = igb_phy_sw_reset(hw);
2364 if (ret_val) {
2365 hw_dbg("Error committing the PHY changes\n");
2366 return ret_val;
2367 }
2368
2369 /* msec_delay(1000); */
2370 usleep_range(1000, 2000);
2371out:
2372 return ret_val;
2373}
2374
2375/**
2376 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2377 * @hw: pointer to the HW structure
2378 *
2379 * In the case of a PHY power down to save power, or to turn off link during a
2380 * driver unload, restore the link to previous settings.
2381 **/
2382void igb_power_up_phy_copper(struct e1000_hw *hw)
2383{
2384 u16 mii_reg = 0;
2385
2386 /* The PHY will retain its settings across a power down/up cycle */
2387 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2388 mii_reg &= ~MII_CR_POWER_DOWN;
2389 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2390}
2391
2392/**
2393 * igb_power_down_phy_copper - Power down copper PHY
2394 * @hw: pointer to the HW structure
2395 *
2396 * Power down PHY to save power when interface is down and wake on lan
2397 * is not enabled.
2398 **/
2399void igb_power_down_phy_copper(struct e1000_hw *hw)
2400{
2401 u16 mii_reg = 0;
2402
2403 /* The PHY will retain its settings across a power down/up cycle */
2404 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2405 mii_reg |= MII_CR_POWER_DOWN;
2406 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2407 usleep_range(1000, 2000);
2408}
2409
2410/**
2411 * igb_check_polarity_82580 - Checks the polarity.
2412 * @hw: pointer to the HW structure
2413 *
2414 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2415 *
2416 * Polarity is determined based on the PHY specific status register.
2417 **/
2418static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2419{
2420 struct e1000_phy_info *phy = &hw->phy;
2421 s32 ret_val;
2422 u16 data;
2423
2424
2425 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2426
2427 if (!ret_val)
2428 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2429 ? e1000_rev_polarity_reversed
2430 : e1000_rev_polarity_normal;
2431
2432 return ret_val;
2433}
2434
2435/**
2436 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2437 * @hw: pointer to the HW structure
2438 *
2439 * Calls the PHY setup function to force speed and duplex. Clears the
2440 * auto-crossover to force MDI manually. Waits for link and returns
2441 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2442 **/
2443s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2444{
2445 struct e1000_phy_info *phy = &hw->phy;
2446 s32 ret_val;
2447 u16 phy_data;
2448 bool link;
2449
2450 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2451 if (ret_val)
2452 goto out;
2453
2454 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2455
2456 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2457 if (ret_val)
2458 goto out;
2459
2460 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2461 * forced whenever speed and duplex are forced.
2462 */
2463 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2464 if (ret_val)
2465 goto out;
2466
2467 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2468
2469 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2470 if (ret_val)
2471 goto out;
2472
2473 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2474
2475 udelay(1);
2476
2477 if (phy->autoneg_wait_to_complete) {
2478 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2479
2480 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2481 if (ret_val)
2482 goto out;
2483
2484 if (!link)
2485 hw_dbg("Link taking longer than expected.\n");
2486
2487 /* Try once more */
2488 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2489 if (ret_val)
2490 goto out;
2491 }
2492
2493out:
2494 return ret_val;
2495}
2496
2497/**
2498 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2499 * @hw: pointer to the HW structure
2500 *
2501 * Read PHY status to determine if link is up. If link is up, then
2502 * set/determine 10base-T extended distance and polarity correction. Read
2503 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2504 * determine on the cable length, local and remote receiver.
2505 **/
2506s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2507{
2508 struct e1000_phy_info *phy = &hw->phy;
2509 s32 ret_val;
2510 u16 data;
2511 bool link;
2512
2513 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2514 if (ret_val)
2515 goto out;
2516
2517 if (!link) {
2518 hw_dbg("Phy info is only valid if link is up\n");
2519 ret_val = -E1000_ERR_CONFIG;
2520 goto out;
2521 }
2522
2523 phy->polarity_correction = true;
2524
2525 ret_val = igb_check_polarity_82580(hw);
2526 if (ret_val)
2527 goto out;
2528
2529 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2530 if (ret_val)
2531 goto out;
2532
2533 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2534
2535 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2536 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2537 ret_val = hw->phy.ops.get_cable_length(hw);
2538 if (ret_val)
2539 goto out;
2540
2541 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2542 if (ret_val)
2543 goto out;
2544
2545 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2546 ? e1000_1000t_rx_status_ok
2547 : e1000_1000t_rx_status_not_ok;
2548
2549 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2550 ? e1000_1000t_rx_status_ok
2551 : e1000_1000t_rx_status_not_ok;
2552 } else {
2553 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2554 phy->local_rx = e1000_1000t_rx_status_undefined;
2555 phy->remote_rx = e1000_1000t_rx_status_undefined;
2556 }
2557
2558out:
2559 return ret_val;
2560}
2561
2562/**
2563 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2564 * @hw: pointer to the HW structure
2565 *
2566 * Reads the diagnostic status register and verifies result is valid before
2567 * placing it in the phy_cable_length field.
2568 **/
2569s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2570{
2571 struct e1000_phy_info *phy = &hw->phy;
2572 s32 ret_val;
2573 u16 phy_data, length;
2574
2575 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2576 if (ret_val)
2577 goto out;
2578
2579 length = FIELD_GET(I82580_DSTATUS_CABLE_LENGTH, phy_data);
2580
2581 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2582 ret_val = -E1000_ERR_PHY;
2583
2584 phy->cable_length = length;
2585
2586out:
2587 return ret_val;
2588}
2589
2590/**
2591 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2592 * @hw: pointer to the HW structure
2593 *
2594 * Sets up Master/slave mode
2595 **/
2596static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2597{
2598 s32 ret_val;
2599 u16 phy_data;
2600
2601 /* Resolve Master/Slave mode */
2602 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2603 if (ret_val)
2604 return ret_val;
2605
2606 /* load defaults for future use */
2607 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2608 ((phy_data & CR_1000T_MS_VALUE) ?
2609 e1000_ms_force_master :
2610 e1000_ms_force_slave) : e1000_ms_auto;
2611
2612 switch (hw->phy.ms_type) {
2613 case e1000_ms_force_master:
2614 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2615 break;
2616 case e1000_ms_force_slave:
2617 phy_data |= CR_1000T_MS_ENABLE;
2618 phy_data &= ~(CR_1000T_MS_VALUE);
2619 break;
2620 case e1000_ms_auto:
2621 phy_data &= ~CR_1000T_MS_ENABLE;
2622 fallthrough;
2623 default:
2624 break;
2625 }
2626
2627 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2628}
1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24#include <linux/if_ether.h>
25#include <linux/delay.h>
26
27#include "e1000_mac.h"
28#include "e1000_phy.h"
29
30static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
31static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
32 u16 *phy_ctrl);
33static s32 igb_wait_autoneg(struct e1000_hw *hw);
34static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
35
36/* Cable length tables */
37static const u16 e1000_m88_cable_length_table[] = {
38 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
39
40static const u16 e1000_igp_2_cable_length_table[] = {
41 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
42 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
43 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
44 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
45 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
46 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
47 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
48 104, 109, 114, 118, 121, 124};
49
50/**
51 * igb_check_reset_block - Check if PHY reset is blocked
52 * @hw: pointer to the HW structure
53 *
54 * Read the PHY management control register and check whether a PHY reset
55 * is blocked. If a reset is not blocked return 0, otherwise
56 * return E1000_BLK_PHY_RESET (12).
57 **/
58s32 igb_check_reset_block(struct e1000_hw *hw)
59{
60 u32 manc;
61
62 manc = rd32(E1000_MANC);
63
64 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
65}
66
67/**
68 * igb_get_phy_id - Retrieve the PHY ID and revision
69 * @hw: pointer to the HW structure
70 *
71 * Reads the PHY registers and stores the PHY ID and possibly the PHY
72 * revision in the hardware structure.
73 **/
74s32 igb_get_phy_id(struct e1000_hw *hw)
75{
76 struct e1000_phy_info *phy = &hw->phy;
77 s32 ret_val = 0;
78 u16 phy_id;
79
80 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
81 if (ret_val)
82 goto out;
83
84 phy->id = (u32)(phy_id << 16);
85 udelay(20);
86 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
87 if (ret_val)
88 goto out;
89
90 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
91 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
92
93out:
94 return ret_val;
95}
96
97/**
98 * igb_phy_reset_dsp - Reset PHY DSP
99 * @hw: pointer to the HW structure
100 *
101 * Reset the digital signal processor.
102 **/
103static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
104{
105 s32 ret_val = 0;
106
107 if (!(hw->phy.ops.write_reg))
108 goto out;
109
110 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
111 if (ret_val)
112 goto out;
113
114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
115
116out:
117 return ret_val;
118}
119
120/**
121 * igb_read_phy_reg_mdic - Read MDI control register
122 * @hw: pointer to the HW structure
123 * @offset: register offset to be read
124 * @data: pointer to the read data
125 *
126 * Reads the MDI control regsiter in the PHY at offset and stores the
127 * information read to data.
128 **/
129s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
130{
131 struct e1000_phy_info *phy = &hw->phy;
132 u32 i, mdic = 0;
133 s32 ret_val = 0;
134
135 if (offset > MAX_PHY_REG_ADDRESS) {
136 hw_dbg("PHY Address %d is out of range\n", offset);
137 ret_val = -E1000_ERR_PARAM;
138 goto out;
139 }
140
141 /* Set up Op-code, Phy Address, and register offset in the MDI
142 * Control register. The MAC will take care of interfacing with the
143 * PHY to retrieve the desired data.
144 */
145 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
146 (phy->addr << E1000_MDIC_PHY_SHIFT) |
147 (E1000_MDIC_OP_READ));
148
149 wr32(E1000_MDIC, mdic);
150
151 /* Poll the ready bit to see if the MDI read completed
152 * Increasing the time out as testing showed failures with
153 * the lower time out
154 */
155 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
156 udelay(50);
157 mdic = rd32(E1000_MDIC);
158 if (mdic & E1000_MDIC_READY)
159 break;
160 }
161 if (!(mdic & E1000_MDIC_READY)) {
162 hw_dbg("MDI Read did not complete\n");
163 ret_val = -E1000_ERR_PHY;
164 goto out;
165 }
166 if (mdic & E1000_MDIC_ERROR) {
167 hw_dbg("MDI Error\n");
168 ret_val = -E1000_ERR_PHY;
169 goto out;
170 }
171 *data = (u16) mdic;
172
173out:
174 return ret_val;
175}
176
177/**
178 * igb_write_phy_reg_mdic - Write MDI control register
179 * @hw: pointer to the HW structure
180 * @offset: register offset to write to
181 * @data: data to write to register at offset
182 *
183 * Writes data to MDI control register in the PHY at offset.
184 **/
185s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
186{
187 struct e1000_phy_info *phy = &hw->phy;
188 u32 i, mdic = 0;
189 s32 ret_val = 0;
190
191 if (offset > MAX_PHY_REG_ADDRESS) {
192 hw_dbg("PHY Address %d is out of range\n", offset);
193 ret_val = -E1000_ERR_PARAM;
194 goto out;
195 }
196
197 /* Set up Op-code, Phy Address, and register offset in the MDI
198 * Control register. The MAC will take care of interfacing with the
199 * PHY to retrieve the desired data.
200 */
201 mdic = (((u32)data) |
202 (offset << E1000_MDIC_REG_SHIFT) |
203 (phy->addr << E1000_MDIC_PHY_SHIFT) |
204 (E1000_MDIC_OP_WRITE));
205
206 wr32(E1000_MDIC, mdic);
207
208 /* Poll the ready bit to see if the MDI read completed
209 * Increasing the time out as testing showed failures with
210 * the lower time out
211 */
212 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
213 udelay(50);
214 mdic = rd32(E1000_MDIC);
215 if (mdic & E1000_MDIC_READY)
216 break;
217 }
218 if (!(mdic & E1000_MDIC_READY)) {
219 hw_dbg("MDI Write did not complete\n");
220 ret_val = -E1000_ERR_PHY;
221 goto out;
222 }
223 if (mdic & E1000_MDIC_ERROR) {
224 hw_dbg("MDI Error\n");
225 ret_val = -E1000_ERR_PHY;
226 goto out;
227 }
228
229out:
230 return ret_val;
231}
232
233/**
234 * igb_read_phy_reg_i2c - Read PHY register using i2c
235 * @hw: pointer to the HW structure
236 * @offset: register offset to be read
237 * @data: pointer to the read data
238 *
239 * Reads the PHY register at offset using the i2c interface and stores the
240 * retrieved information in data.
241 **/
242s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
243{
244 struct e1000_phy_info *phy = &hw->phy;
245 u32 i, i2ccmd = 0;
246
247 /* Set up Op-code, Phy Address, and register address in the I2CCMD
248 * register. The MAC will take care of interfacing with the
249 * PHY to retrieve the desired data.
250 */
251 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
252 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
253 (E1000_I2CCMD_OPCODE_READ));
254
255 wr32(E1000_I2CCMD, i2ccmd);
256
257 /* Poll the ready bit to see if the I2C read completed */
258 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
259 udelay(50);
260 i2ccmd = rd32(E1000_I2CCMD);
261 if (i2ccmd & E1000_I2CCMD_READY)
262 break;
263 }
264 if (!(i2ccmd & E1000_I2CCMD_READY)) {
265 hw_dbg("I2CCMD Read did not complete\n");
266 return -E1000_ERR_PHY;
267 }
268 if (i2ccmd & E1000_I2CCMD_ERROR) {
269 hw_dbg("I2CCMD Error bit set\n");
270 return -E1000_ERR_PHY;
271 }
272
273 /* Need to byte-swap the 16-bit value. */
274 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
275
276 return 0;
277}
278
279/**
280 * igb_write_phy_reg_i2c - Write PHY register using i2c
281 * @hw: pointer to the HW structure
282 * @offset: register offset to write to
283 * @data: data to write at register offset
284 *
285 * Writes the data to PHY register at the offset using the i2c interface.
286 **/
287s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
288{
289 struct e1000_phy_info *phy = &hw->phy;
290 u32 i, i2ccmd = 0;
291 u16 phy_data_swapped;
292
293 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
294 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
295 hw_dbg("PHY I2C Address %d is out of range.\n",
296 hw->phy.addr);
297 return -E1000_ERR_CONFIG;
298 }
299
300 /* Swap the data bytes for the I2C interface */
301 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
302
303 /* Set up Op-code, Phy Address, and register address in the I2CCMD
304 * register. The MAC will take care of interfacing with the
305 * PHY to retrieve the desired data.
306 */
307 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
308 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
309 E1000_I2CCMD_OPCODE_WRITE |
310 phy_data_swapped);
311
312 wr32(E1000_I2CCMD, i2ccmd);
313
314 /* Poll the ready bit to see if the I2C read completed */
315 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
316 udelay(50);
317 i2ccmd = rd32(E1000_I2CCMD);
318 if (i2ccmd & E1000_I2CCMD_READY)
319 break;
320 }
321 if (!(i2ccmd & E1000_I2CCMD_READY)) {
322 hw_dbg("I2CCMD Write did not complete\n");
323 return -E1000_ERR_PHY;
324 }
325 if (i2ccmd & E1000_I2CCMD_ERROR) {
326 hw_dbg("I2CCMD Error bit set\n");
327 return -E1000_ERR_PHY;
328 }
329
330 return 0;
331}
332
333/**
334 * igb_read_sfp_data_byte - Reads SFP module data.
335 * @hw: pointer to the HW structure
336 * @offset: byte location offset to be read
337 * @data: read data buffer pointer
338 *
339 * Reads one byte from SFP module data stored
340 * in SFP resided EEPROM memory or SFP diagnostic area.
341 * Function should be called with
342 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
343 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
344 * access
345 **/
346s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
347{
348 u32 i = 0;
349 u32 i2ccmd = 0;
350 u32 data_local = 0;
351
352 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
353 hw_dbg("I2CCMD command address exceeds upper limit\n");
354 return -E1000_ERR_PHY;
355 }
356
357 /* Set up Op-code, EEPROM Address,in the I2CCMD
358 * register. The MAC will take care of interfacing with the
359 * EEPROM to retrieve the desired data.
360 */
361 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
362 E1000_I2CCMD_OPCODE_READ);
363
364 wr32(E1000_I2CCMD, i2ccmd);
365
366 /* Poll the ready bit to see if the I2C read completed */
367 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
368 udelay(50);
369 data_local = rd32(E1000_I2CCMD);
370 if (data_local & E1000_I2CCMD_READY)
371 break;
372 }
373 if (!(data_local & E1000_I2CCMD_READY)) {
374 hw_dbg("I2CCMD Read did not complete\n");
375 return -E1000_ERR_PHY;
376 }
377 if (data_local & E1000_I2CCMD_ERROR) {
378 hw_dbg("I2CCMD Error bit set\n");
379 return -E1000_ERR_PHY;
380 }
381 *data = (u8) data_local & 0xFF;
382
383 return 0;
384}
385
386/**
387 * igb_read_phy_reg_igp - Read igp PHY register
388 * @hw: pointer to the HW structure
389 * @offset: register offset to be read
390 * @data: pointer to the read data
391 *
392 * Acquires semaphore, if necessary, then reads the PHY register at offset
393 * and storing the retrieved information in data. Release any acquired
394 * semaphores before exiting.
395 **/
396s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
397{
398 s32 ret_val = 0;
399
400 if (!(hw->phy.ops.acquire))
401 goto out;
402
403 ret_val = hw->phy.ops.acquire(hw);
404 if (ret_val)
405 goto out;
406
407 if (offset > MAX_PHY_MULTI_PAGE_REG) {
408 ret_val = igb_write_phy_reg_mdic(hw,
409 IGP01E1000_PHY_PAGE_SELECT,
410 (u16)offset);
411 if (ret_val) {
412 hw->phy.ops.release(hw);
413 goto out;
414 }
415 }
416
417 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
418 data);
419
420 hw->phy.ops.release(hw);
421
422out:
423 return ret_val;
424}
425
426/**
427 * igb_write_phy_reg_igp - Write igp PHY register
428 * @hw: pointer to the HW structure
429 * @offset: register offset to write to
430 * @data: data to write at register offset
431 *
432 * Acquires semaphore, if necessary, then writes the data to PHY register
433 * at the offset. Release any acquired semaphores before exiting.
434 **/
435s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
436{
437 s32 ret_val = 0;
438
439 if (!(hw->phy.ops.acquire))
440 goto out;
441
442 ret_val = hw->phy.ops.acquire(hw);
443 if (ret_val)
444 goto out;
445
446 if (offset > MAX_PHY_MULTI_PAGE_REG) {
447 ret_val = igb_write_phy_reg_mdic(hw,
448 IGP01E1000_PHY_PAGE_SELECT,
449 (u16)offset);
450 if (ret_val) {
451 hw->phy.ops.release(hw);
452 goto out;
453 }
454 }
455
456 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
457 data);
458
459 hw->phy.ops.release(hw);
460
461out:
462 return ret_val;
463}
464
465/**
466 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
467 * @hw: pointer to the HW structure
468 *
469 * Sets up Carrier-sense on Transmit and downshift values.
470 **/
471s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
472{
473 struct e1000_phy_info *phy = &hw->phy;
474 s32 ret_val;
475 u16 phy_data;
476
477 if (phy->reset_disable) {
478 ret_val = 0;
479 goto out;
480 }
481
482 if (phy->type == e1000_phy_82580) {
483 ret_val = hw->phy.ops.reset(hw);
484 if (ret_val) {
485 hw_dbg("Error resetting the PHY.\n");
486 goto out;
487 }
488 }
489
490 /* Enable CRS on TX. This must be set for half-duplex operation. */
491 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
492 if (ret_val)
493 goto out;
494
495 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
496
497 /* Enable downshift */
498 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
499
500 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
501 if (ret_val)
502 goto out;
503
504 /* Set MDI/MDIX mode */
505 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
506 if (ret_val)
507 goto out;
508 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
509 /* Options:
510 * 0 - Auto (default)
511 * 1 - MDI mode
512 * 2 - MDI-X mode
513 */
514 switch (hw->phy.mdix) {
515 case 1:
516 break;
517 case 2:
518 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
519 break;
520 case 0:
521 default:
522 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
523 break;
524 }
525 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
526
527out:
528 return ret_val;
529}
530
531/**
532 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
533 * @hw: pointer to the HW structure
534 *
535 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
536 * and downshift values are set also.
537 **/
538s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
539{
540 struct e1000_phy_info *phy = &hw->phy;
541 s32 ret_val;
542 u16 phy_data;
543
544 if (phy->reset_disable) {
545 ret_val = 0;
546 goto out;
547 }
548
549 /* Enable CRS on TX. This must be set for half-duplex operation. */
550 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
551 if (ret_val)
552 goto out;
553
554 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
555
556 /* Options:
557 * MDI/MDI-X = 0 (default)
558 * 0 - Auto for all speeds
559 * 1 - MDI mode
560 * 2 - MDI-X mode
561 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
562 */
563 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
564
565 switch (phy->mdix) {
566 case 1:
567 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
568 break;
569 case 2:
570 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
571 break;
572 case 3:
573 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
574 break;
575 case 0:
576 default:
577 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
578 break;
579 }
580
581 /* Options:
582 * disable_polarity_correction = 0 (default)
583 * Automatic Correction for Reversed Cable Polarity
584 * 0 - Disabled
585 * 1 - Enabled
586 */
587 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
588 if (phy->disable_polarity_correction == 1)
589 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
590
591 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
592 if (ret_val)
593 goto out;
594
595 if (phy->revision < E1000_REVISION_4) {
596 /* Force TX_CLK in the Extended PHY Specific Control Register
597 * to 25MHz clock.
598 */
599 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
600 &phy_data);
601 if (ret_val)
602 goto out;
603
604 phy_data |= M88E1000_EPSCR_TX_CLK_25;
605
606 if ((phy->revision == E1000_REVISION_2) &&
607 (phy->id == M88E1111_I_PHY_ID)) {
608 /* 82573L PHY - set the downshift counter to 5x. */
609 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
610 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
611 } else {
612 /* Configure Master and Slave downshift values */
613 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
614 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
615 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
616 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
617 }
618 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
619 phy_data);
620 if (ret_val)
621 goto out;
622 }
623
624 /* Commit the changes. */
625 ret_val = igb_phy_sw_reset(hw);
626 if (ret_val) {
627 hw_dbg("Error committing the PHY changes\n");
628 goto out;
629 }
630
631out:
632 return ret_val;
633}
634
635/**
636 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
637 * @hw: pointer to the HW structure
638 *
639 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
640 * Also enables and sets the downshift parameters.
641 **/
642s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
643{
644 struct e1000_phy_info *phy = &hw->phy;
645 s32 ret_val;
646 u16 phy_data;
647
648 if (phy->reset_disable)
649 return 0;
650
651 /* Enable CRS on Tx. This must be set for half-duplex operation. */
652 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
653 if (ret_val)
654 return ret_val;
655
656 /* Options:
657 * MDI/MDI-X = 0 (default)
658 * 0 - Auto for all speeds
659 * 1 - MDI mode
660 * 2 - MDI-X mode
661 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
662 */
663 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
664
665 switch (phy->mdix) {
666 case 1:
667 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
668 break;
669 case 2:
670 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
671 break;
672 case 3:
673 /* M88E1112 does not support this mode) */
674 if (phy->id != M88E1112_E_PHY_ID) {
675 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
676 break;
677 }
678 case 0:
679 default:
680 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
681 break;
682 }
683
684 /* Options:
685 * disable_polarity_correction = 0 (default)
686 * Automatic Correction for Reversed Cable Polarity
687 * 0 - Disabled
688 * 1 - Enabled
689 */
690 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
691 if (phy->disable_polarity_correction == 1)
692 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
693
694 /* Enable downshift and setting it to X6 */
695 if (phy->id == M88E1543_E_PHY_ID) {
696 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
697 ret_val =
698 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
699 if (ret_val)
700 return ret_val;
701
702 ret_val = igb_phy_sw_reset(hw);
703 if (ret_val) {
704 hw_dbg("Error committing the PHY changes\n");
705 return ret_val;
706 }
707 }
708
709 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
710 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
711 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
712
713 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
714 if (ret_val)
715 return ret_val;
716
717 /* Commit the changes. */
718 ret_val = igb_phy_sw_reset(hw);
719 if (ret_val) {
720 hw_dbg("Error committing the PHY changes\n");
721 return ret_val;
722 }
723 ret_val = igb_set_master_slave_mode(hw);
724 if (ret_val)
725 return ret_val;
726
727 return 0;
728}
729
730/**
731 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
732 * @hw: pointer to the HW structure
733 *
734 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
735 * igp PHY's.
736 **/
737s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
738{
739 struct e1000_phy_info *phy = &hw->phy;
740 s32 ret_val;
741 u16 data;
742
743 if (phy->reset_disable) {
744 ret_val = 0;
745 goto out;
746 }
747
748 ret_val = phy->ops.reset(hw);
749 if (ret_val) {
750 hw_dbg("Error resetting the PHY.\n");
751 goto out;
752 }
753
754 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
755 * timeout issues when LFS is enabled.
756 */
757 msleep(100);
758
759 /* The NVM settings will configure LPLU in D3 for
760 * non-IGP1 PHYs.
761 */
762 if (phy->type == e1000_phy_igp) {
763 /* disable lplu d3 during driver init */
764 if (phy->ops.set_d3_lplu_state)
765 ret_val = phy->ops.set_d3_lplu_state(hw, false);
766 if (ret_val) {
767 hw_dbg("Error Disabling LPLU D3\n");
768 goto out;
769 }
770 }
771
772 /* disable lplu d0 during driver init */
773 ret_val = phy->ops.set_d0_lplu_state(hw, false);
774 if (ret_val) {
775 hw_dbg("Error Disabling LPLU D0\n");
776 goto out;
777 }
778 /* Configure mdi-mdix settings */
779 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
780 if (ret_val)
781 goto out;
782
783 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
784
785 switch (phy->mdix) {
786 case 1:
787 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
788 break;
789 case 2:
790 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
791 break;
792 case 0:
793 default:
794 data |= IGP01E1000_PSCR_AUTO_MDIX;
795 break;
796 }
797 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
798 if (ret_val)
799 goto out;
800
801 /* set auto-master slave resolution settings */
802 if (hw->mac.autoneg) {
803 /* when autonegotiation advertisement is only 1000Mbps then we
804 * should disable SmartSpeed and enable Auto MasterSlave
805 * resolution as hardware default.
806 */
807 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
808 /* Disable SmartSpeed */
809 ret_val = phy->ops.read_reg(hw,
810 IGP01E1000_PHY_PORT_CONFIG,
811 &data);
812 if (ret_val)
813 goto out;
814
815 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
816 ret_val = phy->ops.write_reg(hw,
817 IGP01E1000_PHY_PORT_CONFIG,
818 data);
819 if (ret_val)
820 goto out;
821
822 /* Set auto Master/Slave resolution process */
823 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
824 if (ret_val)
825 goto out;
826
827 data &= ~CR_1000T_MS_ENABLE;
828 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
829 if (ret_val)
830 goto out;
831 }
832
833 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
834 if (ret_val)
835 goto out;
836
837 /* load defaults for future use */
838 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
839 ((data & CR_1000T_MS_VALUE) ?
840 e1000_ms_force_master :
841 e1000_ms_force_slave) :
842 e1000_ms_auto;
843
844 switch (phy->ms_type) {
845 case e1000_ms_force_master:
846 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
847 break;
848 case e1000_ms_force_slave:
849 data |= CR_1000T_MS_ENABLE;
850 data &= ~(CR_1000T_MS_VALUE);
851 break;
852 case e1000_ms_auto:
853 data &= ~CR_1000T_MS_ENABLE;
854 default:
855 break;
856 }
857 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
858 if (ret_val)
859 goto out;
860 }
861
862out:
863 return ret_val;
864}
865
866/**
867 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
868 * @hw: pointer to the HW structure
869 *
870 * Performs initial bounds checking on autoneg advertisement parameter, then
871 * configure to advertise the full capability. Setup the PHY to autoneg
872 * and restart the negotiation process between the link partner. If
873 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
874 **/
875static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
876{
877 struct e1000_phy_info *phy = &hw->phy;
878 s32 ret_val;
879 u16 phy_ctrl;
880
881 /* Perform some bounds checking on the autoneg advertisement
882 * parameter.
883 */
884 phy->autoneg_advertised &= phy->autoneg_mask;
885
886 /* If autoneg_advertised is zero, we assume it was not defaulted
887 * by the calling code so we set to advertise full capability.
888 */
889 if (phy->autoneg_advertised == 0)
890 phy->autoneg_advertised = phy->autoneg_mask;
891
892 hw_dbg("Reconfiguring auto-neg advertisement params\n");
893 ret_val = igb_phy_setup_autoneg(hw);
894 if (ret_val) {
895 hw_dbg("Error Setting up Auto-Negotiation\n");
896 goto out;
897 }
898 hw_dbg("Restarting Auto-Neg\n");
899
900 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
901 * the Auto Neg Restart bit in the PHY control register.
902 */
903 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
904 if (ret_val)
905 goto out;
906
907 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
908 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
909 if (ret_val)
910 goto out;
911
912 /* Does the user want to wait for Auto-Neg to complete here, or
913 * check at a later time (for example, callback routine).
914 */
915 if (phy->autoneg_wait_to_complete) {
916 ret_val = igb_wait_autoneg(hw);
917 if (ret_val) {
918 hw_dbg("Error while waiting for autoneg to complete\n");
919 goto out;
920 }
921 }
922
923 hw->mac.get_link_status = true;
924
925out:
926 return ret_val;
927}
928
929/**
930 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
931 * @hw: pointer to the HW structure
932 *
933 * Reads the MII auto-neg advertisement register and/or the 1000T control
934 * register and if the PHY is already setup for auto-negotiation, then
935 * return successful. Otherwise, setup advertisement and flow control to
936 * the appropriate values for the wanted auto-negotiation.
937 **/
938static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
939{
940 struct e1000_phy_info *phy = &hw->phy;
941 s32 ret_val;
942 u16 mii_autoneg_adv_reg;
943 u16 mii_1000t_ctrl_reg = 0;
944
945 phy->autoneg_advertised &= phy->autoneg_mask;
946
947 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
948 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
949 if (ret_val)
950 goto out;
951
952 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
953 /* Read the MII 1000Base-T Control Register (Address 9). */
954 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
955 &mii_1000t_ctrl_reg);
956 if (ret_val)
957 goto out;
958 }
959
960 /* Need to parse both autoneg_advertised and fc and set up
961 * the appropriate PHY registers. First we will parse for
962 * autoneg_advertised software override. Since we can advertise
963 * a plethora of combinations, we need to check each bit
964 * individually.
965 */
966
967 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
968 * Advertisement Register (Address 4) and the 1000 mb speed bits in
969 * the 1000Base-T Control Register (Address 9).
970 */
971 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
972 NWAY_AR_100TX_HD_CAPS |
973 NWAY_AR_10T_FD_CAPS |
974 NWAY_AR_10T_HD_CAPS);
975 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
976
977 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
978
979 /* Do we want to advertise 10 Mb Half Duplex? */
980 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
981 hw_dbg("Advertise 10mb Half duplex\n");
982 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
983 }
984
985 /* Do we want to advertise 10 Mb Full Duplex? */
986 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
987 hw_dbg("Advertise 10mb Full duplex\n");
988 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
989 }
990
991 /* Do we want to advertise 100 Mb Half Duplex? */
992 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
993 hw_dbg("Advertise 100mb Half duplex\n");
994 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
995 }
996
997 /* Do we want to advertise 100 Mb Full Duplex? */
998 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
999 hw_dbg("Advertise 100mb Full duplex\n");
1000 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1001 }
1002
1003 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1004 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1005 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1006
1007 /* Do we want to advertise 1000 Mb Full Duplex? */
1008 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1009 hw_dbg("Advertise 1000mb Full duplex\n");
1010 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1011 }
1012
1013 /* Check for a software override of the flow control settings, and
1014 * setup the PHY advertisement registers accordingly. If
1015 * auto-negotiation is enabled, then software will have to set the
1016 * "PAUSE" bits to the correct value in the Auto-Negotiation
1017 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1018 * negotiation.
1019 *
1020 * The possible values of the "fc" parameter are:
1021 * 0: Flow control is completely disabled
1022 * 1: Rx flow control is enabled (we can receive pause frames
1023 * but not send pause frames).
1024 * 2: Tx flow control is enabled (we can send pause frames
1025 * but we do not support receiving pause frames).
1026 * 3: Both Rx and TX flow control (symmetric) are enabled.
1027 * other: No software override. The flow control configuration
1028 * in the EEPROM is used.
1029 */
1030 switch (hw->fc.current_mode) {
1031 case e1000_fc_none:
1032 /* Flow control (RX & TX) is completely disabled by a
1033 * software over-ride.
1034 */
1035 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1036 break;
1037 case e1000_fc_rx_pause:
1038 /* RX Flow control is enabled, and TX Flow control is
1039 * disabled, by a software over-ride.
1040 *
1041 * Since there really isn't a way to advertise that we are
1042 * capable of RX Pause ONLY, we will advertise that we
1043 * support both symmetric and asymmetric RX PAUSE. Later
1044 * (in e1000_config_fc_after_link_up) we will disable the
1045 * hw's ability to send PAUSE frames.
1046 */
1047 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1048 break;
1049 case e1000_fc_tx_pause:
1050 /* TX Flow control is enabled, and RX Flow control is
1051 * disabled, by a software over-ride.
1052 */
1053 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1054 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1055 break;
1056 case e1000_fc_full:
1057 /* Flow control (both RX and TX) is enabled by a software
1058 * over-ride.
1059 */
1060 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1061 break;
1062 default:
1063 hw_dbg("Flow control param set incorrectly\n");
1064 ret_val = -E1000_ERR_CONFIG;
1065 goto out;
1066 }
1067
1068 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1069 if (ret_val)
1070 goto out;
1071
1072 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1073
1074 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1075 ret_val = phy->ops.write_reg(hw,
1076 PHY_1000T_CTRL,
1077 mii_1000t_ctrl_reg);
1078 if (ret_val)
1079 goto out;
1080 }
1081
1082out:
1083 return ret_val;
1084}
1085
1086/**
1087 * igb_setup_copper_link - Configure copper link settings
1088 * @hw: pointer to the HW structure
1089 *
1090 * Calls the appropriate function to configure the link for auto-neg or forced
1091 * speed and duplex. Then we check for link, once link is established calls
1092 * to configure collision distance and flow control are called. If link is
1093 * not established, we return -E1000_ERR_PHY (-2).
1094 **/
1095s32 igb_setup_copper_link(struct e1000_hw *hw)
1096{
1097 s32 ret_val;
1098 bool link;
1099
1100 if (hw->mac.autoneg) {
1101 /* Setup autoneg and flow control advertisement and perform
1102 * autonegotiation.
1103 */
1104 ret_val = igb_copper_link_autoneg(hw);
1105 if (ret_val)
1106 goto out;
1107 } else {
1108 /* PHY will be set to 10H, 10F, 100H or 100F
1109 * depending on user settings.
1110 */
1111 hw_dbg("Forcing Speed and Duplex\n");
1112 ret_val = hw->phy.ops.force_speed_duplex(hw);
1113 if (ret_val) {
1114 hw_dbg("Error Forcing Speed and Duplex\n");
1115 goto out;
1116 }
1117 }
1118
1119 /* Check link status. Wait up to 100 microseconds for link to become
1120 * valid.
1121 */
1122 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1123 if (ret_val)
1124 goto out;
1125
1126 if (link) {
1127 hw_dbg("Valid link established!!!\n");
1128 igb_config_collision_dist(hw);
1129 ret_val = igb_config_fc_after_link_up(hw);
1130 } else {
1131 hw_dbg("Unable to establish link!!!\n");
1132 }
1133
1134out:
1135 return ret_val;
1136}
1137
1138/**
1139 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1140 * @hw: pointer to the HW structure
1141 *
1142 * Calls the PHY setup function to force speed and duplex. Clears the
1143 * auto-crossover to force MDI manually. Waits for link and returns
1144 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1145 **/
1146s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1147{
1148 struct e1000_phy_info *phy = &hw->phy;
1149 s32 ret_val;
1150 u16 phy_data;
1151 bool link;
1152
1153 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1154 if (ret_val)
1155 goto out;
1156
1157 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1158
1159 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1160 if (ret_val)
1161 goto out;
1162
1163 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1164 * forced whenever speed and duplex are forced.
1165 */
1166 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1167 if (ret_val)
1168 goto out;
1169
1170 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1171 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1172
1173 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1174 if (ret_val)
1175 goto out;
1176
1177 hw_dbg("IGP PSCR: %X\n", phy_data);
1178
1179 udelay(1);
1180
1181 if (phy->autoneg_wait_to_complete) {
1182 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1183
1184 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1185 if (ret_val)
1186 goto out;
1187
1188 if (!link)
1189 hw_dbg("Link taking longer than expected.\n");
1190
1191 /* Try once more */
1192 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1193 if (ret_val)
1194 goto out;
1195 }
1196
1197out:
1198 return ret_val;
1199}
1200
1201/**
1202 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1203 * @hw: pointer to the HW structure
1204 *
1205 * Calls the PHY setup function to force speed and duplex. Clears the
1206 * auto-crossover to force MDI manually. Resets the PHY to commit the
1207 * changes. If time expires while waiting for link up, we reset the DSP.
1208 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1209 * successful completion, else return corresponding error code.
1210 **/
1211s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1212{
1213 struct e1000_phy_info *phy = &hw->phy;
1214 s32 ret_val;
1215 u16 phy_data;
1216 bool link;
1217
1218 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1219 if (phy->type != e1000_phy_i210) {
1220 /* Clear Auto-Crossover to force MDI manually. M88E1000
1221 * requires MDI forced whenever speed and duplex are forced.
1222 */
1223 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1224 &phy_data);
1225 if (ret_val)
1226 goto out;
1227
1228 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1229 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1230 phy_data);
1231 if (ret_val)
1232 goto out;
1233
1234 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1235 }
1236
1237 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1238 if (ret_val)
1239 goto out;
1240
1241 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1242
1243 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1244 if (ret_val)
1245 goto out;
1246
1247 /* Reset the phy to commit changes. */
1248 ret_val = igb_phy_sw_reset(hw);
1249 if (ret_val)
1250 goto out;
1251
1252 if (phy->autoneg_wait_to_complete) {
1253 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1254
1255 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1256 if (ret_val)
1257 goto out;
1258
1259 if (!link) {
1260 bool reset_dsp = true;
1261
1262 switch (hw->phy.id) {
1263 case I347AT4_E_PHY_ID:
1264 case M88E1112_E_PHY_ID:
1265 case M88E1543_E_PHY_ID:
1266 case M88E1512_E_PHY_ID:
1267 case I210_I_PHY_ID:
1268 reset_dsp = false;
1269 break;
1270 default:
1271 if (hw->phy.type != e1000_phy_m88)
1272 reset_dsp = false;
1273 break;
1274 }
1275 if (!reset_dsp) {
1276 hw_dbg("Link taking longer than expected.\n");
1277 } else {
1278 /* We didn't get link.
1279 * Reset the DSP and cross our fingers.
1280 */
1281 ret_val = phy->ops.write_reg(hw,
1282 M88E1000_PHY_PAGE_SELECT,
1283 0x001d);
1284 if (ret_val)
1285 goto out;
1286 ret_val = igb_phy_reset_dsp(hw);
1287 if (ret_val)
1288 goto out;
1289 }
1290 }
1291
1292 /* Try once more */
1293 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1294 100000, &link);
1295 if (ret_val)
1296 goto out;
1297 }
1298
1299 if (hw->phy.type != e1000_phy_m88 ||
1300 hw->phy.id == I347AT4_E_PHY_ID ||
1301 hw->phy.id == M88E1112_E_PHY_ID ||
1302 hw->phy.id == M88E1543_E_PHY_ID ||
1303 hw->phy.id == M88E1512_E_PHY_ID ||
1304 hw->phy.id == I210_I_PHY_ID)
1305 goto out;
1306
1307 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1308 if (ret_val)
1309 goto out;
1310
1311 /* Resetting the phy means we need to re-force TX_CLK in the
1312 * Extended PHY Specific Control Register to 25MHz clock from
1313 * the reset value of 2.5MHz.
1314 */
1315 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1316 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1317 if (ret_val)
1318 goto out;
1319
1320 /* In addition, we must re-enable CRS on Tx for both half and full
1321 * duplex.
1322 */
1323 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1324 if (ret_val)
1325 goto out;
1326
1327 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1328 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1329
1330out:
1331 return ret_val;
1332}
1333
1334/**
1335 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1336 * @hw: pointer to the HW structure
1337 * @phy_ctrl: pointer to current value of PHY_CONTROL
1338 *
1339 * Forces speed and duplex on the PHY by doing the following: disable flow
1340 * control, force speed/duplex on the MAC, disable auto speed detection,
1341 * disable auto-negotiation, configure duplex, configure speed, configure
1342 * the collision distance, write configuration to CTRL register. The
1343 * caller must write to the PHY_CONTROL register for these settings to
1344 * take affect.
1345 **/
1346static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1347 u16 *phy_ctrl)
1348{
1349 struct e1000_mac_info *mac = &hw->mac;
1350 u32 ctrl;
1351
1352 /* Turn off flow control when forcing speed/duplex */
1353 hw->fc.current_mode = e1000_fc_none;
1354
1355 /* Force speed/duplex on the mac */
1356 ctrl = rd32(E1000_CTRL);
1357 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1358 ctrl &= ~E1000_CTRL_SPD_SEL;
1359
1360 /* Disable Auto Speed Detection */
1361 ctrl &= ~E1000_CTRL_ASDE;
1362
1363 /* Disable autoneg on the phy */
1364 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1365
1366 /* Forcing Full or Half Duplex? */
1367 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1368 ctrl &= ~E1000_CTRL_FD;
1369 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1370 hw_dbg("Half Duplex\n");
1371 } else {
1372 ctrl |= E1000_CTRL_FD;
1373 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1374 hw_dbg("Full Duplex\n");
1375 }
1376
1377 /* Forcing 10mb or 100mb? */
1378 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1379 ctrl |= E1000_CTRL_SPD_100;
1380 *phy_ctrl |= MII_CR_SPEED_100;
1381 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1382 hw_dbg("Forcing 100mb\n");
1383 } else {
1384 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1385 *phy_ctrl |= MII_CR_SPEED_10;
1386 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1387 hw_dbg("Forcing 10mb\n");
1388 }
1389
1390 igb_config_collision_dist(hw);
1391
1392 wr32(E1000_CTRL, ctrl);
1393}
1394
1395/**
1396 * igb_set_d3_lplu_state - Sets low power link up state for D3
1397 * @hw: pointer to the HW structure
1398 * @active: boolean used to enable/disable lplu
1399 *
1400 * Success returns 0, Failure returns 1
1401 *
1402 * The low power link up (lplu) state is set to the power management level D3
1403 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1404 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1405 * is used during Dx states where the power conservation is most important.
1406 * During driver activity, SmartSpeed should be enabled so performance is
1407 * maintained.
1408 **/
1409s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1410{
1411 struct e1000_phy_info *phy = &hw->phy;
1412 s32 ret_val = 0;
1413 u16 data;
1414
1415 if (!(hw->phy.ops.read_reg))
1416 goto out;
1417
1418 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1419 if (ret_val)
1420 goto out;
1421
1422 if (!active) {
1423 data &= ~IGP02E1000_PM_D3_LPLU;
1424 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1425 data);
1426 if (ret_val)
1427 goto out;
1428 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1429 * during Dx states where the power conservation is most
1430 * important. During driver activity we should enable
1431 * SmartSpeed, so performance is maintained.
1432 */
1433 if (phy->smart_speed == e1000_smart_speed_on) {
1434 ret_val = phy->ops.read_reg(hw,
1435 IGP01E1000_PHY_PORT_CONFIG,
1436 &data);
1437 if (ret_val)
1438 goto out;
1439
1440 data |= IGP01E1000_PSCFR_SMART_SPEED;
1441 ret_val = phy->ops.write_reg(hw,
1442 IGP01E1000_PHY_PORT_CONFIG,
1443 data);
1444 if (ret_val)
1445 goto out;
1446 } else if (phy->smart_speed == e1000_smart_speed_off) {
1447 ret_val = phy->ops.read_reg(hw,
1448 IGP01E1000_PHY_PORT_CONFIG,
1449 &data);
1450 if (ret_val)
1451 goto out;
1452
1453 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1454 ret_val = phy->ops.write_reg(hw,
1455 IGP01E1000_PHY_PORT_CONFIG,
1456 data);
1457 if (ret_val)
1458 goto out;
1459 }
1460 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1461 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1462 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1463 data |= IGP02E1000_PM_D3_LPLU;
1464 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1465 data);
1466 if (ret_val)
1467 goto out;
1468
1469 /* When LPLU is enabled, we should disable SmartSpeed */
1470 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1471 &data);
1472 if (ret_val)
1473 goto out;
1474
1475 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1476 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1477 data);
1478 }
1479
1480out:
1481 return ret_val;
1482}
1483
1484/**
1485 * igb_check_downshift - Checks whether a downshift in speed occurred
1486 * @hw: pointer to the HW structure
1487 *
1488 * Success returns 0, Failure returns 1
1489 *
1490 * A downshift is detected by querying the PHY link health.
1491 **/
1492s32 igb_check_downshift(struct e1000_hw *hw)
1493{
1494 struct e1000_phy_info *phy = &hw->phy;
1495 s32 ret_val;
1496 u16 phy_data, offset, mask;
1497
1498 switch (phy->type) {
1499 case e1000_phy_i210:
1500 case e1000_phy_m88:
1501 case e1000_phy_gg82563:
1502 offset = M88E1000_PHY_SPEC_STATUS;
1503 mask = M88E1000_PSSR_DOWNSHIFT;
1504 break;
1505 case e1000_phy_igp_2:
1506 case e1000_phy_igp:
1507 case e1000_phy_igp_3:
1508 offset = IGP01E1000_PHY_LINK_HEALTH;
1509 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1510 break;
1511 default:
1512 /* speed downshift not supported */
1513 phy->speed_downgraded = false;
1514 ret_val = 0;
1515 goto out;
1516 }
1517
1518 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1519
1520 if (!ret_val)
1521 phy->speed_downgraded = (phy_data & mask) ? true : false;
1522
1523out:
1524 return ret_val;
1525}
1526
1527/**
1528 * igb_check_polarity_m88 - Checks the polarity.
1529 * @hw: pointer to the HW structure
1530 *
1531 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1532 *
1533 * Polarity is determined based on the PHY specific status register.
1534 **/
1535s32 igb_check_polarity_m88(struct e1000_hw *hw)
1536{
1537 struct e1000_phy_info *phy = &hw->phy;
1538 s32 ret_val;
1539 u16 data;
1540
1541 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1542
1543 if (!ret_val)
1544 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1545 ? e1000_rev_polarity_reversed
1546 : e1000_rev_polarity_normal;
1547
1548 return ret_val;
1549}
1550
1551/**
1552 * igb_check_polarity_igp - Checks the polarity.
1553 * @hw: pointer to the HW structure
1554 *
1555 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1556 *
1557 * Polarity is determined based on the PHY port status register, and the
1558 * current speed (since there is no polarity at 100Mbps).
1559 **/
1560static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1561{
1562 struct e1000_phy_info *phy = &hw->phy;
1563 s32 ret_val;
1564 u16 data, offset, mask;
1565
1566 /* Polarity is determined based on the speed of
1567 * our connection.
1568 */
1569 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1570 if (ret_val)
1571 goto out;
1572
1573 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1574 IGP01E1000_PSSR_SPEED_1000MBPS) {
1575 offset = IGP01E1000_PHY_PCS_INIT_REG;
1576 mask = IGP01E1000_PHY_POLARITY_MASK;
1577 } else {
1578 /* This really only applies to 10Mbps since
1579 * there is no polarity for 100Mbps (always 0).
1580 */
1581 offset = IGP01E1000_PHY_PORT_STATUS;
1582 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1583 }
1584
1585 ret_val = phy->ops.read_reg(hw, offset, &data);
1586
1587 if (!ret_val)
1588 phy->cable_polarity = (data & mask)
1589 ? e1000_rev_polarity_reversed
1590 : e1000_rev_polarity_normal;
1591
1592out:
1593 return ret_val;
1594}
1595
1596/**
1597 * igb_wait_autoneg - Wait for auto-neg completion
1598 * @hw: pointer to the HW structure
1599 *
1600 * Waits for auto-negotiation to complete or for the auto-negotiation time
1601 * limit to expire, which ever happens first.
1602 **/
1603static s32 igb_wait_autoneg(struct e1000_hw *hw)
1604{
1605 s32 ret_val = 0;
1606 u16 i, phy_status;
1607
1608 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1609 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1610 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1611 if (ret_val)
1612 break;
1613 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1614 if (ret_val)
1615 break;
1616 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1617 break;
1618 msleep(100);
1619 }
1620
1621 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1622 * has completed.
1623 */
1624 return ret_val;
1625}
1626
1627/**
1628 * igb_phy_has_link - Polls PHY for link
1629 * @hw: pointer to the HW structure
1630 * @iterations: number of times to poll for link
1631 * @usec_interval: delay between polling attempts
1632 * @success: pointer to whether polling was successful or not
1633 *
1634 * Polls the PHY status register for link, 'iterations' number of times.
1635 **/
1636s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1637 u32 usec_interval, bool *success)
1638{
1639 s32 ret_val = 0;
1640 u16 i, phy_status;
1641
1642 for (i = 0; i < iterations; i++) {
1643 /* Some PHYs require the PHY_STATUS register to be read
1644 * twice due to the link bit being sticky. No harm doing
1645 * it across the board.
1646 */
1647 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1648 if (ret_val && usec_interval > 0) {
1649 /* If the first read fails, another entity may have
1650 * ownership of the resources, wait and try again to
1651 * see if they have relinquished the resources yet.
1652 */
1653 if (usec_interval >= 1000)
1654 mdelay(usec_interval/1000);
1655 else
1656 udelay(usec_interval);
1657 }
1658 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1659 if (ret_val)
1660 break;
1661 if (phy_status & MII_SR_LINK_STATUS)
1662 break;
1663 if (usec_interval >= 1000)
1664 mdelay(usec_interval/1000);
1665 else
1666 udelay(usec_interval);
1667 }
1668
1669 *success = (i < iterations) ? true : false;
1670
1671 return ret_val;
1672}
1673
1674/**
1675 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1676 * @hw: pointer to the HW structure
1677 *
1678 * Reads the PHY specific status register to retrieve the cable length
1679 * information. The cable length is determined by averaging the minimum and
1680 * maximum values to get the "average" cable length. The m88 PHY has four
1681 * possible cable length values, which are:
1682 * Register Value Cable Length
1683 * 0 < 50 meters
1684 * 1 50 - 80 meters
1685 * 2 80 - 110 meters
1686 * 3 110 - 140 meters
1687 * 4 > 140 meters
1688 **/
1689s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1690{
1691 struct e1000_phy_info *phy = &hw->phy;
1692 s32 ret_val;
1693 u16 phy_data, index;
1694
1695 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1696 if (ret_val)
1697 goto out;
1698
1699 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1700 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1701 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1702 ret_val = -E1000_ERR_PHY;
1703 goto out;
1704 }
1705
1706 phy->min_cable_length = e1000_m88_cable_length_table[index];
1707 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1708
1709 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1710
1711out:
1712 return ret_val;
1713}
1714
1715s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1716{
1717 struct e1000_phy_info *phy = &hw->phy;
1718 s32 ret_val;
1719 u16 phy_data, phy_data2, index, default_page, is_cm;
1720 int len_tot = 0;
1721 u16 len_min;
1722 u16 len_max;
1723
1724 switch (hw->phy.id) {
1725 case M88E1543_E_PHY_ID:
1726 case M88E1512_E_PHY_ID:
1727 case I347AT4_E_PHY_ID:
1728 case I210_I_PHY_ID:
1729 /* Remember the original page select and set it to 7 */
1730 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1731 &default_page);
1732 if (ret_val)
1733 goto out;
1734
1735 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1736 if (ret_val)
1737 goto out;
1738
1739 /* Check if the unit of cable length is meters or cm */
1740 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1741 if (ret_val)
1742 goto out;
1743
1744 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1745
1746 /* Get cable length from Pair 0 length Regs */
1747 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL0, &phy_data);
1748 if (ret_val)
1749 goto out;
1750
1751 phy->pair_length[0] = phy_data / (is_cm ? 100 : 1);
1752 len_tot = phy->pair_length[0];
1753 len_min = phy->pair_length[0];
1754 len_max = phy->pair_length[0];
1755
1756 /* Get cable length from Pair 1 length Regs */
1757 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL1, &phy_data);
1758 if (ret_val)
1759 goto out;
1760
1761 phy->pair_length[1] = phy_data / (is_cm ? 100 : 1);
1762 len_tot += phy->pair_length[1];
1763 len_min = min(len_min, phy->pair_length[1]);
1764 len_max = max(len_max, phy->pair_length[1]);
1765
1766 /* Get cable length from Pair 2 length Regs */
1767 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL2, &phy_data);
1768 if (ret_val)
1769 goto out;
1770
1771 phy->pair_length[2] = phy_data / (is_cm ? 100 : 1);
1772 len_tot += phy->pair_length[2];
1773 len_min = min(len_min, phy->pair_length[2]);
1774 len_max = max(len_max, phy->pair_length[2]);
1775
1776 /* Get cable length from Pair 3 length Regs */
1777 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL3, &phy_data);
1778 if (ret_val)
1779 goto out;
1780
1781 phy->pair_length[3] = phy_data / (is_cm ? 100 : 1);
1782 len_tot += phy->pair_length[3];
1783 len_min = min(len_min, phy->pair_length[3]);
1784 len_max = max(len_max, phy->pair_length[3]);
1785
1786 /* Populate the phy structure with cable length in meters */
1787 phy->min_cable_length = len_min;
1788 phy->max_cable_length = len_max;
1789 phy->cable_length = len_tot / 4;
1790
1791 /* Reset the page selec to its original value */
1792 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1793 default_page);
1794 if (ret_val)
1795 goto out;
1796 break;
1797 case M88E1112_E_PHY_ID:
1798 /* Remember the original page select and set it to 5 */
1799 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1800 &default_page);
1801 if (ret_val)
1802 goto out;
1803
1804 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1805 if (ret_val)
1806 goto out;
1807
1808 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1809 &phy_data);
1810 if (ret_val)
1811 goto out;
1812
1813 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1814 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1815 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1816 ret_val = -E1000_ERR_PHY;
1817 goto out;
1818 }
1819
1820 phy->min_cable_length = e1000_m88_cable_length_table[index];
1821 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1822
1823 phy->cable_length = (phy->min_cable_length +
1824 phy->max_cable_length) / 2;
1825
1826 /* Reset the page select to its original value */
1827 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1828 default_page);
1829 if (ret_val)
1830 goto out;
1831
1832 break;
1833 default:
1834 ret_val = -E1000_ERR_PHY;
1835 goto out;
1836 }
1837
1838out:
1839 return ret_val;
1840}
1841
1842/**
1843 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1844 * @hw: pointer to the HW structure
1845 *
1846 * The automatic gain control (agc) normalizes the amplitude of the
1847 * received signal, adjusting for the attenuation produced by the
1848 * cable. By reading the AGC registers, which represent the
1849 * combination of coarse and fine gain value, the value can be put
1850 * into a lookup table to obtain the approximate cable length
1851 * for each channel.
1852 **/
1853s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1854{
1855 struct e1000_phy_info *phy = &hw->phy;
1856 s32 ret_val = 0;
1857 u16 phy_data, i, agc_value = 0;
1858 u16 cur_agc_index, max_agc_index = 0;
1859 u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1;
1860 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1861 IGP02E1000_PHY_AGC_A,
1862 IGP02E1000_PHY_AGC_B,
1863 IGP02E1000_PHY_AGC_C,
1864 IGP02E1000_PHY_AGC_D
1865 };
1866
1867 /* Read the AGC registers for all channels */
1868 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1869 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1870 if (ret_val)
1871 goto out;
1872
1873 /* Getting bits 15:9, which represent the combination of
1874 * coarse and fine gain values. The result is a number
1875 * that can be put into the lookup table to obtain the
1876 * approximate cable length.
1877 */
1878 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1879 IGP02E1000_AGC_LENGTH_MASK;
1880
1881 /* Array index bound check. */
1882 if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) ||
1883 (cur_agc_index == 0)) {
1884 ret_val = -E1000_ERR_PHY;
1885 goto out;
1886 }
1887
1888 /* Remove min & max AGC values from calculation. */
1889 if (e1000_igp_2_cable_length_table[min_agc_index] >
1890 e1000_igp_2_cable_length_table[cur_agc_index])
1891 min_agc_index = cur_agc_index;
1892 if (e1000_igp_2_cable_length_table[max_agc_index] <
1893 e1000_igp_2_cable_length_table[cur_agc_index])
1894 max_agc_index = cur_agc_index;
1895
1896 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1897 }
1898
1899 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1900 e1000_igp_2_cable_length_table[max_agc_index]);
1901 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1902
1903 /* Calculate cable length with the error range of +/- 10 meters. */
1904 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1905 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1906 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1907
1908 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1909
1910out:
1911 return ret_val;
1912}
1913
1914/**
1915 * igb_get_phy_info_m88 - Retrieve PHY information
1916 * @hw: pointer to the HW structure
1917 *
1918 * Valid for only copper links. Read the PHY status register (sticky read)
1919 * to verify that link is up. Read the PHY special control register to
1920 * determine the polarity and 10base-T extended distance. Read the PHY
1921 * special status register to determine MDI/MDIx and current speed. If
1922 * speed is 1000, then determine cable length, local and remote receiver.
1923 **/
1924s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1925{
1926 struct e1000_phy_info *phy = &hw->phy;
1927 s32 ret_val;
1928 u16 phy_data;
1929 bool link;
1930
1931 if (phy->media_type != e1000_media_type_copper) {
1932 hw_dbg("Phy info is only valid for copper media\n");
1933 ret_val = -E1000_ERR_CONFIG;
1934 goto out;
1935 }
1936
1937 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1938 if (ret_val)
1939 goto out;
1940
1941 if (!link) {
1942 hw_dbg("Phy info is only valid if link is up\n");
1943 ret_val = -E1000_ERR_CONFIG;
1944 goto out;
1945 }
1946
1947 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1948 if (ret_val)
1949 goto out;
1950
1951 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1952 ? true : false;
1953
1954 ret_val = igb_check_polarity_m88(hw);
1955 if (ret_val)
1956 goto out;
1957
1958 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1959 if (ret_val)
1960 goto out;
1961
1962 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1963
1964 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1965 ret_val = phy->ops.get_cable_length(hw);
1966 if (ret_val)
1967 goto out;
1968
1969 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1970 if (ret_val)
1971 goto out;
1972
1973 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1974 ? e1000_1000t_rx_status_ok
1975 : e1000_1000t_rx_status_not_ok;
1976
1977 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1978 ? e1000_1000t_rx_status_ok
1979 : e1000_1000t_rx_status_not_ok;
1980 } else {
1981 /* Set values to "undefined" */
1982 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1983 phy->local_rx = e1000_1000t_rx_status_undefined;
1984 phy->remote_rx = e1000_1000t_rx_status_undefined;
1985 }
1986
1987out:
1988 return ret_val;
1989}
1990
1991/**
1992 * igb_get_phy_info_igp - Retrieve igp PHY information
1993 * @hw: pointer to the HW structure
1994 *
1995 * Read PHY status to determine if link is up. If link is up, then
1996 * set/determine 10base-T extended distance and polarity correction. Read
1997 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1998 * determine on the cable length, local and remote receiver.
1999 **/
2000s32 igb_get_phy_info_igp(struct e1000_hw *hw)
2001{
2002 struct e1000_phy_info *phy = &hw->phy;
2003 s32 ret_val;
2004 u16 data;
2005 bool link;
2006
2007 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2008 if (ret_val)
2009 goto out;
2010
2011 if (!link) {
2012 hw_dbg("Phy info is only valid if link is up\n");
2013 ret_val = -E1000_ERR_CONFIG;
2014 goto out;
2015 }
2016
2017 phy->polarity_correction = true;
2018
2019 ret_val = igb_check_polarity_igp(hw);
2020 if (ret_val)
2021 goto out;
2022
2023 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2024 if (ret_val)
2025 goto out;
2026
2027 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2028
2029 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2030 IGP01E1000_PSSR_SPEED_1000MBPS) {
2031 ret_val = phy->ops.get_cable_length(hw);
2032 if (ret_val)
2033 goto out;
2034
2035 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2036 if (ret_val)
2037 goto out;
2038
2039 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2040 ? e1000_1000t_rx_status_ok
2041 : e1000_1000t_rx_status_not_ok;
2042
2043 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2044 ? e1000_1000t_rx_status_ok
2045 : e1000_1000t_rx_status_not_ok;
2046 } else {
2047 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2048 phy->local_rx = e1000_1000t_rx_status_undefined;
2049 phy->remote_rx = e1000_1000t_rx_status_undefined;
2050 }
2051
2052out:
2053 return ret_val;
2054}
2055
2056/**
2057 * igb_phy_sw_reset - PHY software reset
2058 * @hw: pointer to the HW structure
2059 *
2060 * Does a software reset of the PHY by reading the PHY control register and
2061 * setting/write the control register reset bit to the PHY.
2062 **/
2063s32 igb_phy_sw_reset(struct e1000_hw *hw)
2064{
2065 s32 ret_val = 0;
2066 u16 phy_ctrl;
2067
2068 if (!(hw->phy.ops.read_reg))
2069 goto out;
2070
2071 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2072 if (ret_val)
2073 goto out;
2074
2075 phy_ctrl |= MII_CR_RESET;
2076 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2077 if (ret_val)
2078 goto out;
2079
2080 udelay(1);
2081
2082out:
2083 return ret_val;
2084}
2085
2086/**
2087 * igb_phy_hw_reset - PHY hardware reset
2088 * @hw: pointer to the HW structure
2089 *
2090 * Verify the reset block is not blocking us from resetting. Acquire
2091 * semaphore (if necessary) and read/set/write the device control reset
2092 * bit in the PHY. Wait the appropriate delay time for the device to
2093 * reset and release the semaphore (if necessary).
2094 **/
2095s32 igb_phy_hw_reset(struct e1000_hw *hw)
2096{
2097 struct e1000_phy_info *phy = &hw->phy;
2098 s32 ret_val;
2099 u32 ctrl;
2100
2101 ret_val = igb_check_reset_block(hw);
2102 if (ret_val) {
2103 ret_val = 0;
2104 goto out;
2105 }
2106
2107 ret_val = phy->ops.acquire(hw);
2108 if (ret_val)
2109 goto out;
2110
2111 ctrl = rd32(E1000_CTRL);
2112 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2113 wrfl();
2114
2115 udelay(phy->reset_delay_us);
2116
2117 wr32(E1000_CTRL, ctrl);
2118 wrfl();
2119
2120 udelay(150);
2121
2122 phy->ops.release(hw);
2123
2124 ret_val = phy->ops.get_cfg_done(hw);
2125
2126out:
2127 return ret_val;
2128}
2129
2130/**
2131 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2132 * @hw: pointer to the HW structure
2133 *
2134 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2135 **/
2136s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2137{
2138 hw_dbg("Running IGP 3 PHY init script\n");
2139
2140 /* PHY init IGP 3 */
2141 /* Enable rise/fall, 10-mode work in class-A */
2142 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2143 /* Remove all caps from Replica path filter */
2144 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2145 /* Bias trimming for ADC, AFE and Driver (Default) */
2146 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2147 /* Increase Hybrid poly bias */
2148 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2149 /* Add 4% to TX amplitude in Giga mode */
2150 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2151 /* Disable trimming (TTT) */
2152 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2153 /* Poly DC correction to 94.6% + 2% for all channels */
2154 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2155 /* ABS DC correction to 95.9% */
2156 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2157 /* BG temp curve trim */
2158 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2159 /* Increasing ADC OPAMP stage 1 currents to max */
2160 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2161 /* Force 1000 ( required for enabling PHY regs configuration) */
2162 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2163 /* Set upd_freq to 6 */
2164 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2165 /* Disable NPDFE */
2166 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2167 /* Disable adaptive fixed FFE (Default) */
2168 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2169 /* Enable FFE hysteresis */
2170 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2171 /* Fixed FFE for short cable lengths */
2172 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2173 /* Fixed FFE for medium cable lengths */
2174 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2175 /* Fixed FFE for long cable lengths */
2176 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2177 /* Enable Adaptive Clip Threshold */
2178 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2179 /* AHT reset limit to 1 */
2180 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2181 /* Set AHT master delay to 127 msec */
2182 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2183 /* Set scan bits for AHT */
2184 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2185 /* Set AHT Preset bits */
2186 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2187 /* Change integ_factor of channel A to 3 */
2188 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2189 /* Change prop_factor of channels BCD to 8 */
2190 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2191 /* Change cg_icount + enable integbp for channels BCD */
2192 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2193 /* Change cg_icount + enable integbp + change prop_factor_master
2194 * to 8 for channel A
2195 */
2196 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2197 /* Disable AHT in Slave mode on channel A */
2198 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2199 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2200 * Enable SPD+B2B
2201 */
2202 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2203 /* Enable restart AN on an1000_dis change */
2204 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2205 /* Enable wh_fifo read clock in 10/100 modes */
2206 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2207 /* Restart AN, Speed selection is 1000 */
2208 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2209
2210 return 0;
2211}
2212
2213/**
2214 * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY
2215 * @hw: pointer to the HW structure
2216 *
2217 * Initialize Marvel 1512 to work correctly with Avoton.
2218 **/
2219s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
2220{
2221 struct e1000_phy_info *phy = &hw->phy;
2222 s32 ret_val = 0;
2223
2224 /* Switch to PHY page 0xFF. */
2225 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2226 if (ret_val)
2227 goto out;
2228
2229 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2230 if (ret_val)
2231 goto out;
2232
2233 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2234 if (ret_val)
2235 goto out;
2236
2237 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2238 if (ret_val)
2239 goto out;
2240
2241 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2242 if (ret_val)
2243 goto out;
2244
2245 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2246 if (ret_val)
2247 goto out;
2248
2249 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2250 if (ret_val)
2251 goto out;
2252
2253 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2254 if (ret_val)
2255 goto out;
2256
2257 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2258 if (ret_val)
2259 goto out;
2260
2261 /* Switch to PHY page 0xFB. */
2262 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2263 if (ret_val)
2264 goto out;
2265
2266 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2267 if (ret_val)
2268 goto out;
2269
2270 /* Switch to PHY page 0x12. */
2271 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2272 if (ret_val)
2273 goto out;
2274
2275 /* Change mode to SGMII-to-Copper */
2276 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2277 if (ret_val)
2278 goto out;
2279
2280 /* Return the PHY to page 0. */
2281 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2282 if (ret_val)
2283 goto out;
2284
2285 ret_val = igb_phy_sw_reset(hw);
2286 if (ret_val) {
2287 hw_dbg("Error committing the PHY changes\n");
2288 return ret_val;
2289 }
2290
2291 /* msec_delay(1000); */
2292 usleep_range(1000, 2000);
2293out:
2294 return ret_val;
2295}
2296
2297/**
2298 * igb_initialize_M88E1543_phy - Initialize M88E1512 PHY
2299 * @hw: pointer to the HW structure
2300 *
2301 * Initialize Marvell 1543 to work correctly with Avoton.
2302 **/
2303s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw)
2304{
2305 struct e1000_phy_info *phy = &hw->phy;
2306 s32 ret_val = 0;
2307
2308 /* Switch to PHY page 0xFF. */
2309 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2310 if (ret_val)
2311 goto out;
2312
2313 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2314 if (ret_val)
2315 goto out;
2316
2317 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2318 if (ret_val)
2319 goto out;
2320
2321 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2322 if (ret_val)
2323 goto out;
2324
2325 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2326 if (ret_val)
2327 goto out;
2328
2329 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2330 if (ret_val)
2331 goto out;
2332
2333 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2334 if (ret_val)
2335 goto out;
2336
2337 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2338 if (ret_val)
2339 goto out;
2340
2341 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2342 if (ret_val)
2343 goto out;
2344
2345 /* Switch to PHY page 0xFB. */
2346 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2347 if (ret_val)
2348 goto out;
2349
2350 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D);
2351 if (ret_val)
2352 goto out;
2353
2354 /* Switch to PHY page 0x12. */
2355 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2356 if (ret_val)
2357 goto out;
2358
2359 /* Change mode to SGMII-to-Copper */
2360 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2361 if (ret_val)
2362 goto out;
2363
2364 /* Switch to PHY page 1. */
2365 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2366 if (ret_val)
2367 goto out;
2368
2369 /* Change mode to 1000BASE-X/SGMII and autoneg enable */
2370 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2371 if (ret_val)
2372 goto out;
2373
2374 /* Return the PHY to page 0. */
2375 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2376 if (ret_val)
2377 goto out;
2378
2379 ret_val = igb_phy_sw_reset(hw);
2380 if (ret_val) {
2381 hw_dbg("Error committing the PHY changes\n");
2382 return ret_val;
2383 }
2384
2385 /* msec_delay(1000); */
2386 usleep_range(1000, 2000);
2387out:
2388 return ret_val;
2389}
2390
2391/**
2392 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2393 * @hw: pointer to the HW structure
2394 *
2395 * In the case of a PHY power down to save power, or to turn off link during a
2396 * driver unload, restore the link to previous settings.
2397 **/
2398void igb_power_up_phy_copper(struct e1000_hw *hw)
2399{
2400 u16 mii_reg = 0;
2401
2402 /* The PHY will retain its settings across a power down/up cycle */
2403 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2404 mii_reg &= ~MII_CR_POWER_DOWN;
2405 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2406}
2407
2408/**
2409 * igb_power_down_phy_copper - Power down copper PHY
2410 * @hw: pointer to the HW structure
2411 *
2412 * Power down PHY to save power when interface is down and wake on lan
2413 * is not enabled.
2414 **/
2415void igb_power_down_phy_copper(struct e1000_hw *hw)
2416{
2417 u16 mii_reg = 0;
2418
2419 /* The PHY will retain its settings across a power down/up cycle */
2420 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2421 mii_reg |= MII_CR_POWER_DOWN;
2422 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2423 usleep_range(1000, 2000);
2424}
2425
2426/**
2427 * igb_check_polarity_82580 - Checks the polarity.
2428 * @hw: pointer to the HW structure
2429 *
2430 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2431 *
2432 * Polarity is determined based on the PHY specific status register.
2433 **/
2434static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2435{
2436 struct e1000_phy_info *phy = &hw->phy;
2437 s32 ret_val;
2438 u16 data;
2439
2440
2441 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2442
2443 if (!ret_val)
2444 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2445 ? e1000_rev_polarity_reversed
2446 : e1000_rev_polarity_normal;
2447
2448 return ret_val;
2449}
2450
2451/**
2452 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2453 * @hw: pointer to the HW structure
2454 *
2455 * Calls the PHY setup function to force speed and duplex. Clears the
2456 * auto-crossover to force MDI manually. Waits for link and returns
2457 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2458 **/
2459s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2460{
2461 struct e1000_phy_info *phy = &hw->phy;
2462 s32 ret_val;
2463 u16 phy_data;
2464 bool link;
2465
2466 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2467 if (ret_val)
2468 goto out;
2469
2470 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2471
2472 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2473 if (ret_val)
2474 goto out;
2475
2476 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2477 * forced whenever speed and duplex are forced.
2478 */
2479 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2480 if (ret_val)
2481 goto out;
2482
2483 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2484
2485 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2486 if (ret_val)
2487 goto out;
2488
2489 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2490
2491 udelay(1);
2492
2493 if (phy->autoneg_wait_to_complete) {
2494 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2495
2496 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2497 if (ret_val)
2498 goto out;
2499
2500 if (!link)
2501 hw_dbg("Link taking longer than expected.\n");
2502
2503 /* Try once more */
2504 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2505 if (ret_val)
2506 goto out;
2507 }
2508
2509out:
2510 return ret_val;
2511}
2512
2513/**
2514 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2515 * @hw: pointer to the HW structure
2516 *
2517 * Read PHY status to determine if link is up. If link is up, then
2518 * set/determine 10base-T extended distance and polarity correction. Read
2519 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2520 * determine on the cable length, local and remote receiver.
2521 **/
2522s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2523{
2524 struct e1000_phy_info *phy = &hw->phy;
2525 s32 ret_val;
2526 u16 data;
2527 bool link;
2528
2529 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2530 if (ret_val)
2531 goto out;
2532
2533 if (!link) {
2534 hw_dbg("Phy info is only valid if link is up\n");
2535 ret_val = -E1000_ERR_CONFIG;
2536 goto out;
2537 }
2538
2539 phy->polarity_correction = true;
2540
2541 ret_val = igb_check_polarity_82580(hw);
2542 if (ret_val)
2543 goto out;
2544
2545 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2546 if (ret_val)
2547 goto out;
2548
2549 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2550
2551 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2552 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2553 ret_val = hw->phy.ops.get_cable_length(hw);
2554 if (ret_val)
2555 goto out;
2556
2557 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2558 if (ret_val)
2559 goto out;
2560
2561 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2562 ? e1000_1000t_rx_status_ok
2563 : e1000_1000t_rx_status_not_ok;
2564
2565 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2566 ? e1000_1000t_rx_status_ok
2567 : e1000_1000t_rx_status_not_ok;
2568 } else {
2569 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2570 phy->local_rx = e1000_1000t_rx_status_undefined;
2571 phy->remote_rx = e1000_1000t_rx_status_undefined;
2572 }
2573
2574out:
2575 return ret_val;
2576}
2577
2578/**
2579 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2580 * @hw: pointer to the HW structure
2581 *
2582 * Reads the diagnostic status register and verifies result is valid before
2583 * placing it in the phy_cable_length field.
2584 **/
2585s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2586{
2587 struct e1000_phy_info *phy = &hw->phy;
2588 s32 ret_val;
2589 u16 phy_data, length;
2590
2591 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2592 if (ret_val)
2593 goto out;
2594
2595 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2596 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2597
2598 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2599 ret_val = -E1000_ERR_PHY;
2600
2601 phy->cable_length = length;
2602
2603out:
2604 return ret_val;
2605}
2606
2607/**
2608 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2609 * @hw: pointer to the HW structure
2610 *
2611 * Sets up Master/slave mode
2612 **/
2613static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2614{
2615 s32 ret_val;
2616 u16 phy_data;
2617
2618 /* Resolve Master/Slave mode */
2619 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2620 if (ret_val)
2621 return ret_val;
2622
2623 /* load defaults for future use */
2624 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2625 ((phy_data & CR_1000T_MS_VALUE) ?
2626 e1000_ms_force_master :
2627 e1000_ms_force_slave) : e1000_ms_auto;
2628
2629 switch (hw->phy.ms_type) {
2630 case e1000_ms_force_master:
2631 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2632 break;
2633 case e1000_ms_force_slave:
2634 phy_data |= CR_1000T_MS_ENABLE;
2635 phy_data &= ~(CR_1000T_MS_VALUE);
2636 break;
2637 case e1000_ms_auto:
2638 phy_data &= ~CR_1000T_MS_ENABLE;
2639 /* fall-through */
2640 default:
2641 break;
2642 }
2643
2644 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2645}