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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4#ifndef _E1000_82575_H_
5#define _E1000_82575_H_
6
7void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
8void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
9void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
10void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
11s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
12 u8 *data);
13s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
14 u8 data);
15
16#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
17 (ID_LED_DEF1_DEF2 << 8) | \
18 (ID_LED_DEF1_DEF2 << 4) | \
19 (ID_LED_OFF1_ON2))
20
21#define E1000_RAR_ENTRIES_82575 16
22#define E1000_RAR_ENTRIES_82576 24
23#define E1000_RAR_ENTRIES_82580 24
24#define E1000_RAR_ENTRIES_I350 32
25
26#define E1000_SW_SYNCH_MB 0x00000100
27#define E1000_STAT_DEV_RST_SET 0x00100000
28#define E1000_CTRL_DEV_RST 0x20000000
29
30/* SRRCTL bit definitions */
31#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
32#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
33#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
34#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
35#define E1000_SRRCTL_DROP_EN 0x80000000
36#define E1000_SRRCTL_TIMESTAMP 0x40000000
37
38
39#define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
40#define E1000_MRQC_ENABLE_VMDQ 0x00000003
41#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
42#define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005
43#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
44#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
45
46#define E1000_EICR_TX_QUEUE ( \
47 E1000_EICR_TX_QUEUE0 | \
48 E1000_EICR_TX_QUEUE1 | \
49 E1000_EICR_TX_QUEUE2 | \
50 E1000_EICR_TX_QUEUE3)
51
52#define E1000_EICR_RX_QUEUE ( \
53 E1000_EICR_RX_QUEUE0 | \
54 E1000_EICR_RX_QUEUE1 | \
55 E1000_EICR_RX_QUEUE2 | \
56 E1000_EICR_RX_QUEUE3)
57
58/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
59#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
60#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
61
62/* Receive Descriptor - Advanced */
63union e1000_adv_rx_desc {
64 struct {
65 __le64 pkt_addr; /* Packet buffer address */
66 __le64 hdr_addr; /* Header buffer address */
67 } read;
68 struct {
69 struct {
70 struct {
71 __le16 pkt_info; /* RSS type, Packet type */
72 __le16 hdr_info; /* Split Head, buf len */
73 } lo_dword;
74 union {
75 __le32 rss; /* RSS Hash */
76 struct {
77 __le16 ip_id; /* IP id */
78 __le16 csum; /* Packet Checksum */
79 } csum_ip;
80 } hi_dword;
81 } lower;
82 struct {
83 __le32 status_error; /* ext status/error */
84 __le16 length; /* Packet length */
85 __le16 vlan; /* VLAN tag */
86 } upper;
87 } wb; /* writeback */
88};
89
90#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
91#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
92#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
93#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
94
95/* Transmit Descriptor - Advanced */
96union e1000_adv_tx_desc {
97 struct {
98 __le64 buffer_addr; /* Address of descriptor's data buf */
99 __le32 cmd_type_len;
100 __le32 olinfo_status;
101 } read;
102 struct {
103 __le64 rsvd; /* Reserved */
104 __le32 nxtseq_seed;
105 __le32 status;
106 } wb;
107};
108
109/* Adv Transmit Descriptor Config Masks */
110#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
111#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
112#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
113#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
114#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
115#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
116#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
117#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
118#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
119#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
120
121/* Context descriptors */
122struct e1000_adv_tx_context_desc {
123 __le32 vlan_macip_lens;
124 __le32 seqnum_seed;
125 __le32 type_tucmd_mlhl;
126 __le32 mss_l4len_idx;
127};
128
129#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
130#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
131#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
132#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
133#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
134/* IPSec Encrypt Enable for ESP */
135#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
136#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
137/* Adv ctxt IPSec SA IDX mask */
138/* Adv ctxt IPSec ESP len mask */
139
140/* Additional Transmit Descriptor Control definitions */
141#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
142/* Tx Queue Arbitration Priority 0=low, 1=high */
143
144/* Additional Receive Descriptor Control definitions */
145#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
146
147/* Direct Cache Access (DCA) definitions */
148#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
149#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
150
151#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
152#define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
153#define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
154#define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
155#define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
156
157#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
158#define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
159#define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
160#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
161#define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
162
163/* Additional DCA related definitions, note change in position of CPUID */
164#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
165#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
166#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
167#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
168
169/* ETQF register bit definitions */
170#define E1000_ETQF_FILTER_ENABLE BIT(26)
171#define E1000_ETQF_1588 BIT(30)
172#define E1000_ETQF_IMM_INT BIT(29)
173#define E1000_ETQF_QUEUE_ENABLE BIT(31)
174#define E1000_ETQF_QUEUE_SHIFT 16
175#define E1000_ETQF_QUEUE_MASK 0x00070000
176#define E1000_ETQF_ETYPE_MASK 0x0000FFFF
177
178/* FTQF register bit definitions */
179#define E1000_FTQF_VF_BP 0x00008000
180#define E1000_FTQF_1588_TIME_STAMP 0x08000000
181#define E1000_FTQF_MASK 0xF0000000
182#define E1000_FTQF_MASK_PROTO_BP 0x10000000
183#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
184
185#define E1000_NVM_APME_82575 0x0400
186#define MAX_NUM_VFS 8
187
188#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
189#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
190#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
191#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
192#define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */
193
194/* Easy defines for setting default pool, would normally be left a zero */
195#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
196#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
197
198/* Other useful VMD_CTL register defines */
199#define E1000_VT_CTL_IGNORE_MAC BIT(28)
200#define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29)
201#define E1000_VT_CTL_VM_REPL_EN BIT(30)
202
203/* Per VM Offload register setup */
204#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
205#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
206#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
207#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
208#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
209#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
210#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
211#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
212#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
213#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
214
215#define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
216#define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
217#define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
218
219#define E1000_VLVF_ARRAY_SIZE 32
220#define E1000_VLVF_VLANID_MASK 0x00000FFF
221#define E1000_VLVF_POOLSEL_SHIFT 12
222#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
223#define E1000_VLVF_LVLAN 0x00100000
224#define E1000_VLVF_VLANID_ENABLE 0x80000000
225
226#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
227#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
228
229#define E1000_IOVCTL 0x05BBC
230#define E1000_IOVCTL_REUSE_VFQ 0x00000001
231
232#define E1000_RPLOLR_STRVLAN 0x40000000
233#define E1000_RPLOLR_STRCRC 0x80000000
234
235#define E1000_DTXCTL_8023LL 0x0004
236#define E1000_DTXCTL_VLAN_ADDED 0x0008
237#define E1000_DTXCTL_OOS_ENABLE 0x0010
238#define E1000_DTXCTL_MDP_EN 0x0020
239#define E1000_DTXCTL_SPOOF_INT 0x0040
240
241#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT BIT(14)
242
243#define ALL_QUEUES 0xFFFF
244
245/* RX packet buffer size defines */
246#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
247void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
248void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
249void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
250u16 igb_rxpbs_adjust_82580(u32 data);
251s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
252s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
253s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
254s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status);
255
256#define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
257#define E1000_EMC_INTERNAL_DATA 0x00
258#define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
259#define E1000_EMC_DIODE1_DATA 0x01
260#define E1000_EMC_DIODE1_THERM_LIMIT 0x19
261#define E1000_EMC_DIODE2_DATA 0x23
262#define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
263#define E1000_EMC_DIODE3_DATA 0x2A
264#define E1000_EMC_DIODE3_THERM_LIMIT 0x30
265#endif
1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24#ifndef _E1000_82575_H_
25#define _E1000_82575_H_
26
27void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
28void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
29void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
30void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
31s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
32 u8 *data);
33s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
34 u8 data);
35
36#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
37 (ID_LED_DEF1_DEF2 << 8) | \
38 (ID_LED_DEF1_DEF2 << 4) | \
39 (ID_LED_OFF1_ON2))
40
41#define E1000_RAR_ENTRIES_82575 16
42#define E1000_RAR_ENTRIES_82576 24
43#define E1000_RAR_ENTRIES_82580 24
44#define E1000_RAR_ENTRIES_I350 32
45
46#define E1000_SW_SYNCH_MB 0x00000100
47#define E1000_STAT_DEV_RST_SET 0x00100000
48#define E1000_CTRL_DEV_RST 0x20000000
49
50/* SRRCTL bit definitions */
51#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
52#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
53#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
54#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
55#define E1000_SRRCTL_DROP_EN 0x80000000
56#define E1000_SRRCTL_TIMESTAMP 0x40000000
57
58
59#define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
60#define E1000_MRQC_ENABLE_VMDQ 0x00000003
61#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
62#define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005
63#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
64#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
65
66#define E1000_EICR_TX_QUEUE ( \
67 E1000_EICR_TX_QUEUE0 | \
68 E1000_EICR_TX_QUEUE1 | \
69 E1000_EICR_TX_QUEUE2 | \
70 E1000_EICR_TX_QUEUE3)
71
72#define E1000_EICR_RX_QUEUE ( \
73 E1000_EICR_RX_QUEUE0 | \
74 E1000_EICR_RX_QUEUE1 | \
75 E1000_EICR_RX_QUEUE2 | \
76 E1000_EICR_RX_QUEUE3)
77
78/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
79#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
80#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
81
82/* Receive Descriptor - Advanced */
83union e1000_adv_rx_desc {
84 struct {
85 __le64 pkt_addr; /* Packet buffer address */
86 __le64 hdr_addr; /* Header buffer address */
87 } read;
88 struct {
89 struct {
90 struct {
91 __le16 pkt_info; /* RSS type, Packet type */
92 __le16 hdr_info; /* Split Head, buf len */
93 } lo_dword;
94 union {
95 __le32 rss; /* RSS Hash */
96 struct {
97 __le16 ip_id; /* IP id */
98 __le16 csum; /* Packet Checksum */
99 } csum_ip;
100 } hi_dword;
101 } lower;
102 struct {
103 __le32 status_error; /* ext status/error */
104 __le16 length; /* Packet length */
105 __le16 vlan; /* VLAN tag */
106 } upper;
107 } wb; /* writeback */
108};
109
110#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
111#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
112#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
113#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
114
115/* Transmit Descriptor - Advanced */
116union e1000_adv_tx_desc {
117 struct {
118 __le64 buffer_addr; /* Address of descriptor's data buf */
119 __le32 cmd_type_len;
120 __le32 olinfo_status;
121 } read;
122 struct {
123 __le64 rsvd; /* Reserved */
124 __le32 nxtseq_seed;
125 __le32 status;
126 } wb;
127};
128
129/* Adv Transmit Descriptor Config Masks */
130#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
131#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
132#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
133#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
134#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
135#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
136#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
137#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
138#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
139#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
140
141/* Context descriptors */
142struct e1000_adv_tx_context_desc {
143 __le32 vlan_macip_lens;
144 __le32 seqnum_seed;
145 __le32 type_tucmd_mlhl;
146 __le32 mss_l4len_idx;
147};
148
149#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
150#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
151#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
152#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
153/* IPSec Encrypt Enable for ESP */
154#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
155#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
156/* Adv ctxt IPSec SA IDX mask */
157/* Adv ctxt IPSec ESP len mask */
158
159/* Additional Transmit Descriptor Control definitions */
160#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
161/* Tx Queue Arbitration Priority 0=low, 1=high */
162
163/* Additional Receive Descriptor Control definitions */
164#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
165
166/* Direct Cache Access (DCA) definitions */
167#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
168#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
169
170#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
171#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
172#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
173#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
174#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
175
176#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
177#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
178#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
179#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
180#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
181
182/* Additional DCA related definitions, note change in position of CPUID */
183#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
184#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
185#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
186#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
187
188/* ETQF register bit definitions */
189#define E1000_ETQF_FILTER_ENABLE (1 << 26)
190#define E1000_ETQF_1588 (1 << 30)
191
192/* FTQF register bit definitions */
193#define E1000_FTQF_VF_BP 0x00008000
194#define E1000_FTQF_1588_TIME_STAMP 0x08000000
195#define E1000_FTQF_MASK 0xF0000000
196#define E1000_FTQF_MASK_PROTO_BP 0x10000000
197#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
198
199#define E1000_NVM_APME_82575 0x0400
200#define MAX_NUM_VFS 8
201
202#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
203#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
204#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
205#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
206#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
207
208/* Easy defines for setting default pool, would normally be left a zero */
209#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
210#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
211
212/* Other useful VMD_CTL register defines */
213#define E1000_VT_CTL_IGNORE_MAC (1 << 28)
214#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
215#define E1000_VT_CTL_VM_REPL_EN (1 << 30)
216
217/* Per VM Offload register setup */
218#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
219#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
220#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
221#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
222#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
223#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
224#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
225#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
226#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
227#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
228
229#define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
230#define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
231#define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
232
233#define E1000_VLVF_ARRAY_SIZE 32
234#define E1000_VLVF_VLANID_MASK 0x00000FFF
235#define E1000_VLVF_POOLSEL_SHIFT 12
236#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
237#define E1000_VLVF_LVLAN 0x00100000
238#define E1000_VLVF_VLANID_ENABLE 0x80000000
239
240#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
241#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
242
243#define E1000_IOVCTL 0x05BBC
244#define E1000_IOVCTL_REUSE_VFQ 0x00000001
245
246#define E1000_RPLOLR_STRVLAN 0x40000000
247#define E1000_RPLOLR_STRCRC 0x80000000
248
249#define E1000_DTXCTL_8023LL 0x0004
250#define E1000_DTXCTL_VLAN_ADDED 0x0008
251#define E1000_DTXCTL_OOS_ENABLE 0x0010
252#define E1000_DTXCTL_MDP_EN 0x0020
253#define E1000_DTXCTL_SPOOF_INT 0x0040
254
255#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
256
257#define ALL_QUEUES 0xFFFF
258
259/* RX packet buffer size defines */
260#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
261void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
262void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
263void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
264u16 igb_rxpbs_adjust_82580(u32 data);
265s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
266s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
267s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
268s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status);
269
270#define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
271#define E1000_EMC_INTERNAL_DATA 0x00
272#define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
273#define E1000_EMC_DIODE1_DATA 0x01
274#define E1000_EMC_DIODE1_THERM_LIMIT 0x19
275#define E1000_EMC_DIODE2_DATA 0x23
276#define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
277#define E1000_EMC_DIODE3_DATA 0x2A
278#define E1000_EMC_DIODE3_THERM_LIMIT 0x30
279#endif