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1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
2/*
3 * Copyright 2008 - 2016 Freescale Semiconductor Inc.
4 * Copyright 2020 NXP
5 */
6
7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9#include <linux/init.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/of_mdio.h>
13#include <linux/of_net.h>
14#include <linux/io.h>
15#include <linux/if_arp.h>
16#include <linux/if_vlan.h>
17#include <linux/icmp.h>
18#include <linux/ip.h>
19#include <linux/ipv6.h>
20#include <linux/platform_device.h>
21#include <linux/udp.h>
22#include <linux/tcp.h>
23#include <linux/net.h>
24#include <linux/skbuff.h>
25#include <linux/etherdevice.h>
26#include <linux/if_ether.h>
27#include <linux/highmem.h>
28#include <linux/percpu.h>
29#include <linux/dma-mapping.h>
30#include <linux/sort.h>
31#include <linux/phy_fixed.h>
32#include <linux/bpf.h>
33#include <linux/bpf_trace.h>
34#include <soc/fsl/bman.h>
35#include <soc/fsl/qman.h>
36#include "fman.h"
37#include "fman_port.h"
38#include "mac.h"
39#include "dpaa_eth.h"
40
41/* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
42 * using trace events only need to #include <trace/events/sched.h>
43 */
44#define CREATE_TRACE_POINTS
45#include "dpaa_eth_trace.h"
46
47static int debug = -1;
48module_param(debug, int, 0444);
49MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
50
51static u16 tx_timeout = 1000;
52module_param(tx_timeout, ushort, 0444);
53MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
54
55#define FM_FD_STAT_RX_ERRORS \
56 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \
57 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
58 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \
59 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
60 FM_FD_ERR_PRS_HDR_ERR)
61
62#define FM_FD_STAT_TX_ERRORS \
63 (FM_FD_ERR_UNSUPPORTED_FORMAT | \
64 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
65
66#define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
67 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
68 NETIF_MSG_IFDOWN | NETIF_MSG_HW)
69
70#define DPAA_INGRESS_CS_THRESHOLD 0x10000000
71/* Ingress congestion threshold on FMan ports
72 * The size in bytes of the ingress tail-drop threshold on FMan ports.
73 * Traffic piling up above this value will be rejected by QMan and discarded
74 * by FMan.
75 */
76
77/* Size in bytes of the FQ taildrop threshold */
78#define DPAA_FQ_TD 0x200000
79
80#define DPAA_CS_THRESHOLD_1G 0x06000000
81/* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
82 * The size in bytes of the egress Congestion State notification threshold on
83 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
84 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
85 * and the larger the frame size, the more acute the problem.
86 * So we have to find a balance between these factors:
87 * - avoiding the device staying congested for a prolonged time (risking
88 * the netdev watchdog to fire - see also the tx_timeout module param);
89 * - affecting performance of protocols such as TCP, which otherwise
90 * behave well under the congestion notification mechanism;
91 * - preventing the Tx cores from tightly-looping (as if the congestion
92 * threshold was too low to be effective);
93 * - running out of memory if the CS threshold is set too high.
94 */
95
96#define DPAA_CS_THRESHOLD_10G 0x10000000
97/* The size in bytes of the egress Congestion State notification threshold on
98 * 10G ports, range 0x1000 .. 0x10000000
99 */
100
101/* Largest value that the FQD's OAL field can hold */
102#define FSL_QMAN_MAX_OAL 127
103
104/* Default alignment for start of data in an Rx FD */
105#ifdef CONFIG_DPAA_ERRATUM_A050385
106/* aligning data start to 64 avoids DMA transaction splits, unless the buffer
107 * is crossing a 4k page boundary
108 */
109#define DPAA_FD_DATA_ALIGNMENT (fman_has_errata_a050385() ? 64 : 16)
110/* aligning to 256 avoids DMA transaction splits caused by 4k page boundary
111 * crossings; also, all SG fragments except the last must have a size multiple
112 * of 256 to avoid DMA transaction splits
113 */
114#define DPAA_A050385_ALIGN 256
115#define DPAA_FD_RX_DATA_ALIGNMENT (fman_has_errata_a050385() ? \
116 DPAA_A050385_ALIGN : 16)
117#else
118#define DPAA_FD_DATA_ALIGNMENT 16
119#define DPAA_FD_RX_DATA_ALIGNMENT DPAA_FD_DATA_ALIGNMENT
120#endif
121
122/* The DPAA requires 256 bytes reserved and mapped for the SGT */
123#define DPAA_SGT_SIZE 256
124
125/* Values for the L3R field of the FM Parse Results
126 */
127/* L3 Type field: First IP Present IPv4 */
128#define FM_L3_PARSE_RESULT_IPV4 0x8000
129/* L3 Type field: First IP Present IPv6 */
130#define FM_L3_PARSE_RESULT_IPV6 0x4000
131/* Values for the L4R field of the FM Parse Results */
132/* L4 Type field: UDP */
133#define FM_L4_PARSE_RESULT_UDP 0x40
134/* L4 Type field: TCP */
135#define FM_L4_PARSE_RESULT_TCP 0x20
136
137/* FD status field indicating whether the FM Parser has attempted to validate
138 * the L4 csum of the frame.
139 * Note that having this bit set doesn't necessarily imply that the checksum
140 * is valid. One would have to check the parse results to find that out.
141 */
142#define FM_FD_STAT_L4CV 0x00000004
143
144#define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
145#define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
146
147#define FSL_DPAA_BPID_INV 0xff
148#define FSL_DPAA_ETH_MAX_BUF_COUNT 128
149#define FSL_DPAA_ETH_REFILL_THRESHOLD 80
150
151#define DPAA_TX_PRIV_DATA_SIZE 16
152#define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
153#define DPAA_TIME_STAMP_SIZE 8
154#define DPAA_HASH_RESULTS_SIZE 8
155#define DPAA_HWA_SIZE (DPAA_PARSE_RESULTS_SIZE + DPAA_TIME_STAMP_SIZE \
156 + DPAA_HASH_RESULTS_SIZE)
157#define DPAA_RX_PRIV_DATA_DEFAULT_SIZE (DPAA_TX_PRIV_DATA_SIZE + \
158 XDP_PACKET_HEADROOM - DPAA_HWA_SIZE)
159#ifdef CONFIG_DPAA_ERRATUM_A050385
160#define DPAA_RX_PRIV_DATA_A050385_SIZE (DPAA_A050385_ALIGN - DPAA_HWA_SIZE)
161#define DPAA_RX_PRIV_DATA_SIZE (fman_has_errata_a050385() ? \
162 DPAA_RX_PRIV_DATA_A050385_SIZE : \
163 DPAA_RX_PRIV_DATA_DEFAULT_SIZE)
164#else
165#define DPAA_RX_PRIV_DATA_SIZE DPAA_RX_PRIV_DATA_DEFAULT_SIZE
166#endif
167
168#define DPAA_ETH_PCD_RXQ_NUM 128
169
170#define DPAA_ENQUEUE_RETRIES 100000
171
172enum port_type {RX, TX};
173
174struct fm_port_fqs {
175 struct dpaa_fq *tx_defq;
176 struct dpaa_fq *tx_errq;
177 struct dpaa_fq *rx_defq;
178 struct dpaa_fq *rx_errq;
179 struct dpaa_fq *rx_pcdq;
180};
181
182/* All the dpa bps in use at any moment */
183static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
184
185#define DPAA_BP_RAW_SIZE 4096
186
187#ifdef CONFIG_DPAA_ERRATUM_A050385
188#define dpaa_bp_size(raw_size) (SKB_WITH_OVERHEAD(raw_size) & \
189 ~(DPAA_A050385_ALIGN - 1))
190#else
191#define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size)
192#endif
193
194static int dpaa_max_frm;
195
196static int dpaa_rx_extra_headroom;
197
198#define dpaa_get_max_mtu() \
199 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
200
201static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed);
202
203static int dpaa_netdev_init(struct net_device *net_dev,
204 const struct net_device_ops *dpaa_ops,
205 u16 tx_timeout)
206{
207 struct dpaa_priv *priv = netdev_priv(net_dev);
208 struct device *dev = net_dev->dev.parent;
209 struct mac_device *mac_dev = priv->mac_dev;
210 struct dpaa_percpu_priv *percpu_priv;
211 const u8 *mac_addr;
212 int i, err;
213
214 /* Although we access another CPU's private data here
215 * we do it at initialization so it is safe
216 */
217 for_each_possible_cpu(i) {
218 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
219 percpu_priv->net_dev = net_dev;
220 }
221
222 net_dev->netdev_ops = dpaa_ops;
223 mac_addr = mac_dev->addr;
224
225 net_dev->mem_start = (unsigned long)priv->mac_dev->res->start;
226 net_dev->mem_end = (unsigned long)priv->mac_dev->res->end;
227
228 net_dev->min_mtu = ETH_MIN_MTU;
229 net_dev->max_mtu = dpaa_get_max_mtu();
230
231 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
232 NETIF_F_RXHASH);
233
234 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
235 /* The kernels enables GSO automatically, if we declare NETIF_F_SG.
236 * For conformity, we'll still declare GSO explicitly.
237 */
238 net_dev->features |= NETIF_F_GSO;
239 net_dev->features |= NETIF_F_RXCSUM;
240
241 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
242 net_dev->lltx = true;
243 /* we do not want shared skbs on TX */
244 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
245
246 net_dev->features |= net_dev->hw_features;
247 net_dev->vlan_features = net_dev->features;
248
249 net_dev->xdp_features = NETDEV_XDP_ACT_BASIC |
250 NETDEV_XDP_ACT_REDIRECT |
251 NETDEV_XDP_ACT_NDO_XMIT;
252
253 if (is_valid_ether_addr(mac_addr)) {
254 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
255 eth_hw_addr_set(net_dev, mac_addr);
256 } else {
257 eth_hw_addr_random(net_dev);
258 err = mac_dev->change_addr(mac_dev->fman_mac,
259 (const enet_addr_t *)net_dev->dev_addr);
260 if (err) {
261 dev_err(dev, "Failed to set random MAC address\n");
262 return -EINVAL;
263 }
264 dev_info(dev, "Using random MAC address: %pM\n",
265 net_dev->dev_addr);
266 }
267
268 net_dev->ethtool_ops = &dpaa_ethtool_ops;
269
270 net_dev->needed_headroom = priv->tx_headroom;
271 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
272
273 /* The rest of the config is filled in by the mac device already */
274 mac_dev->phylink_config.dev = &net_dev->dev;
275 mac_dev->phylink_config.type = PHYLINK_NETDEV;
276 mac_dev->update_speed = dpaa_eth_cgr_set_speed;
277 mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
278 dev_fwnode(mac_dev->dev),
279 mac_dev->phy_if,
280 mac_dev->phylink_ops);
281 if (IS_ERR(mac_dev->phylink)) {
282 err = PTR_ERR(mac_dev->phylink);
283 dev_err_probe(dev, err, "Could not create phylink\n");
284 return err;
285 }
286
287 /* start without the RUNNING flag, phylib controls it later */
288 netif_carrier_off(net_dev);
289
290 err = register_netdev(net_dev);
291 if (err < 0) {
292 dev_err(dev, "register_netdev() = %d\n", err);
293 phylink_destroy(mac_dev->phylink);
294 return err;
295 }
296
297 return 0;
298}
299
300static int dpaa_stop(struct net_device *net_dev)
301{
302 struct mac_device *mac_dev;
303 struct dpaa_priv *priv;
304 int i, error;
305 int err = 0;
306
307 priv = netdev_priv(net_dev);
308 mac_dev = priv->mac_dev;
309
310 netif_tx_stop_all_queues(net_dev);
311 /* Allow the Fman (Tx) port to process in-flight frames before we
312 * try switching it off.
313 */
314 msleep(200);
315
316 phylink_stop(mac_dev->phylink);
317 mac_dev->disable(mac_dev->fman_mac);
318
319 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
320 error = fman_port_disable(mac_dev->port[i]);
321 if (error)
322 err = error;
323 }
324
325 phylink_disconnect_phy(mac_dev->phylink);
326 net_dev->phydev = NULL;
327
328 msleep(200);
329
330 return err;
331}
332
333static void dpaa_tx_timeout(struct net_device *net_dev, unsigned int txqueue)
334{
335 struct dpaa_percpu_priv *percpu_priv;
336 const struct dpaa_priv *priv;
337
338 priv = netdev_priv(net_dev);
339 percpu_priv = this_cpu_ptr(priv->percpu_priv);
340
341 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
342 jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
343
344 percpu_priv->stats.tx_errors++;
345}
346
347/* Calculates the statistics for the given device by adding the statistics
348 * collected by each CPU.
349 */
350static void dpaa_get_stats64(struct net_device *net_dev,
351 struct rtnl_link_stats64 *s)
352{
353 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
354 struct dpaa_priv *priv = netdev_priv(net_dev);
355 struct dpaa_percpu_priv *percpu_priv;
356 u64 *netstats = (u64 *)s;
357 u64 *cpustats;
358 int i, j;
359
360 for_each_possible_cpu(i) {
361 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
362
363 cpustats = (u64 *)&percpu_priv->stats;
364
365 /* add stats from all CPUs */
366 for (j = 0; j < numstats; j++)
367 netstats[j] += cpustats[j];
368 }
369}
370
371static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
372 void *type_data)
373{
374 struct dpaa_priv *priv = netdev_priv(net_dev);
375 int num_txqs_per_tc = dpaa_num_txqs_per_tc();
376 struct tc_mqprio_qopt *mqprio = type_data;
377 u8 num_tc;
378 int i;
379
380 if (type != TC_SETUP_QDISC_MQPRIO)
381 return -EOPNOTSUPP;
382
383 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
384 num_tc = mqprio->num_tc;
385
386 if (num_tc == priv->num_tc)
387 return 0;
388
389 if (!num_tc) {
390 netdev_reset_tc(net_dev);
391 goto out;
392 }
393
394 if (num_tc > DPAA_TC_NUM) {
395 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
396 DPAA_TC_NUM);
397 return -EINVAL;
398 }
399
400 netdev_set_num_tc(net_dev, num_tc);
401
402 for (i = 0; i < num_tc; i++)
403 netdev_set_tc_queue(net_dev, i, num_txqs_per_tc,
404 i * num_txqs_per_tc);
405
406out:
407 priv->num_tc = num_tc ? : 1;
408 netif_set_real_num_tx_queues(net_dev, priv->num_tc * num_txqs_per_tc);
409 return 0;
410}
411
412static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
413{
414 struct dpaa_eth_data *eth_data;
415 struct device *dpaa_dev;
416 struct mac_device *mac_dev;
417
418 dpaa_dev = &pdev->dev;
419 eth_data = dpaa_dev->platform_data;
420 if (!eth_data) {
421 dev_err(dpaa_dev, "eth_data missing\n");
422 return ERR_PTR(-ENODEV);
423 }
424 mac_dev = eth_data->mac_dev;
425 if (!mac_dev) {
426 dev_err(dpaa_dev, "mac_dev missing\n");
427 return ERR_PTR(-EINVAL);
428 }
429
430 return mac_dev;
431}
432
433static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
434{
435 const struct dpaa_priv *priv;
436 struct mac_device *mac_dev;
437 struct sockaddr old_addr;
438 int err;
439
440 priv = netdev_priv(net_dev);
441
442 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN);
443
444 err = eth_mac_addr(net_dev, addr);
445 if (err < 0) {
446 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
447 return err;
448 }
449
450 mac_dev = priv->mac_dev;
451
452 err = mac_dev->change_addr(mac_dev->fman_mac,
453 (const enet_addr_t *)net_dev->dev_addr);
454 if (err < 0) {
455 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
456 err);
457 /* reverting to previous address */
458 eth_mac_addr(net_dev, &old_addr);
459
460 return err;
461 }
462
463 return 0;
464}
465
466static int dpaa_addr_sync(struct net_device *net_dev, const u8 *addr)
467{
468 const struct dpaa_priv *priv = netdev_priv(net_dev);
469
470 return priv->mac_dev->add_hash_mac_addr(priv->mac_dev->fman_mac,
471 (enet_addr_t *)addr);
472}
473
474static int dpaa_addr_unsync(struct net_device *net_dev, const u8 *addr)
475{
476 const struct dpaa_priv *priv = netdev_priv(net_dev);
477
478 return priv->mac_dev->remove_hash_mac_addr(priv->mac_dev->fman_mac,
479 (enet_addr_t *)addr);
480}
481
482static void dpaa_set_rx_mode(struct net_device *net_dev)
483{
484 const struct dpaa_priv *priv;
485 int err;
486
487 priv = netdev_priv(net_dev);
488
489 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
490 priv->mac_dev->promisc = !priv->mac_dev->promisc;
491 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
492 priv->mac_dev->promisc);
493 if (err < 0)
494 netif_err(priv, drv, net_dev,
495 "mac_dev->set_promisc() = %d\n",
496 err);
497 }
498
499 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
500 priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
501 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
502 priv->mac_dev->allmulti);
503 if (err < 0)
504 netif_err(priv, drv, net_dev,
505 "mac_dev->set_allmulti() = %d\n",
506 err);
507 }
508
509 err = __dev_mc_sync(net_dev, dpaa_addr_sync, dpaa_addr_unsync);
510 if (err < 0)
511 netif_err(priv, drv, net_dev, "dpaa_addr_sync() = %d\n",
512 err);
513}
514
515static struct dpaa_bp *dpaa_bpid2pool(int bpid)
516{
517 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
518 return NULL;
519
520 return dpaa_bp_array[bpid];
521}
522
523/* checks if this bpool is already allocated */
524static bool dpaa_bpid2pool_use(int bpid)
525{
526 if (dpaa_bpid2pool(bpid)) {
527 refcount_inc(&dpaa_bp_array[bpid]->refs);
528 return true;
529 }
530
531 return false;
532}
533
534/* called only once per bpid by dpaa_bp_alloc_pool() */
535static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
536{
537 dpaa_bp_array[bpid] = dpaa_bp;
538 refcount_set(&dpaa_bp->refs, 1);
539}
540
541static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
542{
543 int err;
544
545 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
546 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
547 __func__);
548 return -EINVAL;
549 }
550
551 /* If the pool is already specified, we only create one per bpid */
552 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
553 dpaa_bpid2pool_use(dpaa_bp->bpid))
554 return 0;
555
556 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
557 dpaa_bp->pool = bman_new_pool();
558 if (!dpaa_bp->pool) {
559 pr_err("%s: bman_new_pool() failed\n",
560 __func__);
561 return -ENODEV;
562 }
563
564 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
565 }
566
567 if (dpaa_bp->seed_cb) {
568 err = dpaa_bp->seed_cb(dpaa_bp);
569 if (err)
570 goto pool_seed_failed;
571 }
572
573 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
574
575 return 0;
576
577pool_seed_failed:
578 pr_err("%s: pool seeding failed\n", __func__);
579 bman_free_pool(dpaa_bp->pool);
580
581 return err;
582}
583
584/* remove and free all the buffers from the given buffer pool */
585static void dpaa_bp_drain(struct dpaa_bp *bp)
586{
587 u8 num = 8;
588 int ret;
589
590 do {
591 struct bm_buffer bmb[8];
592 int i;
593
594 ret = bman_acquire(bp->pool, bmb, num);
595 if (ret < 0) {
596 if (num == 8) {
597 /* we have less than 8 buffers left;
598 * drain them one by one
599 */
600 num = 1;
601 ret = 1;
602 continue;
603 } else {
604 /* Pool is fully drained */
605 break;
606 }
607 }
608
609 if (bp->free_buf_cb)
610 for (i = 0; i < num; i++)
611 bp->free_buf_cb(bp, &bmb[i]);
612 } while (ret > 0);
613}
614
615static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
616{
617 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
618
619 /* the mapping between bpid and dpaa_bp is done very late in the
620 * allocation procedure; if something failed before the mapping, the bp
621 * was not configured, therefore we don't need the below instructions
622 */
623 if (!bp)
624 return;
625
626 if (!refcount_dec_and_test(&bp->refs))
627 return;
628
629 if (bp->free_buf_cb)
630 dpaa_bp_drain(bp);
631
632 dpaa_bp_array[bp->bpid] = NULL;
633 bman_free_pool(bp->pool);
634}
635
636static void dpaa_bps_free(struct dpaa_priv *priv)
637{
638 dpaa_bp_free(priv->dpaa_bp);
639}
640
641/* Use multiple WQs for FQ assignment:
642 * - Tx Confirmation queues go to WQ1.
643 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
644 * to be scheduled, in case there are many more FQs in WQ6).
645 * - Rx Default goes to WQ6.
646 * - Tx queues go to different WQs depending on their priority. Equal
647 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
648 * WQ0 (highest priority).
649 * This ensures that Tx-confirmed buffers are timely released. In particular,
650 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
651 * are greatly outnumbered by other FQs in the system, while
652 * dequeue scheduling is round-robin.
653 */
654static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
655{
656 switch (fq->fq_type) {
657 case FQ_TYPE_TX_CONFIRM:
658 case FQ_TYPE_TX_CONF_MQ:
659 fq->wq = 1;
660 break;
661 case FQ_TYPE_RX_ERROR:
662 case FQ_TYPE_TX_ERROR:
663 fq->wq = 5;
664 break;
665 case FQ_TYPE_RX_DEFAULT:
666 case FQ_TYPE_RX_PCD:
667 fq->wq = 6;
668 break;
669 case FQ_TYPE_TX:
670 switch (idx / dpaa_num_txqs_per_tc()) {
671 case 0:
672 /* Low priority (best effort) */
673 fq->wq = 6;
674 break;
675 case 1:
676 /* Medium priority */
677 fq->wq = 2;
678 break;
679 case 2:
680 /* High priority */
681 fq->wq = 1;
682 break;
683 case 3:
684 /* Very high priority */
685 fq->wq = 0;
686 break;
687 default:
688 WARN(1, "Too many TX FQs: more than %zu!\n",
689 dpaa_max_num_txqs());
690 }
691 break;
692 default:
693 WARN(1, "Invalid FQ type %d for FQID %d!\n",
694 fq->fq_type, fq->fqid);
695 }
696}
697
698static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
699 u32 start, u32 count,
700 struct list_head *list,
701 enum dpaa_fq_type fq_type)
702{
703 struct dpaa_fq *dpaa_fq;
704 int i;
705
706 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq),
707 GFP_KERNEL);
708 if (!dpaa_fq)
709 return NULL;
710
711 for (i = 0; i < count; i++) {
712 dpaa_fq[i].fq_type = fq_type;
713 dpaa_fq[i].fqid = start ? start + i : 0;
714 list_add_tail(&dpaa_fq[i].list, list);
715 }
716
717 for (i = 0; i < count; i++)
718 dpaa_assign_wq(dpaa_fq + i, i);
719
720 return dpaa_fq;
721}
722
723static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
724 struct fm_port_fqs *port_fqs)
725{
726 struct dpaa_fq *dpaa_fq;
727 u32 fq_base, fq_base_aligned, i;
728
729 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
730 if (!dpaa_fq)
731 goto fq_alloc_failed;
732
733 port_fqs->rx_errq = &dpaa_fq[0];
734
735 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
736 if (!dpaa_fq)
737 goto fq_alloc_failed;
738
739 port_fqs->rx_defq = &dpaa_fq[0];
740
741 /* the PCD FQIDs range needs to be aligned for correct operation */
742 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
743 goto fq_alloc_failed;
744
745 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
746
747 for (i = fq_base; i < fq_base_aligned; i++)
748 qman_release_fqid(i);
749
750 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
751 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
752 qman_release_fqid(i);
753
754 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
755 list, FQ_TYPE_RX_PCD);
756 if (!dpaa_fq)
757 goto fq_alloc_failed;
758
759 port_fqs->rx_pcdq = &dpaa_fq[0];
760
761 if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list,
762 FQ_TYPE_TX_CONF_MQ))
763 goto fq_alloc_failed;
764
765 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
766 if (!dpaa_fq)
767 goto fq_alloc_failed;
768
769 port_fqs->tx_errq = &dpaa_fq[0];
770
771 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
772 if (!dpaa_fq)
773 goto fq_alloc_failed;
774
775 port_fqs->tx_defq = &dpaa_fq[0];
776
777 if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list, FQ_TYPE_TX))
778 goto fq_alloc_failed;
779
780 return 0;
781
782fq_alloc_failed:
783 dev_err(dev, "dpaa_fq_alloc() failed\n");
784 return -ENOMEM;
785}
786
787static u32 rx_pool_channel;
788static DEFINE_SPINLOCK(rx_pool_channel_init);
789
790static int dpaa_get_channel(void)
791{
792 spin_lock(&rx_pool_channel_init);
793 if (!rx_pool_channel) {
794 u32 pool;
795 int ret;
796
797 ret = qman_alloc_pool(&pool);
798
799 if (!ret)
800 rx_pool_channel = pool;
801 }
802 spin_unlock(&rx_pool_channel_init);
803 if (!rx_pool_channel)
804 return -ENOMEM;
805 return rx_pool_channel;
806}
807
808static void dpaa_release_channel(void)
809{
810 qman_release_pool(rx_pool_channel);
811}
812
813static void dpaa_eth_add_channel(u16 channel, struct device *dev)
814{
815 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
816 const cpumask_t *cpus = qman_affine_cpus();
817 struct qman_portal *portal;
818 int cpu;
819
820 for_each_cpu_and(cpu, cpus, cpu_online_mask) {
821 portal = qman_get_affine_portal(cpu);
822 qman_p_static_dequeue_add(portal, pool);
823 qman_start_using_portal(portal, dev);
824 }
825}
826
827/* Congestion group state change notification callback.
828 * Stops the device's egress queues while they are congested and
829 * wakes them upon exiting congested state.
830 * Also updates some CGR-related stats.
831 */
832static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
833 int congested)
834{
835 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
836 struct dpaa_priv, cgr_data.cgr);
837
838 if (congested) {
839 priv->cgr_data.congestion_start_jiffies = jiffies;
840 netif_tx_stop_all_queues(priv->net_dev);
841 priv->cgr_data.cgr_congested_count++;
842 } else {
843 priv->cgr_data.congested_jiffies +=
844 (jiffies - priv->cgr_data.congestion_start_jiffies);
845 netif_tx_wake_all_queues(priv->net_dev);
846 }
847}
848
849static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
850{
851 struct qm_mcc_initcgr initcgr;
852 u32 cs_th;
853 int err;
854
855 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
856 if (err < 0) {
857 if (netif_msg_drv(priv))
858 pr_err("%s: Error %d allocating CGR ID\n",
859 __func__, err);
860 goto out_error;
861 }
862 priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
863
864 /* Enable Congestion State Change Notifications and CS taildrop */
865 memset(&initcgr, 0, sizeof(initcgr));
866 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
867 initcgr.cgr.cscn_en = QM_CGR_EN;
868
869 /* Set different thresholds based on the configured MAC speed.
870 * This may turn suboptimal if the MAC is reconfigured at another
871 * speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
872 * callback.
873 */
874 if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
875 cs_th = DPAA_CS_THRESHOLD_10G;
876 else
877 cs_th = DPAA_CS_THRESHOLD_1G;
878 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
879
880 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
881 initcgr.cgr.cstd_en = QM_CGR_EN;
882
883 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
884 &initcgr);
885 if (err < 0) {
886 if (netif_msg_drv(priv))
887 pr_err("%s: Error %d creating CGR with ID %d\n",
888 __func__, err, priv->cgr_data.cgr.cgrid);
889 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
890 goto out_error;
891 }
892 if (netif_msg_drv(priv))
893 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
894 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
895 priv->cgr_data.cgr.chan);
896
897out_error:
898 return err;
899}
900
901static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
902{
903 struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
904 struct dpaa_priv *priv = netdev_priv(net_dev);
905 struct qm_mcc_initcgr opts = { };
906 u32 cs_th;
907 int err;
908
909 opts.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
910 switch (speed) {
911 case SPEED_10000:
912 cs_th = DPAA_CS_THRESHOLD_10G;
913 break;
914 case SPEED_1000:
915 default:
916 cs_th = DPAA_CS_THRESHOLD_1G;
917 break;
918 }
919 qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, cs_th, 1);
920
921 err = qman_update_cgr_safe(&priv->cgr_data.cgr, &opts);
922 if (err)
923 netdev_err(net_dev, "could not update speed: %d\n", err);
924}
925
926static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
927 struct dpaa_fq *fq,
928 const struct qman_fq *template)
929{
930 fq->fq_base = *template;
931 fq->net_dev = priv->net_dev;
932
933 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
934 fq->channel = priv->channel;
935}
936
937static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
938 struct dpaa_fq *fq,
939 struct fman_port *port,
940 const struct qman_fq *template)
941{
942 fq->fq_base = *template;
943 fq->net_dev = priv->net_dev;
944
945 if (port) {
946 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
947 fq->channel = (u16)fman_port_get_qman_channel_id(port);
948 } else {
949 fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
950 }
951}
952
953static int dpaa_fq_setup(struct dpaa_priv *priv,
954 const struct dpaa_fq_cbs *fq_cbs,
955 struct fman_port *tx_port)
956{
957 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
958 const cpumask_t *affine_cpus = qman_affine_cpus();
959 struct dpaa_fq *fq;
960 u16 *channels;
961
962 channels = kcalloc(num_possible_cpus(), sizeof(u16), GFP_KERNEL);
963 if (!channels)
964 return -ENOMEM;
965
966 for_each_cpu_and(cpu, affine_cpus, cpu_online_mask)
967 channels[num_portals++] = qman_affine_channel(cpu);
968
969 if (num_portals == 0)
970 dev_err(priv->net_dev->dev.parent,
971 "No Qman software (affine) channels found\n");
972
973 /* Initialize each FQ in the list */
974 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
975 switch (fq->fq_type) {
976 case FQ_TYPE_RX_DEFAULT:
977 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
978 break;
979 case FQ_TYPE_RX_ERROR:
980 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
981 break;
982 case FQ_TYPE_RX_PCD:
983 if (!num_portals)
984 continue;
985 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
986 fq->channel = channels[portal_cnt++ % num_portals];
987 break;
988 case FQ_TYPE_TX:
989 dpaa_setup_egress(priv, fq, tx_port,
990 &fq_cbs->egress_ern);
991 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
992 break;
993 case FQ_TYPE_TX_CONF_MQ:
994 priv->conf_fqs[conf_cnt++] = &fq->fq_base;
995 fallthrough;
996 case FQ_TYPE_TX_CONFIRM:
997 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
998 break;
999 case FQ_TYPE_TX_ERROR:
1000 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
1001 break;
1002 default:
1003 dev_warn(priv->net_dev->dev.parent,
1004 "Unknown FQ type detected!\n");
1005 break;
1006 }
1007 }
1008
1009 kfree(channels);
1010
1011 return 0;
1012}
1013
1014static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
1015 struct qman_fq *tx_fq)
1016{
1017 int i;
1018
1019 for (i = 0; i < dpaa_max_num_txqs(); i++)
1020 if (priv->egress_fqs[i] == tx_fq)
1021 return i;
1022
1023 return -EINVAL;
1024}
1025
1026static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
1027{
1028 const struct dpaa_priv *priv;
1029 struct qman_fq *confq = NULL;
1030 struct qm_mcc_initfq initfq;
1031 struct device *dev;
1032 struct qman_fq *fq;
1033 int queue_id;
1034 int err;
1035
1036 priv = netdev_priv(dpaa_fq->net_dev);
1037 dev = dpaa_fq->net_dev->dev.parent;
1038
1039 if (dpaa_fq->fqid == 0)
1040 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1041
1042 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
1043
1044 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
1045 if (err) {
1046 dev_err(dev, "qman_create_fq() failed\n");
1047 return err;
1048 }
1049 fq = &dpaa_fq->fq_base;
1050
1051 if (dpaa_fq->init) {
1052 memset(&initfq, 0, sizeof(initfq));
1053
1054 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
1055 /* Note: we may get to keep an empty FQ in cache */
1056 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
1057
1058 /* Try to reduce the number of portal interrupts for
1059 * Tx Confirmation FQs.
1060 */
1061 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
1062 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
1063
1064 /* FQ placement */
1065 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1066
1067 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
1068
1069 /* Put all egress queues in a congestion group of their own.
1070 * Sensu stricto, the Tx confirmation queues are Rx FQs,
1071 * rather than Tx - but they nonetheless account for the
1072 * memory footprint on behalf of egress traffic. We therefore
1073 * place them in the netdev's CGR, along with the Tx FQs.
1074 */
1075 if (dpaa_fq->fq_type == FQ_TYPE_TX ||
1076 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
1077 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
1078 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1079 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1080 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1081 /* Set a fixed overhead accounting, in an attempt to
1082 * reduce the impact of fixed-size skb shells and the
1083 * driver's needed headroom on system memory. This is
1084 * especially the case when the egress traffic is
1085 * composed of small datagrams.
1086 * Unfortunately, QMan's OAL value is capped to an
1087 * insufficient value, but even that is better than
1088 * no overhead accounting at all.
1089 */
1090 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1091 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1092 qm_fqd_set_oal(&initfq.fqd,
1093 min(sizeof(struct sk_buff) +
1094 priv->tx_headroom,
1095 (size_t)FSL_QMAN_MAX_OAL));
1096 }
1097
1098 if (td_enable) {
1099 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1100 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1101 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1102 }
1103
1104 if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1105 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1106 if (queue_id >= 0)
1107 confq = priv->conf_fqs[queue_id];
1108 if (confq) {
1109 initfq.we_mask |=
1110 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1111 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1112 * A2V=1 (contextA A2 field is valid)
1113 * A0V=1 (contextA A0 field is valid)
1114 * B0V=1 (contextB field is valid)
1115 * ContextA A2: EBD=1 (deallocate buffers inside FMan)
1116 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1117 */
1118 qm_fqd_context_a_set64(&initfq.fqd,
1119 0x1e00000080000000ULL);
1120 }
1121 }
1122
1123 /* Put all the ingress queues in our "ingress CGR". */
1124 if (priv->use_ingress_cgr &&
1125 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1126 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
1127 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
1128 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1129 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1130 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1131 /* Set a fixed overhead accounting, just like for the
1132 * egress CGR.
1133 */
1134 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1135 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1136 qm_fqd_set_oal(&initfq.fqd,
1137 min(sizeof(struct sk_buff) +
1138 priv->tx_headroom,
1139 (size_t)FSL_QMAN_MAX_OAL));
1140 }
1141
1142 /* Initialization common to all ingress queues */
1143 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1144 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1145 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
1146 QM_FQCTRL_CTXASTASHING);
1147 initfq.fqd.context_a.stashing.exclusive =
1148 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
1149 QM_STASHING_EXCL_ANNOTATION;
1150 qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1151 DIV_ROUND_UP(sizeof(struct qman_fq),
1152 64));
1153 }
1154
1155 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1156 if (err < 0) {
1157 dev_err(dev, "qman_init_fq(%u) = %d\n",
1158 qman_fq_fqid(fq), err);
1159 qman_destroy_fq(fq);
1160 return err;
1161 }
1162 }
1163
1164 dpaa_fq->fqid = qman_fq_fqid(fq);
1165
1166 if (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1167 dpaa_fq->fq_type == FQ_TYPE_RX_PCD) {
1168 err = xdp_rxq_info_reg(&dpaa_fq->xdp_rxq, dpaa_fq->net_dev,
1169 dpaa_fq->fqid, 0);
1170 if (err) {
1171 dev_err(dev, "xdp_rxq_info_reg() = %d\n", err);
1172 return err;
1173 }
1174
1175 err = xdp_rxq_info_reg_mem_model(&dpaa_fq->xdp_rxq,
1176 MEM_TYPE_PAGE_ORDER0, NULL);
1177 if (err) {
1178 dev_err(dev, "xdp_rxq_info_reg_mem_model() = %d\n",
1179 err);
1180 xdp_rxq_info_unreg(&dpaa_fq->xdp_rxq);
1181 return err;
1182 }
1183 }
1184
1185 return 0;
1186}
1187
1188static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
1189{
1190 const struct dpaa_priv *priv;
1191 struct dpaa_fq *dpaa_fq;
1192 int err, error;
1193
1194 err = 0;
1195
1196 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1197 priv = netdev_priv(dpaa_fq->net_dev);
1198
1199 if (dpaa_fq->init) {
1200 err = qman_retire_fq(fq, NULL);
1201 if (err < 0 && netif_msg_drv(priv))
1202 dev_err(dev, "qman_retire_fq(%u) = %d\n",
1203 qman_fq_fqid(fq), err);
1204
1205 error = qman_oos_fq(fq);
1206 if (error < 0 && netif_msg_drv(priv)) {
1207 dev_err(dev, "qman_oos_fq(%u) = %d\n",
1208 qman_fq_fqid(fq), error);
1209 if (err >= 0)
1210 err = error;
1211 }
1212 }
1213
1214 if ((dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1215 dpaa_fq->fq_type == FQ_TYPE_RX_PCD) &&
1216 xdp_rxq_info_is_reg(&dpaa_fq->xdp_rxq))
1217 xdp_rxq_info_unreg(&dpaa_fq->xdp_rxq);
1218
1219 qman_destroy_fq(fq);
1220 list_del(&dpaa_fq->list);
1221
1222 return err;
1223}
1224
1225static int dpaa_fq_free(struct device *dev, struct list_head *list)
1226{
1227 struct dpaa_fq *dpaa_fq, *tmp;
1228 int err, error;
1229
1230 err = 0;
1231 list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1232 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1233 if (error < 0 && err >= 0)
1234 err = error;
1235 }
1236
1237 return err;
1238}
1239
1240static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
1241 struct dpaa_fq *defq,
1242 struct dpaa_buffer_layout *buf_layout)
1243{
1244 struct fman_buffer_prefix_content buf_prefix_content;
1245 struct fman_port_params params;
1246 int err;
1247
1248 memset(¶ms, 0, sizeof(params));
1249 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1250
1251 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1252 buf_prefix_content.pass_prs_result = true;
1253 buf_prefix_content.pass_hash_result = true;
1254 buf_prefix_content.pass_time_stamp = true;
1255 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1256
1257 params.specific_params.non_rx_params.err_fqid = errq->fqid;
1258 params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1259
1260 err = fman_port_config(port, ¶ms);
1261 if (err) {
1262 pr_err("%s: fman_port_config failed\n", __func__);
1263 return err;
1264 }
1265
1266 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1267 if (err) {
1268 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1269 __func__);
1270 return err;
1271 }
1272
1273 err = fman_port_init(port);
1274 if (err)
1275 pr_err("%s: fm_port_init failed\n", __func__);
1276
1277 return err;
1278}
1279
1280static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp *bp,
1281 struct dpaa_fq *errq,
1282 struct dpaa_fq *defq, struct dpaa_fq *pcdq,
1283 struct dpaa_buffer_layout *buf_layout)
1284{
1285 struct fman_buffer_prefix_content buf_prefix_content;
1286 struct fman_port_rx_params *rx_p;
1287 struct fman_port_params params;
1288 int err;
1289
1290 memset(¶ms, 0, sizeof(params));
1291 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1292
1293 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1294 buf_prefix_content.pass_prs_result = true;
1295 buf_prefix_content.pass_hash_result = true;
1296 buf_prefix_content.pass_time_stamp = true;
1297 buf_prefix_content.data_align = DPAA_FD_RX_DATA_ALIGNMENT;
1298
1299 rx_p = ¶ms.specific_params.rx_params;
1300 rx_p->err_fqid = errq->fqid;
1301 rx_p->dflt_fqid = defq->fqid;
1302 if (pcdq) {
1303 rx_p->pcd_base_fqid = pcdq->fqid;
1304 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
1305 }
1306
1307 rx_p->ext_buf_pools.num_of_pools_used = 1;
1308 rx_p->ext_buf_pools.ext_buf_pool[0].id = bp->bpid;
1309 rx_p->ext_buf_pools.ext_buf_pool[0].size = (u16)bp->size;
1310
1311 err = fman_port_config(port, ¶ms);
1312 if (err) {
1313 pr_err("%s: fman_port_config failed\n", __func__);
1314 return err;
1315 }
1316
1317 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1318 if (err) {
1319 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1320 __func__);
1321 return err;
1322 }
1323
1324 err = fman_port_init(port);
1325 if (err)
1326 pr_err("%s: fm_port_init failed\n", __func__);
1327
1328 return err;
1329}
1330
1331static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1332 struct dpaa_bp *bp,
1333 struct fm_port_fqs *port_fqs,
1334 struct dpaa_buffer_layout *buf_layout,
1335 struct device *dev)
1336{
1337 struct fman_port *rxport = mac_dev->port[RX];
1338 struct fman_port *txport = mac_dev->port[TX];
1339 int err;
1340
1341 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1342 port_fqs->tx_defq, &buf_layout[TX]);
1343 if (err)
1344 return err;
1345
1346 err = dpaa_eth_init_rx_port(rxport, bp, port_fqs->rx_errq,
1347 port_fqs->rx_defq, port_fqs->rx_pcdq,
1348 &buf_layout[RX]);
1349
1350 return err;
1351}
1352
1353static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1354 struct bm_buffer *bmb, int cnt)
1355{
1356 int err;
1357
1358 err = bman_release(dpaa_bp->pool, bmb, cnt);
1359 /* Should never occur, address anyway to avoid leaking the buffers */
1360 if (WARN_ON(err) && dpaa_bp->free_buf_cb)
1361 while (cnt-- > 0)
1362 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1363
1364 return cnt;
1365}
1366
1367static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1368{
1369 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1370 struct dpaa_bp *dpaa_bp;
1371 int i = 0, j;
1372
1373 memset(bmb, 0, sizeof(bmb));
1374
1375 do {
1376 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1377 if (!dpaa_bp)
1378 return;
1379
1380 j = 0;
1381 do {
1382 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1383
1384 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1385
1386 j++; i++;
1387 } while (j < ARRAY_SIZE(bmb) &&
1388 !qm_sg_entry_is_final(&sgt[i - 1]) &&
1389 sgt[i - 1].bpid == sgt[i].bpid);
1390
1391 dpaa_bman_release(dpaa_bp, bmb, j);
1392 } while (!qm_sg_entry_is_final(&sgt[i - 1]));
1393}
1394
1395static void dpaa_fd_release(const struct net_device *net_dev,
1396 const struct qm_fd *fd)
1397{
1398 struct qm_sg_entry *sgt;
1399 struct dpaa_bp *dpaa_bp;
1400 struct bm_buffer bmb;
1401 dma_addr_t addr;
1402 void *vaddr;
1403
1404 bmb.data = 0;
1405 bm_buffer_set64(&bmb, qm_fd_addr(fd));
1406
1407 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1408 if (!dpaa_bp)
1409 return;
1410
1411 if (qm_fd_get_format(fd) == qm_fd_sg) {
1412 vaddr = phys_to_virt(qm_fd_addr(fd));
1413 sgt = vaddr + qm_fd_get_offset(fd);
1414
1415 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, qm_fd_addr(fd),
1416 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1417
1418 dpaa_release_sgt_members(sgt);
1419
1420 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev,
1421 virt_to_page(vaddr), 0, DPAA_BP_RAW_SIZE,
1422 DMA_FROM_DEVICE);
1423 if (dma_mapping_error(dpaa_bp->priv->rx_dma_dev, addr)) {
1424 netdev_err(net_dev, "DMA mapping failed\n");
1425 return;
1426 }
1427 bm_buffer_set64(&bmb, addr);
1428 }
1429
1430 dpaa_bman_release(dpaa_bp, &bmb, 1);
1431}
1432
1433static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1434 const union qm_mr_entry *msg)
1435{
1436 switch (msg->ern.rc & QM_MR_RC_MASK) {
1437 case QM_MR_RC_CGR_TAILDROP:
1438 percpu_priv->ern_cnt.cg_tdrop++;
1439 break;
1440 case QM_MR_RC_WRED:
1441 percpu_priv->ern_cnt.wred++;
1442 break;
1443 case QM_MR_RC_ERROR:
1444 percpu_priv->ern_cnt.err_cond++;
1445 break;
1446 case QM_MR_RC_ORPWINDOW_EARLY:
1447 percpu_priv->ern_cnt.early_window++;
1448 break;
1449 case QM_MR_RC_ORPWINDOW_LATE:
1450 percpu_priv->ern_cnt.late_window++;
1451 break;
1452 case QM_MR_RC_FQ_TAILDROP:
1453 percpu_priv->ern_cnt.fq_tdrop++;
1454 break;
1455 case QM_MR_RC_ORPWINDOW_RETIRED:
1456 percpu_priv->ern_cnt.fq_retired++;
1457 break;
1458 case QM_MR_RC_ORP_ZERO:
1459 percpu_priv->ern_cnt.orp_zero++;
1460 break;
1461 }
1462}
1463
1464/* Turn on HW checksum computation for this outgoing frame.
1465 * If the current protocol is not something we support in this regard
1466 * (or if the stack has already computed the SW checksum), we do nothing.
1467 *
1468 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1469 * otherwise.
1470 *
1471 * Note that this function may modify the fd->cmd field and the skb data buffer
1472 * (the Parse Results area).
1473 */
1474static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1475 struct sk_buff *skb,
1476 struct qm_fd *fd,
1477 void *parse_results)
1478{
1479 struct fman_prs_result *parse_result;
1480 u16 ethertype = ntohs(skb->protocol);
1481 struct ipv6hdr *ipv6h = NULL;
1482 struct iphdr *iph;
1483 int retval = 0;
1484 u8 l4_proto;
1485
1486 if (skb->ip_summed != CHECKSUM_PARTIAL)
1487 return 0;
1488
1489 /* Note: L3 csum seems to be already computed in sw, but we can't choose
1490 * L4 alone from the FM configuration anyway.
1491 */
1492
1493 /* Fill in some fields of the Parse Results array, so the FMan
1494 * can find them as if they came from the FMan Parser.
1495 */
1496 parse_result = (struct fman_prs_result *)parse_results;
1497
1498 /* If we're dealing with VLAN, get the real Ethernet type */
1499 if (ethertype == ETH_P_8021Q)
1500 ethertype = ntohs(skb_vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1501
1502 /* Fill in the relevant L3 parse result fields
1503 * and read the L4 protocol type
1504 */
1505 switch (ethertype) {
1506 case ETH_P_IP:
1507 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1508 iph = ip_hdr(skb);
1509 WARN_ON(!iph);
1510 l4_proto = iph->protocol;
1511 break;
1512 case ETH_P_IPV6:
1513 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1514 ipv6h = ipv6_hdr(skb);
1515 WARN_ON(!ipv6h);
1516 l4_proto = ipv6h->nexthdr;
1517 break;
1518 default:
1519 /* We shouldn't even be here */
1520 if (net_ratelimit())
1521 netif_alert(priv, tx_err, priv->net_dev,
1522 "Can't compute HW csum for L3 proto 0x%x\n",
1523 ntohs(skb->protocol));
1524 retval = -EIO;
1525 goto return_error;
1526 }
1527
1528 /* Fill in the relevant L4 parse result fields */
1529 switch (l4_proto) {
1530 case IPPROTO_UDP:
1531 parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1532 break;
1533 case IPPROTO_TCP:
1534 parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1535 break;
1536 default:
1537 if (net_ratelimit())
1538 netif_alert(priv, tx_err, priv->net_dev,
1539 "Can't compute HW csum for L4 proto 0x%x\n",
1540 l4_proto);
1541 retval = -EIO;
1542 goto return_error;
1543 }
1544
1545 /* At index 0 is IPOffset_1 as defined in the Parse Results */
1546 parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1547 parse_result->l4_off = (u8)skb_transport_offset(skb);
1548
1549 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1550 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
1551
1552 /* On P1023 and similar platforms fd->cmd interpretation could
1553 * be disabled by setting CONTEXT_A bit ICMD; currently this bit
1554 * is not set so we do not need to check; in the future, if/when
1555 * using context_a we need to check this bit
1556 */
1557
1558return_error:
1559 return retval;
1560}
1561
1562static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1563{
1564 struct net_device *net_dev = dpaa_bp->priv->net_dev;
1565 struct bm_buffer bmb[8];
1566 dma_addr_t addr;
1567 struct page *p;
1568 u8 i;
1569
1570 for (i = 0; i < 8; i++) {
1571 p = dev_alloc_pages(0);
1572 if (unlikely(!p)) {
1573 netdev_err(net_dev, "dev_alloc_pages() failed\n");
1574 goto release_previous_buffs;
1575 }
1576
1577 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, p, 0,
1578 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1579 if (unlikely(dma_mapping_error(dpaa_bp->priv->rx_dma_dev,
1580 addr))) {
1581 netdev_err(net_dev, "DMA map failed\n");
1582 goto release_previous_buffs;
1583 }
1584
1585 bmb[i].data = 0;
1586 bm_buffer_set64(&bmb[i], addr);
1587 }
1588
1589release_bufs:
1590 return dpaa_bman_release(dpaa_bp, bmb, i);
1591
1592release_previous_buffs:
1593 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1594
1595 bm_buffer_set64(&bmb[i], 0);
1596 /* Avoid releasing a completely null buffer; bman_release() requires
1597 * at least one buffer.
1598 */
1599 if (likely(i))
1600 goto release_bufs;
1601
1602 return 0;
1603}
1604
1605static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1606{
1607 int i;
1608
1609 /* Give each CPU an allotment of "config_count" buffers */
1610 for_each_possible_cpu(i) {
1611 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1612 int j;
1613
1614 /* Although we access another CPU's counters here
1615 * we do it at boot time so it is safe
1616 */
1617 for (j = 0; j < dpaa_bp->config_count; j += 8)
1618 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1619 }
1620 return 0;
1621}
1622
1623/* Add buffers/(pages) for Rx processing whenever bpool count falls below
1624 * REFILL_THRESHOLD.
1625 */
1626static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
1627{
1628 int count = *countptr;
1629 int new_bufs;
1630
1631 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1632 do {
1633 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1634 if (unlikely(!new_bufs)) {
1635 /* Avoid looping forever if we've temporarily
1636 * run out of memory. We'll try again at the
1637 * next NAPI cycle.
1638 */
1639 break;
1640 }
1641 count += new_bufs;
1642 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1643
1644 *countptr = count;
1645 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1646 return -ENOMEM;
1647 }
1648
1649 return 0;
1650}
1651
1652static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1653{
1654 struct dpaa_bp *dpaa_bp;
1655 int *countptr;
1656
1657 dpaa_bp = priv->dpaa_bp;
1658 if (!dpaa_bp)
1659 return -EINVAL;
1660 countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1661
1662 return dpaa_eth_refill_bpool(dpaa_bp, countptr);
1663}
1664
1665/* Cleanup function for outgoing frame descriptors that were built on Tx path,
1666 * either contiguous frames or scatter/gather ones.
1667 * Skb freeing is not handled here.
1668 *
1669 * This function may be called on error paths in the Tx function, so guard
1670 * against cases when not all fd relevant fields were filled in. To avoid
1671 * reading the invalid transmission timestamp for the error paths set ts to
1672 * false.
1673 *
1674 * Return the skb backpointer, since for S/G frames the buffer containing it
1675 * gets freed here.
1676 *
1677 * No skb backpointer is set when transmitting XDP frames. Cleanup the buffer
1678 * and return NULL in this case.
1679 */
1680static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
1681 const struct qm_fd *fd, bool ts)
1682{
1683 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1684 struct device *dev = priv->net_dev->dev.parent;
1685 struct skb_shared_hwtstamps shhwtstamps;
1686 dma_addr_t addr = qm_fd_addr(fd);
1687 void *vaddr = phys_to_virt(addr);
1688 const struct qm_sg_entry *sgt;
1689 struct dpaa_eth_swbp *swbp;
1690 struct sk_buff *skb;
1691 u64 ns;
1692 int i;
1693
1694 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1695 dma_unmap_page(priv->tx_dma_dev, addr,
1696 qm_fd_get_offset(fd) + DPAA_SGT_SIZE,
1697 dma_dir);
1698
1699 /* The sgt buffer has been allocated with netdev_alloc_frag(),
1700 * it's from lowmem.
1701 */
1702 sgt = vaddr + qm_fd_get_offset(fd);
1703
1704 /* sgt[0] is from lowmem, was dma_map_single()-ed */
1705 dma_unmap_single(priv->tx_dma_dev, qm_sg_addr(&sgt[0]),
1706 qm_sg_entry_get_len(&sgt[0]), dma_dir);
1707
1708 /* remaining pages were mapped with skb_frag_dma_map() */
1709 for (i = 1; (i < DPAA_SGT_MAX_ENTRIES) &&
1710 !qm_sg_entry_is_final(&sgt[i - 1]); i++) {
1711 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1712
1713 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[i]),
1714 qm_sg_entry_get_len(&sgt[i]), dma_dir);
1715 }
1716 } else {
1717 dma_unmap_single(priv->tx_dma_dev, addr,
1718 qm_fd_get_offset(fd) + qm_fd_get_length(fd),
1719 dma_dir);
1720 }
1721
1722 swbp = (struct dpaa_eth_swbp *)vaddr;
1723 skb = swbp->skb;
1724
1725 /* No skb backpointer is set when running XDP. An xdp_frame
1726 * backpointer is saved instead.
1727 */
1728 if (!skb) {
1729 xdp_return_frame(swbp->xdpf);
1730 return NULL;
1731 }
1732
1733 /* DMA unmapping is required before accessing the HW provided info */
1734 if (ts && priv->tx_tstamp &&
1735 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
1736 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1737
1738 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], vaddr,
1739 &ns)) {
1740 shhwtstamps.hwtstamp = ns_to_ktime(ns);
1741 skb_tstamp_tx(skb, &shhwtstamps);
1742 } else {
1743 dev_warn(dev, "fman_port_get_tstamp failed!\n");
1744 }
1745 }
1746
1747 if (qm_fd_get_format(fd) == qm_fd_sg)
1748 /* Free the page that we allocated on Tx for the SGT */
1749 free_pages((unsigned long)vaddr, 0);
1750
1751 return skb;
1752}
1753
1754static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
1755{
1756 /* The parser has run and performed L4 checksum validation.
1757 * We know there were no parser errors (and implicitly no
1758 * L4 csum error), otherwise we wouldn't be here.
1759 */
1760 if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1761 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1762 return CHECKSUM_UNNECESSARY;
1763
1764 /* We're here because either the parser didn't run or the L4 checksum
1765 * was not verified. This may include the case of a UDP frame with
1766 * checksum zero or an L4 proto other than TCP/UDP
1767 */
1768 return CHECKSUM_NONE;
1769}
1770
1771#define PTR_IS_ALIGNED(x, a) (IS_ALIGNED((unsigned long)(x), (a)))
1772
1773/* Build a linear skb around the received buffer.
1774 * We are guaranteed there is enough room at the end of the data buffer to
1775 * accommodate the shared info area of the skb.
1776 */
1777static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
1778 const struct qm_fd *fd)
1779{
1780 ssize_t fd_off = qm_fd_get_offset(fd);
1781 dma_addr_t addr = qm_fd_addr(fd);
1782 struct dpaa_bp *dpaa_bp;
1783 struct sk_buff *skb;
1784 void *vaddr;
1785
1786 vaddr = phys_to_virt(addr);
1787 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1788
1789 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1790 if (!dpaa_bp)
1791 goto free_buffer;
1792
1793 skb = build_skb(vaddr, dpaa_bp->size +
1794 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1795 if (WARN_ONCE(!skb, "Build skb failure on Rx\n"))
1796 goto free_buffer;
1797 skb_reserve(skb, fd_off);
1798 skb_put(skb, qm_fd_get_length(fd));
1799
1800 skb->ip_summed = rx_csum_offload(priv, fd);
1801
1802 return skb;
1803
1804free_buffer:
1805 free_pages((unsigned long)vaddr, 0);
1806 return NULL;
1807}
1808
1809/* Build an skb with the data of the first S/G entry in the linear portion and
1810 * the rest of the frame as skb fragments.
1811 *
1812 * The page fragment holding the S/G Table is recycled here.
1813 */
1814static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
1815 const struct qm_fd *fd)
1816{
1817 ssize_t fd_off = qm_fd_get_offset(fd);
1818 dma_addr_t addr = qm_fd_addr(fd);
1819 const struct qm_sg_entry *sgt;
1820 struct page *page, *head_page;
1821 struct dpaa_bp *dpaa_bp;
1822 void *vaddr, *sg_vaddr;
1823 struct sk_buff *skb;
1824 dma_addr_t sg_addr;
1825 int page_offset;
1826 unsigned int sz;
1827 int *count_ptr;
1828 int i, j;
1829
1830 vaddr = phys_to_virt(addr);
1831 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1832
1833 /* Iterate through the SGT entries and add data buffers to the skb */
1834 sgt = vaddr + fd_off;
1835 skb = NULL;
1836 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1837 /* Extension bit is not supported */
1838 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1839
1840 sg_addr = qm_sg_addr(&sgt[i]);
1841 sg_vaddr = phys_to_virt(sg_addr);
1842 WARN_ON(!PTR_IS_ALIGNED(sg_vaddr, SMP_CACHE_BYTES));
1843
1844 dma_unmap_page(priv->rx_dma_dev, sg_addr,
1845 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1846
1847 /* We may use multiple Rx pools */
1848 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1849 if (!dpaa_bp)
1850 goto free_buffers;
1851
1852 if (!skb) {
1853 sz = dpaa_bp->size +
1854 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1855 skb = build_skb(sg_vaddr, sz);
1856 if (WARN_ON(!skb))
1857 goto free_buffers;
1858
1859 skb->ip_summed = rx_csum_offload(priv, fd);
1860
1861 /* Make sure forwarded skbs will have enough space
1862 * on Tx, if extra headers are added.
1863 */
1864 WARN_ON(fd_off != priv->rx_headroom);
1865 /* The offset to data start within the buffer holding
1866 * the SGT should always be equal to the offset to data
1867 * start within the first buffer holding the frame.
1868 */
1869 WARN_ON_ONCE(fd_off != qm_sg_entry_get_off(&sgt[i]));
1870 skb_reserve(skb, fd_off);
1871 skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1872 } else {
1873 /* Not the first S/G entry; all data from buffer will
1874 * be added in an skb fragment; fragment index is offset
1875 * by one since first S/G entry was incorporated in the
1876 * linear part of the skb.
1877 *
1878 * Caution: 'page' may be a tail page.
1879 */
1880 page = virt_to_page(sg_vaddr);
1881 head_page = virt_to_head_page(sg_vaddr);
1882
1883 /* Compute offset of sg_vaddr in (possibly tail) page */
1884 page_offset = ((unsigned long)sg_vaddr &
1885 (PAGE_SIZE - 1)) +
1886 (page_address(page) - page_address(head_page));
1887
1888 /* Non-initial SGT entries should not have a buffer
1889 * offset.
1890 */
1891 WARN_ON_ONCE(qm_sg_entry_get_off(&sgt[i]));
1892
1893 /* skb_add_rx_frag() does no checking on the page; if
1894 * we pass it a tail page, we'll end up with
1895 * bad page accounting and eventually with segfaults.
1896 */
1897 skb_add_rx_frag(skb, i - 1, head_page, page_offset,
1898 qm_sg_entry_get_len(&sgt[i]),
1899 dpaa_bp->size);
1900 }
1901
1902 /* Update the pool count for the current {cpu x bpool} */
1903 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1904 (*count_ptr)--;
1905
1906 if (qm_sg_entry_is_final(&sgt[i]))
1907 break;
1908 }
1909 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1910
1911 /* free the SG table buffer */
1912 free_pages((unsigned long)vaddr, 0);
1913
1914 return skb;
1915
1916free_buffers:
1917 /* free all the SG entries */
1918 for (j = 0; j < DPAA_SGT_MAX_ENTRIES ; j++) {
1919 sg_addr = qm_sg_addr(&sgt[j]);
1920 sg_vaddr = phys_to_virt(sg_addr);
1921 /* all pages 0..i were unmaped */
1922 if (j > i)
1923 dma_unmap_page(priv->rx_dma_dev, qm_sg_addr(&sgt[j]),
1924 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1925 free_pages((unsigned long)sg_vaddr, 0);
1926 /* counters 0..i-1 were decremented */
1927 if (j >= i) {
1928 dpaa_bp = dpaa_bpid2pool(sgt[j].bpid);
1929 if (dpaa_bp) {
1930 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1931 (*count_ptr)--;
1932 }
1933 }
1934
1935 if (qm_sg_entry_is_final(&sgt[j]))
1936 break;
1937 }
1938 /* free the SGT fragment */
1939 free_pages((unsigned long)vaddr, 0);
1940
1941 return NULL;
1942}
1943
1944static int skb_to_contig_fd(struct dpaa_priv *priv,
1945 struct sk_buff *skb, struct qm_fd *fd,
1946 int *offset)
1947{
1948 struct net_device *net_dev = priv->net_dev;
1949 enum dma_data_direction dma_dir;
1950 struct dpaa_eth_swbp *swbp;
1951 unsigned char *buff_start;
1952 dma_addr_t addr;
1953 int err;
1954
1955 /* We are guaranteed to have at least tx_headroom bytes
1956 * available, so just use that for offset.
1957 */
1958 fd->bpid = FSL_DPAA_BPID_INV;
1959 buff_start = skb->data - priv->tx_headroom;
1960 dma_dir = DMA_TO_DEVICE;
1961
1962 swbp = (struct dpaa_eth_swbp *)buff_start;
1963 swbp->skb = skb;
1964
1965 /* Enable L3/L4 hardware checksum computation.
1966 *
1967 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1968 * need to write into the skb.
1969 */
1970 err = dpaa_enable_tx_csum(priv, skb, fd,
1971 buff_start + DPAA_TX_PRIV_DATA_SIZE);
1972 if (unlikely(err < 0)) {
1973 if (net_ratelimit())
1974 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1975 err);
1976 return err;
1977 }
1978
1979 /* Fill in the rest of the FD fields */
1980 qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1981 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1982
1983 /* Map the entire buffer size that may be seen by FMan, but no more */
1984 addr = dma_map_single(priv->tx_dma_dev, buff_start,
1985 priv->tx_headroom + skb->len, dma_dir);
1986 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
1987 if (net_ratelimit())
1988 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1989 return -EINVAL;
1990 }
1991 qm_fd_addr_set64(fd, addr);
1992
1993 return 0;
1994}
1995
1996static int skb_to_sg_fd(struct dpaa_priv *priv,
1997 struct sk_buff *skb, struct qm_fd *fd)
1998{
1999 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
2000 const int nr_frags = skb_shinfo(skb)->nr_frags;
2001 struct net_device *net_dev = priv->net_dev;
2002 struct dpaa_eth_swbp *swbp;
2003 struct qm_sg_entry *sgt;
2004 void *buff_start;
2005 skb_frag_t *frag;
2006 dma_addr_t addr;
2007 size_t frag_len;
2008 struct page *p;
2009 int i, j, err;
2010
2011 /* get a page to store the SGTable */
2012 p = dev_alloc_pages(0);
2013 if (unlikely(!p)) {
2014 netdev_err(net_dev, "dev_alloc_pages() failed\n");
2015 return -ENOMEM;
2016 }
2017 buff_start = page_address(p);
2018
2019 /* Enable L3/L4 hardware checksum computation.
2020 *
2021 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
2022 * need to write into the skb.
2023 */
2024 err = dpaa_enable_tx_csum(priv, skb, fd,
2025 buff_start + DPAA_TX_PRIV_DATA_SIZE);
2026 if (unlikely(err < 0)) {
2027 if (net_ratelimit())
2028 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
2029 err);
2030 goto csum_failed;
2031 }
2032
2033 /* SGT[0] is used by the linear part */
2034 sgt = (struct qm_sg_entry *)(buff_start + priv->tx_headroom);
2035 frag_len = skb_headlen(skb);
2036 qm_sg_entry_set_len(&sgt[0], frag_len);
2037 sgt[0].bpid = FSL_DPAA_BPID_INV;
2038 sgt[0].offset = 0;
2039 addr = dma_map_single(priv->tx_dma_dev, skb->data,
2040 skb_headlen(skb), dma_dir);
2041 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2042 netdev_err(priv->net_dev, "DMA mapping failed\n");
2043 err = -EINVAL;
2044 goto sg0_map_failed;
2045 }
2046 qm_sg_entry_set64(&sgt[0], addr);
2047
2048 /* populate the rest of SGT entries */
2049 for (i = 0; i < nr_frags; i++) {
2050 frag = &skb_shinfo(skb)->frags[i];
2051 frag_len = skb_frag_size(frag);
2052 WARN_ON(!skb_frag_page(frag));
2053 addr = skb_frag_dma_map(priv->tx_dma_dev, frag, 0,
2054 frag_len, dma_dir);
2055 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2056 netdev_err(priv->net_dev, "DMA mapping failed\n");
2057 err = -EINVAL;
2058 goto sg_map_failed;
2059 }
2060
2061 qm_sg_entry_set_len(&sgt[i + 1], frag_len);
2062 sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
2063 sgt[i + 1].offset = 0;
2064
2065 /* keep the offset in the address */
2066 qm_sg_entry_set64(&sgt[i + 1], addr);
2067 }
2068
2069 /* Set the final bit in the last used entry of the SGT */
2070 qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
2071
2072 /* set fd offset to priv->tx_headroom */
2073 qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
2074
2075 /* DMA map the SGT page */
2076 swbp = (struct dpaa_eth_swbp *)buff_start;
2077 swbp->skb = skb;
2078
2079 addr = dma_map_page(priv->tx_dma_dev, p, 0,
2080 priv->tx_headroom + DPAA_SGT_SIZE, dma_dir);
2081 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2082 netdev_err(priv->net_dev, "DMA mapping failed\n");
2083 err = -EINVAL;
2084 goto sgt_map_failed;
2085 }
2086
2087 fd->bpid = FSL_DPAA_BPID_INV;
2088 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
2089 qm_fd_addr_set64(fd, addr);
2090
2091 return 0;
2092
2093sgt_map_failed:
2094sg_map_failed:
2095 for (j = 0; j < i; j++)
2096 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[j]),
2097 qm_sg_entry_get_len(&sgt[j]), dma_dir);
2098sg0_map_failed:
2099csum_failed:
2100 free_pages((unsigned long)buff_start, 0);
2101
2102 return err;
2103}
2104
2105static inline int dpaa_xmit(struct dpaa_priv *priv,
2106 struct rtnl_link_stats64 *percpu_stats,
2107 int queue,
2108 struct qm_fd *fd)
2109{
2110 struct qman_fq *egress_fq;
2111 int err, i;
2112
2113 egress_fq = priv->egress_fqs[queue];
2114 if (fd->bpid == FSL_DPAA_BPID_INV)
2115 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2116
2117 /* Trace this Tx fd */
2118 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2119
2120 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2121 err = qman_enqueue(egress_fq, fd);
2122 if (err != -EBUSY)
2123 break;
2124 }
2125
2126 if (unlikely(err < 0)) {
2127 percpu_stats->tx_fifo_errors++;
2128 return err;
2129 }
2130
2131 percpu_stats->tx_packets++;
2132 percpu_stats->tx_bytes += qm_fd_get_length(fd);
2133
2134 return 0;
2135}
2136
2137#ifdef CONFIG_DPAA_ERRATUM_A050385
2138static int dpaa_a050385_wa_skb(struct net_device *net_dev, struct sk_buff **s)
2139{
2140 struct dpaa_priv *priv = netdev_priv(net_dev);
2141 struct sk_buff *new_skb, *skb = *s;
2142 unsigned char *start, i;
2143
2144 /* check linear buffer alignment */
2145 if (!PTR_IS_ALIGNED(skb->data, DPAA_A050385_ALIGN))
2146 goto workaround;
2147
2148 /* linear buffers just need to have an aligned start */
2149 if (!skb_is_nonlinear(skb))
2150 return 0;
2151
2152 /* linear data size for nonlinear skbs needs to be aligned */
2153 if (!IS_ALIGNED(skb_headlen(skb), DPAA_A050385_ALIGN))
2154 goto workaround;
2155
2156 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2157 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2158
2159 /* all fragments need to have aligned start addresses */
2160 if (!IS_ALIGNED(skb_frag_off(frag), DPAA_A050385_ALIGN))
2161 goto workaround;
2162
2163 /* all but last fragment need to have aligned sizes */
2164 if (!IS_ALIGNED(skb_frag_size(frag), DPAA_A050385_ALIGN) &&
2165 (i < skb_shinfo(skb)->nr_frags - 1))
2166 goto workaround;
2167 }
2168
2169 return 0;
2170
2171workaround:
2172 /* copy all the skb content into a new linear buffer */
2173 new_skb = netdev_alloc_skb(net_dev, skb->len + DPAA_A050385_ALIGN - 1 +
2174 priv->tx_headroom);
2175 if (!new_skb)
2176 return -ENOMEM;
2177
2178 /* NET_SKB_PAD bytes already reserved, adding up to tx_headroom */
2179 skb_reserve(new_skb, priv->tx_headroom - NET_SKB_PAD);
2180
2181 /* Workaround for DPAA_A050385 requires data start to be aligned */
2182 start = PTR_ALIGN(new_skb->data, DPAA_A050385_ALIGN);
2183 if (start - new_skb->data)
2184 skb_reserve(new_skb, start - new_skb->data);
2185
2186 skb_put(new_skb, skb->len);
2187 skb_copy_bits(skb, 0, new_skb->data, skb->len);
2188 skb_copy_header(new_skb, skb);
2189 new_skb->dev = skb->dev;
2190
2191 /* Copy relevant timestamp info from the old skb to the new */
2192 if (priv->tx_tstamp) {
2193 skb_shinfo(new_skb)->tx_flags = skb_shinfo(skb)->tx_flags;
2194 skb_shinfo(new_skb)->hwtstamps = skb_shinfo(skb)->hwtstamps;
2195 skb_shinfo(new_skb)->tskey = skb_shinfo(skb)->tskey;
2196 if (skb->sk)
2197 skb_set_owner_w(new_skb, skb->sk);
2198 }
2199
2200 /* We move the headroom when we align it so we have to reset the
2201 * network and transport header offsets relative to the new data
2202 * pointer. The checksum offload relies on these offsets.
2203 */
2204 skb_set_network_header(new_skb, skb_network_offset(skb));
2205 skb_set_transport_header(new_skb, skb_transport_offset(skb));
2206
2207 dev_kfree_skb(skb);
2208 *s = new_skb;
2209
2210 return 0;
2211}
2212
2213static int dpaa_a050385_wa_xdpf(struct dpaa_priv *priv,
2214 struct xdp_frame **init_xdpf)
2215{
2216 struct xdp_frame *new_xdpf, *xdpf = *init_xdpf;
2217 void *new_buff, *aligned_data;
2218 struct page *p;
2219 u32 data_shift;
2220 int headroom;
2221
2222 /* Check the data alignment and make sure the headroom is large
2223 * enough to store the xdpf backpointer. Use an aligned headroom
2224 * value.
2225 *
2226 * Due to alignment constraints, we give XDP access to the full 256
2227 * byte frame headroom. If the XDP program uses all of it, copy the
2228 * data to a new buffer and make room for storing the backpointer.
2229 */
2230 if (PTR_IS_ALIGNED(xdpf->data, DPAA_FD_DATA_ALIGNMENT) &&
2231 xdpf->headroom >= priv->tx_headroom) {
2232 xdpf->headroom = priv->tx_headroom;
2233 return 0;
2234 }
2235
2236 /* Try to move the data inside the buffer just enough to align it and
2237 * store the xdpf backpointer. If the available headroom isn't large
2238 * enough, resort to allocating a new buffer and copying the data.
2239 */
2240 aligned_data = PTR_ALIGN_DOWN(xdpf->data, DPAA_FD_DATA_ALIGNMENT);
2241 data_shift = xdpf->data - aligned_data;
2242
2243 /* The XDP frame's headroom needs to be large enough to accommodate
2244 * shifting the data as well as storing the xdpf backpointer.
2245 */
2246 if (xdpf->headroom >= data_shift + priv->tx_headroom) {
2247 memmove(aligned_data, xdpf->data, xdpf->len);
2248 xdpf->data = aligned_data;
2249 xdpf->headroom = priv->tx_headroom;
2250 return 0;
2251 }
2252
2253 /* The new xdp_frame is stored in the new buffer. Reserve enough space
2254 * in the headroom for storing it along with the driver's private
2255 * info. The headroom needs to be aligned to DPAA_FD_DATA_ALIGNMENT to
2256 * guarantee the data's alignment in the buffer.
2257 */
2258 headroom = ALIGN(sizeof(*new_xdpf) + priv->tx_headroom,
2259 DPAA_FD_DATA_ALIGNMENT);
2260
2261 /* Assure the extended headroom and data don't overflow the buffer,
2262 * while maintaining the mandatory tailroom.
2263 */
2264 if (headroom + xdpf->len > DPAA_BP_RAW_SIZE -
2265 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
2266 return -ENOMEM;
2267
2268 p = dev_alloc_pages(0);
2269 if (unlikely(!p))
2270 return -ENOMEM;
2271
2272 /* Copy the data to the new buffer at a properly aligned offset */
2273 new_buff = page_address(p);
2274 memcpy(new_buff + headroom, xdpf->data, xdpf->len);
2275
2276 /* Create an XDP frame around the new buffer in a similar fashion
2277 * to xdp_convert_buff_to_frame.
2278 */
2279 new_xdpf = new_buff;
2280 new_xdpf->data = new_buff + headroom;
2281 new_xdpf->len = xdpf->len;
2282 new_xdpf->headroom = priv->tx_headroom;
2283 new_xdpf->frame_sz = DPAA_BP_RAW_SIZE;
2284 new_xdpf->mem.type = MEM_TYPE_PAGE_ORDER0;
2285
2286 /* Release the initial buffer */
2287 xdp_return_frame_rx_napi(xdpf);
2288
2289 *init_xdpf = new_xdpf;
2290 return 0;
2291}
2292#endif
2293
2294static netdev_tx_t
2295dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2296{
2297 const int queue_mapping = skb_get_queue_mapping(skb);
2298 struct rtnl_link_stats64 *percpu_stats;
2299 struct dpaa_percpu_priv *percpu_priv;
2300 struct netdev_queue *txq;
2301 struct dpaa_priv *priv;
2302 struct qm_fd fd;
2303 bool nonlinear;
2304 int offset = 0;
2305 int err = 0;
2306
2307 priv = netdev_priv(net_dev);
2308 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2309 percpu_stats = &percpu_priv->stats;
2310
2311 qm_fd_clear_fd(&fd);
2312
2313 /* Packet data is always read as 32-bit words, so zero out any part of
2314 * the skb which might be sent if we have to pad the packet
2315 */
2316 if (__skb_put_padto(skb, ETH_ZLEN, false))
2317 goto enomem;
2318
2319 nonlinear = skb_is_nonlinear(skb);
2320 if (!nonlinear) {
2321 /* We're going to store the skb backpointer at the beginning
2322 * of the data buffer, so we need a privately owned skb
2323 *
2324 * We've made sure skb is not shared in dev->priv_flags,
2325 * we need to verify the skb head is not cloned
2326 */
2327 if (skb_cow_head(skb, priv->tx_headroom))
2328 goto enomem;
2329
2330 WARN_ON(skb_is_nonlinear(skb));
2331 }
2332
2333 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2334 * make sure we don't feed FMan with more fragments than it supports.
2335 */
2336 if (unlikely(nonlinear &&
2337 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
2338 /* If the egress skb contains more fragments than we support
2339 * we have no choice but to linearize it ourselves.
2340 */
2341 if (__skb_linearize(skb))
2342 goto enomem;
2343
2344 nonlinear = skb_is_nonlinear(skb);
2345 }
2346
2347#ifdef CONFIG_DPAA_ERRATUM_A050385
2348 if (unlikely(fman_has_errata_a050385())) {
2349 if (dpaa_a050385_wa_skb(net_dev, &skb))
2350 goto enomem;
2351 nonlinear = skb_is_nonlinear(skb);
2352 }
2353#endif
2354
2355 if (nonlinear) {
2356 /* Just create a S/G fd based on the skb */
2357 err = skb_to_sg_fd(priv, skb, &fd);
2358 percpu_priv->tx_frag_skbuffs++;
2359 } else {
2360 /* Create a contig FD from this skb */
2361 err = skb_to_contig_fd(priv, skb, &fd, &offset);
2362 }
2363 if (unlikely(err < 0))
2364 goto skb_to_fd_failed;
2365
2366 txq = netdev_get_tx_queue(net_dev, queue_mapping);
2367
2368 /* LLTX requires to do our own update of trans_start */
2369 txq_trans_cond_update(txq);
2370
2371 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
2372 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD);
2373 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2374 }
2375
2376 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2377 return NETDEV_TX_OK;
2378
2379 dpaa_cleanup_tx_fd(priv, &fd, false);
2380skb_to_fd_failed:
2381enomem:
2382 percpu_stats->tx_errors++;
2383 dev_kfree_skb(skb);
2384 return NETDEV_TX_OK;
2385}
2386
2387static void dpaa_rx_error(struct net_device *net_dev,
2388 const struct dpaa_priv *priv,
2389 struct dpaa_percpu_priv *percpu_priv,
2390 const struct qm_fd *fd,
2391 u32 fqid)
2392{
2393 if (net_ratelimit())
2394 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2395 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2396
2397 percpu_priv->stats.rx_errors++;
2398
2399 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2400 percpu_priv->rx_errors.dme++;
2401 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2402 percpu_priv->rx_errors.fpe++;
2403 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2404 percpu_priv->rx_errors.fse++;
2405 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2406 percpu_priv->rx_errors.phe++;
2407
2408 dpaa_fd_release(net_dev, fd);
2409}
2410
2411static void dpaa_tx_error(struct net_device *net_dev,
2412 const struct dpaa_priv *priv,
2413 struct dpaa_percpu_priv *percpu_priv,
2414 const struct qm_fd *fd,
2415 u32 fqid)
2416{
2417 struct sk_buff *skb;
2418
2419 if (net_ratelimit())
2420 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2421 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2422
2423 percpu_priv->stats.tx_errors++;
2424
2425 skb = dpaa_cleanup_tx_fd(priv, fd, false);
2426 dev_kfree_skb(skb);
2427}
2428
2429static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2430{
2431 struct dpaa_napi_portal *np =
2432 container_of(napi, struct dpaa_napi_portal, napi);
2433 int cleaned;
2434
2435 np->xdp_act = 0;
2436
2437 cleaned = qman_p_poll_dqrr(np->p, budget);
2438
2439 if (np->xdp_act & XDP_REDIRECT)
2440 xdp_do_flush();
2441
2442 if (cleaned < budget) {
2443 napi_complete_done(napi, cleaned);
2444 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2445 } else if (np->down) {
2446 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2447 }
2448
2449 return cleaned;
2450}
2451
2452static void dpaa_tx_conf(struct net_device *net_dev,
2453 const struct dpaa_priv *priv,
2454 struct dpaa_percpu_priv *percpu_priv,
2455 const struct qm_fd *fd,
2456 u32 fqid)
2457{
2458 struct sk_buff *skb;
2459
2460 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2461 if (net_ratelimit())
2462 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2463 be32_to_cpu(fd->status) &
2464 FM_FD_STAT_TX_ERRORS);
2465
2466 percpu_priv->stats.tx_errors++;
2467 }
2468
2469 percpu_priv->tx_confirm++;
2470
2471 skb = dpaa_cleanup_tx_fd(priv, fd, true);
2472
2473 consume_skb(skb);
2474}
2475
2476static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2477 struct qman_portal *portal, bool sched_napi)
2478{
2479 if (sched_napi) {
2480 /* Disable QMan IRQ and invoke NAPI */
2481 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2482
2483 percpu_priv->np.p = portal;
2484 napi_schedule(&percpu_priv->np.napi);
2485 percpu_priv->in_interrupt++;
2486 return 1;
2487 }
2488 return 0;
2489}
2490
2491static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2492 struct qman_fq *fq,
2493 const struct qm_dqrr_entry *dq,
2494 bool sched_napi)
2495{
2496 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2497 struct dpaa_percpu_priv *percpu_priv;
2498 struct net_device *net_dev;
2499 struct dpaa_bp *dpaa_bp;
2500 struct dpaa_priv *priv;
2501
2502 net_dev = dpaa_fq->net_dev;
2503 priv = netdev_priv(net_dev);
2504 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2505 if (!dpaa_bp)
2506 return qman_cb_dqrr_consume;
2507
2508 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2509
2510 if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
2511 return qman_cb_dqrr_stop;
2512
2513 dpaa_eth_refill_bpools(priv);
2514 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2515
2516 return qman_cb_dqrr_consume;
2517}
2518
2519static int dpaa_xdp_xmit_frame(struct net_device *net_dev,
2520 struct xdp_frame *xdpf)
2521{
2522 struct dpaa_priv *priv = netdev_priv(net_dev);
2523 struct rtnl_link_stats64 *percpu_stats;
2524 struct dpaa_percpu_priv *percpu_priv;
2525 struct dpaa_eth_swbp *swbp;
2526 struct netdev_queue *txq;
2527 void *buff_start;
2528 struct qm_fd fd;
2529 dma_addr_t addr;
2530 int err;
2531
2532 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2533 percpu_stats = &percpu_priv->stats;
2534
2535#ifdef CONFIG_DPAA_ERRATUM_A050385
2536 if (unlikely(fman_has_errata_a050385())) {
2537 if (dpaa_a050385_wa_xdpf(priv, &xdpf)) {
2538 err = -ENOMEM;
2539 goto out_error;
2540 }
2541 }
2542#endif
2543
2544 if (xdpf->headroom < DPAA_TX_PRIV_DATA_SIZE) {
2545 err = -EINVAL;
2546 goto out_error;
2547 }
2548
2549 buff_start = xdpf->data - xdpf->headroom;
2550
2551 /* Leave empty the skb backpointer at the start of the buffer.
2552 * Save the XDP frame for easy cleanup on confirmation.
2553 */
2554 swbp = (struct dpaa_eth_swbp *)buff_start;
2555 swbp->skb = NULL;
2556 swbp->xdpf = xdpf;
2557
2558 qm_fd_clear_fd(&fd);
2559 fd.bpid = FSL_DPAA_BPID_INV;
2560 fd.cmd |= cpu_to_be32(FM_FD_CMD_FCO);
2561 qm_fd_set_contig(&fd, xdpf->headroom, xdpf->len);
2562
2563 addr = dma_map_single(priv->tx_dma_dev, buff_start,
2564 xdpf->headroom + xdpf->len,
2565 DMA_TO_DEVICE);
2566 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2567 err = -EINVAL;
2568 goto out_error;
2569 }
2570
2571 qm_fd_addr_set64(&fd, addr);
2572
2573 /* Bump the trans_start */
2574 txq = netdev_get_tx_queue(net_dev, smp_processor_id());
2575 txq_trans_cond_update(txq);
2576
2577 err = dpaa_xmit(priv, percpu_stats, smp_processor_id(), &fd);
2578 if (err) {
2579 dma_unmap_single(priv->tx_dma_dev, addr,
2580 qm_fd_get_offset(&fd) + qm_fd_get_length(&fd),
2581 DMA_TO_DEVICE);
2582 goto out_error;
2583 }
2584
2585 return 0;
2586
2587out_error:
2588 percpu_stats->tx_errors++;
2589 return err;
2590}
2591
2592static u32 dpaa_run_xdp(struct dpaa_priv *priv, struct qm_fd *fd, void *vaddr,
2593 struct dpaa_fq *dpaa_fq, unsigned int *xdp_meta_len)
2594{
2595 ssize_t fd_off = qm_fd_get_offset(fd);
2596 struct bpf_prog *xdp_prog;
2597 struct xdp_frame *xdpf;
2598 struct xdp_buff xdp;
2599 u32 xdp_act;
2600 int err;
2601
2602 xdp_prog = READ_ONCE(priv->xdp_prog);
2603 if (!xdp_prog)
2604 return XDP_PASS;
2605
2606 xdp_init_buff(&xdp, DPAA_BP_RAW_SIZE - DPAA_TX_PRIV_DATA_SIZE,
2607 &dpaa_fq->xdp_rxq);
2608 xdp_prepare_buff(&xdp, vaddr + fd_off - XDP_PACKET_HEADROOM,
2609 XDP_PACKET_HEADROOM, qm_fd_get_length(fd), true);
2610
2611 /* We reserve a fixed headroom of 256 bytes under the erratum and we
2612 * offer it all to XDP programs to use. If no room is left for the
2613 * xdpf backpointer on TX, we will need to copy the data.
2614 * Disable metadata support since data realignments might be required
2615 * and the information can be lost.
2616 */
2617#ifdef CONFIG_DPAA_ERRATUM_A050385
2618 if (unlikely(fman_has_errata_a050385())) {
2619 xdp_set_data_meta_invalid(&xdp);
2620 xdp.data_hard_start = vaddr;
2621 xdp.frame_sz = DPAA_BP_RAW_SIZE;
2622 }
2623#endif
2624
2625 xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
2626
2627 /* Update the length and the offset of the FD */
2628 qm_fd_set_contig(fd, xdp.data - vaddr, xdp.data_end - xdp.data);
2629
2630 switch (xdp_act) {
2631 case XDP_PASS:
2632#ifdef CONFIG_DPAA_ERRATUM_A050385
2633 *xdp_meta_len = xdp_data_meta_unsupported(&xdp) ? 0 :
2634 xdp.data - xdp.data_meta;
2635#else
2636 *xdp_meta_len = xdp.data - xdp.data_meta;
2637#endif
2638 break;
2639 case XDP_TX:
2640 /* We can access the full headroom when sending the frame
2641 * back out
2642 */
2643 xdp.data_hard_start = vaddr;
2644 xdp.frame_sz = DPAA_BP_RAW_SIZE;
2645 xdpf = xdp_convert_buff_to_frame(&xdp);
2646 if (unlikely(!xdpf)) {
2647 free_pages((unsigned long)vaddr, 0);
2648 break;
2649 }
2650
2651 if (dpaa_xdp_xmit_frame(priv->net_dev, xdpf))
2652 xdp_return_frame_rx_napi(xdpf);
2653
2654 break;
2655 case XDP_REDIRECT:
2656 /* Allow redirect to use the full headroom */
2657 xdp.data_hard_start = vaddr;
2658 xdp.frame_sz = DPAA_BP_RAW_SIZE;
2659
2660 err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
2661 if (err) {
2662 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
2663 free_pages((unsigned long)vaddr, 0);
2664 }
2665 break;
2666 default:
2667 bpf_warn_invalid_xdp_action(priv->net_dev, xdp_prog, xdp_act);
2668 fallthrough;
2669 case XDP_ABORTED:
2670 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
2671 fallthrough;
2672 case XDP_DROP:
2673 /* Free the buffer */
2674 free_pages((unsigned long)vaddr, 0);
2675 break;
2676 }
2677
2678 return xdp_act;
2679}
2680
2681static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2682 struct qman_fq *fq,
2683 const struct qm_dqrr_entry *dq,
2684 bool sched_napi)
2685{
2686 bool ts_valid = false, hash_valid = false;
2687 struct skb_shared_hwtstamps *shhwtstamps;
2688 unsigned int skb_len, xdp_meta_len = 0;
2689 struct rtnl_link_stats64 *percpu_stats;
2690 struct dpaa_percpu_priv *percpu_priv;
2691 const struct qm_fd *fd = &dq->fd;
2692 dma_addr_t addr = qm_fd_addr(fd);
2693 struct dpaa_napi_portal *np;
2694 enum qm_fd_format fd_format;
2695 struct net_device *net_dev;
2696 u32 fd_status, hash_offset;
2697 struct qm_sg_entry *sgt;
2698 struct dpaa_bp *dpaa_bp;
2699 struct dpaa_fq *dpaa_fq;
2700 struct dpaa_priv *priv;
2701 struct sk_buff *skb;
2702 int *count_ptr;
2703 u32 xdp_act;
2704 void *vaddr;
2705 u32 hash;
2706 u64 ns;
2707
2708 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2709 fd_status = be32_to_cpu(fd->status);
2710 fd_format = qm_fd_get_format(fd);
2711 net_dev = dpaa_fq->net_dev;
2712 priv = netdev_priv(net_dev);
2713 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2714 if (!dpaa_bp)
2715 return qman_cb_dqrr_consume;
2716
2717 /* Trace the Rx fd */
2718 trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2719
2720 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2721 percpu_stats = &percpu_priv->stats;
2722 np = &percpu_priv->np;
2723
2724 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi)))
2725 return qman_cb_dqrr_stop;
2726
2727 /* Make sure we didn't run out of buffers */
2728 if (unlikely(dpaa_eth_refill_bpools(priv))) {
2729 /* Unable to refill the buffer pool due to insufficient
2730 * system memory. Just release the frame back into the pool,
2731 * otherwise we'll soon end up with an empty buffer pool.
2732 */
2733 dpaa_fd_release(net_dev, &dq->fd);
2734 return qman_cb_dqrr_consume;
2735 }
2736
2737 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2738 if (net_ratelimit())
2739 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2740 fd_status & FM_FD_STAT_RX_ERRORS);
2741
2742 percpu_stats->rx_errors++;
2743 dpaa_fd_release(net_dev, fd);
2744 return qman_cb_dqrr_consume;
2745 }
2746
2747 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
2748 DMA_FROM_DEVICE);
2749
2750 /* prefetch the first 64 bytes of the frame or the SGT start */
2751 vaddr = phys_to_virt(addr);
2752 prefetch(vaddr + qm_fd_get_offset(fd));
2753
2754 /* The only FD types that we may receive are contig and S/G */
2755 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2756
2757 /* Account for either the contig buffer or the SGT buffer (depending on
2758 * which case we were in) having been removed from the pool.
2759 */
2760 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2761 (*count_ptr)--;
2762
2763 /* Extract the timestamp stored in the headroom before running XDP */
2764 if (priv->rx_tstamp) {
2765 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns))
2766 ts_valid = true;
2767 else
2768 WARN_ONCE(1, "fman_port_get_tstamp failed!\n");
2769 }
2770
2771 /* Extract the hash stored in the headroom before running XDP */
2772 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
2773 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
2774 &hash_offset)) {
2775 hash = be32_to_cpu(*(__be32 *)(vaddr + hash_offset));
2776 hash_valid = true;
2777 }
2778
2779 if (likely(fd_format == qm_fd_contig)) {
2780 xdp_act = dpaa_run_xdp(priv, (struct qm_fd *)fd, vaddr,
2781 dpaa_fq, &xdp_meta_len);
2782 np->xdp_act |= xdp_act;
2783 if (xdp_act != XDP_PASS) {
2784 percpu_stats->rx_packets++;
2785 percpu_stats->rx_bytes += qm_fd_get_length(fd);
2786 return qman_cb_dqrr_consume;
2787 }
2788 skb = contig_fd_to_skb(priv, fd);
2789 } else {
2790 /* XDP doesn't support S/G frames. Return the fragments to the
2791 * buffer pool and release the SGT.
2792 */
2793 if (READ_ONCE(priv->xdp_prog)) {
2794 WARN_ONCE(1, "S/G frames not supported under XDP\n");
2795 sgt = vaddr + qm_fd_get_offset(fd);
2796 dpaa_release_sgt_members(sgt);
2797 free_pages((unsigned long)vaddr, 0);
2798 return qman_cb_dqrr_consume;
2799 }
2800 skb = sg_fd_to_skb(priv, fd);
2801 }
2802 if (!skb)
2803 return qman_cb_dqrr_consume;
2804
2805 if (xdp_meta_len)
2806 skb_metadata_set(skb, xdp_meta_len);
2807
2808 /* Set the previously extracted timestamp */
2809 if (ts_valid) {
2810 shhwtstamps = skb_hwtstamps(skb);
2811 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2812 shhwtstamps->hwtstamp = ns_to_ktime(ns);
2813 }
2814
2815 skb->protocol = eth_type_trans(skb, net_dev);
2816
2817 /* Set the previously extracted hash */
2818 if (hash_valid) {
2819 enum pkt_hash_types type;
2820
2821 /* if L4 exists, it was used in the hash generation */
2822 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
2823 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
2824 skb_set_hash(skb, hash, type);
2825 }
2826
2827 skb_len = skb->len;
2828
2829 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
2830 percpu_stats->rx_dropped++;
2831 return qman_cb_dqrr_consume;
2832 }
2833
2834 percpu_stats->rx_packets++;
2835 percpu_stats->rx_bytes += skb_len;
2836
2837 return qman_cb_dqrr_consume;
2838}
2839
2840static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2841 struct qman_fq *fq,
2842 const struct qm_dqrr_entry *dq,
2843 bool sched_napi)
2844{
2845 struct dpaa_percpu_priv *percpu_priv;
2846 struct net_device *net_dev;
2847 struct dpaa_priv *priv;
2848
2849 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2850 priv = netdev_priv(net_dev);
2851
2852 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2853
2854 if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
2855 return qman_cb_dqrr_stop;
2856
2857 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2858
2859 return qman_cb_dqrr_consume;
2860}
2861
2862static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2863 struct qman_fq *fq,
2864 const struct qm_dqrr_entry *dq,
2865 bool sched_napi)
2866{
2867 struct dpaa_percpu_priv *percpu_priv;
2868 struct net_device *net_dev;
2869 struct dpaa_priv *priv;
2870
2871 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2872 priv = netdev_priv(net_dev);
2873
2874 /* Trace the fd */
2875 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2876
2877 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2878
2879 if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
2880 return qman_cb_dqrr_stop;
2881
2882 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2883
2884 return qman_cb_dqrr_consume;
2885}
2886
2887static void egress_ern(struct qman_portal *portal,
2888 struct qman_fq *fq,
2889 const union qm_mr_entry *msg)
2890{
2891 const struct qm_fd *fd = &msg->ern.fd;
2892 struct dpaa_percpu_priv *percpu_priv;
2893 const struct dpaa_priv *priv;
2894 struct net_device *net_dev;
2895 struct sk_buff *skb;
2896
2897 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2898 priv = netdev_priv(net_dev);
2899 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2900
2901 percpu_priv->stats.tx_dropped++;
2902 percpu_priv->stats.tx_fifo_errors++;
2903 count_ern(percpu_priv, msg);
2904
2905 skb = dpaa_cleanup_tx_fd(priv, fd, false);
2906 dev_kfree_skb_any(skb);
2907}
2908
2909static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2910 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2911 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2912 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2913 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2914 .egress_ern = { .cb = { .ern = egress_ern } }
2915};
2916
2917static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2918{
2919 struct dpaa_percpu_priv *percpu_priv;
2920 int i;
2921
2922 for_each_online_cpu(i) {
2923 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2924
2925 percpu_priv->np.down = false;
2926 napi_enable(&percpu_priv->np.napi);
2927 }
2928}
2929
2930static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2931{
2932 struct dpaa_percpu_priv *percpu_priv;
2933 int i;
2934
2935 for_each_online_cpu(i) {
2936 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2937
2938 percpu_priv->np.down = true;
2939 napi_disable(&percpu_priv->np.napi);
2940 }
2941}
2942
2943static int dpaa_open(struct net_device *net_dev)
2944{
2945 struct mac_device *mac_dev;
2946 struct dpaa_priv *priv;
2947 int err, i;
2948
2949 priv = netdev_priv(net_dev);
2950 mac_dev = priv->mac_dev;
2951 dpaa_eth_napi_enable(priv);
2952
2953 err = phylink_of_phy_connect(mac_dev->phylink,
2954 mac_dev->dev->of_node, 0);
2955 if (err)
2956 goto phy_init_failed;
2957
2958 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2959 err = fman_port_enable(mac_dev->port[i]);
2960 if (err)
2961 goto mac_start_failed;
2962 }
2963
2964 err = priv->mac_dev->enable(mac_dev->fman_mac);
2965 if (err < 0) {
2966 netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
2967 goto mac_start_failed;
2968 }
2969 phylink_start(mac_dev->phylink);
2970
2971 netif_tx_start_all_queues(net_dev);
2972
2973 return 0;
2974
2975mac_start_failed:
2976 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2977 fman_port_disable(mac_dev->port[i]);
2978 phylink_disconnect_phy(mac_dev->phylink);
2979
2980phy_init_failed:
2981 dpaa_eth_napi_disable(priv);
2982
2983 return err;
2984}
2985
2986static int dpaa_eth_stop(struct net_device *net_dev)
2987{
2988 struct dpaa_priv *priv;
2989 int err;
2990
2991 err = dpaa_stop(net_dev);
2992
2993 priv = netdev_priv(net_dev);
2994 dpaa_eth_napi_disable(priv);
2995
2996 return err;
2997}
2998
2999static bool xdp_validate_mtu(struct dpaa_priv *priv, int mtu)
3000{
3001 int max_contig_data = priv->dpaa_bp->size - priv->rx_headroom;
3002
3003 /* We do not support S/G fragments when XDP is enabled.
3004 * Limit the MTU in relation to the buffer size.
3005 */
3006 if (mtu + VLAN_ETH_HLEN + ETH_FCS_LEN > max_contig_data) {
3007 dev_warn(priv->net_dev->dev.parent,
3008 "The maximum MTU for XDP is %d\n",
3009 max_contig_data - VLAN_ETH_HLEN - ETH_FCS_LEN);
3010 return false;
3011 }
3012
3013 return true;
3014}
3015
3016static int dpaa_change_mtu(struct net_device *net_dev, int new_mtu)
3017{
3018 struct dpaa_priv *priv = netdev_priv(net_dev);
3019
3020 if (priv->xdp_prog && !xdp_validate_mtu(priv, new_mtu))
3021 return -EINVAL;
3022
3023 WRITE_ONCE(net_dev->mtu, new_mtu);
3024 return 0;
3025}
3026
3027static int dpaa_setup_xdp(struct net_device *net_dev, struct netdev_bpf *bpf)
3028{
3029 struct dpaa_priv *priv = netdev_priv(net_dev);
3030 struct bpf_prog *old_prog;
3031 int err;
3032 bool up;
3033
3034 /* S/G fragments are not supported in XDP-mode */
3035 if (bpf->prog && !xdp_validate_mtu(priv, net_dev->mtu)) {
3036 NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP");
3037 return -EINVAL;
3038 }
3039
3040 up = netif_running(net_dev);
3041
3042 if (up)
3043 dpaa_eth_stop(net_dev);
3044
3045 old_prog = xchg(&priv->xdp_prog, bpf->prog);
3046 if (old_prog)
3047 bpf_prog_put(old_prog);
3048
3049 if (up) {
3050 err = dpaa_open(net_dev);
3051 if (err) {
3052 NL_SET_ERR_MSG_MOD(bpf->extack, "dpaa_open() failed");
3053 return err;
3054 }
3055 }
3056
3057 return 0;
3058}
3059
3060static int dpaa_xdp(struct net_device *net_dev, struct netdev_bpf *xdp)
3061{
3062 switch (xdp->command) {
3063 case XDP_SETUP_PROG:
3064 return dpaa_setup_xdp(net_dev, xdp);
3065 default:
3066 return -EINVAL;
3067 }
3068}
3069
3070static int dpaa_xdp_xmit(struct net_device *net_dev, int n,
3071 struct xdp_frame **frames, u32 flags)
3072{
3073 struct xdp_frame *xdpf;
3074 int i, nxmit = 0;
3075
3076 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3077 return -EINVAL;
3078
3079 if (!netif_running(net_dev))
3080 return -ENETDOWN;
3081
3082 for (i = 0; i < n; i++) {
3083 xdpf = frames[i];
3084 if (dpaa_xdp_xmit_frame(net_dev, xdpf))
3085 break;
3086 nxmit++;
3087 }
3088
3089 return nxmit;
3090}
3091
3092static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3093{
3094 struct dpaa_priv *priv = netdev_priv(dev);
3095 struct hwtstamp_config config;
3096
3097 if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
3098 return -EFAULT;
3099
3100 switch (config.tx_type) {
3101 case HWTSTAMP_TX_OFF:
3102 /* Couldn't disable rx/tx timestamping separately.
3103 * Do nothing here.
3104 */
3105 priv->tx_tstamp = false;
3106 break;
3107 case HWTSTAMP_TX_ON:
3108 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
3109 priv->tx_tstamp = true;
3110 break;
3111 default:
3112 return -ERANGE;
3113 }
3114
3115 if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
3116 /* Couldn't disable rx/tx timestamping separately.
3117 * Do nothing here.
3118 */
3119 priv->rx_tstamp = false;
3120 } else {
3121 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
3122 priv->rx_tstamp = true;
3123 /* TS is set for all frame types, not only those requested */
3124 config.rx_filter = HWTSTAMP_FILTER_ALL;
3125 }
3126
3127 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
3128 -EFAULT : 0;
3129}
3130
3131static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
3132{
3133 int ret = -EINVAL;
3134 struct dpaa_priv *priv = netdev_priv(net_dev);
3135
3136 if (cmd == SIOCGMIIREG) {
3137 if (net_dev->phydev)
3138 return phylink_mii_ioctl(priv->mac_dev->phylink, rq,
3139 cmd);
3140 }
3141
3142 if (cmd == SIOCSHWTSTAMP)
3143 return dpaa_ts_ioctl(net_dev, rq, cmd);
3144
3145 return ret;
3146}
3147
3148static const struct net_device_ops dpaa_ops = {
3149 .ndo_open = dpaa_open,
3150 .ndo_start_xmit = dpaa_start_xmit,
3151 .ndo_stop = dpaa_eth_stop,
3152 .ndo_tx_timeout = dpaa_tx_timeout,
3153 .ndo_get_stats64 = dpaa_get_stats64,
3154 .ndo_change_carrier = fixed_phy_change_carrier,
3155 .ndo_set_mac_address = dpaa_set_mac_address,
3156 .ndo_validate_addr = eth_validate_addr,
3157 .ndo_set_rx_mode = dpaa_set_rx_mode,
3158 .ndo_eth_ioctl = dpaa_ioctl,
3159 .ndo_setup_tc = dpaa_setup_tc,
3160 .ndo_change_mtu = dpaa_change_mtu,
3161 .ndo_bpf = dpaa_xdp,
3162 .ndo_xdp_xmit = dpaa_xdp_xmit,
3163};
3164
3165static int dpaa_napi_add(struct net_device *net_dev)
3166{
3167 struct dpaa_priv *priv = netdev_priv(net_dev);
3168 struct dpaa_percpu_priv *percpu_priv;
3169 int cpu;
3170
3171 for_each_possible_cpu(cpu) {
3172 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
3173
3174 netif_napi_add(net_dev, &percpu_priv->np.napi, dpaa_eth_poll);
3175 }
3176
3177 return 0;
3178}
3179
3180static void dpaa_napi_del(struct net_device *net_dev)
3181{
3182 struct dpaa_priv *priv = netdev_priv(net_dev);
3183 struct dpaa_percpu_priv *percpu_priv;
3184 int cpu;
3185
3186 for_each_possible_cpu(cpu) {
3187 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
3188
3189 __netif_napi_del(&percpu_priv->np.napi);
3190 }
3191 synchronize_net();
3192}
3193
3194static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
3195 struct bm_buffer *bmb)
3196{
3197 dma_addr_t addr = bm_buf_addr(bmb);
3198
3199 dma_unmap_page(bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
3200 DMA_FROM_DEVICE);
3201
3202 skb_free_frag(phys_to_virt(addr));
3203}
3204
3205/* Alloc the dpaa_bp struct and configure default values */
3206static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
3207{
3208 struct dpaa_bp *dpaa_bp;
3209
3210 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
3211 if (!dpaa_bp)
3212 return ERR_PTR(-ENOMEM);
3213
3214 dpaa_bp->bpid = FSL_DPAA_BPID_INV;
3215 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
3216 if (!dpaa_bp->percpu_count)
3217 return ERR_PTR(-ENOMEM);
3218
3219 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
3220
3221 dpaa_bp->seed_cb = dpaa_bp_seed;
3222 dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
3223
3224 return dpaa_bp;
3225}
3226
3227/* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
3228 * We won't be sending congestion notifications to FMan; for now, we just use
3229 * this CGR to generate enqueue rejections to FMan in order to drop the frames
3230 * before they reach our ingress queues and eat up memory.
3231 */
3232static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
3233{
3234 struct qm_mcc_initcgr initcgr;
3235 u32 cs_th;
3236 int err;
3237
3238 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
3239 if (err < 0) {
3240 if (netif_msg_drv(priv))
3241 pr_err("Error %d allocating CGR ID\n", err);
3242 goto out_error;
3243 }
3244
3245 /* Enable CS TD, but disable Congestion State Change Notifications. */
3246 memset(&initcgr, 0, sizeof(initcgr));
3247 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
3248 initcgr.cgr.cscn_en = QM_CGR_EN;
3249 cs_th = DPAA_INGRESS_CS_THRESHOLD;
3250 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
3251
3252 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
3253 initcgr.cgr.cstd_en = QM_CGR_EN;
3254
3255 /* This CGR will be associated with the SWP affined to the current CPU.
3256 * However, we'll place all our ingress FQs in it.
3257 */
3258 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
3259 &initcgr);
3260 if (err < 0) {
3261 if (netif_msg_drv(priv))
3262 pr_err("Error %d creating ingress CGR with ID %d\n",
3263 err, priv->ingress_cgr.cgrid);
3264 qman_release_cgrid(priv->ingress_cgr.cgrid);
3265 goto out_error;
3266 }
3267 if (netif_msg_drv(priv))
3268 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
3269 priv->ingress_cgr.cgrid, priv->mac_dev->addr);
3270
3271 priv->use_ingress_cgr = true;
3272
3273out_error:
3274 return err;
3275}
3276
3277static u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl,
3278 enum port_type port)
3279{
3280 u16 headroom;
3281
3282 /* The frame headroom must accommodate:
3283 * - the driver private data area
3284 * - parse results, hash results, timestamp if selected
3285 * If either hash results or time stamp are selected, both will
3286 * be copied to/from the frame headroom, as TS is located between PR and
3287 * HR in the IC and IC copy size has a granularity of 16bytes
3288 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
3289 *
3290 * Also make sure the headroom is a multiple of data_align bytes
3291 */
3292 headroom = (u16)(bl[port].priv_data_size + DPAA_HWA_SIZE);
3293
3294 if (port == RX) {
3295#ifdef CONFIG_DPAA_ERRATUM_A050385
3296 if (unlikely(fman_has_errata_a050385()))
3297 headroom = XDP_PACKET_HEADROOM;
3298#endif
3299
3300 return ALIGN(headroom, DPAA_FD_RX_DATA_ALIGNMENT);
3301 } else {
3302 return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
3303 }
3304}
3305
3306static int dpaa_eth_probe(struct platform_device *pdev)
3307{
3308 struct net_device *net_dev = NULL;
3309 struct dpaa_bp *dpaa_bp = NULL;
3310 struct dpaa_fq *dpaa_fq, *tmp;
3311 struct dpaa_priv *priv = NULL;
3312 struct fm_port_fqs port_fqs;
3313 struct mac_device *mac_dev;
3314 int err = 0, channel;
3315 struct device *dev;
3316
3317 dev = &pdev->dev;
3318
3319 err = bman_is_probed();
3320 if (!err)
3321 return -EPROBE_DEFER;
3322 if (err < 0) {
3323 dev_err(dev, "failing probe due to bman probe error\n");
3324 return -ENODEV;
3325 }
3326 err = qman_is_probed();
3327 if (!err)
3328 return -EPROBE_DEFER;
3329 if (err < 0) {
3330 dev_err(dev, "failing probe due to qman probe error\n");
3331 return -ENODEV;
3332 }
3333 err = bman_portals_probed();
3334 if (!err)
3335 return -EPROBE_DEFER;
3336 if (err < 0) {
3337 dev_err(dev,
3338 "failing probe due to bman portals probe error\n");
3339 return -ENODEV;
3340 }
3341 err = qman_portals_probed();
3342 if (!err)
3343 return -EPROBE_DEFER;
3344 if (err < 0) {
3345 dev_err(dev,
3346 "failing probe due to qman portals probe error\n");
3347 return -ENODEV;
3348 }
3349
3350 /* Allocate this early, so we can store relevant information in
3351 * the private area
3352 */
3353 net_dev = alloc_etherdev_mq(sizeof(*priv), dpaa_max_num_txqs());
3354 if (!net_dev) {
3355 dev_err(dev, "alloc_etherdev_mq() failed\n");
3356 return -ENOMEM;
3357 }
3358
3359 /* Do this here, so we can be verbose early */
3360 SET_NETDEV_DEV(net_dev, dev->parent);
3361 dev_set_drvdata(dev, net_dev);
3362
3363 priv = netdev_priv(net_dev);
3364 priv->net_dev = net_dev;
3365
3366 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
3367
3368 priv->egress_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
3369 sizeof(*priv->egress_fqs),
3370 GFP_KERNEL);
3371 if (!priv->egress_fqs) {
3372 err = -ENOMEM;
3373 goto free_netdev;
3374 }
3375
3376 priv->conf_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
3377 sizeof(*priv->conf_fqs),
3378 GFP_KERNEL);
3379 if (!priv->conf_fqs) {
3380 err = -ENOMEM;
3381 goto free_netdev;
3382 }
3383
3384 mac_dev = dpaa_mac_dev_get(pdev);
3385 if (IS_ERR(mac_dev)) {
3386 netdev_err(net_dev, "dpaa_mac_dev_get() failed\n");
3387 err = PTR_ERR(mac_dev);
3388 goto free_netdev;
3389 }
3390
3391 /* Devices used for DMA mapping */
3392 priv->rx_dma_dev = fman_port_get_device(mac_dev->port[RX]);
3393 priv->tx_dma_dev = fman_port_get_device(mac_dev->port[TX]);
3394 err = dma_coerce_mask_and_coherent(priv->rx_dma_dev, DMA_BIT_MASK(40));
3395 if (!err)
3396 err = dma_coerce_mask_and_coherent(priv->tx_dma_dev,
3397 DMA_BIT_MASK(40));
3398 if (err) {
3399 netdev_err(net_dev, "dma_coerce_mask_and_coherent() failed\n");
3400 goto free_netdev;
3401 }
3402
3403 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
3404 * we choose conservatively and let the user explicitly set a higher
3405 * MTU via ifconfig. Otherwise, the user may end up with different MTUs
3406 * in the same LAN.
3407 * If on the other hand fsl_fm_max_frm has been chosen below 1500,
3408 * start with the maximum allowed.
3409 */
3410 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
3411
3412 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
3413 net_dev->mtu);
3414
3415 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
3416 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
3417
3418 /* bp init */
3419 dpaa_bp = dpaa_bp_alloc(dev);
3420 if (IS_ERR(dpaa_bp)) {
3421 err = PTR_ERR(dpaa_bp);
3422 goto free_dpaa_bps;
3423 }
3424 /* the raw size of the buffers used for reception */
3425 dpaa_bp->raw_size = DPAA_BP_RAW_SIZE;
3426 /* avoid runtime computations by keeping the usable size here */
3427 dpaa_bp->size = dpaa_bp_size(dpaa_bp->raw_size);
3428 dpaa_bp->priv = priv;
3429
3430 err = dpaa_bp_alloc_pool(dpaa_bp);
3431 if (err < 0)
3432 goto free_dpaa_bps;
3433 priv->dpaa_bp = dpaa_bp;
3434
3435 INIT_LIST_HEAD(&priv->dpaa_fq_list);
3436
3437 memset(&port_fqs, 0, sizeof(port_fqs));
3438
3439 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
3440 if (err < 0) {
3441 dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
3442 goto free_dpaa_bps;
3443 }
3444
3445 priv->mac_dev = mac_dev;
3446
3447 channel = dpaa_get_channel();
3448 if (channel < 0) {
3449 dev_err(dev, "dpaa_get_channel() failed\n");
3450 err = channel;
3451 goto free_dpaa_bps;
3452 }
3453
3454 priv->channel = (u16)channel;
3455
3456 /* Walk the CPUs with affine portals
3457 * and add this pool channel to each's dequeue mask.
3458 */
3459 dpaa_eth_add_channel(priv->channel, &pdev->dev);
3460
3461 err = dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
3462 if (err)
3463 goto free_dpaa_bps;
3464
3465 /* Create a congestion group for this netdev, with
3466 * dynamically-allocated CGR ID.
3467 * Must be executed after probing the MAC, but before
3468 * assigning the egress FQs to the CGRs.
3469 */
3470 err = dpaa_eth_cgr_init(priv);
3471 if (err < 0) {
3472 dev_err(dev, "Error initializing CGR\n");
3473 goto free_dpaa_bps;
3474 }
3475
3476 err = dpaa_ingress_cgr_init(priv);
3477 if (err < 0) {
3478 dev_err(dev, "Error initializing ingress CGR\n");
3479 goto delete_egress_cgr;
3480 }
3481
3482 /* Add the FQs to the interface, and make them active */
3483 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
3484 err = dpaa_fq_init(dpaa_fq, false);
3485 if (err < 0)
3486 goto free_dpaa_fqs;
3487 }
3488
3489 priv->tx_headroom = dpaa_get_headroom(priv->buf_layout, TX);
3490 priv->rx_headroom = dpaa_get_headroom(priv->buf_layout, RX);
3491
3492 /* All real interfaces need their ports initialized */
3493 err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs,
3494 &priv->buf_layout[0], dev);
3495 if (err)
3496 goto free_dpaa_fqs;
3497
3498 /* Rx traffic distribution based on keygen hashing defaults to on */
3499 priv->keygen_in_use = true;
3500
3501 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
3502 if (!priv->percpu_priv) {
3503 dev_err(dev, "devm_alloc_percpu() failed\n");
3504 err = -ENOMEM;
3505 goto free_dpaa_fqs;
3506 }
3507
3508 priv->num_tc = 1;
3509 netif_set_real_num_tx_queues(net_dev,
3510 priv->num_tc * dpaa_num_txqs_per_tc());
3511
3512 /* Initialize NAPI */
3513 err = dpaa_napi_add(net_dev);
3514 if (err < 0)
3515 goto delete_dpaa_napi;
3516
3517 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
3518 if (err < 0)
3519 goto delete_dpaa_napi;
3520
3521 dpaa_eth_sysfs_init(&net_dev->dev);
3522
3523 netif_info(priv, probe, net_dev, "Probed interface %s\n",
3524 net_dev->name);
3525
3526 return 0;
3527
3528delete_dpaa_napi:
3529 dpaa_napi_del(net_dev);
3530free_dpaa_fqs:
3531 dpaa_fq_free(dev, &priv->dpaa_fq_list);
3532 qman_delete_cgr_safe(&priv->ingress_cgr);
3533 qman_release_cgrid(priv->ingress_cgr.cgrid);
3534delete_egress_cgr:
3535 qman_delete_cgr_safe(&priv->cgr_data.cgr);
3536 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
3537free_dpaa_bps:
3538 dpaa_bps_free(priv);
3539free_netdev:
3540 dev_set_drvdata(dev, NULL);
3541 free_netdev(net_dev);
3542
3543 return err;
3544}
3545
3546static void dpaa_remove(struct platform_device *pdev)
3547{
3548 struct net_device *net_dev;
3549 struct dpaa_priv *priv;
3550 struct device *dev;
3551 int err;
3552
3553 dev = &pdev->dev;
3554 net_dev = dev_get_drvdata(dev);
3555
3556 priv = netdev_priv(net_dev);
3557
3558 dpaa_eth_sysfs_remove(dev);
3559
3560 dev_set_drvdata(dev, NULL);
3561 unregister_netdev(net_dev);
3562 phylink_destroy(priv->mac_dev->phylink);
3563
3564 err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
3565 if (err)
3566 dev_err(dev, "Failed to free FQs on remove (%pE)\n",
3567 ERR_PTR(err));
3568
3569 qman_delete_cgr_safe(&priv->ingress_cgr);
3570 qman_release_cgrid(priv->ingress_cgr.cgrid);
3571 qman_delete_cgr_safe(&priv->cgr_data.cgr);
3572 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
3573
3574 dpaa_napi_del(net_dev);
3575
3576 dpaa_bps_free(priv);
3577
3578 free_netdev(net_dev);
3579}
3580
3581static const struct platform_device_id dpaa_devtype[] = {
3582 {
3583 .name = "dpaa-ethernet",
3584 .driver_data = 0,
3585 }, {
3586 }
3587};
3588MODULE_DEVICE_TABLE(platform, dpaa_devtype);
3589
3590static struct platform_driver dpaa_driver = {
3591 .driver = {
3592 .name = KBUILD_MODNAME,
3593 },
3594 .id_table = dpaa_devtype,
3595 .probe = dpaa_eth_probe,
3596 .remove = dpaa_remove
3597};
3598
3599static int __init dpaa_load(void)
3600{
3601 int err;
3602
3603 pr_debug("FSL DPAA Ethernet driver\n");
3604
3605 /* initialize dpaa_eth mirror values */
3606 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
3607 dpaa_max_frm = fman_get_max_frm();
3608
3609 err = platform_driver_register(&dpaa_driver);
3610 if (err < 0)
3611 pr_err("Error, platform_driver_register() = %d\n", err);
3612
3613 return err;
3614}
3615module_init(dpaa_load);
3616
3617static void __exit dpaa_unload(void)
3618{
3619 platform_driver_unregister(&dpaa_driver);
3620
3621 /* Only one channel is used and needs to be released after all
3622 * interfaces are removed
3623 */
3624 dpaa_release_channel();
3625}
3626module_exit(dpaa_unload);
3627
3628MODULE_LICENSE("Dual BSD/GPL");
3629MODULE_DESCRIPTION("FSL DPAA Ethernet driver");