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1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10#include <linux/module.h>
11#include <linux/delay.h>
12#include <linux/rtsx_pci.h>
13
14#include "rtsx_pcr.h"
15
16static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
17{
18 u8 val;
19
20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
21 return val & 0x0F;
22}
23
24static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
25{
26 u8 driving_3v3[4][3] = {
27 {0x11, 0x11, 0x18},
28 {0x55, 0x55, 0x5C},
29 {0xFF, 0xFF, 0xFF},
30 {0x96, 0x96, 0x96},
31 };
32 u8 driving_1v8[4][3] = {
33 {0xC4, 0xC4, 0xC4},
34 {0x3C, 0x3C, 0x3C},
35 {0xFE, 0xFE, 0xFE},
36 {0xB3, 0xB3, 0xB3},
37 };
38 u8 (*driving)[3], drive_sel;
39
40 if (voltage == OUTPUT_3V3) {
41 driving = driving_3v3;
42 drive_sel = pcr->sd30_drive_sel_3v3;
43 } else {
44 driving = driving_1v8;
45 drive_sel = pcr->sd30_drive_sel_1v8;
46 }
47
48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
49 0xFF, driving[drive_sel][0]);
50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
51 0xFF, driving[drive_sel][1]);
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
53 0xFF, driving[drive_sel][2]);
54}
55
56static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
57{
58 struct pci_dev *pdev = pcr->pci;
59 u32 reg;
60
61 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
63
64 if (!rtsx_vendor_setting_valid(reg)) {
65 pcr_dbg(pcr, "skip fetch vendor setting\n");
66 return;
67 }
68
69 pcr->aspm_en = rtsx_reg_to_aspm(reg);
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
71 pcr->card_drive_sel &= 0x3F;
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
73
74 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
76
77 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
78 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg);
79
80 if (rtsx_check_mmc_support(reg))
81 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
82 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
83 if (rtsx_reg_check_reverse_socket(reg))
84 pcr->flags |= PCR_REVERSE_SOCKET;
85}
86
87static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
88{
89 struct rtsx_cr_option *option = &(pcr->option);
90
91 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
92 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
93 | PM_L1_1_EN | PM_L1_2_EN))
94 rtsx_pci_disable_oobs_polling(pcr);
95 else
96 rtsx_pci_enable_oobs_polling(pcr);
97 }
98
99 if (option->ltr_en) {
100 if (option->ltr_enabled)
101 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
102 }
103}
104
105static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
106{
107 /* Set relink_time to 0 */
108 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
109 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
110 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
111 RELINK_TIME_MASK, 0);
112
113 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
114 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
115
116 if (!runtime) {
117 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
118 CD_RESUME_EN_MASK, 0);
119 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
120 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
121 }
122
123 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
124}
125
126static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
127{
128 u8 cnt, sv;
129 u16 j = 0;
130 u8 tmp;
131 u8 val;
132 int i;
133
134 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
135 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
136 udelay(1);
137
138 pcr_dbg(pcr, "Enable efuse por!");
139 pcr_dbg(pcr, "save efuse to autoload");
140
141 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
142 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
143 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
144 /* Wait transfer end */
145 for (j = 0; j < 1024; j++) {
146 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
147 if ((tmp & 0x80) == 0)
148 break;
149 }
150 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
151 cnt = val & 0x0F;
152 sv = val & 0x10;
153
154 if (sv) {
155 for (i = 0; i < 4; i++) {
156 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
157 REG_EFUSE_ADD_MASK, 0x04 + i);
158 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
159 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
160 /* Wait transfer end */
161 for (j = 0; j < 1024; j++) {
162 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
163 if ((tmp & 0x80) == 0)
164 break;
165 }
166 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
167 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
168 }
169 } else {
170 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
171 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
172 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
173 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
174 }
175
176 for (i = 0; i < cnt * 4; i++) {
177 if (sv)
178 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
179 REG_EFUSE_ADD_MASK, 0x08 + i);
180 else
181 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
182 REG_EFUSE_ADD_MASK, 0x04 + i);
183 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
184 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
185 /* Wait transfer end */
186 for (j = 0; j < 1024; j++) {
187 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
188 if ((tmp & 0x80) == 0)
189 break;
190 }
191 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
192 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
193 }
194 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
195 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
196 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
197 pcr_dbg(pcr, "Disable efuse por!");
198}
199
200static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
201{
202 u8 val;
203
204 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
205 if (val & 0x02) {
206 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
207 if (val & RTS525A_LOAD_BIOS_FLAG) {
208 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
209 RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
210
211 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
212 REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
213
214 pcr_dbg(pcr, "Power ON efuse!");
215 mdelay(1);
216 rts52xa_save_content_from_efuse(pcr);
217 } else {
218 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
219 if (!(val & 0x08))
220 rts52xa_save_content_from_efuse(pcr);
221 }
222 } else {
223 pcr_dbg(pcr, "Load from autoload");
224 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
225 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
226 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
227 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
228 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
229 }
230}
231
232static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
233{
234 struct rtsx_cr_option *option = &(pcr->option);
235
236 rts5249_init_from_cfg(pcr);
237
238 rtsx_pci_init_cmd(pcr);
239
240 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
241 rts52xa_save_content_to_autoload_space(pcr);
242
243 /* Rest L1SUB Config */
244 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
245 /* Configure GPIO as output */
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
247 /* Reset ASPM state to default value */
248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
249 /* Switch LDO3318 source from DV33 to card_3v3 */
250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
251 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
252 /* LED shine disabled, set initial shine cycle period */
253 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
254 /* Configure driving */
255 rts5249_fill_driving(pcr, OUTPUT_3V3);
256 if (pcr->flags & PCR_REVERSE_SOCKET)
257 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
258 else
259 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
260
261 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
262
263 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
264 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
265 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
266 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
267 }
268
269 if (pcr->rtd3_en) {
270 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
271 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01);
272 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30);
273 } else {
274 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01);
275 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33);
276 }
277 } else {
278 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
279 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
280 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
281 } else {
282 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
283 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
284 }
285 }
286
287
288 /*
289 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
290 * to drive low, and we forcibly request clock.
291 */
292 if (option->force_clkreq_0)
293 rtsx_pci_write_register(pcr, PETXCFG,
294 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
295 else
296 rtsx_pci_write_register(pcr, PETXCFG,
297 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
298
299 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
300 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
301 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
302 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
303 pcr_dbg(pcr, "Power OFF efuse!");
304 }
305
306 return 0;
307}
308
309static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
310{
311 int err;
312
313 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
314 if (err < 0)
315 return err;
316
317 err = rtsx_pci_write_phy_register(pcr, PHY_REV,
318 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
319 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
320 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
321 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
322 PHY_REV_STOP_CLKWR);
323 if (err < 0)
324 return err;
325
326 msleep(1);
327
328 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
329 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
330 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
331 if (err < 0)
332 return err;
333
334 err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
335 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
336 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
337 PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
338 if (err < 0)
339 return err;
340
341 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
342 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
343 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
344 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
345 if (err < 0)
346 return err;
347
348 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
349 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
350 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
351 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
352 PHY_FLD4_BER_CHK_EN);
353 if (err < 0)
354 return err;
355 err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
356 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
357 if (err < 0)
358 return err;
359 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
360 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
361 if (err < 0)
362 return err;
363 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
364 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
365 PHY_FLD3_RXDELINK);
366 if (err < 0)
367 return err;
368
369 return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
370 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
371 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
372 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
373}
374
375static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
376{
377 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
378}
379
380static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
381{
382 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
383}
384
385static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
386{
387 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
388}
389
390static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
391{
392 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
393}
394
395static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
396{
397 int err;
398 struct rtsx_cr_option *option = &pcr->option;
399
400 if (option->ocp_en)
401 rtsx_pci_enable_ocp(pcr);
402
403 rtsx_pci_init_cmd(pcr);
404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
405 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
406 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
407 LDO3318_PWR_MASK, 0x02);
408 err = rtsx_pci_send_cmd(pcr, 100);
409 if (err < 0)
410 return err;
411
412 msleep(5);
413
414 rtsx_pci_init_cmd(pcr);
415 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
416 SD_POWER_MASK, SD_VCC_POWER_ON);
417 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
418 LDO3318_PWR_MASK, 0x06);
419 return rtsx_pci_send_cmd(pcr, 100);
420}
421
422static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
423{
424 struct rtsx_cr_option *option = &pcr->option;
425
426 if (option->ocp_en)
427 rtsx_pci_disable_ocp(pcr);
428
429 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
430
431 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
432 return 0;
433}
434
435static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
436{
437 int err;
438 u16 append;
439
440 switch (voltage) {
441 case OUTPUT_3V3:
442 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
443 PHY_TUNE_VOLTAGE_3V3);
444 if (err < 0)
445 return err;
446 break;
447 case OUTPUT_1V8:
448 append = PHY_TUNE_D18_1V8;
449 if (CHK_PCI_PID(pcr, 0x5249)) {
450 err = rtsx_pci_update_phy(pcr, PHY_BACR,
451 PHY_BACR_BASIC_MASK, 0);
452 if (err < 0)
453 return err;
454 append = PHY_TUNE_D18_1V7;
455 }
456
457 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
458 append);
459 if (err < 0)
460 return err;
461 break;
462 default:
463 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
464 return -EINVAL;
465 }
466
467 /* set pad drive */
468 rtsx_pci_init_cmd(pcr);
469 rts5249_fill_driving(pcr, voltage);
470 return rtsx_pci_send_cmd(pcr, 100);
471}
472
473static const struct pcr_ops rts5249_pcr_ops = {
474 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
475 .extra_init_hw = rts5249_extra_init_hw,
476 .optimize_phy = rts5249_optimize_phy,
477 .turn_on_led = rtsx_base_turn_on_led,
478 .turn_off_led = rtsx_base_turn_off_led,
479 .enable_auto_blink = rtsx_base_enable_auto_blink,
480 .disable_auto_blink = rtsx_base_disable_auto_blink,
481 .card_power_on = rtsx_base_card_power_on,
482 .card_power_off = rtsx_base_card_power_off,
483 .switch_output_voltage = rtsx_base_switch_output_voltage,
484};
485
486/* SD Pull Control Enable:
487 * SD_DAT[3:0] ==> pull up
488 * SD_CD ==> pull up
489 * SD_WP ==> pull up
490 * SD_CMD ==> pull up
491 * SD_CLK ==> pull down
492 */
493static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
494 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
495 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
496 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
497 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
498 0,
499};
500
501/* SD Pull Control Disable:
502 * SD_DAT[3:0] ==> pull down
503 * SD_CD ==> pull up
504 * SD_WP ==> pull down
505 * SD_CMD ==> pull down
506 * SD_CLK ==> pull down
507 */
508static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
509 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
510 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
511 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
512 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
513 0,
514};
515
516/* MS Pull Control Enable:
517 * MS CD ==> pull up
518 * others ==> pull down
519 */
520static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
521 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
522 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
523 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
524 0,
525};
526
527/* MS Pull Control Disable:
528 * MS CD ==> pull up
529 * others ==> pull down
530 */
531static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
532 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
533 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
534 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
535 0,
536};
537
538void rts5249_init_params(struct rtsx_pcr *pcr)
539{
540 struct rtsx_cr_option *option = &(pcr->option);
541
542 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
543 pcr->num_slots = 2;
544 pcr->ops = &rts5249_pcr_ops;
545
546 pcr->flags = 0;
547 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
548 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
549 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
550 pcr->aspm_en = ASPM_L1_EN;
551 pcr->aspm_mode = ASPM_MODE_CFG;
552 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
553 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
554
555 pcr->ic_version = rts5249_get_ic_version(pcr);
556 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
557 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
558 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
559 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
560
561 pcr->reg_pm_ctrl3 = PM_CTRL3;
562
563 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
564 | LTR_L1SS_PWR_GATE_EN);
565 option->ltr_en = true;
566
567 /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
568 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
569 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
570 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
571 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
572 option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
573 option->ltr_l1off_snooze_sspwrgate =
574 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
575}
576
577static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
578{
579 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
580
581 return __rtsx_pci_write_phy_register(pcr, addr, val);
582}
583
584static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
585{
586 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
587
588 return __rtsx_pci_read_phy_register(pcr, addr, val);
589}
590
591static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
592{
593 int err;
594
595 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
596 D3_DELINK_MODE_EN, 0x00);
597 if (err < 0)
598 return err;
599
600 rtsx_pci_write_phy_register(pcr, PHY_PCR,
601 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
602 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
603 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
604 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
605
606 if (is_version(pcr, 0x524A, IC_VER_A)) {
607 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
608 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
609 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
610 PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
611 PHY_SSCCR2_TIME2_WIDTH);
612 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
613 PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
614 PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
615 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
616 PHY_ANA1D_DEBUG_ADDR);
617 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
618 PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
619 PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
620 PHY_DIG1E_RCLK_TX_EN_KEEP |
621 PHY_DIG1E_RCLK_TX_TERM_KEEP |
622 PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
623 PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
624 PHY_DIG1E_RX_EN_KEEP);
625 }
626
627 rtsx_pci_write_phy_register(pcr, PHY_ANA08,
628 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
629 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
630
631 return 0;
632}
633
634static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
635{
636 rts5249_extra_init_hw(pcr);
637
638 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
639 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
640 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
641 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
642 LDO_VCC_LMT_EN);
643 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
644 if (is_version(pcr, 0x524A, IC_VER_A)) {
645 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
646 LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
647 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
648 LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
649 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
650 LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
651 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
652 LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
653 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
654 LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
655 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
656 SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
657 }
658
659 return 0;
660}
661
662static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
663{
664 struct rtsx_cr_option *option = &(pcr->option);
665
666 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
667 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
668 int aspm_L1_1, aspm_L1_2;
669 u8 val = 0;
670
671 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
672 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
673
674 if (active) {
675 /* Run, latency: 60us */
676 if (aspm_L1_1)
677 val = option->ltr_l1off_snooze_sspwrgate;
678 } else {
679 /* L1off, latency: 300us */
680 if (aspm_L1_2)
681 val = option->ltr_l1off_sspwrgate;
682 }
683
684 if (aspm_L1_1 || aspm_L1_2) {
685 if (rtsx_check_dev_flag(pcr,
686 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
687 if (card_exist)
688 val &= ~L1OFF_MBIAS2_EN_5250;
689 else
690 val |= L1OFF_MBIAS2_EN_5250;
691 }
692 }
693 rtsx_set_l1off_sub(pcr, val);
694}
695
696static const struct pcr_ops rts524a_pcr_ops = {
697 .write_phy = rts524a_write_phy,
698 .read_phy = rts524a_read_phy,
699 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
700 .extra_init_hw = rts524a_extra_init_hw,
701 .optimize_phy = rts524a_optimize_phy,
702 .turn_on_led = rtsx_base_turn_on_led,
703 .turn_off_led = rtsx_base_turn_off_led,
704 .enable_auto_blink = rtsx_base_enable_auto_blink,
705 .disable_auto_blink = rtsx_base_disable_auto_blink,
706 .card_power_on = rtsx_base_card_power_on,
707 .card_power_off = rtsx_base_card_power_off,
708 .switch_output_voltage = rtsx_base_switch_output_voltage,
709 .force_power_down = rts52xa_force_power_down,
710 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
711};
712
713void rts524a_init_params(struct rtsx_pcr *pcr)
714{
715 rts5249_init_params(pcr);
716 pcr->aspm_mode = ASPM_MODE_REG;
717 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
718 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
719 pcr->option.ltr_l1off_snooze_sspwrgate =
720 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
721
722 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
723 pcr->ops = &rts524a_pcr_ops;
724
725 pcr->option.ocp_en = 1;
726 if (pcr->option.ocp_en)
727 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
728 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
729 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
730
731}
732
733static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
734{
735 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
736 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
737 return rtsx_base_card_power_on(pcr, card);
738}
739
740static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
741{
742 switch (voltage) {
743 case OUTPUT_3V3:
744 rtsx_pci_write_register(pcr, LDO_CONFIG2,
745 LDO_D3318_MASK, LDO_D3318_33V);
746 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
747 break;
748 case OUTPUT_1V8:
749 rtsx_pci_write_register(pcr, LDO_CONFIG2,
750 LDO_D3318_MASK, LDO_D3318_18V);
751 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
752 SD_IO_USING_1V8);
753 break;
754 default:
755 return -EINVAL;
756 }
757
758 rtsx_pci_init_cmd(pcr);
759 rts5249_fill_driving(pcr, voltage);
760 return rtsx_pci_send_cmd(pcr, 100);
761}
762
763static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
764{
765 int err;
766
767 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
768 D3_DELINK_MODE_EN, 0x00);
769 if (err < 0)
770 return err;
771
772 rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
773 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
774 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
775 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
776
777 rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
778 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
779 _PHY_CMU_DEBUG_EN);
780
781 if (is_version(pcr, 0x525A, IC_VER_A))
782 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
783 _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
784 _PHY_REV0_CDR_RX_IDLE_BYPASS);
785
786 return 0;
787}
788
789static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
790{
791 rts5249_extra_init_hw(pcr);
792
793 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
794
795 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
796 if (is_version(pcr, 0x525A, IC_VER_A)) {
797 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
798 L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
799 rtsx_pci_write_register(pcr, RREF_CFG,
800 RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
801 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
802 LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
803 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
804 LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
805 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
806 LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
807 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
808 LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
809 rtsx_pci_write_register(pcr, OOBS_CONFIG,
810 OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
811 }
812
813 return 0;
814}
815
816static const struct pcr_ops rts525a_pcr_ops = {
817 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
818 .extra_init_hw = rts525a_extra_init_hw,
819 .optimize_phy = rts525a_optimize_phy,
820 .turn_on_led = rtsx_base_turn_on_led,
821 .turn_off_led = rtsx_base_turn_off_led,
822 .enable_auto_blink = rtsx_base_enable_auto_blink,
823 .disable_auto_blink = rtsx_base_disable_auto_blink,
824 .card_power_on = rts525a_card_power_on,
825 .card_power_off = rtsx_base_card_power_off,
826 .switch_output_voltage = rts525a_switch_output_voltage,
827 .force_power_down = rts52xa_force_power_down,
828 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
829};
830
831void rts525a_init_params(struct rtsx_pcr *pcr)
832{
833 rts5249_init_params(pcr);
834 pcr->aspm_mode = ASPM_MODE_REG;
835 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
836 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
837 pcr->option.ltr_l1off_snooze_sspwrgate =
838 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
839
840 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
841 pcr->ops = &rts525a_pcr_ops;
842
843 pcr->option.ocp_en = 1;
844 if (pcr->option.ocp_en)
845 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
846 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
847 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
848}