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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28#include <linux/firmware.h>
29
30#include "amdgpu.h"
31#include "amdgpu_vce.h"
32#include "cikd.h"
33#include "vce/vce_2_0_d.h"
34#include "vce/vce_2_0_sh_mask.h"
35#include "smu/smu_7_0_1_d.h"
36#include "smu/smu_7_0_1_sh_mask.h"
37#include "oss/oss_2_0_d.h"
38#include "oss/oss_2_0_sh_mask.h"
39
40#define VCE_V2_0_FW_SIZE (256 * 1024)
41#define VCE_V2_0_STACK_SIZE (64 * 1024)
42#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
43#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
44
45static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
46static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
47
48/**
49 * vce_v2_0_ring_get_rptr - get read pointer
50 *
51 * @ring: amdgpu_ring pointer
52 *
53 * Returns the current hardware read pointer
54 */
55static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
56{
57 struct amdgpu_device *adev = ring->adev;
58
59 if (ring->me == 0)
60 return RREG32(mmVCE_RB_RPTR);
61 else
62 return RREG32(mmVCE_RB_RPTR2);
63}
64
65/**
66 * vce_v2_0_ring_get_wptr - get write pointer
67 *
68 * @ring: amdgpu_ring pointer
69 *
70 * Returns the current hardware write pointer
71 */
72static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
73{
74 struct amdgpu_device *adev = ring->adev;
75
76 if (ring->me == 0)
77 return RREG32(mmVCE_RB_WPTR);
78 else
79 return RREG32(mmVCE_RB_WPTR2);
80}
81
82/**
83 * vce_v2_0_ring_set_wptr - set write pointer
84 *
85 * @ring: amdgpu_ring pointer
86 *
87 * Commits the write pointer to the hardware
88 */
89static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
90{
91 struct amdgpu_device *adev = ring->adev;
92
93 if (ring->me == 0)
94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
95 else
96 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
97}
98
99static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
100{
101 int i, j;
102
103 for (i = 0; i < 10; ++i) {
104 for (j = 0; j < 100; ++j) {
105 uint32_t status = RREG32(mmVCE_LMI_STATUS);
106
107 if (status & 0x337f)
108 return 0;
109 mdelay(10);
110 }
111 }
112
113 return -ETIMEDOUT;
114}
115
116static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
117{
118 int i, j;
119
120 for (i = 0; i < 10; ++i) {
121 for (j = 0; j < 100; ++j) {
122 uint32_t status = RREG32(mmVCE_STATUS);
123
124 if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
125 return 0;
126 mdelay(10);
127 }
128
129 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
130 WREG32_P(mmVCE_SOFT_RESET,
131 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
132 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
133 mdelay(10);
134 WREG32_P(mmVCE_SOFT_RESET, 0,
135 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
136 mdelay(10);
137 }
138
139 return -ETIMEDOUT;
140}
141
142static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
143{
144 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
145}
146
147static void vce_v2_0_init_cg(struct amdgpu_device *adev)
148{
149 u32 tmp;
150
151 tmp = RREG32(mmVCE_CLOCK_GATING_A);
152 tmp &= ~0xfff;
153 tmp |= ((0 << 0) | (4 << 4));
154 tmp |= 0x40000;
155 WREG32(mmVCE_CLOCK_GATING_A, tmp);
156
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
158 tmp &= ~0xfff;
159 tmp |= ((0 << 0) | (4 << 4));
160 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
161
162 tmp = RREG32(mmVCE_CLOCK_GATING_B);
163 tmp |= 0x10;
164 tmp &= ~0x100000;
165 WREG32(mmVCE_CLOCK_GATING_B, tmp);
166}
167
168static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
169{
170 uint32_t size, offset;
171
172 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
174 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
175 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
176
177 WREG32(mmVCE_LMI_CTRL, 0x00398000);
178 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
179 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
180 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
181 WREG32(mmVCE_LMI_VM_CTRL, 0);
182
183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
184
185 offset = AMDGPU_VCE_FIRMWARE_OFFSET;
186 size = VCE_V2_0_FW_SIZE;
187 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
188 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
189
190 offset += size;
191 size = VCE_V2_0_STACK_SIZE;
192 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
193 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
194
195 offset += size;
196 size = VCE_V2_0_DATA_SIZE;
197 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
198 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
199
200 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
201 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
202}
203
204static bool vce_v2_0_is_idle(void *handle)
205{
206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
207
208 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
209}
210
211static int vce_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
212{
213 struct amdgpu_device *adev = ip_block->adev;
214 unsigned i;
215
216 for (i = 0; i < adev->usec_timeout; i++) {
217 if (vce_v2_0_is_idle(adev))
218 return 0;
219 }
220 return -ETIMEDOUT;
221}
222
223/**
224 * vce_v2_0_start - start VCE block
225 *
226 * @adev: amdgpu_device pointer
227 *
228 * Setup and start the VCE block
229 */
230static int vce_v2_0_start(struct amdgpu_device *adev)
231{
232 struct amdgpu_ring *ring;
233 int r;
234
235 /* set BUSY flag */
236 WREG32_P(mmVCE_STATUS, 1, ~1);
237
238 vce_v2_0_init_cg(adev);
239 vce_v2_0_disable_cg(adev);
240
241 vce_v2_0_mc_resume(adev);
242
243 ring = &adev->vce.ring[0];
244 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
245 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
246 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
247 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
248 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
249
250 ring = &adev->vce.ring[1];
251 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
252 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
253 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
254 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
255 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
256
257 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
258 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
259 mdelay(100);
260 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
261
262 r = vce_v2_0_firmware_loaded(adev);
263
264 /* clear BUSY flag */
265 WREG32_P(mmVCE_STATUS, 0, ~1);
266
267 if (r) {
268 DRM_ERROR("VCE not responding, giving up!!!\n");
269 return r;
270 }
271
272 return 0;
273}
274
275static int vce_v2_0_stop(struct amdgpu_device *adev)
276{
277 struct amdgpu_ip_block *ip_block;
278 int i;
279 int status;
280
281
282 if (vce_v2_0_lmi_clean(adev)) {
283 DRM_INFO("vce is not idle \n");
284 return 0;
285 }
286
287 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCN);
288 if (!ip_block)
289 return -EINVAL;
290
291 if (vce_v2_0_wait_for_idle(ip_block)) {
292 DRM_INFO("VCE is busy, Can't set clock gating");
293 return 0;
294 }
295
296 /* Stall UMC and register bus before resetting VCPU */
297 WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
298
299 for (i = 0; i < 100; ++i) {
300 status = RREG32(mmVCE_LMI_STATUS);
301 if (status & 0x240)
302 break;
303 mdelay(1);
304 }
305
306 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);
307
308 /* put LMI, VCPU, RBC etc... into reset */
309 WREG32_P(mmVCE_SOFT_RESET, 1, ~0x1);
310
311 WREG32(mmVCE_STATUS, 0);
312
313 return 0;
314}
315
316static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
317{
318 u32 tmp;
319
320 if (gated) {
321 tmp = RREG32(mmVCE_CLOCK_GATING_B);
322 tmp |= 0xe70000;
323 WREG32(mmVCE_CLOCK_GATING_B, tmp);
324
325 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
326 tmp |= 0xff000000;
327 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
328
329 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
330 tmp &= ~0x3fc;
331 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
332
333 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
334 } else {
335 tmp = RREG32(mmVCE_CLOCK_GATING_B);
336 tmp |= 0xe7;
337 tmp &= ~0xe70000;
338 WREG32(mmVCE_CLOCK_GATING_B, tmp);
339
340 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
341 tmp |= 0x1fe000;
342 tmp &= ~0xff000000;
343 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
344
345 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
346 tmp |= 0x3fc;
347 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
348 }
349}
350
351static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
352{
353 u32 orig, tmp;
354
355/* LMI_MC/LMI_UMC always set in dynamic,
356 * set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0}
357 */
358 tmp = RREG32(mmVCE_CLOCK_GATING_B);
359 tmp &= ~0x00060006;
360
361/* Exception for ECPU, IH, SEM, SYS blocks needs to be turned on/off by SW */
362 if (gated) {
363 tmp |= 0xe10000;
364 WREG32(mmVCE_CLOCK_GATING_B, tmp);
365 } else {
366 tmp |= 0xe1;
367 tmp &= ~0xe10000;
368 WREG32(mmVCE_CLOCK_GATING_B, tmp);
369 }
370
371 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
372 tmp &= ~0x1fe000;
373 tmp &= ~0xff000000;
374 if (tmp != orig)
375 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
376
377 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
378 tmp &= ~0x3fc;
379 if (tmp != orig)
380 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
381
382 /* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
383 WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
384
385 if(gated)
386 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
387}
388
389static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
390 bool sw_cg)
391{
392 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
393 if (sw_cg)
394 vce_v2_0_set_sw_cg(adev, true);
395 else
396 vce_v2_0_set_dyn_cg(adev, true);
397 } else {
398 vce_v2_0_disable_cg(adev);
399
400 if (sw_cg)
401 vce_v2_0_set_sw_cg(adev, false);
402 else
403 vce_v2_0_set_dyn_cg(adev, false);
404 }
405}
406
407static int vce_v2_0_early_init(struct amdgpu_ip_block *ip_block)
408{
409 struct amdgpu_device *adev = ip_block->adev;
410
411 adev->vce.num_rings = 2;
412
413 vce_v2_0_set_ring_funcs(adev);
414 vce_v2_0_set_irq_funcs(adev);
415
416 return 0;
417}
418
419static int vce_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
420{
421 struct amdgpu_ring *ring;
422 int r, i;
423 struct amdgpu_device *adev = ip_block->adev;
424
425 /* VCE */
426 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);
427 if (r)
428 return r;
429
430 r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
431 VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
432 if (r)
433 return r;
434
435 r = amdgpu_vce_resume(adev);
436 if (r)
437 return r;
438
439 for (i = 0; i < adev->vce.num_rings; i++) {
440 enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i);
441
442 ring = &adev->vce.ring[i];
443 sprintf(ring->name, "vce%d", i);
444 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
445 hw_prio, NULL);
446 if (r)
447 return r;
448 }
449
450 return r;
451}
452
453static int vce_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
454{
455 int r;
456 struct amdgpu_device *adev = ip_block->adev;
457
458 r = amdgpu_vce_suspend(adev);
459 if (r)
460 return r;
461
462 return amdgpu_vce_sw_fini(adev);
463}
464
465static int vce_v2_0_hw_init(struct amdgpu_ip_block *ip_block)
466{
467 int r, i;
468 struct amdgpu_device *adev = ip_block->adev;
469
470 amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
471 vce_v2_0_enable_mgcg(adev, true, false);
472
473 for (i = 0; i < adev->vce.num_rings; i++) {
474 r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
475 if (r)
476 return r;
477 }
478
479 DRM_INFO("VCE initialized successfully.\n");
480
481 return 0;
482}
483
484static int vce_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
485{
486 cancel_delayed_work_sync(&ip_block->adev->vce.idle_work);
487
488 return 0;
489}
490
491static int vce_v2_0_suspend(struct amdgpu_ip_block *ip_block)
492{
493 int r;
494 struct amdgpu_device *adev = ip_block->adev;
495
496
497 /*
498 * Proper cleanups before halting the HW engine:
499 * - cancel the delayed idle work
500 * - enable powergating
501 * - enable clockgating
502 * - disable dpm
503 *
504 * TODO: to align with the VCN implementation, move the
505 * jobs for clockgating/powergating/dpm setting to
506 * ->set_powergating_state().
507 */
508 cancel_delayed_work_sync(&adev->vce.idle_work);
509
510 if (adev->pm.dpm_enabled) {
511 amdgpu_dpm_enable_vce(adev, false);
512 } else {
513 amdgpu_asic_set_vce_clocks(adev, 0, 0);
514 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
515 AMD_PG_STATE_GATE);
516 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
517 AMD_CG_STATE_GATE);
518 }
519
520 r = vce_v2_0_hw_fini(ip_block);
521 if (r)
522 return r;
523
524 return amdgpu_vce_suspend(adev);
525}
526
527static int vce_v2_0_resume(struct amdgpu_ip_block *ip_block)
528{
529 int r;
530
531 r = amdgpu_vce_resume(ip_block->adev);
532 if (r)
533 return r;
534
535 return vce_v2_0_hw_init(ip_block);
536}
537
538static int vce_v2_0_soft_reset(struct amdgpu_ip_block *ip_block)
539{
540 struct amdgpu_device *adev = ip_block->adev;
541
542 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
543 mdelay(5);
544
545 return vce_v2_0_start(adev);
546}
547
548static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
549 struct amdgpu_irq_src *source,
550 unsigned type,
551 enum amdgpu_interrupt_state state)
552{
553 uint32_t val = 0;
554
555 if (state == AMDGPU_IRQ_STATE_ENABLE)
556 val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
557
558 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
559 return 0;
560}
561
562static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
563 struct amdgpu_irq_src *source,
564 struct amdgpu_iv_entry *entry)
565{
566 DRM_DEBUG("IH: VCE\n");
567 switch (entry->src_data[0]) {
568 case 0:
569 case 1:
570 amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
571 break;
572 default:
573 DRM_ERROR("Unhandled interrupt: %d %d\n",
574 entry->src_id, entry->src_data[0]);
575 break;
576 }
577
578 return 0;
579}
580
581static int vce_v2_0_set_clockgating_state(void *handle,
582 enum amd_clockgating_state state)
583{
584 bool gate = false;
585 bool sw_cg = false;
586
587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
588
589 if (state == AMD_CG_STATE_GATE) {
590 gate = true;
591 sw_cg = true;
592 }
593
594 vce_v2_0_enable_mgcg(adev, gate, sw_cg);
595
596 return 0;
597}
598
599static int vce_v2_0_set_powergating_state(void *handle,
600 enum amd_powergating_state state)
601{
602 /* This doesn't actually powergate the VCE block.
603 * That's done in the dpm code via the SMC. This
604 * just re-inits the block as necessary. The actual
605 * gating still happens in the dpm code. We should
606 * revisit this when there is a cleaner line between
607 * the smc and the hw blocks
608 */
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610
611 if (state == AMD_PG_STATE_GATE)
612 return vce_v2_0_stop(adev);
613 else
614 return vce_v2_0_start(adev);
615}
616
617static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
618 .name = "vce_v2_0",
619 .early_init = vce_v2_0_early_init,
620 .sw_init = vce_v2_0_sw_init,
621 .sw_fini = vce_v2_0_sw_fini,
622 .hw_init = vce_v2_0_hw_init,
623 .hw_fini = vce_v2_0_hw_fini,
624 .suspend = vce_v2_0_suspend,
625 .resume = vce_v2_0_resume,
626 .is_idle = vce_v2_0_is_idle,
627 .wait_for_idle = vce_v2_0_wait_for_idle,
628 .soft_reset = vce_v2_0_soft_reset,
629 .set_clockgating_state = vce_v2_0_set_clockgating_state,
630 .set_powergating_state = vce_v2_0_set_powergating_state,
631};
632
633static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
634 .type = AMDGPU_RING_TYPE_VCE,
635 .align_mask = 0xf,
636 .nop = VCE_CMD_NO_OP,
637 .support_64bit_ptrs = false,
638 .no_user_fence = true,
639 .get_rptr = vce_v2_0_ring_get_rptr,
640 .get_wptr = vce_v2_0_ring_get_wptr,
641 .set_wptr = vce_v2_0_ring_set_wptr,
642 .parse_cs = amdgpu_vce_ring_parse_cs,
643 .emit_frame_size = 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
644 .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
645 .emit_ib = amdgpu_vce_ring_emit_ib,
646 .emit_fence = amdgpu_vce_ring_emit_fence,
647 .test_ring = amdgpu_vce_ring_test_ring,
648 .test_ib = amdgpu_vce_ring_test_ib,
649 .insert_nop = amdgpu_ring_insert_nop,
650 .pad_ib = amdgpu_ring_generic_pad_ib,
651 .begin_use = amdgpu_vce_ring_begin_use,
652 .end_use = amdgpu_vce_ring_end_use,
653};
654
655static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
656{
657 int i;
658
659 for (i = 0; i < adev->vce.num_rings; i++) {
660 adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;
661 adev->vce.ring[i].me = i;
662 }
663}
664
665static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
666 .set = vce_v2_0_set_interrupt_state,
667 .process = vce_v2_0_process_interrupt,
668};
669
670static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
671{
672 adev->vce.irq.num_types = 1;
673 adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
674};
675
676const struct amdgpu_ip_block_version vce_v2_0_ip_block =
677{
678 .type = AMD_IP_BLOCK_TYPE_VCE,
679 .major = 2,
680 .minor = 0,
681 .rev = 0,
682 .funcs = &vce_v2_0_ip_funcs,
683};
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28#include <linux/firmware.h>
29#include <drm/drmP.h>
30#include "amdgpu.h"
31#include "amdgpu_vce.h"
32#include "cikd.h"
33
34#include "vce/vce_2_0_d.h"
35#include "vce/vce_2_0_sh_mask.h"
36
37#include "oss/oss_2_0_d.h"
38#include "oss/oss_2_0_sh_mask.h"
39
40#define VCE_V2_0_FW_SIZE (256 * 1024)
41#define VCE_V2_0_STACK_SIZE (64 * 1024)
42#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
43
44static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
45static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
46static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
47
48/**
49 * vce_v2_0_ring_get_rptr - get read pointer
50 *
51 * @ring: amdgpu_ring pointer
52 *
53 * Returns the current hardware read pointer
54 */
55static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
56{
57 struct amdgpu_device *adev = ring->adev;
58
59 if (ring == &adev->vce.ring[0])
60 return RREG32(mmVCE_RB_RPTR);
61 else
62 return RREG32(mmVCE_RB_RPTR2);
63}
64
65/**
66 * vce_v2_0_ring_get_wptr - get write pointer
67 *
68 * @ring: amdgpu_ring pointer
69 *
70 * Returns the current hardware write pointer
71 */
72static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
73{
74 struct amdgpu_device *adev = ring->adev;
75
76 if (ring == &adev->vce.ring[0])
77 return RREG32(mmVCE_RB_WPTR);
78 else
79 return RREG32(mmVCE_RB_WPTR2);
80}
81
82/**
83 * vce_v2_0_ring_set_wptr - set write pointer
84 *
85 * @ring: amdgpu_ring pointer
86 *
87 * Commits the write pointer to the hardware
88 */
89static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
90{
91 struct amdgpu_device *adev = ring->adev;
92
93 if (ring == &adev->vce.ring[0])
94 WREG32(mmVCE_RB_WPTR, ring->wptr);
95 else
96 WREG32(mmVCE_RB_WPTR2, ring->wptr);
97}
98
99/**
100 * vce_v2_0_start - start VCE block
101 *
102 * @adev: amdgpu_device pointer
103 *
104 * Setup and start the VCE block
105 */
106static int vce_v2_0_start(struct amdgpu_device *adev)
107{
108 struct amdgpu_ring *ring;
109 int i, j, r;
110
111 vce_v2_0_mc_resume(adev);
112
113 /* set BUSY flag */
114 WREG32_P(mmVCE_STATUS, 1, ~1);
115
116 ring = &adev->vce.ring[0];
117 WREG32(mmVCE_RB_RPTR, ring->wptr);
118 WREG32(mmVCE_RB_WPTR, ring->wptr);
119 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
120 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
121 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
122
123 ring = &adev->vce.ring[1];
124 WREG32(mmVCE_RB_RPTR2, ring->wptr);
125 WREG32(mmVCE_RB_WPTR2, ring->wptr);
126 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
127 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
128 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
129
130 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
131
132 WREG32_P(mmVCE_SOFT_RESET,
133 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
134 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
135
136 mdelay(100);
137
138 WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
139
140 for (i = 0; i < 10; ++i) {
141 uint32_t status;
142 for (j = 0; j < 100; ++j) {
143 status = RREG32(mmVCE_STATUS);
144 if (status & 2)
145 break;
146 mdelay(10);
147 }
148 r = 0;
149 if (status & 2)
150 break;
151
152 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
153 WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
154 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
155 mdelay(10);
156 WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
157 mdelay(10);
158 r = -1;
159 }
160
161 /* clear BUSY flag */
162 WREG32_P(mmVCE_STATUS, 0, ~1);
163
164 if (r) {
165 DRM_ERROR("VCE not responding, giving up!!!\n");
166 return r;
167 }
168
169 return 0;
170}
171
172static int vce_v2_0_early_init(void *handle)
173{
174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175
176 vce_v2_0_set_ring_funcs(adev);
177 vce_v2_0_set_irq_funcs(adev);
178
179 return 0;
180}
181
182static int vce_v2_0_sw_init(void *handle)
183{
184 struct amdgpu_ring *ring;
185 int r;
186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
187
188 /* VCE */
189 r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
190 if (r)
191 return r;
192
193 r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
194 VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
195 if (r)
196 return r;
197
198 r = amdgpu_vce_resume(adev);
199 if (r)
200 return r;
201
202 ring = &adev->vce.ring[0];
203 sprintf(ring->name, "vce0");
204 r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
205 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
206 if (r)
207 return r;
208
209 ring = &adev->vce.ring[1];
210 sprintf(ring->name, "vce1");
211 r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
212 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
213 if (r)
214 return r;
215
216 return r;
217}
218
219static int vce_v2_0_sw_fini(void *handle)
220{
221 int r;
222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
223
224 r = amdgpu_vce_suspend(adev);
225 if (r)
226 return r;
227
228 r = amdgpu_vce_sw_fini(adev);
229 if (r)
230 return r;
231
232 return r;
233}
234
235static int vce_v2_0_hw_init(void *handle)
236{
237 struct amdgpu_ring *ring;
238 int r;
239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
240
241 r = vce_v2_0_start(adev);
242 if (r)
243 return r;
244
245 ring = &adev->vce.ring[0];
246 ring->ready = true;
247 r = amdgpu_ring_test_ring(ring);
248 if (r) {
249 ring->ready = false;
250 return r;
251 }
252
253 ring = &adev->vce.ring[1];
254 ring->ready = true;
255 r = amdgpu_ring_test_ring(ring);
256 if (r) {
257 ring->ready = false;
258 return r;
259 }
260
261 DRM_INFO("VCE initialized successfully.\n");
262
263 return 0;
264}
265
266static int vce_v2_0_hw_fini(void *handle)
267{
268 return 0;
269}
270
271static int vce_v2_0_suspend(void *handle)
272{
273 int r;
274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
275
276 r = vce_v2_0_hw_fini(adev);
277 if (r)
278 return r;
279
280 r = amdgpu_vce_suspend(adev);
281 if (r)
282 return r;
283
284 return r;
285}
286
287static int vce_v2_0_resume(void *handle)
288{
289 int r;
290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
291
292 r = amdgpu_vce_resume(adev);
293 if (r)
294 return r;
295
296 r = vce_v2_0_hw_init(adev);
297 if (r)
298 return r;
299
300 return r;
301}
302
303static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
304{
305 u32 tmp;
306
307 if (gated) {
308 tmp = RREG32(mmVCE_CLOCK_GATING_B);
309 tmp |= 0xe70000;
310 WREG32(mmVCE_CLOCK_GATING_B, tmp);
311
312 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
313 tmp |= 0xff000000;
314 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
315
316 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
317 tmp &= ~0x3fc;
318 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
319
320 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
321 } else {
322 tmp = RREG32(mmVCE_CLOCK_GATING_B);
323 tmp |= 0xe7;
324 tmp &= ~0xe70000;
325 WREG32(mmVCE_CLOCK_GATING_B, tmp);
326
327 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
328 tmp |= 0x1fe000;
329 tmp &= ~0xff000000;
330 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
331
332 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
333 tmp |= 0x3fc;
334 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
335 }
336}
337
338static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
339{
340 u32 orig, tmp;
341
342 tmp = RREG32(mmVCE_CLOCK_GATING_B);
343 tmp &= ~0x00060006;
344 if (gated) {
345 tmp |= 0xe10000;
346 } else {
347 tmp |= 0xe1;
348 tmp &= ~0xe10000;
349 }
350 WREG32(mmVCE_CLOCK_GATING_B, tmp);
351
352 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
353 tmp &= ~0x1fe000;
354 tmp &= ~0xff000000;
355 if (tmp != orig)
356 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
357
358 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
359 tmp &= ~0x3fc;
360 if (tmp != orig)
361 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
362
363 if (gated)
364 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
365}
366
367static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
368{
369 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
370}
371
372static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
373{
374 bool sw_cg = false;
375
376 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
377 if (sw_cg)
378 vce_v2_0_set_sw_cg(adev, true);
379 else
380 vce_v2_0_set_dyn_cg(adev, true);
381 } else {
382 vce_v2_0_disable_cg(adev);
383
384 if (sw_cg)
385 vce_v2_0_set_sw_cg(adev, false);
386 else
387 vce_v2_0_set_dyn_cg(adev, false);
388 }
389}
390
391static void vce_v2_0_init_cg(struct amdgpu_device *adev)
392{
393 u32 tmp;
394
395 tmp = RREG32(mmVCE_CLOCK_GATING_A);
396 tmp &= ~0xfff;
397 tmp |= ((0 << 0) | (4 << 4));
398 tmp |= 0x40000;
399 WREG32(mmVCE_CLOCK_GATING_A, tmp);
400
401 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
402 tmp &= ~0xfff;
403 tmp |= ((0 << 0) | (4 << 4));
404 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
405
406 tmp = RREG32(mmVCE_CLOCK_GATING_B);
407 tmp |= 0x10;
408 tmp &= ~0x100000;
409 WREG32(mmVCE_CLOCK_GATING_B, tmp);
410}
411
412static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
413{
414 uint64_t addr = adev->vce.gpu_addr;
415 uint32_t size;
416
417 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
418 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
419 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
420 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
421
422 WREG32(mmVCE_LMI_CTRL, 0x00398000);
423 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
424 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
425 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
426 WREG32(mmVCE_LMI_VM_CTRL, 0);
427
428 addr += AMDGPU_VCE_FIRMWARE_OFFSET;
429 size = VCE_V2_0_FW_SIZE;
430 WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
431 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
432
433 addr += size;
434 size = VCE_V2_0_STACK_SIZE;
435 WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
436 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
437
438 addr += size;
439 size = VCE_V2_0_DATA_SIZE;
440 WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
441 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
442
443 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
444
445 WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
446 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
447
448 vce_v2_0_init_cg(adev);
449}
450
451static bool vce_v2_0_is_idle(void *handle)
452{
453 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
454
455 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
456}
457
458static int vce_v2_0_wait_for_idle(void *handle)
459{
460 unsigned i;
461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
462
463 for (i = 0; i < adev->usec_timeout; i++) {
464 if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
465 return 0;
466 }
467 return -ETIMEDOUT;
468}
469
470static int vce_v2_0_soft_reset(void *handle)
471{
472 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
473
474 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
475 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
476 mdelay(5);
477
478 return vce_v2_0_start(adev);
479}
480
481static void vce_v2_0_print_status(void *handle)
482{
483 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
484
485 dev_info(adev->dev, "VCE 2.0 registers\n");
486 dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
487 RREG32(mmVCE_STATUS));
488 dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
489 RREG32(mmVCE_VCPU_CNTL));
490 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
491 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
492 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
493 RREG32(mmVCE_VCPU_CACHE_SIZE0));
494 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
495 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
496 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
497 RREG32(mmVCE_VCPU_CACHE_SIZE1));
498 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
499 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
500 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
501 RREG32(mmVCE_VCPU_CACHE_SIZE2));
502 dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
503 RREG32(mmVCE_SOFT_RESET));
504 dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
505 RREG32(mmVCE_RB_BASE_LO2));
506 dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
507 RREG32(mmVCE_RB_BASE_HI2));
508 dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
509 RREG32(mmVCE_RB_SIZE2));
510 dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
511 RREG32(mmVCE_RB_RPTR2));
512 dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
513 RREG32(mmVCE_RB_WPTR2));
514 dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
515 RREG32(mmVCE_RB_BASE_LO));
516 dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
517 RREG32(mmVCE_RB_BASE_HI));
518 dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
519 RREG32(mmVCE_RB_SIZE));
520 dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
521 RREG32(mmVCE_RB_RPTR));
522 dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
523 RREG32(mmVCE_RB_WPTR));
524 dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
525 RREG32(mmVCE_CLOCK_GATING_A));
526 dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
527 RREG32(mmVCE_CLOCK_GATING_B));
528 dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
529 RREG32(mmVCE_CGTT_CLK_OVERRIDE));
530 dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
531 RREG32(mmVCE_UENC_CLOCK_GATING));
532 dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
533 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
534 dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
535 RREG32(mmVCE_SYS_INT_EN));
536 dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
537 RREG32(mmVCE_LMI_CTRL2));
538 dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
539 RREG32(mmVCE_LMI_CTRL));
540 dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
541 RREG32(mmVCE_LMI_VM_CTRL));
542 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
543 RREG32(mmVCE_LMI_SWAP_CNTL));
544 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
545 RREG32(mmVCE_LMI_SWAP_CNTL1));
546 dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
547 RREG32(mmVCE_LMI_CACHE_CTRL));
548}
549
550static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
551 struct amdgpu_irq_src *source,
552 unsigned type,
553 enum amdgpu_interrupt_state state)
554{
555 uint32_t val = 0;
556
557 if (state == AMDGPU_IRQ_STATE_ENABLE)
558 val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
559
560 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
561 return 0;
562}
563
564static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
565 struct amdgpu_irq_src *source,
566 struct amdgpu_iv_entry *entry)
567{
568 DRM_DEBUG("IH: VCE\n");
569 switch (entry->src_data) {
570 case 0:
571 amdgpu_fence_process(&adev->vce.ring[0]);
572 break;
573 case 1:
574 amdgpu_fence_process(&adev->vce.ring[1]);
575 break;
576 default:
577 DRM_ERROR("Unhandled interrupt: %d %d\n",
578 entry->src_id, entry->src_data);
579 break;
580 }
581
582 return 0;
583}
584
585static int vce_v2_0_set_clockgating_state(void *handle,
586 enum amd_clockgating_state state)
587{
588 bool gate = false;
589 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
590
591 if (state == AMD_CG_STATE_GATE)
592 gate = true;
593
594 vce_v2_0_enable_mgcg(adev, gate);
595
596 return 0;
597}
598
599static int vce_v2_0_set_powergating_state(void *handle,
600 enum amd_powergating_state state)
601{
602 /* This doesn't actually powergate the VCE block.
603 * That's done in the dpm code via the SMC. This
604 * just re-inits the block as necessary. The actual
605 * gating still happens in the dpm code. We should
606 * revisit this when there is a cleaner line between
607 * the smc and the hw blocks
608 */
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610
611 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
612 return 0;
613
614 if (state == AMD_PG_STATE_GATE)
615 /* XXX do we need a vce_v2_0_stop()? */
616 return 0;
617 else
618 return vce_v2_0_start(adev);
619}
620
621const struct amd_ip_funcs vce_v2_0_ip_funcs = {
622 .early_init = vce_v2_0_early_init,
623 .late_init = NULL,
624 .sw_init = vce_v2_0_sw_init,
625 .sw_fini = vce_v2_0_sw_fini,
626 .hw_init = vce_v2_0_hw_init,
627 .hw_fini = vce_v2_0_hw_fini,
628 .suspend = vce_v2_0_suspend,
629 .resume = vce_v2_0_resume,
630 .is_idle = vce_v2_0_is_idle,
631 .wait_for_idle = vce_v2_0_wait_for_idle,
632 .soft_reset = vce_v2_0_soft_reset,
633 .print_status = vce_v2_0_print_status,
634 .set_clockgating_state = vce_v2_0_set_clockgating_state,
635 .set_powergating_state = vce_v2_0_set_powergating_state,
636};
637
638static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
639 .get_rptr = vce_v2_0_ring_get_rptr,
640 .get_wptr = vce_v2_0_ring_get_wptr,
641 .set_wptr = vce_v2_0_ring_set_wptr,
642 .parse_cs = amdgpu_vce_ring_parse_cs,
643 .emit_ib = amdgpu_vce_ring_emit_ib,
644 .emit_fence = amdgpu_vce_ring_emit_fence,
645 .test_ring = amdgpu_vce_ring_test_ring,
646 .test_ib = amdgpu_vce_ring_test_ib,
647 .insert_nop = amdgpu_ring_insert_nop,
648 .pad_ib = amdgpu_ring_generic_pad_ib,
649};
650
651static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
652{
653 adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
654 adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
655}
656
657static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
658 .set = vce_v2_0_set_interrupt_state,
659 .process = vce_v2_0_process_interrupt,
660};
661
662static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
663{
664 adev->vce.irq.num_types = 1;
665 adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
666};