Loading...
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/aperture.h>
30#include <linux/power_supply.h>
31#include <linux/kthread.h>
32#include <linux/module.h>
33#include <linux/console.h>
34#include <linux/slab.h>
35#include <linux/iommu.h>
36#include <linux/pci.h>
37#include <linux/pci-p2pdma.h>
38#include <linux/apple-gmux.h>
39
40#include <drm/drm_atomic_helper.h>
41#include <drm/drm_client_event.h>
42#include <drm/drm_crtc_helper.h>
43#include <drm/drm_probe_helper.h>
44#include <drm/amdgpu_drm.h>
45#include <linux/device.h>
46#include <linux/vgaarb.h>
47#include <linux/vga_switcheroo.h>
48#include <linux/efi.h>
49#include "amdgpu.h"
50#include "amdgpu_trace.h"
51#include "amdgpu_i2c.h"
52#include "atom.h"
53#include "amdgpu_atombios.h"
54#include "amdgpu_atomfirmware.h"
55#include "amd_pcie.h"
56#ifdef CONFIG_DRM_AMDGPU_SI
57#include "si.h"
58#endif
59#ifdef CONFIG_DRM_AMDGPU_CIK
60#include "cik.h"
61#endif
62#include "vi.h"
63#include "soc15.h"
64#include "nv.h"
65#include "bif/bif_4_1_d.h"
66#include <linux/firmware.h>
67#include "amdgpu_vf_error.h"
68
69#include "amdgpu_amdkfd.h"
70#include "amdgpu_pm.h"
71
72#include "amdgpu_xgmi.h"
73#include "amdgpu_ras.h"
74#include "amdgpu_pmu.h"
75#include "amdgpu_fru_eeprom.h"
76#include "amdgpu_reset.h"
77#include "amdgpu_virt.h"
78#include "amdgpu_dev_coredump.h"
79
80#include <linux/suspend.h>
81#include <drm/task_barrier.h>
82#include <linux/pm_runtime.h>
83
84#include <drm/drm_drv.h>
85
86#if IS_ENABLED(CONFIG_X86)
87#include <asm/intel-family.h>
88#endif
89
90MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
91MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
92MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
93MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
94MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
95MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
96MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
97
98#define AMDGPU_RESUME_MS 2000
99#define AMDGPU_MAX_RETRY_LIMIT 2
100#define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
101#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2)
102#define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2)
103#define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2)
104
105static const struct drm_driver amdgpu_kms_driver;
106
107const char *amdgpu_asic_name[] = {
108 "TAHITI",
109 "PITCAIRN",
110 "VERDE",
111 "OLAND",
112 "HAINAN",
113 "BONAIRE",
114 "KAVERI",
115 "KABINI",
116 "HAWAII",
117 "MULLINS",
118 "TOPAZ",
119 "TONGA",
120 "FIJI",
121 "CARRIZO",
122 "STONEY",
123 "POLARIS10",
124 "POLARIS11",
125 "POLARIS12",
126 "VEGAM",
127 "VEGA10",
128 "VEGA12",
129 "VEGA20",
130 "RAVEN",
131 "ARCTURUS",
132 "RENOIR",
133 "ALDEBARAN",
134 "NAVI10",
135 "CYAN_SKILLFISH",
136 "NAVI14",
137 "NAVI12",
138 "SIENNA_CICHLID",
139 "NAVY_FLOUNDER",
140 "VANGOGH",
141 "DIMGREY_CAVEFISH",
142 "BEIGE_GOBY",
143 "YELLOW_CARP",
144 "IP DISCOVERY",
145 "LAST",
146};
147
148#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM - 1, 0)
149/*
150 * Default init level where all blocks are expected to be initialized. This is
151 * the level of initialization expected by default and also after a full reset
152 * of the device.
153 */
154struct amdgpu_init_level amdgpu_init_default = {
155 .level = AMDGPU_INIT_LEVEL_DEFAULT,
156 .hwini_ip_block_mask = AMDGPU_IP_BLK_MASK_ALL,
157};
158
159struct amdgpu_init_level amdgpu_init_recovery = {
160 .level = AMDGPU_INIT_LEVEL_RESET_RECOVERY,
161 .hwini_ip_block_mask = AMDGPU_IP_BLK_MASK_ALL,
162};
163
164/*
165 * Minimal blocks needed to be initialized before a XGMI hive can be reset. This
166 * is used for cases like reset on initialization where the entire hive needs to
167 * be reset before first use.
168 */
169struct amdgpu_init_level amdgpu_init_minimal_xgmi = {
170 .level = AMDGPU_INIT_LEVEL_MINIMAL_XGMI,
171 .hwini_ip_block_mask =
172 BIT(AMD_IP_BLOCK_TYPE_GMC) | BIT(AMD_IP_BLOCK_TYPE_SMC) |
173 BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) |
174 BIT(AMD_IP_BLOCK_TYPE_PSP)
175};
176
177static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev,
178 enum amd_ip_block_type block)
179{
180 return (adev->init_lvl->hwini_ip_block_mask & (1U << block)) != 0;
181}
182
183void amdgpu_set_init_level(struct amdgpu_device *adev,
184 enum amdgpu_init_lvl_id lvl)
185{
186 switch (lvl) {
187 case AMDGPU_INIT_LEVEL_MINIMAL_XGMI:
188 adev->init_lvl = &amdgpu_init_minimal_xgmi;
189 break;
190 case AMDGPU_INIT_LEVEL_RESET_RECOVERY:
191 adev->init_lvl = &amdgpu_init_recovery;
192 break;
193 case AMDGPU_INIT_LEVEL_DEFAULT:
194 fallthrough;
195 default:
196 adev->init_lvl = &amdgpu_init_default;
197 break;
198 }
199}
200
201static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev);
202
203/**
204 * DOC: pcie_replay_count
205 *
206 * The amdgpu driver provides a sysfs API for reporting the total number
207 * of PCIe replays (NAKs)
208 * The file pcie_replay_count is used for this and returns the total
209 * number of replays as a sum of the NAKs generated and NAKs received
210 */
211
212static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
213 struct device_attribute *attr, char *buf)
214{
215 struct drm_device *ddev = dev_get_drvdata(dev);
216 struct amdgpu_device *adev = drm_to_adev(ddev);
217 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
218
219 return sysfs_emit(buf, "%llu\n", cnt);
220}
221
222static DEVICE_ATTR(pcie_replay_count, 0444,
223 amdgpu_device_get_pcie_replay_count, NULL);
224
225static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,
226 struct bin_attribute *attr, char *buf,
227 loff_t ppos, size_t count)
228{
229 struct device *dev = kobj_to_dev(kobj);
230 struct drm_device *ddev = dev_get_drvdata(dev);
231 struct amdgpu_device *adev = drm_to_adev(ddev);
232 ssize_t bytes_read;
233
234 switch (ppos) {
235 case AMDGPU_SYS_REG_STATE_XGMI:
236 bytes_read = amdgpu_asic_get_reg_state(
237 adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count);
238 break;
239 case AMDGPU_SYS_REG_STATE_WAFL:
240 bytes_read = amdgpu_asic_get_reg_state(
241 adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count);
242 break;
243 case AMDGPU_SYS_REG_STATE_PCIE:
244 bytes_read = amdgpu_asic_get_reg_state(
245 adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count);
246 break;
247 case AMDGPU_SYS_REG_STATE_USR:
248 bytes_read = amdgpu_asic_get_reg_state(
249 adev, AMDGPU_REG_STATE_TYPE_USR, buf, count);
250 break;
251 case AMDGPU_SYS_REG_STATE_USR_1:
252 bytes_read = amdgpu_asic_get_reg_state(
253 adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count);
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 return bytes_read;
260}
261
262BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,
263 AMDGPU_SYS_REG_STATE_END);
264
265int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)
266{
267 int ret;
268
269 if (!amdgpu_asic_get_reg_state_supported(adev))
270 return 0;
271
272 ret = sysfs_create_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
273
274 return ret;
275}
276
277void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev)
278{
279 if (!amdgpu_asic_get_reg_state_supported(adev))
280 return;
281 sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
282}
283
284int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block)
285{
286 int r;
287
288 if (ip_block->version->funcs->suspend) {
289 r = ip_block->version->funcs->suspend(ip_block);
290 if (r) {
291 dev_err(ip_block->adev->dev,
292 "suspend of IP block <%s> failed %d\n",
293 ip_block->version->funcs->name, r);
294 return r;
295 }
296 }
297
298 ip_block->status.hw = false;
299 return 0;
300}
301
302int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block)
303{
304 int r;
305
306 if (ip_block->version->funcs->resume) {
307 r = ip_block->version->funcs->resume(ip_block);
308 if (r) {
309 dev_err(ip_block->adev->dev,
310 "resume of IP block <%s> failed %d\n",
311 ip_block->version->funcs->name, r);
312 return r;
313 }
314 }
315
316 ip_block->status.hw = true;
317 return 0;
318}
319
320/**
321 * DOC: board_info
322 *
323 * The amdgpu driver provides a sysfs API for giving board related information.
324 * It provides the form factor information in the format
325 *
326 * type : form factor
327 *
328 * Possible form factor values
329 *
330 * - "cem" - PCIE CEM card
331 * - "oam" - Open Compute Accelerator Module
332 * - "unknown" - Not known
333 *
334 */
335
336static ssize_t amdgpu_device_get_board_info(struct device *dev,
337 struct device_attribute *attr,
338 char *buf)
339{
340 struct drm_device *ddev = dev_get_drvdata(dev);
341 struct amdgpu_device *adev = drm_to_adev(ddev);
342 enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;
343 const char *pkg;
344
345 if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)
346 pkg_type = adev->smuio.funcs->get_pkg_type(adev);
347
348 switch (pkg_type) {
349 case AMDGPU_PKG_TYPE_CEM:
350 pkg = "cem";
351 break;
352 case AMDGPU_PKG_TYPE_OAM:
353 pkg = "oam";
354 break;
355 default:
356 pkg = "unknown";
357 break;
358 }
359
360 return sysfs_emit(buf, "%s : %s\n", "type", pkg);
361}
362
363static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL);
364
365static struct attribute *amdgpu_board_attrs[] = {
366 &dev_attr_board_info.attr,
367 NULL,
368};
369
370static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,
371 struct attribute *attr, int n)
372{
373 struct device *dev = kobj_to_dev(kobj);
374 struct drm_device *ddev = dev_get_drvdata(dev);
375 struct amdgpu_device *adev = drm_to_adev(ddev);
376
377 if (adev->flags & AMD_IS_APU)
378 return 0;
379
380 return attr->mode;
381}
382
383static const struct attribute_group amdgpu_board_attrs_group = {
384 .attrs = amdgpu_board_attrs,
385 .is_visible = amdgpu_board_attrs_is_visible
386};
387
388static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
389
390
391/**
392 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
393 *
394 * @dev: drm_device pointer
395 *
396 * Returns true if the device is a dGPU with ATPX power control,
397 * otherwise return false.
398 */
399bool amdgpu_device_supports_px(struct drm_device *dev)
400{
401 struct amdgpu_device *adev = drm_to_adev(dev);
402
403 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
404 return true;
405 return false;
406}
407
408/**
409 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
410 *
411 * @dev: drm_device pointer
412 *
413 * Returns true if the device is a dGPU with ACPI power control,
414 * otherwise return false.
415 */
416bool amdgpu_device_supports_boco(struct drm_device *dev)
417{
418 struct amdgpu_device *adev = drm_to_adev(dev);
419
420 if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
421 return false;
422
423 if (adev->has_pr3 ||
424 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
425 return true;
426 return false;
427}
428
429/**
430 * amdgpu_device_supports_baco - Does the device support BACO
431 *
432 * @dev: drm_device pointer
433 *
434 * Return:
435 * 1 if the device supporte BACO;
436 * 3 if the device support MACO (only works if BACO is supported)
437 * otherwise return 0.
438 */
439int amdgpu_device_supports_baco(struct drm_device *dev)
440{
441 struct amdgpu_device *adev = drm_to_adev(dev);
442
443 return amdgpu_asic_supports_baco(adev);
444}
445
446void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev)
447{
448 struct drm_device *dev;
449 int bamaco_support;
450
451 dev = adev_to_drm(adev);
452
453 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
454 bamaco_support = amdgpu_device_supports_baco(dev);
455
456 switch (amdgpu_runtime_pm) {
457 case 2:
458 if (bamaco_support & MACO_SUPPORT) {
459 adev->pm.rpm_mode = AMDGPU_RUNPM_BAMACO;
460 dev_info(adev->dev, "Forcing BAMACO for runtime pm\n");
461 } else if (bamaco_support == BACO_SUPPORT) {
462 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
463 dev_info(adev->dev, "Requested mode BAMACO not available,fallback to use BACO\n");
464 }
465 break;
466 case 1:
467 if (bamaco_support & BACO_SUPPORT) {
468 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
469 dev_info(adev->dev, "Forcing BACO for runtime pm\n");
470 }
471 break;
472 case -1:
473 case -2:
474 if (amdgpu_device_supports_px(dev)) { /* enable PX as runtime mode */
475 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
476 dev_info(adev->dev, "Using ATPX for runtime pm\n");
477 } else if (amdgpu_device_supports_boco(dev)) { /* enable boco as runtime mode */
478 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
479 dev_info(adev->dev, "Using BOCO for runtime pm\n");
480 } else {
481 if (!bamaco_support)
482 goto no_runtime_pm;
483
484 switch (adev->asic_type) {
485 case CHIP_VEGA20:
486 case CHIP_ARCTURUS:
487 /* BACO are not supported on vega20 and arctrus */
488 break;
489 case CHIP_VEGA10:
490 /* enable BACO as runpm mode if noretry=0 */
491 if (!adev->gmc.noretry)
492 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
493 break;
494 default:
495 /* enable BACO as runpm mode on CI+ */
496 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
497 break;
498 }
499
500 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
501 if (bamaco_support & MACO_SUPPORT) {
502 adev->pm.rpm_mode = AMDGPU_RUNPM_BAMACO;
503 dev_info(adev->dev, "Using BAMACO for runtime pm\n");
504 } else {
505 dev_info(adev->dev, "Using BACO for runtime pm\n");
506 }
507 }
508 }
509 break;
510 case 0:
511 dev_info(adev->dev, "runtime pm is manually disabled\n");
512 break;
513 default:
514 break;
515 }
516
517no_runtime_pm:
518 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
519 dev_info(adev->dev, "Runtime PM not available\n");
520}
521/**
522 * amdgpu_device_supports_smart_shift - Is the device dGPU with
523 * smart shift support
524 *
525 * @dev: drm_device pointer
526 *
527 * Returns true if the device is a dGPU with Smart Shift support,
528 * otherwise returns false.
529 */
530bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
531{
532 return (amdgpu_device_supports_boco(dev) &&
533 amdgpu_acpi_is_power_shift_control_supported());
534}
535
536/*
537 * VRAM access helper functions
538 */
539
540/**
541 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
542 *
543 * @adev: amdgpu_device pointer
544 * @pos: offset of the buffer in vram
545 * @buf: virtual address of the buffer in system memory
546 * @size: read/write size, sizeof(@buf) must > @size
547 * @write: true - write to vram, otherwise - read from vram
548 */
549void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
550 void *buf, size_t size, bool write)
551{
552 unsigned long flags;
553 uint32_t hi = ~0, tmp = 0;
554 uint32_t *data = buf;
555 uint64_t last;
556 int idx;
557
558 if (!drm_dev_enter(adev_to_drm(adev), &idx))
559 return;
560
561 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
562
563 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
564 for (last = pos + size; pos < last; pos += 4) {
565 tmp = pos >> 31;
566
567 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
568 if (tmp != hi) {
569 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
570 hi = tmp;
571 }
572 if (write)
573 WREG32_NO_KIQ(mmMM_DATA, *data++);
574 else
575 *data++ = RREG32_NO_KIQ(mmMM_DATA);
576 }
577
578 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
579 drm_dev_exit(idx);
580}
581
582/**
583 * amdgpu_device_aper_access - access vram by vram aperature
584 *
585 * @adev: amdgpu_device pointer
586 * @pos: offset of the buffer in vram
587 * @buf: virtual address of the buffer in system memory
588 * @size: read/write size, sizeof(@buf) must > @size
589 * @write: true - write to vram, otherwise - read from vram
590 *
591 * The return value means how many bytes have been transferred.
592 */
593size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
594 void *buf, size_t size, bool write)
595{
596#ifdef CONFIG_64BIT
597 void __iomem *addr;
598 size_t count = 0;
599 uint64_t last;
600
601 if (!adev->mman.aper_base_kaddr)
602 return 0;
603
604 last = min(pos + size, adev->gmc.visible_vram_size);
605 if (last > pos) {
606 addr = adev->mman.aper_base_kaddr + pos;
607 count = last - pos;
608
609 if (write) {
610 memcpy_toio(addr, buf, count);
611 /* Make sure HDP write cache flush happens without any reordering
612 * after the system memory contents are sent over PCIe device
613 */
614 mb();
615 amdgpu_device_flush_hdp(adev, NULL);
616 } else {
617 amdgpu_device_invalidate_hdp(adev, NULL);
618 /* Make sure HDP read cache is invalidated before issuing a read
619 * to the PCIe device
620 */
621 mb();
622 memcpy_fromio(buf, addr, count);
623 }
624
625 }
626
627 return count;
628#else
629 return 0;
630#endif
631}
632
633/**
634 * amdgpu_device_vram_access - read/write a buffer in vram
635 *
636 * @adev: amdgpu_device pointer
637 * @pos: offset of the buffer in vram
638 * @buf: virtual address of the buffer in system memory
639 * @size: read/write size, sizeof(@buf) must > @size
640 * @write: true - write to vram, otherwise - read from vram
641 */
642void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
643 void *buf, size_t size, bool write)
644{
645 size_t count;
646
647 /* try to using vram apreature to access vram first */
648 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
649 size -= count;
650 if (size) {
651 /* using MM to access rest vram */
652 pos += count;
653 buf += count;
654 amdgpu_device_mm_access(adev, pos, buf, size, write);
655 }
656}
657
658/*
659 * register access helper functions.
660 */
661
662/* Check if hw access should be skipped because of hotplug or device error */
663bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
664{
665 if (adev->no_hw_access)
666 return true;
667
668#ifdef CONFIG_LOCKDEP
669 /*
670 * This is a bit complicated to understand, so worth a comment. What we assert
671 * here is that the GPU reset is not running on another thread in parallel.
672 *
673 * For this we trylock the read side of the reset semaphore, if that succeeds
674 * we know that the reset is not running in paralell.
675 *
676 * If the trylock fails we assert that we are either already holding the read
677 * side of the lock or are the reset thread itself and hold the write side of
678 * the lock.
679 */
680 if (in_task()) {
681 if (down_read_trylock(&adev->reset_domain->sem))
682 up_read(&adev->reset_domain->sem);
683 else
684 lockdep_assert_held(&adev->reset_domain->sem);
685 }
686#endif
687 return false;
688}
689
690/**
691 * amdgpu_device_rreg - read a memory mapped IO or indirect register
692 *
693 * @adev: amdgpu_device pointer
694 * @reg: dword aligned register offset
695 * @acc_flags: access flags which require special behavior
696 *
697 * Returns the 32 bit value from the offset specified.
698 */
699uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
700 uint32_t reg, uint32_t acc_flags)
701{
702 uint32_t ret;
703
704 if (amdgpu_device_skip_hw_access(adev))
705 return 0;
706
707 if ((reg * 4) < adev->rmmio_size) {
708 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
709 amdgpu_sriov_runtime(adev) &&
710 down_read_trylock(&adev->reset_domain->sem)) {
711 ret = amdgpu_kiq_rreg(adev, reg, 0);
712 up_read(&adev->reset_domain->sem);
713 } else {
714 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
715 }
716 } else {
717 ret = adev->pcie_rreg(adev, reg * 4);
718 }
719
720 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
721
722 return ret;
723}
724
725/*
726 * MMIO register read with bytes helper functions
727 * @offset:bytes offset from MMIO start
728 */
729
730/**
731 * amdgpu_mm_rreg8 - read a memory mapped IO register
732 *
733 * @adev: amdgpu_device pointer
734 * @offset: byte aligned register offset
735 *
736 * Returns the 8 bit value from the offset specified.
737 */
738uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
739{
740 if (amdgpu_device_skip_hw_access(adev))
741 return 0;
742
743 if (offset < adev->rmmio_size)
744 return (readb(adev->rmmio + offset));
745 BUG();
746}
747
748
749/**
750 * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
751 *
752 * @adev: amdgpu_device pointer
753 * @reg: dword aligned register offset
754 * @acc_flags: access flags which require special behavior
755 * @xcc_id: xcc accelerated compute core id
756 *
757 * Returns the 32 bit value from the offset specified.
758 */
759uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
760 uint32_t reg, uint32_t acc_flags,
761 uint32_t xcc_id)
762{
763 uint32_t ret, rlcg_flag;
764
765 if (amdgpu_device_skip_hw_access(adev))
766 return 0;
767
768 if ((reg * 4) < adev->rmmio_size) {
769 if (amdgpu_sriov_vf(adev) &&
770 !amdgpu_sriov_runtime(adev) &&
771 adev->gfx.rlc.rlcg_reg_access_supported &&
772 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
773 GC_HWIP, false,
774 &rlcg_flag)) {
775 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id));
776 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
777 amdgpu_sriov_runtime(adev) &&
778 down_read_trylock(&adev->reset_domain->sem)) {
779 ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
780 up_read(&adev->reset_domain->sem);
781 } else {
782 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
783 }
784 } else {
785 ret = adev->pcie_rreg(adev, reg * 4);
786 }
787
788 return ret;
789}
790
791/*
792 * MMIO register write with bytes helper functions
793 * @offset:bytes offset from MMIO start
794 * @value: the value want to be written to the register
795 */
796
797/**
798 * amdgpu_mm_wreg8 - read a memory mapped IO register
799 *
800 * @adev: amdgpu_device pointer
801 * @offset: byte aligned register offset
802 * @value: 8 bit value to write
803 *
804 * Writes the value specified to the offset specified.
805 */
806void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
807{
808 if (amdgpu_device_skip_hw_access(adev))
809 return;
810
811 if (offset < adev->rmmio_size)
812 writeb(value, adev->rmmio + offset);
813 else
814 BUG();
815}
816
817/**
818 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
819 *
820 * @adev: amdgpu_device pointer
821 * @reg: dword aligned register offset
822 * @v: 32 bit value to write to the register
823 * @acc_flags: access flags which require special behavior
824 *
825 * Writes the value specified to the offset specified.
826 */
827void amdgpu_device_wreg(struct amdgpu_device *adev,
828 uint32_t reg, uint32_t v,
829 uint32_t acc_flags)
830{
831 if (amdgpu_device_skip_hw_access(adev))
832 return;
833
834 if ((reg * 4) < adev->rmmio_size) {
835 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
836 amdgpu_sriov_runtime(adev) &&
837 down_read_trylock(&adev->reset_domain->sem)) {
838 amdgpu_kiq_wreg(adev, reg, v, 0);
839 up_read(&adev->reset_domain->sem);
840 } else {
841 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
842 }
843 } else {
844 adev->pcie_wreg(adev, reg * 4, v);
845 }
846
847 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
848}
849
850/**
851 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
852 *
853 * @adev: amdgpu_device pointer
854 * @reg: mmio/rlc register
855 * @v: value to write
856 * @xcc_id: xcc accelerated compute core id
857 *
858 * this function is invoked only for the debugfs register access
859 */
860void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
861 uint32_t reg, uint32_t v,
862 uint32_t xcc_id)
863{
864 if (amdgpu_device_skip_hw_access(adev))
865 return;
866
867 if (amdgpu_sriov_fullaccess(adev) &&
868 adev->gfx.rlc.funcs &&
869 adev->gfx.rlc.funcs->is_rlcg_access_range) {
870 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
871 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
872 } else if ((reg * 4) >= adev->rmmio_size) {
873 adev->pcie_wreg(adev, reg * 4, v);
874 } else {
875 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
876 }
877}
878
879/**
880 * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
881 *
882 * @adev: amdgpu_device pointer
883 * @reg: dword aligned register offset
884 * @v: 32 bit value to write to the register
885 * @acc_flags: access flags which require special behavior
886 * @xcc_id: xcc accelerated compute core id
887 *
888 * Writes the value specified to the offset specified.
889 */
890void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
891 uint32_t reg, uint32_t v,
892 uint32_t acc_flags, uint32_t xcc_id)
893{
894 uint32_t rlcg_flag;
895
896 if (amdgpu_device_skip_hw_access(adev))
897 return;
898
899 if ((reg * 4) < adev->rmmio_size) {
900 if (amdgpu_sriov_vf(adev) &&
901 !amdgpu_sriov_runtime(adev) &&
902 adev->gfx.rlc.rlcg_reg_access_supported &&
903 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
904 GC_HWIP, true,
905 &rlcg_flag)) {
906 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id));
907 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
908 amdgpu_sriov_runtime(adev) &&
909 down_read_trylock(&adev->reset_domain->sem)) {
910 amdgpu_kiq_wreg(adev, reg, v, xcc_id);
911 up_read(&adev->reset_domain->sem);
912 } else {
913 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
914 }
915 } else {
916 adev->pcie_wreg(adev, reg * 4, v);
917 }
918}
919
920/**
921 * amdgpu_device_indirect_rreg - read an indirect register
922 *
923 * @adev: amdgpu_device pointer
924 * @reg_addr: indirect register address to read from
925 *
926 * Returns the value of indirect register @reg_addr
927 */
928u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
929 u32 reg_addr)
930{
931 unsigned long flags, pcie_index, pcie_data;
932 void __iomem *pcie_index_offset;
933 void __iomem *pcie_data_offset;
934 u32 r;
935
936 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
937 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
938
939 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
940 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
941 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
942
943 writel(reg_addr, pcie_index_offset);
944 readl(pcie_index_offset);
945 r = readl(pcie_data_offset);
946 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
947
948 return r;
949}
950
951u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
952 u64 reg_addr)
953{
954 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
955 u32 r;
956 void __iomem *pcie_index_offset;
957 void __iomem *pcie_index_hi_offset;
958 void __iomem *pcie_data_offset;
959
960 if (unlikely(!adev->nbio.funcs)) {
961 pcie_index = AMDGPU_PCIE_INDEX_FALLBACK;
962 pcie_data = AMDGPU_PCIE_DATA_FALLBACK;
963 } else {
964 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
965 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
966 }
967
968 if (reg_addr >> 32) {
969 if (unlikely(!adev->nbio.funcs))
970 pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK;
971 else
972 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
973 } else {
974 pcie_index_hi = 0;
975 }
976
977 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
978 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
979 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
980 if (pcie_index_hi != 0)
981 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
982 pcie_index_hi * 4;
983
984 writel(reg_addr, pcie_index_offset);
985 readl(pcie_index_offset);
986 if (pcie_index_hi != 0) {
987 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
988 readl(pcie_index_hi_offset);
989 }
990 r = readl(pcie_data_offset);
991
992 /* clear the high bits */
993 if (pcie_index_hi != 0) {
994 writel(0, pcie_index_hi_offset);
995 readl(pcie_index_hi_offset);
996 }
997
998 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
999
1000 return r;
1001}
1002
1003/**
1004 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
1005 *
1006 * @adev: amdgpu_device pointer
1007 * @reg_addr: indirect register address to read from
1008 *
1009 * Returns the value of indirect register @reg_addr
1010 */
1011u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1012 u32 reg_addr)
1013{
1014 unsigned long flags, pcie_index, pcie_data;
1015 void __iomem *pcie_index_offset;
1016 void __iomem *pcie_data_offset;
1017 u64 r;
1018
1019 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1020 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1021
1022 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1023 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1024 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1025
1026 /* read low 32 bits */
1027 writel(reg_addr, pcie_index_offset);
1028 readl(pcie_index_offset);
1029 r = readl(pcie_data_offset);
1030 /* read high 32 bits */
1031 writel(reg_addr + 4, pcie_index_offset);
1032 readl(pcie_index_offset);
1033 r |= ((u64)readl(pcie_data_offset) << 32);
1034 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1035
1036 return r;
1037}
1038
1039u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1040 u64 reg_addr)
1041{
1042 unsigned long flags, pcie_index, pcie_data;
1043 unsigned long pcie_index_hi = 0;
1044 void __iomem *pcie_index_offset;
1045 void __iomem *pcie_index_hi_offset;
1046 void __iomem *pcie_data_offset;
1047 u64 r;
1048
1049 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1050 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1051 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1052 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1053
1054 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1055 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1056 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1057 if (pcie_index_hi != 0)
1058 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1059 pcie_index_hi * 4;
1060
1061 /* read low 32 bits */
1062 writel(reg_addr, pcie_index_offset);
1063 readl(pcie_index_offset);
1064 if (pcie_index_hi != 0) {
1065 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1066 readl(pcie_index_hi_offset);
1067 }
1068 r = readl(pcie_data_offset);
1069 /* read high 32 bits */
1070 writel(reg_addr + 4, pcie_index_offset);
1071 readl(pcie_index_offset);
1072 if (pcie_index_hi != 0) {
1073 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1074 readl(pcie_index_hi_offset);
1075 }
1076 r |= ((u64)readl(pcie_data_offset) << 32);
1077
1078 /* clear the high bits */
1079 if (pcie_index_hi != 0) {
1080 writel(0, pcie_index_hi_offset);
1081 readl(pcie_index_hi_offset);
1082 }
1083
1084 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1085
1086 return r;
1087}
1088
1089/**
1090 * amdgpu_device_indirect_wreg - write an indirect register address
1091 *
1092 * @adev: amdgpu_device pointer
1093 * @reg_addr: indirect register offset
1094 * @reg_data: indirect register data
1095 *
1096 */
1097void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1098 u32 reg_addr, u32 reg_data)
1099{
1100 unsigned long flags, pcie_index, pcie_data;
1101 void __iomem *pcie_index_offset;
1102 void __iomem *pcie_data_offset;
1103
1104 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1105 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1106
1107 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1108 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1109 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1110
1111 writel(reg_addr, pcie_index_offset);
1112 readl(pcie_index_offset);
1113 writel(reg_data, pcie_data_offset);
1114 readl(pcie_data_offset);
1115 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1116}
1117
1118void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1119 u64 reg_addr, u32 reg_data)
1120{
1121 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
1122 void __iomem *pcie_index_offset;
1123 void __iomem *pcie_index_hi_offset;
1124 void __iomem *pcie_data_offset;
1125
1126 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1127 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1128 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1129 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1130 else
1131 pcie_index_hi = 0;
1132
1133 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1134 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1135 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1136 if (pcie_index_hi != 0)
1137 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1138 pcie_index_hi * 4;
1139
1140 writel(reg_addr, pcie_index_offset);
1141 readl(pcie_index_offset);
1142 if (pcie_index_hi != 0) {
1143 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1144 readl(pcie_index_hi_offset);
1145 }
1146 writel(reg_data, pcie_data_offset);
1147 readl(pcie_data_offset);
1148
1149 /* clear the high bits */
1150 if (pcie_index_hi != 0) {
1151 writel(0, pcie_index_hi_offset);
1152 readl(pcie_index_hi_offset);
1153 }
1154
1155 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1156}
1157
1158/**
1159 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
1160 *
1161 * @adev: amdgpu_device pointer
1162 * @reg_addr: indirect register offset
1163 * @reg_data: indirect register data
1164 *
1165 */
1166void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1167 u32 reg_addr, u64 reg_data)
1168{
1169 unsigned long flags, pcie_index, pcie_data;
1170 void __iomem *pcie_index_offset;
1171 void __iomem *pcie_data_offset;
1172
1173 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1174 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1175
1176 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1177 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1178 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1179
1180 /* write low 32 bits */
1181 writel(reg_addr, pcie_index_offset);
1182 readl(pcie_index_offset);
1183 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1184 readl(pcie_data_offset);
1185 /* write high 32 bits */
1186 writel(reg_addr + 4, pcie_index_offset);
1187 readl(pcie_index_offset);
1188 writel((u32)(reg_data >> 32), pcie_data_offset);
1189 readl(pcie_data_offset);
1190 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1191}
1192
1193void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1194 u64 reg_addr, u64 reg_data)
1195{
1196 unsigned long flags, pcie_index, pcie_data;
1197 unsigned long pcie_index_hi = 0;
1198 void __iomem *pcie_index_offset;
1199 void __iomem *pcie_index_hi_offset;
1200 void __iomem *pcie_data_offset;
1201
1202 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1203 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1204 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1205 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1206
1207 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1208 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1209 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1210 if (pcie_index_hi != 0)
1211 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1212 pcie_index_hi * 4;
1213
1214 /* write low 32 bits */
1215 writel(reg_addr, pcie_index_offset);
1216 readl(pcie_index_offset);
1217 if (pcie_index_hi != 0) {
1218 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1219 readl(pcie_index_hi_offset);
1220 }
1221 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1222 readl(pcie_data_offset);
1223 /* write high 32 bits */
1224 writel(reg_addr + 4, pcie_index_offset);
1225 readl(pcie_index_offset);
1226 if (pcie_index_hi != 0) {
1227 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1228 readl(pcie_index_hi_offset);
1229 }
1230 writel((u32)(reg_data >> 32), pcie_data_offset);
1231 readl(pcie_data_offset);
1232
1233 /* clear the high bits */
1234 if (pcie_index_hi != 0) {
1235 writel(0, pcie_index_hi_offset);
1236 readl(pcie_index_hi_offset);
1237 }
1238
1239 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1240}
1241
1242/**
1243 * amdgpu_device_get_rev_id - query device rev_id
1244 *
1245 * @adev: amdgpu_device pointer
1246 *
1247 * Return device rev_id
1248 */
1249u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
1250{
1251 return adev->nbio.funcs->get_rev_id(adev);
1252}
1253
1254/**
1255 * amdgpu_invalid_rreg - dummy reg read function
1256 *
1257 * @adev: amdgpu_device pointer
1258 * @reg: offset of register
1259 *
1260 * Dummy register read function. Used for register blocks
1261 * that certain asics don't have (all asics).
1262 * Returns the value in the register.
1263 */
1264static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
1265{
1266 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
1267 BUG();
1268 return 0;
1269}
1270
1271static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1272{
1273 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1274 BUG();
1275 return 0;
1276}
1277
1278/**
1279 * amdgpu_invalid_wreg - dummy reg write function
1280 *
1281 * @adev: amdgpu_device pointer
1282 * @reg: offset of register
1283 * @v: value to write to the register
1284 *
1285 * Dummy register read function. Used for register blocks
1286 * that certain asics don't have (all asics).
1287 */
1288static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1289{
1290 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
1291 reg, v);
1292 BUG();
1293}
1294
1295static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1296{
1297 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
1298 reg, v);
1299 BUG();
1300}
1301
1302/**
1303 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
1304 *
1305 * @adev: amdgpu_device pointer
1306 * @reg: offset of register
1307 *
1308 * Dummy register read function. Used for register blocks
1309 * that certain asics don't have (all asics).
1310 * Returns the value in the register.
1311 */
1312static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1313{
1314 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
1315 BUG();
1316 return 0;
1317}
1318
1319static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1320{
1321 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1322 BUG();
1323 return 0;
1324}
1325
1326/**
1327 * amdgpu_invalid_wreg64 - dummy reg write function
1328 *
1329 * @adev: amdgpu_device pointer
1330 * @reg: offset of register
1331 * @v: value to write to the register
1332 *
1333 * Dummy register read function. Used for register blocks
1334 * that certain asics don't have (all asics).
1335 */
1336static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1337{
1338 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
1339 reg, v);
1340 BUG();
1341}
1342
1343static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
1344{
1345 DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
1346 reg, v);
1347 BUG();
1348}
1349
1350/**
1351 * amdgpu_block_invalid_rreg - dummy reg read function
1352 *
1353 * @adev: amdgpu_device pointer
1354 * @block: offset of instance
1355 * @reg: offset of register
1356 *
1357 * Dummy register read function. Used for register blocks
1358 * that certain asics don't have (all asics).
1359 * Returns the value in the register.
1360 */
1361static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
1362 uint32_t block, uint32_t reg)
1363{
1364 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1365 reg, block);
1366 BUG();
1367 return 0;
1368}
1369
1370/**
1371 * amdgpu_block_invalid_wreg - dummy reg write function
1372 *
1373 * @adev: amdgpu_device pointer
1374 * @block: offset of instance
1375 * @reg: offset of register
1376 * @v: value to write to the register
1377 *
1378 * Dummy register read function. Used for register blocks
1379 * that certain asics don't have (all asics).
1380 */
1381static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
1382 uint32_t block,
1383 uint32_t reg, uint32_t v)
1384{
1385 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1386 reg, block, v);
1387 BUG();
1388}
1389
1390/**
1391 * amdgpu_device_asic_init - Wrapper for atom asic_init
1392 *
1393 * @adev: amdgpu_device pointer
1394 *
1395 * Does any asic specific work and then calls atom asic init.
1396 */
1397static int amdgpu_device_asic_init(struct amdgpu_device *adev)
1398{
1399 int ret;
1400
1401 amdgpu_asic_pre_asic_init(adev);
1402
1403 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1404 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
1405 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
1406 amdgpu_psp_wait_for_bootloader(adev);
1407 ret = amdgpu_atomfirmware_asic_init(adev, true);
1408 return ret;
1409 } else {
1410 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
1411 }
1412
1413 return 0;
1414}
1415
1416/**
1417 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
1418 *
1419 * @adev: amdgpu_device pointer
1420 *
1421 * Allocates a scratch page of VRAM for use by various things in the
1422 * driver.
1423 */
1424static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
1425{
1426 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1427 AMDGPU_GEM_DOMAIN_VRAM |
1428 AMDGPU_GEM_DOMAIN_GTT,
1429 &adev->mem_scratch.robj,
1430 &adev->mem_scratch.gpu_addr,
1431 (void **)&adev->mem_scratch.ptr);
1432}
1433
1434/**
1435 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
1436 *
1437 * @adev: amdgpu_device pointer
1438 *
1439 * Frees the VRAM scratch page.
1440 */
1441static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
1442{
1443 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
1444}
1445
1446/**
1447 * amdgpu_device_program_register_sequence - program an array of registers.
1448 *
1449 * @adev: amdgpu_device pointer
1450 * @registers: pointer to the register array
1451 * @array_size: size of the register array
1452 *
1453 * Programs an array or registers with and or masks.
1454 * This is a helper for setting golden registers.
1455 */
1456void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1457 const u32 *registers,
1458 const u32 array_size)
1459{
1460 u32 tmp, reg, and_mask, or_mask;
1461 int i;
1462
1463 if (array_size % 3)
1464 return;
1465
1466 for (i = 0; i < array_size; i += 3) {
1467 reg = registers[i + 0];
1468 and_mask = registers[i + 1];
1469 or_mask = registers[i + 2];
1470
1471 if (and_mask == 0xffffffff) {
1472 tmp = or_mask;
1473 } else {
1474 tmp = RREG32(reg);
1475 tmp &= ~and_mask;
1476 if (adev->family >= AMDGPU_FAMILY_AI)
1477 tmp |= (or_mask & and_mask);
1478 else
1479 tmp |= or_mask;
1480 }
1481 WREG32(reg, tmp);
1482 }
1483}
1484
1485/**
1486 * amdgpu_device_pci_config_reset - reset the GPU
1487 *
1488 * @adev: amdgpu_device pointer
1489 *
1490 * Resets the GPU using the pci config reset sequence.
1491 * Only applicable to asics prior to vega10.
1492 */
1493void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1494{
1495 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1496}
1497
1498/**
1499 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1500 *
1501 * @adev: amdgpu_device pointer
1502 *
1503 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1504 */
1505int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1506{
1507 return pci_reset_function(adev->pdev);
1508}
1509
1510/*
1511 * amdgpu_device_wb_*()
1512 * Writeback is the method by which the GPU updates special pages in memory
1513 * with the status of certain GPU events (fences, ring pointers,etc.).
1514 */
1515
1516/**
1517 * amdgpu_device_wb_fini - Disable Writeback and free memory
1518 *
1519 * @adev: amdgpu_device pointer
1520 *
1521 * Disables Writeback and frees the Writeback memory (all asics).
1522 * Used at driver shutdown.
1523 */
1524static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1525{
1526 if (adev->wb.wb_obj) {
1527 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1528 &adev->wb.gpu_addr,
1529 (void **)&adev->wb.wb);
1530 adev->wb.wb_obj = NULL;
1531 }
1532}
1533
1534/**
1535 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1536 *
1537 * @adev: amdgpu_device pointer
1538 *
1539 * Initializes writeback and allocates writeback memory (all asics).
1540 * Used at driver startup.
1541 * Returns 0 on success or an -error on failure.
1542 */
1543static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1544{
1545 int r;
1546
1547 if (adev->wb.wb_obj == NULL) {
1548 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1549 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1551 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1552 (void **)&adev->wb.wb);
1553 if (r) {
1554 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1555 return r;
1556 }
1557
1558 adev->wb.num_wb = AMDGPU_MAX_WB;
1559 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1560
1561 /* clear wb memory */
1562 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1563 }
1564
1565 return 0;
1566}
1567
1568/**
1569 * amdgpu_device_wb_get - Allocate a wb entry
1570 *
1571 * @adev: amdgpu_device pointer
1572 * @wb: wb index
1573 *
1574 * Allocate a wb slot for use by the driver (all asics).
1575 * Returns 0 on success or -EINVAL on failure.
1576 */
1577int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1578{
1579 unsigned long flags, offset;
1580
1581 spin_lock_irqsave(&adev->wb.lock, flags);
1582 offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1583 if (offset < adev->wb.num_wb) {
1584 __set_bit(offset, adev->wb.used);
1585 spin_unlock_irqrestore(&adev->wb.lock, flags);
1586 *wb = offset << 3; /* convert to dw offset */
1587 return 0;
1588 } else {
1589 spin_unlock_irqrestore(&adev->wb.lock, flags);
1590 return -EINVAL;
1591 }
1592}
1593
1594/**
1595 * amdgpu_device_wb_free - Free a wb entry
1596 *
1597 * @adev: amdgpu_device pointer
1598 * @wb: wb index
1599 *
1600 * Free a wb slot allocated for use by the driver (all asics)
1601 */
1602void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1603{
1604 unsigned long flags;
1605
1606 wb >>= 3;
1607 spin_lock_irqsave(&adev->wb.lock, flags);
1608 if (wb < adev->wb.num_wb)
1609 __clear_bit(wb, adev->wb.used);
1610 spin_unlock_irqrestore(&adev->wb.lock, flags);
1611}
1612
1613/**
1614 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1615 *
1616 * @adev: amdgpu_device pointer
1617 *
1618 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1619 * to fail, but if any of the BARs is not accessible after the size we abort
1620 * driver loading by returning -ENODEV.
1621 */
1622int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1623{
1624 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1625 struct pci_bus *root;
1626 struct resource *res;
1627 unsigned int i;
1628 u16 cmd;
1629 int r;
1630
1631 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1632 return 0;
1633
1634 /* Bypass for VF */
1635 if (amdgpu_sriov_vf(adev))
1636 return 0;
1637
1638 /* resizing on Dell G5 SE platforms causes problems with runtime pm */
1639 if ((amdgpu_runtime_pm != 0) &&
1640 adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
1641 adev->pdev->device == 0x731f &&
1642 adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
1643 return 0;
1644
1645 /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
1646 if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
1647 DRM_WARN("System can't access extended configuration space, please check!!\n");
1648
1649 /* skip if the bios has already enabled large BAR */
1650 if (adev->gmc.real_vram_size &&
1651 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1652 return 0;
1653
1654 /* Check if the root BUS has 64bit memory resources */
1655 root = adev->pdev->bus;
1656 while (root->parent)
1657 root = root->parent;
1658
1659 pci_bus_for_each_resource(root, res, i) {
1660 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1661 res->start > 0x100000000ull)
1662 break;
1663 }
1664
1665 /* Trying to resize is pointless without a root hub window above 4GB */
1666 if (!res)
1667 return 0;
1668
1669 /* Limit the BAR size to what is available */
1670 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1671 rbar_size);
1672
1673 /* Disable memory decoding while we change the BAR addresses and size */
1674 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1675 pci_write_config_word(adev->pdev, PCI_COMMAND,
1676 cmd & ~PCI_COMMAND_MEMORY);
1677
1678 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1679 amdgpu_doorbell_fini(adev);
1680 if (adev->asic_type >= CHIP_BONAIRE)
1681 pci_release_resource(adev->pdev, 2);
1682
1683 pci_release_resource(adev->pdev, 0);
1684
1685 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1686 if (r == -ENOSPC)
1687 DRM_INFO("Not enough PCI address space for a large BAR.");
1688 else if (r && r != -ENOTSUPP)
1689 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1690
1691 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1692
1693 /* When the doorbell or fb BAR isn't available we have no chance of
1694 * using the device.
1695 */
1696 r = amdgpu_doorbell_init(adev);
1697 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1698 return -ENODEV;
1699
1700 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1701
1702 return 0;
1703}
1704
1705static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1706{
1707 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1708 return false;
1709
1710 return true;
1711}
1712
1713/*
1714 * GPU helpers function.
1715 */
1716/**
1717 * amdgpu_device_need_post - check if the hw need post or not
1718 *
1719 * @adev: amdgpu_device pointer
1720 *
1721 * Check if the asic has been initialized (all asics) at driver startup
1722 * or post is needed if hw reset is performed.
1723 * Returns true if need or false if not.
1724 */
1725bool amdgpu_device_need_post(struct amdgpu_device *adev)
1726{
1727 uint32_t reg;
1728
1729 if (amdgpu_sriov_vf(adev))
1730 return false;
1731
1732 if (!amdgpu_device_read_bios(adev))
1733 return false;
1734
1735 if (amdgpu_passthrough(adev)) {
1736 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1737 * some old smc fw still need driver do vPost otherwise gpu hang, while
1738 * those smc fw version above 22.15 doesn't have this flaw, so we force
1739 * vpost executed for smc version below 22.15
1740 */
1741 if (adev->asic_type == CHIP_FIJI) {
1742 int err;
1743 uint32_t fw_ver;
1744
1745 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1746 /* force vPost if error occured */
1747 if (err)
1748 return true;
1749
1750 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1751 release_firmware(adev->pm.fw);
1752 if (fw_ver < 0x00160e00)
1753 return true;
1754 }
1755 }
1756
1757 /* Don't post if we need to reset whole hive on init */
1758 if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI)
1759 return false;
1760
1761 if (adev->has_hw_reset) {
1762 adev->has_hw_reset = false;
1763 return true;
1764 }
1765
1766 /* bios scratch used on CIK+ */
1767 if (adev->asic_type >= CHIP_BONAIRE)
1768 return amdgpu_atombios_scratch_need_asic_init(adev);
1769
1770 /* check MEM_SIZE for older asics */
1771 reg = amdgpu_asic_get_config_memsize(adev);
1772
1773 if ((reg != 0) && (reg != 0xffffffff))
1774 return false;
1775
1776 return true;
1777}
1778
1779/*
1780 * Check whether seamless boot is supported.
1781 *
1782 * So far we only support seamless boot on DCE 3.0 or later.
1783 * If users report that it works on older ASICS as well, we may
1784 * loosen this.
1785 */
1786bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
1787{
1788 switch (amdgpu_seamless) {
1789 case -1:
1790 break;
1791 case 1:
1792 return true;
1793 case 0:
1794 return false;
1795 default:
1796 DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",
1797 amdgpu_seamless);
1798 return false;
1799 }
1800
1801 if (!(adev->flags & AMD_IS_APU))
1802 return false;
1803
1804 if (adev->mman.keep_stolen_vga_memory)
1805 return false;
1806
1807 return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0);
1808}
1809
1810/*
1811 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
1812 * don't support dynamic speed switching. Until we have confirmation from Intel
1813 * that a specific host supports it, it's safer that we keep it disabled for all.
1814 *
1815 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1816 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1817 */
1818static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev)
1819{
1820#if IS_ENABLED(CONFIG_X86)
1821 struct cpuinfo_x86 *c = &cpu_data(0);
1822
1823 /* eGPU change speeds based on USB4 fabric conditions */
1824 if (dev_is_removable(adev->dev))
1825 return true;
1826
1827 if (c->x86_vendor == X86_VENDOR_INTEL)
1828 return false;
1829#endif
1830 return true;
1831}
1832
1833/**
1834 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1835 *
1836 * @adev: amdgpu_device pointer
1837 *
1838 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1839 * be set for this device.
1840 *
1841 * Returns true if it should be used or false if not.
1842 */
1843bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1844{
1845 switch (amdgpu_aspm) {
1846 case -1:
1847 break;
1848 case 0:
1849 return false;
1850 case 1:
1851 return true;
1852 default:
1853 return false;
1854 }
1855 if (adev->flags & AMD_IS_APU)
1856 return false;
1857 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
1858 return false;
1859 return pcie_aspm_enabled(adev->pdev);
1860}
1861
1862/* if we get transitioned to only one device, take VGA back */
1863/**
1864 * amdgpu_device_vga_set_decode - enable/disable vga decode
1865 *
1866 * @pdev: PCI device pointer
1867 * @state: enable/disable vga decode
1868 *
1869 * Enable/disable vga decode (all asics).
1870 * Returns VGA resource flags.
1871 */
1872static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1873 bool state)
1874{
1875 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1876
1877 amdgpu_asic_set_vga_state(adev, state);
1878 if (state)
1879 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1880 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1881 else
1882 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1883}
1884
1885/**
1886 * amdgpu_device_check_block_size - validate the vm block size
1887 *
1888 * @adev: amdgpu_device pointer
1889 *
1890 * Validates the vm block size specified via module parameter.
1891 * The vm block size defines number of bits in page table versus page directory,
1892 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1893 * page table and the remaining bits are in the page directory.
1894 */
1895static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1896{
1897 /* defines number of bits in page table versus page directory,
1898 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1899 * page table and the remaining bits are in the page directory
1900 */
1901 if (amdgpu_vm_block_size == -1)
1902 return;
1903
1904 if (amdgpu_vm_block_size < 9) {
1905 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1906 amdgpu_vm_block_size);
1907 amdgpu_vm_block_size = -1;
1908 }
1909}
1910
1911/**
1912 * amdgpu_device_check_vm_size - validate the vm size
1913 *
1914 * @adev: amdgpu_device pointer
1915 *
1916 * Validates the vm size in GB specified via module parameter.
1917 * The VM size is the size of the GPU virtual memory space in GB.
1918 */
1919static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1920{
1921 /* no need to check the default value */
1922 if (amdgpu_vm_size == -1)
1923 return;
1924
1925 if (amdgpu_vm_size < 1) {
1926 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1927 amdgpu_vm_size);
1928 amdgpu_vm_size = -1;
1929 }
1930}
1931
1932static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1933{
1934 struct sysinfo si;
1935 bool is_os_64 = (sizeof(void *) == 8);
1936 uint64_t total_memory;
1937 uint64_t dram_size_seven_GB = 0x1B8000000;
1938 uint64_t dram_size_three_GB = 0xB8000000;
1939
1940 if (amdgpu_smu_memory_pool_size == 0)
1941 return;
1942
1943 if (!is_os_64) {
1944 DRM_WARN("Not 64-bit OS, feature not supported\n");
1945 goto def_value;
1946 }
1947 si_meminfo(&si);
1948 total_memory = (uint64_t)si.totalram * si.mem_unit;
1949
1950 if ((amdgpu_smu_memory_pool_size == 1) ||
1951 (amdgpu_smu_memory_pool_size == 2)) {
1952 if (total_memory < dram_size_three_GB)
1953 goto def_value1;
1954 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1955 (amdgpu_smu_memory_pool_size == 8)) {
1956 if (total_memory < dram_size_seven_GB)
1957 goto def_value1;
1958 } else {
1959 DRM_WARN("Smu memory pool size not supported\n");
1960 goto def_value;
1961 }
1962 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1963
1964 return;
1965
1966def_value1:
1967 DRM_WARN("No enough system memory\n");
1968def_value:
1969 adev->pm.smu_prv_buffer_size = 0;
1970}
1971
1972static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1973{
1974 if (!(adev->flags & AMD_IS_APU) ||
1975 adev->asic_type < CHIP_RAVEN)
1976 return 0;
1977
1978 switch (adev->asic_type) {
1979 case CHIP_RAVEN:
1980 if (adev->pdev->device == 0x15dd)
1981 adev->apu_flags |= AMD_APU_IS_RAVEN;
1982 if (adev->pdev->device == 0x15d8)
1983 adev->apu_flags |= AMD_APU_IS_PICASSO;
1984 break;
1985 case CHIP_RENOIR:
1986 if ((adev->pdev->device == 0x1636) ||
1987 (adev->pdev->device == 0x164c))
1988 adev->apu_flags |= AMD_APU_IS_RENOIR;
1989 else
1990 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1991 break;
1992 case CHIP_VANGOGH:
1993 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1994 break;
1995 case CHIP_YELLOW_CARP:
1996 break;
1997 case CHIP_CYAN_SKILLFISH:
1998 if ((adev->pdev->device == 0x13FE) ||
1999 (adev->pdev->device == 0x143F))
2000 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
2001 break;
2002 default:
2003 break;
2004 }
2005
2006 return 0;
2007}
2008
2009/**
2010 * amdgpu_device_check_arguments - validate module params
2011 *
2012 * @adev: amdgpu_device pointer
2013 *
2014 * Validates certain module parameters and updates
2015 * the associated values used by the driver (all asics).
2016 */
2017static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
2018{
2019 int i;
2020
2021 if (amdgpu_sched_jobs < 4) {
2022 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
2023 amdgpu_sched_jobs);
2024 amdgpu_sched_jobs = 4;
2025 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
2026 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
2027 amdgpu_sched_jobs);
2028 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
2029 }
2030
2031 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
2032 /* gart size must be greater or equal to 32M */
2033 dev_warn(adev->dev, "gart size (%d) too small\n",
2034 amdgpu_gart_size);
2035 amdgpu_gart_size = -1;
2036 }
2037
2038 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
2039 /* gtt size must be greater or equal to 32M */
2040 dev_warn(adev->dev, "gtt size (%d) too small\n",
2041 amdgpu_gtt_size);
2042 amdgpu_gtt_size = -1;
2043 }
2044
2045 /* valid range is between 4 and 9 inclusive */
2046 if (amdgpu_vm_fragment_size != -1 &&
2047 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
2048 dev_warn(adev->dev, "valid range is between 4 and 9\n");
2049 amdgpu_vm_fragment_size = -1;
2050 }
2051
2052 if (amdgpu_sched_hw_submission < 2) {
2053 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
2054 amdgpu_sched_hw_submission);
2055 amdgpu_sched_hw_submission = 2;
2056 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
2057 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
2058 amdgpu_sched_hw_submission);
2059 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
2060 }
2061
2062 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
2063 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
2064 amdgpu_reset_method = -1;
2065 }
2066
2067 amdgpu_device_check_smu_prv_buffer_size(adev);
2068
2069 amdgpu_device_check_vm_size(adev);
2070
2071 amdgpu_device_check_block_size(adev);
2072
2073 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
2074
2075 for (i = 0; i < MAX_XCP; i++)
2076 adev->enforce_isolation[i] = !!enforce_isolation;
2077
2078 return 0;
2079}
2080
2081/**
2082 * amdgpu_switcheroo_set_state - set switcheroo state
2083 *
2084 * @pdev: pci dev pointer
2085 * @state: vga_switcheroo state
2086 *
2087 * Callback for the switcheroo driver. Suspends or resumes
2088 * the asics before or after it is powered up using ACPI methods.
2089 */
2090static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
2091 enum vga_switcheroo_state state)
2092{
2093 struct drm_device *dev = pci_get_drvdata(pdev);
2094 int r;
2095
2096 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
2097 return;
2098
2099 if (state == VGA_SWITCHEROO_ON) {
2100 pr_info("switched on\n");
2101 /* don't suspend or resume card normally */
2102 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2103
2104 pci_set_power_state(pdev, PCI_D0);
2105 amdgpu_device_load_pci_state(pdev);
2106 r = pci_enable_device(pdev);
2107 if (r)
2108 DRM_WARN("pci_enable_device failed (%d)\n", r);
2109 amdgpu_device_resume(dev, true);
2110
2111 dev->switch_power_state = DRM_SWITCH_POWER_ON;
2112 } else {
2113 pr_info("switched off\n");
2114 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2115 amdgpu_device_prepare(dev);
2116 amdgpu_device_suspend(dev, true);
2117 amdgpu_device_cache_pci_state(pdev);
2118 /* Shut down the device */
2119 pci_disable_device(pdev);
2120 pci_set_power_state(pdev, PCI_D3cold);
2121 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
2122 }
2123}
2124
2125/**
2126 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
2127 *
2128 * @pdev: pci dev pointer
2129 *
2130 * Callback for the switcheroo driver. Check of the switcheroo
2131 * state can be changed.
2132 * Returns true if the state can be changed, false if not.
2133 */
2134static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
2135{
2136 struct drm_device *dev = pci_get_drvdata(pdev);
2137
2138 /*
2139 * FIXME: open_count is protected by drm_global_mutex but that would lead to
2140 * locking inversion with the driver load path. And the access here is
2141 * completely racy anyway. So don't bother with locking for now.
2142 */
2143 return atomic_read(&dev->open_count) == 0;
2144}
2145
2146static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
2147 .set_gpu_state = amdgpu_switcheroo_set_state,
2148 .reprobe = NULL,
2149 .can_switch = amdgpu_switcheroo_can_switch,
2150};
2151
2152/**
2153 * amdgpu_device_ip_set_clockgating_state - set the CG state
2154 *
2155 * @dev: amdgpu_device pointer
2156 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2157 * @state: clockgating state (gate or ungate)
2158 *
2159 * Sets the requested clockgating state for all instances of
2160 * the hardware IP specified.
2161 * Returns the error code from the last instance.
2162 */
2163int amdgpu_device_ip_set_clockgating_state(void *dev,
2164 enum amd_ip_block_type block_type,
2165 enum amd_clockgating_state state)
2166{
2167 struct amdgpu_device *adev = dev;
2168 int i, r = 0;
2169
2170 for (i = 0; i < adev->num_ip_blocks; i++) {
2171 if (!adev->ip_blocks[i].status.valid)
2172 continue;
2173 if (adev->ip_blocks[i].version->type != block_type)
2174 continue;
2175 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
2176 continue;
2177 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
2178 (void *)adev, state);
2179 if (r)
2180 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
2181 adev->ip_blocks[i].version->funcs->name, r);
2182 }
2183 return r;
2184}
2185
2186/**
2187 * amdgpu_device_ip_set_powergating_state - set the PG state
2188 *
2189 * @dev: amdgpu_device pointer
2190 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2191 * @state: powergating state (gate or ungate)
2192 *
2193 * Sets the requested powergating state for all instances of
2194 * the hardware IP specified.
2195 * Returns the error code from the last instance.
2196 */
2197int amdgpu_device_ip_set_powergating_state(void *dev,
2198 enum amd_ip_block_type block_type,
2199 enum amd_powergating_state state)
2200{
2201 struct amdgpu_device *adev = dev;
2202 int i, r = 0;
2203
2204 for (i = 0; i < adev->num_ip_blocks; i++) {
2205 if (!adev->ip_blocks[i].status.valid)
2206 continue;
2207 if (adev->ip_blocks[i].version->type != block_type)
2208 continue;
2209 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
2210 continue;
2211 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
2212 (void *)adev, state);
2213 if (r)
2214 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
2215 adev->ip_blocks[i].version->funcs->name, r);
2216 }
2217 return r;
2218}
2219
2220/**
2221 * amdgpu_device_ip_get_clockgating_state - get the CG state
2222 *
2223 * @adev: amdgpu_device pointer
2224 * @flags: clockgating feature flags
2225 *
2226 * Walks the list of IPs on the device and updates the clockgating
2227 * flags for each IP.
2228 * Updates @flags with the feature flags for each hardware IP where
2229 * clockgating is enabled.
2230 */
2231void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
2232 u64 *flags)
2233{
2234 int i;
2235
2236 for (i = 0; i < adev->num_ip_blocks; i++) {
2237 if (!adev->ip_blocks[i].status.valid)
2238 continue;
2239 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
2240 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
2241 }
2242}
2243
2244/**
2245 * amdgpu_device_ip_wait_for_idle - wait for idle
2246 *
2247 * @adev: amdgpu_device pointer
2248 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2249 *
2250 * Waits for the request hardware IP to be idle.
2251 * Returns 0 for success or a negative error code on failure.
2252 */
2253int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
2254 enum amd_ip_block_type block_type)
2255{
2256 int i, r;
2257
2258 for (i = 0; i < adev->num_ip_blocks; i++) {
2259 if (!adev->ip_blocks[i].status.valid)
2260 continue;
2261 if (adev->ip_blocks[i].version->type == block_type) {
2262 if (adev->ip_blocks[i].version->funcs->wait_for_idle) {
2263 r = adev->ip_blocks[i].version->funcs->wait_for_idle(
2264 &adev->ip_blocks[i]);
2265 if (r)
2266 return r;
2267 }
2268 break;
2269 }
2270 }
2271 return 0;
2272
2273}
2274
2275/**
2276 * amdgpu_device_ip_is_valid - is the hardware IP enabled
2277 *
2278 * @adev: amdgpu_device pointer
2279 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2280 *
2281 * Check if the hardware IP is enable or not.
2282 * Returns true if it the IP is enable, false if not.
2283 */
2284bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,
2285 enum amd_ip_block_type block_type)
2286{
2287 int i;
2288
2289 for (i = 0; i < adev->num_ip_blocks; i++) {
2290 if (adev->ip_blocks[i].version->type == block_type)
2291 return adev->ip_blocks[i].status.valid;
2292 }
2293 return false;
2294
2295}
2296
2297/**
2298 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
2299 *
2300 * @adev: amdgpu_device pointer
2301 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
2302 *
2303 * Returns a pointer to the hardware IP block structure
2304 * if it exists for the asic, otherwise NULL.
2305 */
2306struct amdgpu_ip_block *
2307amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
2308 enum amd_ip_block_type type)
2309{
2310 int i;
2311
2312 for (i = 0; i < adev->num_ip_blocks; i++)
2313 if (adev->ip_blocks[i].version->type == type)
2314 return &adev->ip_blocks[i];
2315
2316 return NULL;
2317}
2318
2319/**
2320 * amdgpu_device_ip_block_version_cmp
2321 *
2322 * @adev: amdgpu_device pointer
2323 * @type: enum amd_ip_block_type
2324 * @major: major version
2325 * @minor: minor version
2326 *
2327 * return 0 if equal or greater
2328 * return 1 if smaller or the ip_block doesn't exist
2329 */
2330int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
2331 enum amd_ip_block_type type,
2332 u32 major, u32 minor)
2333{
2334 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
2335
2336 if (ip_block && ((ip_block->version->major > major) ||
2337 ((ip_block->version->major == major) &&
2338 (ip_block->version->minor >= minor))))
2339 return 0;
2340
2341 return 1;
2342}
2343
2344/**
2345 * amdgpu_device_ip_block_add
2346 *
2347 * @adev: amdgpu_device pointer
2348 * @ip_block_version: pointer to the IP to add
2349 *
2350 * Adds the IP block driver information to the collection of IPs
2351 * on the asic.
2352 */
2353int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
2354 const struct amdgpu_ip_block_version *ip_block_version)
2355{
2356 if (!ip_block_version)
2357 return -EINVAL;
2358
2359 switch (ip_block_version->type) {
2360 case AMD_IP_BLOCK_TYPE_VCN:
2361 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
2362 return 0;
2363 break;
2364 case AMD_IP_BLOCK_TYPE_JPEG:
2365 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
2366 return 0;
2367 break;
2368 default:
2369 break;
2370 }
2371
2372 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2373 ip_block_version->funcs->name);
2374
2375 adev->ip_blocks[adev->num_ip_blocks].adev = adev;
2376
2377 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
2378
2379 return 0;
2380}
2381
2382/**
2383 * amdgpu_device_enable_virtual_display - enable virtual display feature
2384 *
2385 * @adev: amdgpu_device pointer
2386 *
2387 * Enabled the virtual display feature if the user has enabled it via
2388 * the module parameter virtual_display. This feature provides a virtual
2389 * display hardware on headless boards or in virtualized environments.
2390 * This function parses and validates the configuration string specified by
2391 * the user and configues the virtual display configuration (number of
2392 * virtual connectors, crtcs, etc.) specified.
2393 */
2394static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
2395{
2396 adev->enable_virtual_display = false;
2397
2398 if (amdgpu_virtual_display) {
2399 const char *pci_address_name = pci_name(adev->pdev);
2400 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
2401
2402 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
2403 pciaddstr_tmp = pciaddstr;
2404 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
2405 pciaddname = strsep(&pciaddname_tmp, ",");
2406 if (!strcmp("all", pciaddname)
2407 || !strcmp(pci_address_name, pciaddname)) {
2408 long num_crtc;
2409 int res = -1;
2410
2411 adev->enable_virtual_display = true;
2412
2413 if (pciaddname_tmp)
2414 res = kstrtol(pciaddname_tmp, 10,
2415 &num_crtc);
2416
2417 if (!res) {
2418 if (num_crtc < 1)
2419 num_crtc = 1;
2420 if (num_crtc > 6)
2421 num_crtc = 6;
2422 adev->mode_info.num_crtc = num_crtc;
2423 } else {
2424 adev->mode_info.num_crtc = 1;
2425 }
2426 break;
2427 }
2428 }
2429
2430 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
2431 amdgpu_virtual_display, pci_address_name,
2432 adev->enable_virtual_display, adev->mode_info.num_crtc);
2433
2434 kfree(pciaddstr);
2435 }
2436}
2437
2438void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
2439{
2440 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
2441 adev->mode_info.num_crtc = 1;
2442 adev->enable_virtual_display = true;
2443 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
2444 adev->enable_virtual_display, adev->mode_info.num_crtc);
2445 }
2446}
2447
2448/**
2449 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
2450 *
2451 * @adev: amdgpu_device pointer
2452 *
2453 * Parses the asic configuration parameters specified in the gpu info
2454 * firmware and makes them availale to the driver for use in configuring
2455 * the asic.
2456 * Returns 0 on success, -EINVAL on failure.
2457 */
2458static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
2459{
2460 const char *chip_name;
2461 int err;
2462 const struct gpu_info_firmware_header_v1_0 *hdr;
2463
2464 adev->firmware.gpu_info_fw = NULL;
2465
2466 if (adev->mman.discovery_bin)
2467 return 0;
2468
2469 switch (adev->asic_type) {
2470 default:
2471 return 0;
2472 case CHIP_VEGA10:
2473 chip_name = "vega10";
2474 break;
2475 case CHIP_VEGA12:
2476 chip_name = "vega12";
2477 break;
2478 case CHIP_RAVEN:
2479 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2480 chip_name = "raven2";
2481 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2482 chip_name = "picasso";
2483 else
2484 chip_name = "raven";
2485 break;
2486 case CHIP_ARCTURUS:
2487 chip_name = "arcturus";
2488 break;
2489 case CHIP_NAVI12:
2490 chip_name = "navi12";
2491 break;
2492 }
2493
2494 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw,
2495 "amdgpu/%s_gpu_info.bin", chip_name);
2496 if (err) {
2497 dev_err(adev->dev,
2498 "Failed to get gpu_info firmware \"%s_gpu_info.bin\"\n",
2499 chip_name);
2500 goto out;
2501 }
2502
2503 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2504 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2505
2506 switch (hdr->version_major) {
2507 case 1:
2508 {
2509 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2510 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2511 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2512
2513 /*
2514 * Should be droped when DAL no longer needs it.
2515 */
2516 if (adev->asic_type == CHIP_NAVI12)
2517 goto parse_soc_bounding_box;
2518
2519 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2520 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2521 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2522 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2523 adev->gfx.config.max_texture_channel_caches =
2524 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2525 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2526 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2527 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2528 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2529 adev->gfx.config.double_offchip_lds_buf =
2530 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2531 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2532 adev->gfx.cu_info.max_waves_per_simd =
2533 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2534 adev->gfx.cu_info.max_scratch_slots_per_cu =
2535 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2536 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2537 if (hdr->version_minor >= 1) {
2538 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2539 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2540 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2541 adev->gfx.config.num_sc_per_sh =
2542 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2543 adev->gfx.config.num_packer_per_sc =
2544 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2545 }
2546
2547parse_soc_bounding_box:
2548 /*
2549 * soc bounding box info is not integrated in disocovery table,
2550 * we always need to parse it from gpu info firmware if needed.
2551 */
2552 if (hdr->version_minor == 2) {
2553 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2554 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2555 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2556 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2557 }
2558 break;
2559 }
2560 default:
2561 dev_err(adev->dev,
2562 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2563 err = -EINVAL;
2564 goto out;
2565 }
2566out:
2567 return err;
2568}
2569
2570/**
2571 * amdgpu_device_ip_early_init - run early init for hardware IPs
2572 *
2573 * @adev: amdgpu_device pointer
2574 *
2575 * Early initialization pass for hardware IPs. The hardware IPs that make
2576 * up each asic are discovered each IP's early_init callback is run. This
2577 * is the first stage in initializing the asic.
2578 * Returns 0 on success, negative error code on failure.
2579 */
2580static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2581{
2582 struct amdgpu_ip_block *ip_block;
2583 struct pci_dev *parent;
2584 int i, r;
2585 bool total;
2586
2587 amdgpu_device_enable_virtual_display(adev);
2588
2589 if (amdgpu_sriov_vf(adev)) {
2590 r = amdgpu_virt_request_full_gpu(adev, true);
2591 if (r)
2592 return r;
2593 }
2594
2595 switch (adev->asic_type) {
2596#ifdef CONFIG_DRM_AMDGPU_SI
2597 case CHIP_VERDE:
2598 case CHIP_TAHITI:
2599 case CHIP_PITCAIRN:
2600 case CHIP_OLAND:
2601 case CHIP_HAINAN:
2602 adev->family = AMDGPU_FAMILY_SI;
2603 r = si_set_ip_blocks(adev);
2604 if (r)
2605 return r;
2606 break;
2607#endif
2608#ifdef CONFIG_DRM_AMDGPU_CIK
2609 case CHIP_BONAIRE:
2610 case CHIP_HAWAII:
2611 case CHIP_KAVERI:
2612 case CHIP_KABINI:
2613 case CHIP_MULLINS:
2614 if (adev->flags & AMD_IS_APU)
2615 adev->family = AMDGPU_FAMILY_KV;
2616 else
2617 adev->family = AMDGPU_FAMILY_CI;
2618
2619 r = cik_set_ip_blocks(adev);
2620 if (r)
2621 return r;
2622 break;
2623#endif
2624 case CHIP_TOPAZ:
2625 case CHIP_TONGA:
2626 case CHIP_FIJI:
2627 case CHIP_POLARIS10:
2628 case CHIP_POLARIS11:
2629 case CHIP_POLARIS12:
2630 case CHIP_VEGAM:
2631 case CHIP_CARRIZO:
2632 case CHIP_STONEY:
2633 if (adev->flags & AMD_IS_APU)
2634 adev->family = AMDGPU_FAMILY_CZ;
2635 else
2636 adev->family = AMDGPU_FAMILY_VI;
2637
2638 r = vi_set_ip_blocks(adev);
2639 if (r)
2640 return r;
2641 break;
2642 default:
2643 r = amdgpu_discovery_set_ip_blocks(adev);
2644 if (r)
2645 return r;
2646 break;
2647 }
2648
2649 if (amdgpu_has_atpx() &&
2650 (amdgpu_is_atpx_hybrid() ||
2651 amdgpu_has_atpx_dgpu_power_cntl()) &&
2652 ((adev->flags & AMD_IS_APU) == 0) &&
2653 !dev_is_removable(&adev->pdev->dev))
2654 adev->flags |= AMD_IS_PX;
2655
2656 if (!(adev->flags & AMD_IS_APU)) {
2657 parent = pcie_find_root_port(adev->pdev);
2658 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2659 }
2660
2661
2662 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2663 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2664 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2665 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2666 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2667 if (!amdgpu_device_pcie_dynamic_switching_supported(adev))
2668 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
2669
2670 total = true;
2671 for (i = 0; i < adev->num_ip_blocks; i++) {
2672 ip_block = &adev->ip_blocks[i];
2673
2674 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2675 DRM_WARN("disabled ip block: %d <%s>\n",
2676 i, adev->ip_blocks[i].version->funcs->name);
2677 adev->ip_blocks[i].status.valid = false;
2678 } else if (ip_block->version->funcs->early_init) {
2679 r = ip_block->version->funcs->early_init(ip_block);
2680 if (r == -ENOENT) {
2681 adev->ip_blocks[i].status.valid = false;
2682 } else if (r) {
2683 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2684 adev->ip_blocks[i].version->funcs->name, r);
2685 total = false;
2686 } else {
2687 adev->ip_blocks[i].status.valid = true;
2688 }
2689 } else {
2690 adev->ip_blocks[i].status.valid = true;
2691 }
2692 /* get the vbios after the asic_funcs are set up */
2693 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2694 r = amdgpu_device_parse_gpu_info_fw(adev);
2695 if (r)
2696 return r;
2697
2698 /* Read BIOS */
2699 if (amdgpu_device_read_bios(adev)) {
2700 if (!amdgpu_get_bios(adev))
2701 return -EINVAL;
2702
2703 r = amdgpu_atombios_init(adev);
2704 if (r) {
2705 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2706 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2707 return r;
2708 }
2709 }
2710
2711 /*get pf2vf msg info at it's earliest time*/
2712 if (amdgpu_sriov_vf(adev))
2713 amdgpu_virt_init_data_exchange(adev);
2714
2715 }
2716 }
2717 if (!total)
2718 return -ENODEV;
2719
2720 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
2721 if (ip_block->status.valid != false)
2722 amdgpu_amdkfd_device_probe(adev);
2723
2724 adev->cg_flags &= amdgpu_cg_mask;
2725 adev->pg_flags &= amdgpu_pg_mask;
2726
2727 return 0;
2728}
2729
2730static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2731{
2732 int i, r;
2733
2734 for (i = 0; i < adev->num_ip_blocks; i++) {
2735 if (!adev->ip_blocks[i].status.sw)
2736 continue;
2737 if (adev->ip_blocks[i].status.hw)
2738 continue;
2739 if (!amdgpu_ip_member_of_hwini(
2740 adev, adev->ip_blocks[i].version->type))
2741 continue;
2742 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2743 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2744 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2745 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2746 if (r) {
2747 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2748 adev->ip_blocks[i].version->funcs->name, r);
2749 return r;
2750 }
2751 adev->ip_blocks[i].status.hw = true;
2752 }
2753 }
2754
2755 return 0;
2756}
2757
2758static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2759{
2760 int i, r;
2761
2762 for (i = 0; i < adev->num_ip_blocks; i++) {
2763 if (!adev->ip_blocks[i].status.sw)
2764 continue;
2765 if (adev->ip_blocks[i].status.hw)
2766 continue;
2767 if (!amdgpu_ip_member_of_hwini(
2768 adev, adev->ip_blocks[i].version->type))
2769 continue;
2770 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2771 if (r) {
2772 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2773 adev->ip_blocks[i].version->funcs->name, r);
2774 return r;
2775 }
2776 adev->ip_blocks[i].status.hw = true;
2777 }
2778
2779 return 0;
2780}
2781
2782static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2783{
2784 int r = 0;
2785 int i;
2786 uint32_t smu_version;
2787
2788 if (adev->asic_type >= CHIP_VEGA10) {
2789 for (i = 0; i < adev->num_ip_blocks; i++) {
2790 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2791 continue;
2792
2793 if (!amdgpu_ip_member_of_hwini(adev,
2794 AMD_IP_BLOCK_TYPE_PSP))
2795 break;
2796
2797 if (!adev->ip_blocks[i].status.sw)
2798 continue;
2799
2800 /* no need to do the fw loading again if already done*/
2801 if (adev->ip_blocks[i].status.hw == true)
2802 break;
2803
2804 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2805 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
2806 if (r)
2807 return r;
2808 } else {
2809 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2810 if (r) {
2811 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2812 adev->ip_blocks[i].version->funcs->name, r);
2813 return r;
2814 }
2815 adev->ip_blocks[i].status.hw = true;
2816 }
2817 break;
2818 }
2819 }
2820
2821 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2822 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2823
2824 return r;
2825}
2826
2827static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2828{
2829 long timeout;
2830 int r, i;
2831
2832 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2833 struct amdgpu_ring *ring = adev->rings[i];
2834
2835 /* No need to setup the GPU scheduler for rings that don't need it */
2836 if (!ring || ring->no_scheduler)
2837 continue;
2838
2839 switch (ring->funcs->type) {
2840 case AMDGPU_RING_TYPE_GFX:
2841 timeout = adev->gfx_timeout;
2842 break;
2843 case AMDGPU_RING_TYPE_COMPUTE:
2844 timeout = adev->compute_timeout;
2845 break;
2846 case AMDGPU_RING_TYPE_SDMA:
2847 timeout = adev->sdma_timeout;
2848 break;
2849 default:
2850 timeout = adev->video_timeout;
2851 break;
2852 }
2853
2854 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL,
2855 DRM_SCHED_PRIORITY_COUNT,
2856 ring->num_hw_submission, 0,
2857 timeout, adev->reset_domain->wq,
2858 ring->sched_score, ring->name,
2859 adev->dev);
2860 if (r) {
2861 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2862 ring->name);
2863 return r;
2864 }
2865 r = amdgpu_uvd_entity_init(adev, ring);
2866 if (r) {
2867 DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2868 ring->name);
2869 return r;
2870 }
2871 r = amdgpu_vce_entity_init(adev, ring);
2872 if (r) {
2873 DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2874 ring->name);
2875 return r;
2876 }
2877 }
2878
2879 amdgpu_xcp_update_partition_sched_list(adev);
2880
2881 return 0;
2882}
2883
2884
2885/**
2886 * amdgpu_device_ip_init - run init for hardware IPs
2887 *
2888 * @adev: amdgpu_device pointer
2889 *
2890 * Main initialization pass for hardware IPs. The list of all the hardware
2891 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2892 * are run. sw_init initializes the software state associated with each IP
2893 * and hw_init initializes the hardware associated with each IP.
2894 * Returns 0 on success, negative error code on failure.
2895 */
2896static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2897{
2898 bool init_badpage;
2899 int i, r;
2900
2901 r = amdgpu_ras_init(adev);
2902 if (r)
2903 return r;
2904
2905 for (i = 0; i < adev->num_ip_blocks; i++) {
2906 if (!adev->ip_blocks[i].status.valid)
2907 continue;
2908 if (adev->ip_blocks[i].version->funcs->sw_init) {
2909 r = adev->ip_blocks[i].version->funcs->sw_init(&adev->ip_blocks[i]);
2910 if (r) {
2911 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2912 adev->ip_blocks[i].version->funcs->name, r);
2913 goto init_failed;
2914 }
2915 }
2916 adev->ip_blocks[i].status.sw = true;
2917
2918 if (!amdgpu_ip_member_of_hwini(
2919 adev, adev->ip_blocks[i].version->type))
2920 continue;
2921
2922 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2923 /* need to do common hw init early so everything is set up for gmc */
2924 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2925 if (r) {
2926 DRM_ERROR("hw_init %d failed %d\n", i, r);
2927 goto init_failed;
2928 }
2929 adev->ip_blocks[i].status.hw = true;
2930 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2931 /* need to do gmc hw init early so we can allocate gpu mem */
2932 /* Try to reserve bad pages early */
2933 if (amdgpu_sriov_vf(adev))
2934 amdgpu_virt_exchange_data(adev);
2935
2936 r = amdgpu_device_mem_scratch_init(adev);
2937 if (r) {
2938 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2939 goto init_failed;
2940 }
2941 r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]);
2942 if (r) {
2943 DRM_ERROR("hw_init %d failed %d\n", i, r);
2944 goto init_failed;
2945 }
2946 r = amdgpu_device_wb_init(adev);
2947 if (r) {
2948 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2949 goto init_failed;
2950 }
2951 adev->ip_blocks[i].status.hw = true;
2952
2953 /* right after GMC hw init, we create CSA */
2954 if (adev->gfx.mcbp) {
2955 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2956 AMDGPU_GEM_DOMAIN_VRAM |
2957 AMDGPU_GEM_DOMAIN_GTT,
2958 AMDGPU_CSA_SIZE);
2959 if (r) {
2960 DRM_ERROR("allocate CSA failed %d\n", r);
2961 goto init_failed;
2962 }
2963 }
2964
2965 r = amdgpu_seq64_init(adev);
2966 if (r) {
2967 DRM_ERROR("allocate seq64 failed %d\n", r);
2968 goto init_failed;
2969 }
2970 }
2971 }
2972
2973 if (amdgpu_sriov_vf(adev))
2974 amdgpu_virt_init_data_exchange(adev);
2975
2976 r = amdgpu_ib_pool_init(adev);
2977 if (r) {
2978 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2979 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2980 goto init_failed;
2981 }
2982
2983 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2984 if (r)
2985 goto init_failed;
2986
2987 r = amdgpu_device_ip_hw_init_phase1(adev);
2988 if (r)
2989 goto init_failed;
2990
2991 r = amdgpu_device_fw_loading(adev);
2992 if (r)
2993 goto init_failed;
2994
2995 r = amdgpu_device_ip_hw_init_phase2(adev);
2996 if (r)
2997 goto init_failed;
2998
2999 /*
3000 * retired pages will be loaded from eeprom and reserved here,
3001 * it should be called after amdgpu_device_ip_hw_init_phase2 since
3002 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
3003 * for I2C communication which only true at this point.
3004 *
3005 * amdgpu_ras_recovery_init may fail, but the upper only cares the
3006 * failure from bad gpu situation and stop amdgpu init process
3007 * accordingly. For other failed cases, it will still release all
3008 * the resource and print error message, rather than returning one
3009 * negative value to upper level.
3010 *
3011 * Note: theoretically, this should be called before all vram allocations
3012 * to protect retired page from abusing
3013 */
3014 init_badpage = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI);
3015 r = amdgpu_ras_recovery_init(adev, init_badpage);
3016 if (r)
3017 goto init_failed;
3018
3019 /**
3020 * In case of XGMI grab extra reference for reset domain for this device
3021 */
3022 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3023 if (amdgpu_xgmi_add_device(adev) == 0) {
3024 if (!amdgpu_sriov_vf(adev)) {
3025 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3026
3027 if (WARN_ON(!hive)) {
3028 r = -ENOENT;
3029 goto init_failed;
3030 }
3031
3032 if (!hive->reset_domain ||
3033 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
3034 r = -ENOENT;
3035 amdgpu_put_xgmi_hive(hive);
3036 goto init_failed;
3037 }
3038
3039 /* Drop the early temporary reset domain we created for device */
3040 amdgpu_reset_put_reset_domain(adev->reset_domain);
3041 adev->reset_domain = hive->reset_domain;
3042 amdgpu_put_xgmi_hive(hive);
3043 }
3044 }
3045 }
3046
3047 r = amdgpu_device_init_schedulers(adev);
3048 if (r)
3049 goto init_failed;
3050
3051 if (adev->mman.buffer_funcs_ring->sched.ready)
3052 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3053
3054 /* Don't init kfd if whole hive need to be reset during init */
3055 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
3056 kgd2kfd_init_zone_device(adev);
3057 amdgpu_amdkfd_device_init(adev);
3058 }
3059
3060 amdgpu_fru_get_product_info(adev);
3061
3062init_failed:
3063
3064 return r;
3065}
3066
3067/**
3068 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
3069 *
3070 * @adev: amdgpu_device pointer
3071 *
3072 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
3073 * this function before a GPU reset. If the value is retained after a
3074 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
3075 */
3076static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
3077{
3078 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
3079}
3080
3081/**
3082 * amdgpu_device_check_vram_lost - check if vram is valid
3083 *
3084 * @adev: amdgpu_device pointer
3085 *
3086 * Checks the reset magic value written to the gart pointer in VRAM.
3087 * The driver calls this after a GPU reset to see if the contents of
3088 * VRAM is lost or now.
3089 * returns true if vram is lost, false if not.
3090 */
3091static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
3092{
3093 if (memcmp(adev->gart.ptr, adev->reset_magic,
3094 AMDGPU_RESET_MAGIC_NUM))
3095 return true;
3096
3097 if (!amdgpu_in_reset(adev))
3098 return false;
3099
3100 /*
3101 * For all ASICs with baco/mode1 reset, the VRAM is
3102 * always assumed to be lost.
3103 */
3104 switch (amdgpu_asic_reset_method(adev)) {
3105 case AMD_RESET_METHOD_BACO:
3106 case AMD_RESET_METHOD_MODE1:
3107 return true;
3108 default:
3109 return false;
3110 }
3111}
3112
3113/**
3114 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
3115 *
3116 * @adev: amdgpu_device pointer
3117 * @state: clockgating state (gate or ungate)
3118 *
3119 * The list of all the hardware IPs that make up the asic is walked and the
3120 * set_clockgating_state callbacks are run.
3121 * Late initialization pass enabling clockgating for hardware IPs.
3122 * Fini or suspend, pass disabling clockgating for hardware IPs.
3123 * Returns 0 on success, negative error code on failure.
3124 */
3125
3126int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
3127 enum amd_clockgating_state state)
3128{
3129 int i, j, r;
3130
3131 if (amdgpu_emu_mode == 1)
3132 return 0;
3133
3134 for (j = 0; j < adev->num_ip_blocks; j++) {
3135 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
3136 if (!adev->ip_blocks[i].status.late_initialized)
3137 continue;
3138 /* skip CG for GFX, SDMA on S0ix */
3139 if (adev->in_s0ix &&
3140 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3141 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
3142 continue;
3143 /* skip CG for VCE/UVD, it's handled specially */
3144 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
3145 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
3146 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
3147 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
3148 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
3149 /* enable clockgating to save power */
3150 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
3151 state);
3152 if (r) {
3153 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
3154 adev->ip_blocks[i].version->funcs->name, r);
3155 return r;
3156 }
3157 }
3158 }
3159
3160 return 0;
3161}
3162
3163int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
3164 enum amd_powergating_state state)
3165{
3166 int i, j, r;
3167
3168 if (amdgpu_emu_mode == 1)
3169 return 0;
3170
3171 for (j = 0; j < adev->num_ip_blocks; j++) {
3172 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
3173 if (!adev->ip_blocks[i].status.late_initialized)
3174 continue;
3175 /* skip PG for GFX, SDMA on S0ix */
3176 if (adev->in_s0ix &&
3177 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3178 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
3179 continue;
3180 /* skip CG for VCE/UVD, it's handled specially */
3181 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
3182 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
3183 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
3184 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
3185 adev->ip_blocks[i].version->funcs->set_powergating_state) {
3186 /* enable powergating to save power */
3187 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
3188 state);
3189 if (r) {
3190 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
3191 adev->ip_blocks[i].version->funcs->name, r);
3192 return r;
3193 }
3194 }
3195 }
3196 return 0;
3197}
3198
3199static int amdgpu_device_enable_mgpu_fan_boost(void)
3200{
3201 struct amdgpu_gpu_instance *gpu_ins;
3202 struct amdgpu_device *adev;
3203 int i, ret = 0;
3204
3205 mutex_lock(&mgpu_info.mutex);
3206
3207 /*
3208 * MGPU fan boost feature should be enabled
3209 * only when there are two or more dGPUs in
3210 * the system
3211 */
3212 if (mgpu_info.num_dgpu < 2)
3213 goto out;
3214
3215 for (i = 0; i < mgpu_info.num_dgpu; i++) {
3216 gpu_ins = &(mgpu_info.gpu_ins[i]);
3217 adev = gpu_ins->adev;
3218 if (!(adev->flags & AMD_IS_APU) &&
3219 !gpu_ins->mgpu_fan_enabled) {
3220 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
3221 if (ret)
3222 break;
3223
3224 gpu_ins->mgpu_fan_enabled = 1;
3225 }
3226 }
3227
3228out:
3229 mutex_unlock(&mgpu_info.mutex);
3230
3231 return ret;
3232}
3233
3234/**
3235 * amdgpu_device_ip_late_init - run late init for hardware IPs
3236 *
3237 * @adev: amdgpu_device pointer
3238 *
3239 * Late initialization pass for hardware IPs. The list of all the hardware
3240 * IPs that make up the asic is walked and the late_init callbacks are run.
3241 * late_init covers any special initialization that an IP requires
3242 * after all of the have been initialized or something that needs to happen
3243 * late in the init process.
3244 * Returns 0 on success, negative error code on failure.
3245 */
3246static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
3247{
3248 struct amdgpu_gpu_instance *gpu_instance;
3249 int i = 0, r;
3250
3251 for (i = 0; i < adev->num_ip_blocks; i++) {
3252 if (!adev->ip_blocks[i].status.hw)
3253 continue;
3254 if (adev->ip_blocks[i].version->funcs->late_init) {
3255 r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]);
3256 if (r) {
3257 DRM_ERROR("late_init of IP block <%s> failed %d\n",
3258 adev->ip_blocks[i].version->funcs->name, r);
3259 return r;
3260 }
3261 }
3262 adev->ip_blocks[i].status.late_initialized = true;
3263 }
3264
3265 r = amdgpu_ras_late_init(adev);
3266 if (r) {
3267 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
3268 return r;
3269 }
3270
3271 if (!amdgpu_reset_in_recovery(adev))
3272 amdgpu_ras_set_error_query_ready(adev, true);
3273
3274 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
3275 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
3276
3277 amdgpu_device_fill_reset_magic(adev);
3278
3279 r = amdgpu_device_enable_mgpu_fan_boost();
3280 if (r)
3281 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
3282
3283 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
3284 if (amdgpu_passthrough(adev) &&
3285 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
3286 adev->asic_type == CHIP_ALDEBARAN))
3287 amdgpu_dpm_handle_passthrough_sbr(adev, true);
3288
3289 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3290 mutex_lock(&mgpu_info.mutex);
3291
3292 /*
3293 * Reset device p-state to low as this was booted with high.
3294 *
3295 * This should be performed only after all devices from the same
3296 * hive get initialized.
3297 *
3298 * However, it's unknown how many device in the hive in advance.
3299 * As this is counted one by one during devices initializations.
3300 *
3301 * So, we wait for all XGMI interlinked devices initialized.
3302 * This may bring some delays as those devices may come from
3303 * different hives. But that should be OK.
3304 */
3305 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
3306 for (i = 0; i < mgpu_info.num_gpu; i++) {
3307 gpu_instance = &(mgpu_info.gpu_ins[i]);
3308 if (gpu_instance->adev->flags & AMD_IS_APU)
3309 continue;
3310
3311 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
3312 AMDGPU_XGMI_PSTATE_MIN);
3313 if (r) {
3314 DRM_ERROR("pstate setting failed (%d).\n", r);
3315 break;
3316 }
3317 }
3318 }
3319
3320 mutex_unlock(&mgpu_info.mutex);
3321 }
3322
3323 return 0;
3324}
3325
3326static void amdgpu_ip_block_hw_fini(struct amdgpu_ip_block *ip_block)
3327{
3328 int r;
3329
3330 if (!ip_block->version->funcs->hw_fini) {
3331 DRM_ERROR("hw_fini of IP block <%s> not defined\n",
3332 ip_block->version->funcs->name);
3333 } else {
3334 r = ip_block->version->funcs->hw_fini(ip_block);
3335 /* XXX handle errors */
3336 if (r) {
3337 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3338 ip_block->version->funcs->name, r);
3339 }
3340 }
3341
3342 ip_block->status.hw = false;
3343}
3344
3345/**
3346 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
3347 *
3348 * @adev: amdgpu_device pointer
3349 *
3350 * For ASICs need to disable SMC first
3351 */
3352static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
3353{
3354 int i;
3355
3356 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
3357 return;
3358
3359 for (i = 0; i < adev->num_ip_blocks; i++) {
3360 if (!adev->ip_blocks[i].status.hw)
3361 continue;
3362 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3363 amdgpu_ip_block_hw_fini(&adev->ip_blocks[i]);
3364 break;
3365 }
3366 }
3367}
3368
3369static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
3370{
3371 int i, r;
3372
3373 for (i = 0; i < adev->num_ip_blocks; i++) {
3374 if (!adev->ip_blocks[i].version->funcs->early_fini)
3375 continue;
3376
3377 r = adev->ip_blocks[i].version->funcs->early_fini(&adev->ip_blocks[i]);
3378 if (r) {
3379 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
3380 adev->ip_blocks[i].version->funcs->name, r);
3381 }
3382 }
3383
3384 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3385 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3386
3387 amdgpu_amdkfd_suspend(adev, false);
3388
3389 /* Workaroud for ASICs need to disable SMC first */
3390 amdgpu_device_smu_fini_early(adev);
3391
3392 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3393 if (!adev->ip_blocks[i].status.hw)
3394 continue;
3395
3396 amdgpu_ip_block_hw_fini(&adev->ip_blocks[i]);
3397 }
3398
3399 if (amdgpu_sriov_vf(adev)) {
3400 if (amdgpu_virt_release_full_gpu(adev, false))
3401 DRM_ERROR("failed to release exclusive mode on fini\n");
3402 }
3403
3404 return 0;
3405}
3406
3407/**
3408 * amdgpu_device_ip_fini - run fini for hardware IPs
3409 *
3410 * @adev: amdgpu_device pointer
3411 *
3412 * Main teardown pass for hardware IPs. The list of all the hardware
3413 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
3414 * are run. hw_fini tears down the hardware associated with each IP
3415 * and sw_fini tears down any software state associated with each IP.
3416 * Returns 0 on success, negative error code on failure.
3417 */
3418static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
3419{
3420 int i, r;
3421
3422 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
3423 amdgpu_virt_release_ras_err_handler_data(adev);
3424
3425 if (adev->gmc.xgmi.num_physical_nodes > 1)
3426 amdgpu_xgmi_remove_device(adev);
3427
3428 amdgpu_amdkfd_device_fini_sw(adev);
3429
3430 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3431 if (!adev->ip_blocks[i].status.sw)
3432 continue;
3433
3434 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
3435 amdgpu_ucode_free_bo(adev);
3436 amdgpu_free_static_csa(&adev->virt.csa_obj);
3437 amdgpu_device_wb_fini(adev);
3438 amdgpu_device_mem_scratch_fini(adev);
3439 amdgpu_ib_pool_fini(adev);
3440 amdgpu_seq64_fini(adev);
3441 }
3442 if (adev->ip_blocks[i].version->funcs->sw_fini) {
3443 r = adev->ip_blocks[i].version->funcs->sw_fini(&adev->ip_blocks[i]);
3444 /* XXX handle errors */
3445 if (r) {
3446 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
3447 adev->ip_blocks[i].version->funcs->name, r);
3448 }
3449 }
3450 adev->ip_blocks[i].status.sw = false;
3451 adev->ip_blocks[i].status.valid = false;
3452 }
3453
3454 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3455 if (!adev->ip_blocks[i].status.late_initialized)
3456 continue;
3457 if (adev->ip_blocks[i].version->funcs->late_fini)
3458 adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]);
3459 adev->ip_blocks[i].status.late_initialized = false;
3460 }
3461
3462 amdgpu_ras_fini(adev);
3463
3464 return 0;
3465}
3466
3467/**
3468 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
3469 *
3470 * @work: work_struct.
3471 */
3472static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
3473{
3474 struct amdgpu_device *adev =
3475 container_of(work, struct amdgpu_device, delayed_init_work.work);
3476 int r;
3477
3478 r = amdgpu_ib_ring_tests(adev);
3479 if (r)
3480 DRM_ERROR("ib ring test failed (%d).\n", r);
3481}
3482
3483static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
3484{
3485 struct amdgpu_device *adev =
3486 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
3487
3488 WARN_ON_ONCE(adev->gfx.gfx_off_state);
3489 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3490
3491 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3492 adev->gfx.gfx_off_state = true;
3493}
3494
3495/**
3496 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
3497 *
3498 * @adev: amdgpu_device pointer
3499 *
3500 * Main suspend function for hardware IPs. The list of all the hardware
3501 * IPs that make up the asic is walked, clockgating is disabled and the
3502 * suspend callbacks are run. suspend puts the hardware and software state
3503 * in each IP into a state suitable for suspend.
3504 * Returns 0 on success, negative error code on failure.
3505 */
3506static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
3507{
3508 int i, r;
3509
3510 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3511 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3512
3513 /*
3514 * Per PMFW team's suggestion, driver needs to handle gfxoff
3515 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
3516 * scenario. Add the missing df cstate disablement here.
3517 */
3518 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
3519 dev_warn(adev->dev, "Failed to disallow df cstate");
3520
3521 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3522 if (!adev->ip_blocks[i].status.valid)
3523 continue;
3524
3525 /* displays are handled separately */
3526 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
3527 continue;
3528
3529 /* XXX handle errors */
3530 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
3531 if (r)
3532 return r;
3533 }
3534
3535 return 0;
3536}
3537
3538/**
3539 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3540 *
3541 * @adev: amdgpu_device pointer
3542 *
3543 * Main suspend function for hardware IPs. The list of all the hardware
3544 * IPs that make up the asic is walked, clockgating is disabled and the
3545 * suspend callbacks are run. suspend puts the hardware and software state
3546 * in each IP into a state suitable for suspend.
3547 * Returns 0 on success, negative error code on failure.
3548 */
3549static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3550{
3551 int i, r;
3552
3553 if (adev->in_s0ix)
3554 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3555
3556 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3557 if (!adev->ip_blocks[i].status.valid)
3558 continue;
3559 /* displays are handled in phase1 */
3560 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3561 continue;
3562 /* PSP lost connection when err_event_athub occurs */
3563 if (amdgpu_ras_intr_triggered() &&
3564 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3565 adev->ip_blocks[i].status.hw = false;
3566 continue;
3567 }
3568
3569 /* skip unnecessary suspend if we do not initialize them yet */
3570 if (!amdgpu_ip_member_of_hwini(
3571 adev, adev->ip_blocks[i].version->type))
3572 continue;
3573
3574 /* skip suspend of gfx/mes and psp for S0ix
3575 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3576 * like at runtime. PSP is also part of the always on hardware
3577 * so no need to suspend it.
3578 */
3579 if (adev->in_s0ix &&
3580 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3581 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3582 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3583 continue;
3584
3585 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3586 if (adev->in_s0ix &&
3587 (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
3588 IP_VERSION(5, 0, 0)) &&
3589 (adev->ip_blocks[i].version->type ==
3590 AMD_IP_BLOCK_TYPE_SDMA))
3591 continue;
3592
3593 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3594 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3595 * from this location and RLC Autoload automatically also gets loaded
3596 * from here based on PMFW -> PSP message during re-init sequence.
3597 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3598 * the TMR and reload FWs again for IMU enabled APU ASICs.
3599 */
3600 if (amdgpu_in_reset(adev) &&
3601 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3602 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3603 continue;
3604
3605 /* XXX handle errors */
3606 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
3607 adev->ip_blocks[i].status.hw = false;
3608
3609 /* handle putting the SMC in the appropriate state */
3610 if (!amdgpu_sriov_vf(adev)) {
3611 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3612 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3613 if (r) {
3614 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3615 adev->mp1_state, r);
3616 return r;
3617 }
3618 }
3619 }
3620 }
3621
3622 return 0;
3623}
3624
3625/**
3626 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3627 *
3628 * @adev: amdgpu_device pointer
3629 *
3630 * Main suspend function for hardware IPs. The list of all the hardware
3631 * IPs that make up the asic is walked, clockgating is disabled and the
3632 * suspend callbacks are run. suspend puts the hardware and software state
3633 * in each IP into a state suitable for suspend.
3634 * Returns 0 on success, negative error code on failure.
3635 */
3636int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3637{
3638 int r;
3639
3640 if (amdgpu_sriov_vf(adev)) {
3641 amdgpu_virt_fini_data_exchange(adev);
3642 amdgpu_virt_request_full_gpu(adev, false);
3643 }
3644
3645 amdgpu_ttm_set_buffer_funcs_status(adev, false);
3646
3647 r = amdgpu_device_ip_suspend_phase1(adev);
3648 if (r)
3649 return r;
3650 r = amdgpu_device_ip_suspend_phase2(adev);
3651
3652 if (amdgpu_sriov_vf(adev))
3653 amdgpu_virt_release_full_gpu(adev, false);
3654
3655 return r;
3656}
3657
3658static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3659{
3660 int i, r;
3661
3662 static enum amd_ip_block_type ip_order[] = {
3663 AMD_IP_BLOCK_TYPE_COMMON,
3664 AMD_IP_BLOCK_TYPE_GMC,
3665 AMD_IP_BLOCK_TYPE_PSP,
3666 AMD_IP_BLOCK_TYPE_IH,
3667 };
3668
3669 for (i = 0; i < adev->num_ip_blocks; i++) {
3670 int j;
3671 struct amdgpu_ip_block *block;
3672
3673 block = &adev->ip_blocks[i];
3674 block->status.hw = false;
3675
3676 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3677
3678 if (block->version->type != ip_order[j] ||
3679 !block->status.valid)
3680 continue;
3681
3682 r = block->version->funcs->hw_init(&adev->ip_blocks[i]);
3683 if (r) {
3684 dev_err(adev->dev, "RE-INIT-early: %s failed\n",
3685 block->version->funcs->name);
3686 return r;
3687 }
3688 block->status.hw = true;
3689 }
3690 }
3691
3692 return 0;
3693}
3694
3695static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3696{
3697 struct amdgpu_ip_block *block;
3698 int i, r = 0;
3699
3700 static enum amd_ip_block_type ip_order[] = {
3701 AMD_IP_BLOCK_TYPE_SMC,
3702 AMD_IP_BLOCK_TYPE_DCE,
3703 AMD_IP_BLOCK_TYPE_GFX,
3704 AMD_IP_BLOCK_TYPE_SDMA,
3705 AMD_IP_BLOCK_TYPE_MES,
3706 AMD_IP_BLOCK_TYPE_UVD,
3707 AMD_IP_BLOCK_TYPE_VCE,
3708 AMD_IP_BLOCK_TYPE_VCN,
3709 AMD_IP_BLOCK_TYPE_JPEG
3710 };
3711
3712 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3713 block = amdgpu_device_ip_get_ip_block(adev, ip_order[i]);
3714
3715 if (!block)
3716 continue;
3717
3718 if (block->status.valid && !block->status.hw) {
3719 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) {
3720 r = amdgpu_ip_block_resume(block);
3721 } else {
3722 r = block->version->funcs->hw_init(block);
3723 }
3724
3725 if (r) {
3726 dev_err(adev->dev, "RE-INIT-late: %s failed\n",
3727 block->version->funcs->name);
3728 break;
3729 }
3730 block->status.hw = true;
3731 }
3732 }
3733
3734 return r;
3735}
3736
3737/**
3738 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3739 *
3740 * @adev: amdgpu_device pointer
3741 *
3742 * First resume function for hardware IPs. The list of all the hardware
3743 * IPs that make up the asic is walked and the resume callbacks are run for
3744 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3745 * after a suspend and updates the software state as necessary. This
3746 * function is also used for restoring the GPU after a GPU reset.
3747 * Returns 0 on success, negative error code on failure.
3748 */
3749static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3750{
3751 int i, r;
3752
3753 for (i = 0; i < adev->num_ip_blocks; i++) {
3754 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3755 continue;
3756 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3757 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3758 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3759 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3760
3761 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3762 if (r)
3763 return r;
3764 }
3765 }
3766
3767 return 0;
3768}
3769
3770/**
3771 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3772 *
3773 * @adev: amdgpu_device pointer
3774 *
3775 * Second resume function for hardware IPs. The list of all the hardware
3776 * IPs that make up the asic is walked and the resume callbacks are run for
3777 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3778 * functional state after a suspend and updates the software state as
3779 * necessary. This function is also used for restoring the GPU after a GPU
3780 * reset.
3781 * Returns 0 on success, negative error code on failure.
3782 */
3783static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3784{
3785 int i, r;
3786
3787 for (i = 0; i < adev->num_ip_blocks; i++) {
3788 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3789 continue;
3790 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3791 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3792 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3793 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE ||
3794 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3795 continue;
3796 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3797 if (r)
3798 return r;
3799 }
3800
3801 return 0;
3802}
3803
3804/**
3805 * amdgpu_device_ip_resume_phase3 - run resume for hardware IPs
3806 *
3807 * @adev: amdgpu_device pointer
3808 *
3809 * Third resume function for hardware IPs. The list of all the hardware
3810 * IPs that make up the asic is walked and the resume callbacks are run for
3811 * all DCE. resume puts the hardware into a functional state after a suspend
3812 * and updates the software state as necessary. This function is also used
3813 * for restoring the GPU after a GPU reset.
3814 *
3815 * Returns 0 on success, negative error code on failure.
3816 */
3817static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)
3818{
3819 int i, r;
3820
3821 for (i = 0; i < adev->num_ip_blocks; i++) {
3822 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3823 continue;
3824 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
3825 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
3826 if (r)
3827 return r;
3828 }
3829 }
3830
3831 return 0;
3832}
3833
3834/**
3835 * amdgpu_device_ip_resume - run resume for hardware IPs
3836 *
3837 * @adev: amdgpu_device pointer
3838 *
3839 * Main resume function for hardware IPs. The hardware IPs
3840 * are split into two resume functions because they are
3841 * also used in recovering from a GPU reset and some additional
3842 * steps need to be take between them. In this case (S3/S4) they are
3843 * run sequentially.
3844 * Returns 0 on success, negative error code on failure.
3845 */
3846static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3847{
3848 int r;
3849
3850 r = amdgpu_device_ip_resume_phase1(adev);
3851 if (r)
3852 return r;
3853
3854 r = amdgpu_device_fw_loading(adev);
3855 if (r)
3856 return r;
3857
3858 r = amdgpu_device_ip_resume_phase2(adev);
3859
3860 if (adev->mman.buffer_funcs_ring->sched.ready)
3861 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3862
3863 if (r)
3864 return r;
3865
3866 amdgpu_fence_driver_hw_init(adev);
3867
3868 r = amdgpu_device_ip_resume_phase3(adev);
3869
3870 return r;
3871}
3872
3873/**
3874 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3875 *
3876 * @adev: amdgpu_device pointer
3877 *
3878 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3879 */
3880static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3881{
3882 if (amdgpu_sriov_vf(adev)) {
3883 if (adev->is_atom_fw) {
3884 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3885 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3886 } else {
3887 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3888 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3889 }
3890
3891 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3892 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3893 }
3894}
3895
3896/**
3897 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3898 *
3899 * @asic_type: AMD asic type
3900 *
3901 * Check if there is DC (new modesetting infrastructre) support for an asic.
3902 * returns true if DC has support, false if not.
3903 */
3904bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3905{
3906 switch (asic_type) {
3907#ifdef CONFIG_DRM_AMDGPU_SI
3908 case CHIP_HAINAN:
3909#endif
3910 case CHIP_TOPAZ:
3911 /* chips with no display hardware */
3912 return false;
3913#if defined(CONFIG_DRM_AMD_DC)
3914 case CHIP_TAHITI:
3915 case CHIP_PITCAIRN:
3916 case CHIP_VERDE:
3917 case CHIP_OLAND:
3918 /*
3919 * We have systems in the wild with these ASICs that require
3920 * LVDS and VGA support which is not supported with DC.
3921 *
3922 * Fallback to the non-DC driver here by default so as not to
3923 * cause regressions.
3924 */
3925#if defined(CONFIG_DRM_AMD_DC_SI)
3926 return amdgpu_dc > 0;
3927#else
3928 return false;
3929#endif
3930 case CHIP_BONAIRE:
3931 case CHIP_KAVERI:
3932 case CHIP_KABINI:
3933 case CHIP_MULLINS:
3934 /*
3935 * We have systems in the wild with these ASICs that require
3936 * VGA support which is not supported with DC.
3937 *
3938 * Fallback to the non-DC driver here by default so as not to
3939 * cause regressions.
3940 */
3941 return amdgpu_dc > 0;
3942 default:
3943 return amdgpu_dc != 0;
3944#else
3945 default:
3946 if (amdgpu_dc > 0)
3947 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3948 return false;
3949#endif
3950 }
3951}
3952
3953/**
3954 * amdgpu_device_has_dc_support - check if dc is supported
3955 *
3956 * @adev: amdgpu_device pointer
3957 *
3958 * Returns true for supported, false for not supported
3959 */
3960bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3961{
3962 if (adev->enable_virtual_display ||
3963 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3964 return false;
3965
3966 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3967}
3968
3969static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3970{
3971 struct amdgpu_device *adev =
3972 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3973 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3974
3975 /* It's a bug to not have a hive within this function */
3976 if (WARN_ON(!hive))
3977 return;
3978
3979 /*
3980 * Use task barrier to synchronize all xgmi reset works across the
3981 * hive. task_barrier_enter and task_barrier_exit will block
3982 * until all the threads running the xgmi reset works reach
3983 * those points. task_barrier_full will do both blocks.
3984 */
3985 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3986
3987 task_barrier_enter(&hive->tb);
3988 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3989
3990 if (adev->asic_reset_res)
3991 goto fail;
3992
3993 task_barrier_exit(&hive->tb);
3994 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3995
3996 if (adev->asic_reset_res)
3997 goto fail;
3998
3999 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
4000 } else {
4001
4002 task_barrier_full(&hive->tb);
4003 adev->asic_reset_res = amdgpu_asic_reset(adev);
4004 }
4005
4006fail:
4007 if (adev->asic_reset_res)
4008 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
4009 adev->asic_reset_res, adev_to_drm(adev)->unique);
4010 amdgpu_put_xgmi_hive(hive);
4011}
4012
4013static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
4014{
4015 char *input = amdgpu_lockup_timeout;
4016 char *timeout_setting = NULL;
4017 int index = 0;
4018 long timeout;
4019 int ret = 0;
4020
4021 /*
4022 * By default timeout for non compute jobs is 10000
4023 * and 60000 for compute jobs.
4024 * In SR-IOV or passthrough mode, timeout for compute
4025 * jobs are 60000 by default.
4026 */
4027 adev->gfx_timeout = msecs_to_jiffies(10000);
4028 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
4029 if (amdgpu_sriov_vf(adev))
4030 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
4031 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
4032 else
4033 adev->compute_timeout = msecs_to_jiffies(60000);
4034
4035 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
4036 while ((timeout_setting = strsep(&input, ",")) &&
4037 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
4038 ret = kstrtol(timeout_setting, 0, &timeout);
4039 if (ret)
4040 return ret;
4041
4042 if (timeout == 0) {
4043 index++;
4044 continue;
4045 } else if (timeout < 0) {
4046 timeout = MAX_SCHEDULE_TIMEOUT;
4047 dev_warn(adev->dev, "lockup timeout disabled");
4048 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
4049 } else {
4050 timeout = msecs_to_jiffies(timeout);
4051 }
4052
4053 switch (index++) {
4054 case 0:
4055 adev->gfx_timeout = timeout;
4056 break;
4057 case 1:
4058 adev->compute_timeout = timeout;
4059 break;
4060 case 2:
4061 adev->sdma_timeout = timeout;
4062 break;
4063 case 3:
4064 adev->video_timeout = timeout;
4065 break;
4066 default:
4067 break;
4068 }
4069 }
4070 /*
4071 * There is only one value specified and
4072 * it should apply to all non-compute jobs.
4073 */
4074 if (index == 1) {
4075 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
4076 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
4077 adev->compute_timeout = adev->gfx_timeout;
4078 }
4079 }
4080
4081 return ret;
4082}
4083
4084/**
4085 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
4086 *
4087 * @adev: amdgpu_device pointer
4088 *
4089 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
4090 */
4091static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
4092{
4093 struct iommu_domain *domain;
4094
4095 domain = iommu_get_domain_for_dev(adev->dev);
4096 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
4097 adev->ram_is_direct_mapped = true;
4098}
4099
4100#if defined(CONFIG_HSA_AMD_P2P)
4101/**
4102 * amdgpu_device_check_iommu_remap - Check if DMA remapping is enabled.
4103 *
4104 * @adev: amdgpu_device pointer
4105 *
4106 * return if IOMMU remapping bar address
4107 */
4108static bool amdgpu_device_check_iommu_remap(struct amdgpu_device *adev)
4109{
4110 struct iommu_domain *domain;
4111
4112 domain = iommu_get_domain_for_dev(adev->dev);
4113 if (domain && (domain->type == IOMMU_DOMAIN_DMA ||
4114 domain->type == IOMMU_DOMAIN_DMA_FQ))
4115 return true;
4116
4117 return false;
4118}
4119#endif
4120
4121static const struct attribute *amdgpu_dev_attributes[] = {
4122 &dev_attr_pcie_replay_count.attr,
4123 NULL
4124};
4125
4126static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
4127{
4128 if (amdgpu_mcbp == 1)
4129 adev->gfx.mcbp = true;
4130 else if (amdgpu_mcbp == 0)
4131 adev->gfx.mcbp = false;
4132
4133 if (amdgpu_sriov_vf(adev))
4134 adev->gfx.mcbp = true;
4135
4136 if (adev->gfx.mcbp)
4137 DRM_INFO("MCBP is enabled\n");
4138}
4139
4140/**
4141 * amdgpu_device_init - initialize the driver
4142 *
4143 * @adev: amdgpu_device pointer
4144 * @flags: driver flags
4145 *
4146 * Initializes the driver info and hw (all asics).
4147 * Returns 0 for success or an error on failure.
4148 * Called at driver startup.
4149 */
4150int amdgpu_device_init(struct amdgpu_device *adev,
4151 uint32_t flags)
4152{
4153 struct drm_device *ddev = adev_to_drm(adev);
4154 struct pci_dev *pdev = adev->pdev;
4155 int r, i;
4156 bool px = false;
4157 u32 max_MBps;
4158 int tmp;
4159
4160 adev->shutdown = false;
4161 adev->flags = flags;
4162
4163 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
4164 adev->asic_type = amdgpu_force_asic_type;
4165 else
4166 adev->asic_type = flags & AMD_ASIC_MASK;
4167
4168 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
4169 if (amdgpu_emu_mode == 1)
4170 adev->usec_timeout *= 10;
4171 adev->gmc.gart_size = 512 * 1024 * 1024;
4172 adev->accel_working = false;
4173 adev->num_rings = 0;
4174 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
4175 adev->mman.buffer_funcs = NULL;
4176 adev->mman.buffer_funcs_ring = NULL;
4177 adev->vm_manager.vm_pte_funcs = NULL;
4178 adev->vm_manager.vm_pte_num_scheds = 0;
4179 adev->gmc.gmc_funcs = NULL;
4180 adev->harvest_ip_mask = 0x0;
4181 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
4182 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4183
4184 adev->smc_rreg = &amdgpu_invalid_rreg;
4185 adev->smc_wreg = &amdgpu_invalid_wreg;
4186 adev->pcie_rreg = &amdgpu_invalid_rreg;
4187 adev->pcie_wreg = &amdgpu_invalid_wreg;
4188 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
4189 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
4190 adev->pciep_rreg = &amdgpu_invalid_rreg;
4191 adev->pciep_wreg = &amdgpu_invalid_wreg;
4192 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
4193 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
4194 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
4195 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
4196 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
4197 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
4198 adev->didt_rreg = &amdgpu_invalid_rreg;
4199 adev->didt_wreg = &amdgpu_invalid_wreg;
4200 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
4201 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
4202 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
4203 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
4204
4205 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
4206 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
4207 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
4208
4209 /* mutex initialization are all done here so we
4210 * can recall function without having locking issues
4211 */
4212 mutex_init(&adev->firmware.mutex);
4213 mutex_init(&adev->pm.mutex);
4214 mutex_init(&adev->gfx.gpu_clock_mutex);
4215 mutex_init(&adev->srbm_mutex);
4216 mutex_init(&adev->gfx.pipe_reserve_mutex);
4217 mutex_init(&adev->gfx.gfx_off_mutex);
4218 mutex_init(&adev->gfx.partition_mutex);
4219 mutex_init(&adev->grbm_idx_mutex);
4220 mutex_init(&adev->mn_lock);
4221 mutex_init(&adev->virt.vf_errors.lock);
4222 mutex_init(&adev->virt.rlcg_reg_lock);
4223 hash_init(adev->mn_hash);
4224 mutex_init(&adev->psp.mutex);
4225 mutex_init(&adev->notifier_lock);
4226 mutex_init(&adev->pm.stable_pstate_ctx_lock);
4227 mutex_init(&adev->benchmark_mutex);
4228 mutex_init(&adev->gfx.reset_sem_mutex);
4229 /* Initialize the mutex for cleaner shader isolation between GFX and compute processes */
4230 mutex_init(&adev->enforce_isolation_mutex);
4231 mutex_init(&adev->gfx.kfd_sch_mutex);
4232
4233 amdgpu_device_init_apu_flags(adev);
4234
4235 r = amdgpu_device_check_arguments(adev);
4236 if (r)
4237 return r;
4238
4239 spin_lock_init(&adev->mmio_idx_lock);
4240 spin_lock_init(&adev->smc_idx_lock);
4241 spin_lock_init(&adev->pcie_idx_lock);
4242 spin_lock_init(&adev->uvd_ctx_idx_lock);
4243 spin_lock_init(&adev->didt_idx_lock);
4244 spin_lock_init(&adev->gc_cac_idx_lock);
4245 spin_lock_init(&adev->se_cac_idx_lock);
4246 spin_lock_init(&adev->audio_endpt_idx_lock);
4247 spin_lock_init(&adev->mm_stats.lock);
4248 spin_lock_init(&adev->wb.lock);
4249
4250 INIT_LIST_HEAD(&adev->reset_list);
4251
4252 INIT_LIST_HEAD(&adev->ras_list);
4253
4254 INIT_LIST_HEAD(&adev->pm.od_kobj_list);
4255
4256 INIT_DELAYED_WORK(&adev->delayed_init_work,
4257 amdgpu_device_delayed_init_work_handler);
4258 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
4259 amdgpu_device_delay_enable_gfx_off);
4260 /*
4261 * Initialize the enforce_isolation work structures for each XCP
4262 * partition. This work handler is responsible for enforcing shader
4263 * isolation on AMD GPUs. It counts the number of emitted fences for
4264 * each GFX and compute ring. If there are any fences, it schedules
4265 * the `enforce_isolation_work` to be run after a delay. If there are
4266 * no fences, it signals the Kernel Fusion Driver (KFD) to resume the
4267 * runqueue.
4268 */
4269 for (i = 0; i < MAX_XCP; i++) {
4270 INIT_DELAYED_WORK(&adev->gfx.enforce_isolation[i].work,
4271 amdgpu_gfx_enforce_isolation_handler);
4272 adev->gfx.enforce_isolation[i].adev = adev;
4273 adev->gfx.enforce_isolation[i].xcp_id = i;
4274 }
4275
4276 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
4277
4278 adev->gfx.gfx_off_req_count = 1;
4279 adev->gfx.gfx_off_residency = 0;
4280 adev->gfx.gfx_off_entrycount = 0;
4281 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
4282
4283 atomic_set(&adev->throttling_logging_enabled, 1);
4284 /*
4285 * If throttling continues, logging will be performed every minute
4286 * to avoid log flooding. "-1" is subtracted since the thermal
4287 * throttling interrupt comes every second. Thus, the total logging
4288 * interval is 59 seconds(retelimited printk interval) + 1(waiting
4289 * for throttling interrupt) = 60 seconds.
4290 */
4291 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
4292 ratelimit_state_init(&adev->virt.ras_telemetry_rs, 5 * HZ, 1);
4293
4294 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
4295 ratelimit_set_flags(&adev->virt.ras_telemetry_rs, RATELIMIT_MSG_ON_RELEASE);
4296
4297 /* Registers mapping */
4298 /* TODO: block userspace mapping of io register */
4299 if (adev->asic_type >= CHIP_BONAIRE) {
4300 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
4301 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
4302 } else {
4303 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
4304 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
4305 }
4306
4307 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
4308 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
4309
4310 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
4311 if (!adev->rmmio)
4312 return -ENOMEM;
4313
4314 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
4315 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
4316
4317 /*
4318 * Reset domain needs to be present early, before XGMI hive discovered
4319 * (if any) and intitialized to use reset sem and in_gpu reset flag
4320 * early on during init and before calling to RREG32.
4321 */
4322 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
4323 if (!adev->reset_domain)
4324 return -ENOMEM;
4325
4326 /* detect hw virtualization here */
4327 amdgpu_detect_virtualization(adev);
4328
4329 amdgpu_device_get_pcie_info(adev);
4330
4331 r = amdgpu_device_get_job_timeout_settings(adev);
4332 if (r) {
4333 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
4334 return r;
4335 }
4336
4337 amdgpu_device_set_mcbp(adev);
4338
4339 /*
4340 * By default, use default mode where all blocks are expected to be
4341 * initialized. At present a 'swinit' of blocks is required to be
4342 * completed before the need for a different level is detected.
4343 */
4344 amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_DEFAULT);
4345 /* early init functions */
4346 r = amdgpu_device_ip_early_init(adev);
4347 if (r)
4348 return r;
4349
4350 /* Get rid of things like offb */
4351 r = aperture_remove_conflicting_pci_devices(adev->pdev, amdgpu_kms_driver.name);
4352 if (r)
4353 return r;
4354
4355 /* Enable TMZ based on IP_VERSION */
4356 amdgpu_gmc_tmz_set(adev);
4357
4358 if (amdgpu_sriov_vf(adev) &&
4359 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
4360 /* VF MMIO access (except mailbox range) from CPU
4361 * will be blocked during sriov runtime
4362 */
4363 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
4364
4365 amdgpu_gmc_noretry_set(adev);
4366 /* Need to get xgmi info early to decide the reset behavior*/
4367 if (adev->gmc.xgmi.supported) {
4368 r = adev->gfxhub.funcs->get_xgmi_info(adev);
4369 if (r)
4370 return r;
4371 }
4372
4373 /* enable PCIE atomic ops */
4374 if (amdgpu_sriov_vf(adev)) {
4375 if (adev->virt.fw_reserve.p_pf2vf)
4376 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
4377 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
4378 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4379 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
4380 * internal path natively support atomics, set have_atomics_support to true.
4381 */
4382 } else if ((adev->flags & AMD_IS_APU) &&
4383 (amdgpu_ip_version(adev, GC_HWIP, 0) >
4384 IP_VERSION(9, 0, 0))) {
4385 adev->have_atomics_support = true;
4386 } else {
4387 adev->have_atomics_support =
4388 !pci_enable_atomic_ops_to_root(adev->pdev,
4389 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
4390 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4391 }
4392
4393 if (!adev->have_atomics_support)
4394 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
4395
4396 /* doorbell bar mapping and doorbell index init*/
4397 amdgpu_doorbell_init(adev);
4398
4399 if (amdgpu_emu_mode == 1) {
4400 /* post the asic on emulation mode */
4401 emu_soc_asic_init(adev);
4402 goto fence_driver_init;
4403 }
4404
4405 amdgpu_reset_init(adev);
4406
4407 /* detect if we are with an SRIOV vbios */
4408 if (adev->bios)
4409 amdgpu_device_detect_sriov_bios(adev);
4410
4411 /* check if we need to reset the asic
4412 * E.g., driver was not cleanly unloaded previously, etc.
4413 */
4414 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
4415 if (adev->gmc.xgmi.num_physical_nodes) {
4416 dev_info(adev->dev, "Pending hive reset.\n");
4417 amdgpu_set_init_level(adev,
4418 AMDGPU_INIT_LEVEL_MINIMAL_XGMI);
4419 } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
4420 !amdgpu_device_has_display_hardware(adev)) {
4421 r = psp_gpu_reset(adev);
4422 } else {
4423 tmp = amdgpu_reset_method;
4424 /* It should do a default reset when loading or reloading the driver,
4425 * regardless of the module parameter reset_method.
4426 */
4427 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4428 r = amdgpu_asic_reset(adev);
4429 amdgpu_reset_method = tmp;
4430 }
4431
4432 if (r) {
4433 dev_err(adev->dev, "asic reset on init failed\n");
4434 goto failed;
4435 }
4436 }
4437
4438 /* Post card if necessary */
4439 if (amdgpu_device_need_post(adev)) {
4440 if (!adev->bios) {
4441 dev_err(adev->dev, "no vBIOS found\n");
4442 r = -EINVAL;
4443 goto failed;
4444 }
4445 DRM_INFO("GPU posting now...\n");
4446 r = amdgpu_device_asic_init(adev);
4447 if (r) {
4448 dev_err(adev->dev, "gpu post error!\n");
4449 goto failed;
4450 }
4451 }
4452
4453 if (adev->bios) {
4454 if (adev->is_atom_fw) {
4455 /* Initialize clocks */
4456 r = amdgpu_atomfirmware_get_clock_info(adev);
4457 if (r) {
4458 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
4459 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4460 goto failed;
4461 }
4462 } else {
4463 /* Initialize clocks */
4464 r = amdgpu_atombios_get_clock_info(adev);
4465 if (r) {
4466 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
4467 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4468 goto failed;
4469 }
4470 /* init i2c buses */
4471 if (!amdgpu_device_has_dc_support(adev))
4472 amdgpu_atombios_i2c_init(adev);
4473 }
4474 }
4475
4476fence_driver_init:
4477 /* Fence driver */
4478 r = amdgpu_fence_driver_sw_init(adev);
4479 if (r) {
4480 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
4481 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
4482 goto failed;
4483 }
4484
4485 /* init the mode config */
4486 drm_mode_config_init(adev_to_drm(adev));
4487
4488 r = amdgpu_device_ip_init(adev);
4489 if (r) {
4490 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
4491 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
4492 goto release_ras_con;
4493 }
4494
4495 amdgpu_fence_driver_hw_init(adev);
4496
4497 dev_info(adev->dev,
4498 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
4499 adev->gfx.config.max_shader_engines,
4500 adev->gfx.config.max_sh_per_se,
4501 adev->gfx.config.max_cu_per_sh,
4502 adev->gfx.cu_info.number);
4503
4504 adev->accel_working = true;
4505
4506 amdgpu_vm_check_compute_bug(adev);
4507
4508 /* Initialize the buffer migration limit. */
4509 if (amdgpu_moverate >= 0)
4510 max_MBps = amdgpu_moverate;
4511 else
4512 max_MBps = 8; /* Allow 8 MB/s. */
4513 /* Get a log2 for easy divisions. */
4514 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
4515
4516 /*
4517 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
4518 * Otherwise the mgpu fan boost feature will be skipped due to the
4519 * gpu instance is counted less.
4520 */
4521 amdgpu_register_gpu_instance(adev);
4522
4523 /* enable clockgating, etc. after ib tests, etc. since some blocks require
4524 * explicit gating rather than handling it automatically.
4525 */
4526 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
4527 r = amdgpu_device_ip_late_init(adev);
4528 if (r) {
4529 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
4530 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
4531 goto release_ras_con;
4532 }
4533 /* must succeed. */
4534 amdgpu_ras_resume(adev);
4535 queue_delayed_work(system_wq, &adev->delayed_init_work,
4536 msecs_to_jiffies(AMDGPU_RESUME_MS));
4537 }
4538
4539 if (amdgpu_sriov_vf(adev)) {
4540 amdgpu_virt_release_full_gpu(adev, true);
4541 flush_delayed_work(&adev->delayed_init_work);
4542 }
4543
4544 /*
4545 * Place those sysfs registering after `late_init`. As some of those
4546 * operations performed in `late_init` might affect the sysfs
4547 * interfaces creating.
4548 */
4549 r = amdgpu_atombios_sysfs_init(adev);
4550 if (r)
4551 drm_err(&adev->ddev,
4552 "registering atombios sysfs failed (%d).\n", r);
4553
4554 r = amdgpu_pm_sysfs_init(adev);
4555 if (r)
4556 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
4557
4558 r = amdgpu_ucode_sysfs_init(adev);
4559 if (r) {
4560 adev->ucode_sysfs_en = false;
4561 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
4562 } else
4563 adev->ucode_sysfs_en = true;
4564
4565 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
4566 if (r)
4567 dev_err(adev->dev, "Could not create amdgpu device attr\n");
4568
4569 r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group);
4570 if (r)
4571 dev_err(adev->dev,
4572 "Could not create amdgpu board attributes\n");
4573
4574 amdgpu_fru_sysfs_init(adev);
4575 amdgpu_reg_state_sysfs_init(adev);
4576 amdgpu_xcp_cfg_sysfs_init(adev);
4577
4578 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4579 r = amdgpu_pmu_init(adev);
4580 if (r)
4581 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
4582
4583 /* Have stored pci confspace at hand for restore in sudden PCI error */
4584 if (amdgpu_device_cache_pci_state(adev->pdev))
4585 pci_restore_state(pdev);
4586
4587 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
4588 /* this will fail for cards that aren't VGA class devices, just
4589 * ignore it
4590 */
4591 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4592 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
4593
4594 px = amdgpu_device_supports_px(ddev);
4595
4596 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4597 apple_gmux_detect(NULL, NULL)))
4598 vga_switcheroo_register_client(adev->pdev,
4599 &amdgpu_switcheroo_ops, px);
4600
4601 if (px)
4602 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
4603
4604 if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI)
4605 amdgpu_xgmi_reset_on_init(adev);
4606
4607 amdgpu_device_check_iommu_direct_map(adev);
4608
4609 return 0;
4610
4611release_ras_con:
4612 if (amdgpu_sriov_vf(adev))
4613 amdgpu_virt_release_full_gpu(adev, true);
4614
4615 /* failed in exclusive mode due to timeout */
4616 if (amdgpu_sriov_vf(adev) &&
4617 !amdgpu_sriov_runtime(adev) &&
4618 amdgpu_virt_mmio_blocked(adev) &&
4619 !amdgpu_virt_wait_reset(adev)) {
4620 dev_err(adev->dev, "VF exclusive mode timeout\n");
4621 /* Don't send request since VF is inactive. */
4622 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4623 adev->virt.ops = NULL;
4624 r = -EAGAIN;
4625 }
4626 amdgpu_release_ras_context(adev);
4627
4628failed:
4629 amdgpu_vf_error_trans_all(adev);
4630
4631 return r;
4632}
4633
4634static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4635{
4636
4637 /* Clear all CPU mappings pointing to this device */
4638 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4639
4640 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4641 amdgpu_doorbell_fini(adev);
4642
4643 iounmap(adev->rmmio);
4644 adev->rmmio = NULL;
4645 if (adev->mman.aper_base_kaddr)
4646 iounmap(adev->mman.aper_base_kaddr);
4647 adev->mman.aper_base_kaddr = NULL;
4648
4649 /* Memory manager related */
4650 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4651 arch_phys_wc_del(adev->gmc.vram_mtrr);
4652 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4653 }
4654}
4655
4656/**
4657 * amdgpu_device_fini_hw - tear down the driver
4658 *
4659 * @adev: amdgpu_device pointer
4660 *
4661 * Tear down the driver info (all asics).
4662 * Called at driver shutdown.
4663 */
4664void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4665{
4666 dev_info(adev->dev, "amdgpu: finishing device.\n");
4667 flush_delayed_work(&adev->delayed_init_work);
4668
4669 if (adev->mman.initialized)
4670 drain_workqueue(adev->mman.bdev.wq);
4671 adev->shutdown = true;
4672
4673 /* make sure IB test finished before entering exclusive mode
4674 * to avoid preemption on IB test
4675 */
4676 if (amdgpu_sriov_vf(adev)) {
4677 amdgpu_virt_request_full_gpu(adev, false);
4678 amdgpu_virt_fini_data_exchange(adev);
4679 }
4680
4681 /* disable all interrupts */
4682 amdgpu_irq_disable_all(adev);
4683 if (adev->mode_info.mode_config_initialized) {
4684 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4685 drm_helper_force_disable_all(adev_to_drm(adev));
4686 else
4687 drm_atomic_helper_shutdown(adev_to_drm(adev));
4688 }
4689 amdgpu_fence_driver_hw_fini(adev);
4690
4691 if (adev->pm.sysfs_initialized)
4692 amdgpu_pm_sysfs_fini(adev);
4693 if (adev->ucode_sysfs_en)
4694 amdgpu_ucode_sysfs_fini(adev);
4695 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4696 amdgpu_fru_sysfs_fini(adev);
4697
4698 amdgpu_reg_state_sysfs_fini(adev);
4699 amdgpu_xcp_cfg_sysfs_fini(adev);
4700
4701 /* disable ras feature must before hw fini */
4702 amdgpu_ras_pre_fini(adev);
4703
4704 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4705
4706 amdgpu_device_ip_fini_early(adev);
4707
4708 amdgpu_irq_fini_hw(adev);
4709
4710 if (adev->mman.initialized)
4711 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4712
4713 amdgpu_gart_dummy_page_fini(adev);
4714
4715 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4716 amdgpu_device_unmap_mmio(adev);
4717
4718}
4719
4720void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4721{
4722 int idx;
4723 bool px;
4724
4725 amdgpu_device_ip_fini(adev);
4726 amdgpu_fence_driver_sw_fini(adev);
4727 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4728 adev->accel_working = false;
4729 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4730
4731 amdgpu_reset_fini(adev);
4732
4733 /* free i2c buses */
4734 if (!amdgpu_device_has_dc_support(adev))
4735 amdgpu_i2c_fini(adev);
4736
4737 if (amdgpu_emu_mode != 1)
4738 amdgpu_atombios_fini(adev);
4739
4740 kfree(adev->bios);
4741 adev->bios = NULL;
4742
4743 kfree(adev->fru_info);
4744 adev->fru_info = NULL;
4745
4746 px = amdgpu_device_supports_px(adev_to_drm(adev));
4747
4748 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4749 apple_gmux_detect(NULL, NULL)))
4750 vga_switcheroo_unregister_client(adev->pdev);
4751
4752 if (px)
4753 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4754
4755 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4756 vga_client_unregister(adev->pdev);
4757
4758 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4759
4760 iounmap(adev->rmmio);
4761 adev->rmmio = NULL;
4762 amdgpu_doorbell_fini(adev);
4763 drm_dev_exit(idx);
4764 }
4765
4766 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4767 amdgpu_pmu_fini(adev);
4768 if (adev->mman.discovery_bin)
4769 amdgpu_discovery_fini(adev);
4770
4771 amdgpu_reset_put_reset_domain(adev->reset_domain);
4772 adev->reset_domain = NULL;
4773
4774 kfree(adev->pci_state);
4775
4776}
4777
4778/**
4779 * amdgpu_device_evict_resources - evict device resources
4780 * @adev: amdgpu device object
4781 *
4782 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4783 * of the vram memory type. Mainly used for evicting device resources
4784 * at suspend time.
4785 *
4786 */
4787static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4788{
4789 int ret;
4790
4791 /* No need to evict vram on APUs for suspend to ram or s2idle */
4792 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4793 return 0;
4794
4795 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4796 if (ret)
4797 DRM_WARN("evicting device resources failed\n");
4798 return ret;
4799}
4800
4801/*
4802 * Suspend & resume.
4803 */
4804/**
4805 * amdgpu_device_prepare - prepare for device suspend
4806 *
4807 * @dev: drm dev pointer
4808 *
4809 * Prepare to put the hw in the suspend state (all asics).
4810 * Returns 0 for success or an error on failure.
4811 * Called at driver suspend.
4812 */
4813int amdgpu_device_prepare(struct drm_device *dev)
4814{
4815 struct amdgpu_device *adev = drm_to_adev(dev);
4816 int i, r;
4817
4818 amdgpu_choose_low_power_state(adev);
4819
4820 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4821 return 0;
4822
4823 /* Evict the majority of BOs before starting suspend sequence */
4824 r = amdgpu_device_evict_resources(adev);
4825 if (r)
4826 goto unprepare;
4827
4828 flush_delayed_work(&adev->gfx.gfx_off_delay_work);
4829
4830 for (i = 0; i < adev->num_ip_blocks; i++) {
4831 if (!adev->ip_blocks[i].status.valid)
4832 continue;
4833 if (!adev->ip_blocks[i].version->funcs->prepare_suspend)
4834 continue;
4835 r = adev->ip_blocks[i].version->funcs->prepare_suspend(&adev->ip_blocks[i]);
4836 if (r)
4837 goto unprepare;
4838 }
4839
4840 return 0;
4841
4842unprepare:
4843 adev->in_s0ix = adev->in_s3 = false;
4844
4845 return r;
4846}
4847
4848/**
4849 * amdgpu_device_suspend - initiate device suspend
4850 *
4851 * @dev: drm dev pointer
4852 * @notify_clients: notify in-kernel DRM clients
4853 *
4854 * Puts the hw in the suspend state (all asics).
4855 * Returns 0 for success or an error on failure.
4856 * Called at driver suspend.
4857 */
4858int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
4859{
4860 struct amdgpu_device *adev = drm_to_adev(dev);
4861 int r = 0;
4862
4863 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4864 return 0;
4865
4866 adev->in_suspend = true;
4867
4868 if (amdgpu_sriov_vf(adev)) {
4869 amdgpu_virt_fini_data_exchange(adev);
4870 r = amdgpu_virt_request_full_gpu(adev, false);
4871 if (r)
4872 return r;
4873 }
4874
4875 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4876 DRM_WARN("smart shift update failed\n");
4877
4878 if (notify_clients)
4879 drm_client_dev_suspend(adev_to_drm(adev), false);
4880
4881 cancel_delayed_work_sync(&adev->delayed_init_work);
4882
4883 amdgpu_ras_suspend(adev);
4884
4885 amdgpu_device_ip_suspend_phase1(adev);
4886
4887 if (!adev->in_s0ix)
4888 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4889
4890 r = amdgpu_device_evict_resources(adev);
4891 if (r)
4892 return r;
4893
4894 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4895
4896 amdgpu_fence_driver_hw_fini(adev);
4897
4898 amdgpu_device_ip_suspend_phase2(adev);
4899
4900 if (amdgpu_sriov_vf(adev))
4901 amdgpu_virt_release_full_gpu(adev, false);
4902
4903 r = amdgpu_dpm_notify_rlc_state(adev, false);
4904 if (r)
4905 return r;
4906
4907 return 0;
4908}
4909
4910/**
4911 * amdgpu_device_resume - initiate device resume
4912 *
4913 * @dev: drm dev pointer
4914 * @notify_clients: notify in-kernel DRM clients
4915 *
4916 * Bring the hw back to operating state (all asics).
4917 * Returns 0 for success or an error on failure.
4918 * Called at driver resume.
4919 */
4920int amdgpu_device_resume(struct drm_device *dev, bool notify_clients)
4921{
4922 struct amdgpu_device *adev = drm_to_adev(dev);
4923 int r = 0;
4924
4925 if (amdgpu_sriov_vf(adev)) {
4926 r = amdgpu_virt_request_full_gpu(adev, true);
4927 if (r)
4928 return r;
4929 }
4930
4931 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4932 return 0;
4933
4934 if (adev->in_s0ix)
4935 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4936
4937 /* post card */
4938 if (amdgpu_device_need_post(adev)) {
4939 r = amdgpu_device_asic_init(adev);
4940 if (r)
4941 dev_err(adev->dev, "amdgpu asic init failed\n");
4942 }
4943
4944 r = amdgpu_device_ip_resume(adev);
4945
4946 if (r) {
4947 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4948 goto exit;
4949 }
4950
4951 if (!adev->in_s0ix) {
4952 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4953 if (r)
4954 goto exit;
4955 }
4956
4957 r = amdgpu_device_ip_late_init(adev);
4958 if (r)
4959 goto exit;
4960
4961 queue_delayed_work(system_wq, &adev->delayed_init_work,
4962 msecs_to_jiffies(AMDGPU_RESUME_MS));
4963exit:
4964 if (amdgpu_sriov_vf(adev)) {
4965 amdgpu_virt_init_data_exchange(adev);
4966 amdgpu_virt_release_full_gpu(adev, true);
4967 }
4968
4969 if (r)
4970 return r;
4971
4972 /* Make sure IB tests flushed */
4973 flush_delayed_work(&adev->delayed_init_work);
4974
4975 if (notify_clients)
4976 drm_client_dev_resume(adev_to_drm(adev), false);
4977
4978 amdgpu_ras_resume(adev);
4979
4980 if (adev->mode_info.num_crtc) {
4981 /*
4982 * Most of the connector probing functions try to acquire runtime pm
4983 * refs to ensure that the GPU is powered on when connector polling is
4984 * performed. Since we're calling this from a runtime PM callback,
4985 * trying to acquire rpm refs will cause us to deadlock.
4986 *
4987 * Since we're guaranteed to be holding the rpm lock, it's safe to
4988 * temporarily disable the rpm helpers so this doesn't deadlock us.
4989 */
4990#ifdef CONFIG_PM
4991 dev->dev->power.disable_depth++;
4992#endif
4993 if (!adev->dc_enabled)
4994 drm_helper_hpd_irq_event(dev);
4995 else
4996 drm_kms_helper_hotplug_event(dev);
4997#ifdef CONFIG_PM
4998 dev->dev->power.disable_depth--;
4999#endif
5000 }
5001 adev->in_suspend = false;
5002
5003 if (adev->enable_mes)
5004 amdgpu_mes_self_test(adev);
5005
5006 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
5007 DRM_WARN("smart shift update failed\n");
5008
5009 return 0;
5010}
5011
5012/**
5013 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
5014 *
5015 * @adev: amdgpu_device pointer
5016 *
5017 * The list of all the hardware IPs that make up the asic is walked and
5018 * the check_soft_reset callbacks are run. check_soft_reset determines
5019 * if the asic is still hung or not.
5020 * Returns true if any of the IPs are still in a hung state, false if not.
5021 */
5022static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
5023{
5024 int i;
5025 bool asic_hang = false;
5026
5027 if (amdgpu_sriov_vf(adev))
5028 return true;
5029
5030 if (amdgpu_asic_need_full_reset(adev))
5031 return true;
5032
5033 for (i = 0; i < adev->num_ip_blocks; i++) {
5034 if (!adev->ip_blocks[i].status.valid)
5035 continue;
5036 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
5037 adev->ip_blocks[i].status.hang =
5038 adev->ip_blocks[i].version->funcs->check_soft_reset(
5039 &adev->ip_blocks[i]);
5040 if (adev->ip_blocks[i].status.hang) {
5041 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
5042 asic_hang = true;
5043 }
5044 }
5045 return asic_hang;
5046}
5047
5048/**
5049 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
5050 *
5051 * @adev: amdgpu_device pointer
5052 *
5053 * The list of all the hardware IPs that make up the asic is walked and the
5054 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
5055 * handles any IP specific hardware or software state changes that are
5056 * necessary for a soft reset to succeed.
5057 * Returns 0 on success, negative error code on failure.
5058 */
5059static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
5060{
5061 int i, r = 0;
5062
5063 for (i = 0; i < adev->num_ip_blocks; i++) {
5064 if (!adev->ip_blocks[i].status.valid)
5065 continue;
5066 if (adev->ip_blocks[i].status.hang &&
5067 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
5068 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(&adev->ip_blocks[i]);
5069 if (r)
5070 return r;
5071 }
5072 }
5073
5074 return 0;
5075}
5076
5077/**
5078 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
5079 *
5080 * @adev: amdgpu_device pointer
5081 *
5082 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
5083 * reset is necessary to recover.
5084 * Returns true if a full asic reset is required, false if not.
5085 */
5086static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
5087{
5088 int i;
5089
5090 if (amdgpu_asic_need_full_reset(adev))
5091 return true;
5092
5093 for (i = 0; i < adev->num_ip_blocks; i++) {
5094 if (!adev->ip_blocks[i].status.valid)
5095 continue;
5096 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
5097 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
5098 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
5099 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
5100 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
5101 if (adev->ip_blocks[i].status.hang) {
5102 dev_info(adev->dev, "Some block need full reset!\n");
5103 return true;
5104 }
5105 }
5106 }
5107 return false;
5108}
5109
5110/**
5111 * amdgpu_device_ip_soft_reset - do a soft reset
5112 *
5113 * @adev: amdgpu_device pointer
5114 *
5115 * The list of all the hardware IPs that make up the asic is walked and the
5116 * soft_reset callbacks are run if the block is hung. soft_reset handles any
5117 * IP specific hardware or software state changes that are necessary to soft
5118 * reset the IP.
5119 * Returns 0 on success, negative error code on failure.
5120 */
5121static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
5122{
5123 int i, r = 0;
5124
5125 for (i = 0; i < adev->num_ip_blocks; i++) {
5126 if (!adev->ip_blocks[i].status.valid)
5127 continue;
5128 if (adev->ip_blocks[i].status.hang &&
5129 adev->ip_blocks[i].version->funcs->soft_reset) {
5130 r = adev->ip_blocks[i].version->funcs->soft_reset(&adev->ip_blocks[i]);
5131 if (r)
5132 return r;
5133 }
5134 }
5135
5136 return 0;
5137}
5138
5139/**
5140 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
5141 *
5142 * @adev: amdgpu_device pointer
5143 *
5144 * The list of all the hardware IPs that make up the asic is walked and the
5145 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
5146 * handles any IP specific hardware or software state changes that are
5147 * necessary after the IP has been soft reset.
5148 * Returns 0 on success, negative error code on failure.
5149 */
5150static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
5151{
5152 int i, r = 0;
5153
5154 for (i = 0; i < adev->num_ip_blocks; i++) {
5155 if (!adev->ip_blocks[i].status.valid)
5156 continue;
5157 if (adev->ip_blocks[i].status.hang &&
5158 adev->ip_blocks[i].version->funcs->post_soft_reset)
5159 r = adev->ip_blocks[i].version->funcs->post_soft_reset(&adev->ip_blocks[i]);
5160 if (r)
5161 return r;
5162 }
5163
5164 return 0;
5165}
5166
5167/**
5168 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
5169 *
5170 * @adev: amdgpu_device pointer
5171 * @reset_context: amdgpu reset context pointer
5172 *
5173 * do VF FLR and reinitialize Asic
5174 * return 0 means succeeded otherwise failed
5175 */
5176static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
5177 struct amdgpu_reset_context *reset_context)
5178{
5179 int r;
5180 struct amdgpu_hive_info *hive = NULL;
5181
5182 if (test_bit(AMDGPU_HOST_FLR, &reset_context->flags)) {
5183 if (!amdgpu_ras_get_fed_status(adev))
5184 amdgpu_virt_ready_to_reset(adev);
5185 amdgpu_virt_wait_reset(adev);
5186 clear_bit(AMDGPU_HOST_FLR, &reset_context->flags);
5187 r = amdgpu_virt_request_full_gpu(adev, true);
5188 } else {
5189 r = amdgpu_virt_reset_gpu(adev);
5190 }
5191 if (r)
5192 return r;
5193
5194 amdgpu_ras_set_fed(adev, false);
5195 amdgpu_irq_gpu_reset_resume_helper(adev);
5196
5197 /* some sw clean up VF needs to do before recover */
5198 amdgpu_virt_post_reset(adev);
5199
5200 /* Resume IP prior to SMC */
5201 r = amdgpu_device_ip_reinit_early_sriov(adev);
5202 if (r)
5203 return r;
5204
5205 amdgpu_virt_init_data_exchange(adev);
5206
5207 r = amdgpu_device_fw_loading(adev);
5208 if (r)
5209 return r;
5210
5211 /* now we are okay to resume SMC/CP/SDMA */
5212 r = amdgpu_device_ip_reinit_late_sriov(adev);
5213 if (r)
5214 return r;
5215
5216 hive = amdgpu_get_xgmi_hive(adev);
5217 /* Update PSP FW topology after reset */
5218 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
5219 r = amdgpu_xgmi_update_topology(hive, adev);
5220 if (hive)
5221 amdgpu_put_xgmi_hive(hive);
5222 if (r)
5223 return r;
5224
5225 r = amdgpu_ib_ring_tests(adev);
5226 if (r)
5227 return r;
5228
5229 if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST)
5230 amdgpu_inc_vram_lost(adev);
5231
5232 /* need to be called during full access so we can't do it later like
5233 * bare-metal does.
5234 */
5235 amdgpu_amdkfd_post_reset(adev);
5236 amdgpu_virt_release_full_gpu(adev, true);
5237
5238 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5239 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
5240 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
5241 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
5242 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
5243 amdgpu_ras_resume(adev);
5244
5245 amdgpu_virt_ras_telemetry_post_reset(adev);
5246
5247 return 0;
5248}
5249
5250/**
5251 * amdgpu_device_has_job_running - check if there is any job in mirror list
5252 *
5253 * @adev: amdgpu_device pointer
5254 *
5255 * check if there is any job in mirror list
5256 */
5257bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
5258{
5259 int i;
5260 struct drm_sched_job *job;
5261
5262 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5263 struct amdgpu_ring *ring = adev->rings[i];
5264
5265 if (!amdgpu_ring_sched_ready(ring))
5266 continue;
5267
5268 spin_lock(&ring->sched.job_list_lock);
5269 job = list_first_entry_or_null(&ring->sched.pending_list,
5270 struct drm_sched_job, list);
5271 spin_unlock(&ring->sched.job_list_lock);
5272 if (job)
5273 return true;
5274 }
5275 return false;
5276}
5277
5278/**
5279 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
5280 *
5281 * @adev: amdgpu_device pointer
5282 *
5283 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
5284 * a hung GPU.
5285 */
5286bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
5287{
5288
5289 if (amdgpu_gpu_recovery == 0)
5290 goto disabled;
5291
5292 /* Skip soft reset check in fatal error mode */
5293 if (!amdgpu_ras_is_poison_mode_supported(adev))
5294 return true;
5295
5296 if (amdgpu_sriov_vf(adev))
5297 return true;
5298
5299 if (amdgpu_gpu_recovery == -1) {
5300 switch (adev->asic_type) {
5301#ifdef CONFIG_DRM_AMDGPU_SI
5302 case CHIP_VERDE:
5303 case CHIP_TAHITI:
5304 case CHIP_PITCAIRN:
5305 case CHIP_OLAND:
5306 case CHIP_HAINAN:
5307#endif
5308#ifdef CONFIG_DRM_AMDGPU_CIK
5309 case CHIP_KAVERI:
5310 case CHIP_KABINI:
5311 case CHIP_MULLINS:
5312#endif
5313 case CHIP_CARRIZO:
5314 case CHIP_STONEY:
5315 case CHIP_CYAN_SKILLFISH:
5316 goto disabled;
5317 default:
5318 break;
5319 }
5320 }
5321
5322 return true;
5323
5324disabled:
5325 dev_info(adev->dev, "GPU recovery disabled.\n");
5326 return false;
5327}
5328
5329int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
5330{
5331 u32 i;
5332 int ret = 0;
5333
5334 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
5335
5336 dev_info(adev->dev, "GPU mode1 reset\n");
5337
5338 /* Cache the state before bus master disable. The saved config space
5339 * values are used in other cases like restore after mode-2 reset.
5340 */
5341 amdgpu_device_cache_pci_state(adev->pdev);
5342
5343 /* disable BM */
5344 pci_clear_master(adev->pdev);
5345
5346 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
5347 dev_info(adev->dev, "GPU smu mode1 reset\n");
5348 ret = amdgpu_dpm_mode1_reset(adev);
5349 } else {
5350 dev_info(adev->dev, "GPU psp mode1 reset\n");
5351 ret = psp_gpu_reset(adev);
5352 }
5353
5354 if (ret)
5355 goto mode1_reset_failed;
5356
5357 amdgpu_device_load_pci_state(adev->pdev);
5358 ret = amdgpu_psp_wait_for_bootloader(adev);
5359 if (ret)
5360 goto mode1_reset_failed;
5361
5362 /* wait for asic to come out of reset */
5363 for (i = 0; i < adev->usec_timeout; i++) {
5364 u32 memsize = adev->nbio.funcs->get_memsize(adev);
5365
5366 if (memsize != 0xffffffff)
5367 break;
5368 udelay(1);
5369 }
5370
5371 if (i >= adev->usec_timeout) {
5372 ret = -ETIMEDOUT;
5373 goto mode1_reset_failed;
5374 }
5375
5376 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
5377
5378 return 0;
5379
5380mode1_reset_failed:
5381 dev_err(adev->dev, "GPU mode1 reset failed\n");
5382 return ret;
5383}
5384
5385int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
5386 struct amdgpu_reset_context *reset_context)
5387{
5388 int i, r = 0;
5389 struct amdgpu_job *job = NULL;
5390 struct amdgpu_device *tmp_adev = reset_context->reset_req_dev;
5391 bool need_full_reset =
5392 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5393
5394 if (reset_context->reset_req_dev == adev)
5395 job = reset_context->job;
5396
5397 if (amdgpu_sriov_vf(adev))
5398 amdgpu_virt_pre_reset(adev);
5399
5400 amdgpu_fence_driver_isr_toggle(adev, true);
5401
5402 /* block all schedulers and reset given job's ring */
5403 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5404 struct amdgpu_ring *ring = adev->rings[i];
5405
5406 if (!amdgpu_ring_sched_ready(ring))
5407 continue;
5408
5409 /* Clear job fence from fence drv to avoid force_completion
5410 * leave NULL and vm flush fence in fence drv
5411 */
5412 amdgpu_fence_driver_clear_job_fences(ring);
5413
5414 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
5415 amdgpu_fence_driver_force_completion(ring);
5416 }
5417
5418 amdgpu_fence_driver_isr_toggle(adev, false);
5419
5420 if (job && job->vm)
5421 drm_sched_increase_karma(&job->base);
5422
5423 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
5424 /* If reset handler not implemented, continue; otherwise return */
5425 if (r == -EOPNOTSUPP)
5426 r = 0;
5427 else
5428 return r;
5429
5430 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
5431 if (!amdgpu_sriov_vf(adev)) {
5432
5433 if (!need_full_reset)
5434 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
5435
5436 if (!need_full_reset && amdgpu_gpu_recovery &&
5437 amdgpu_device_ip_check_soft_reset(adev)) {
5438 amdgpu_device_ip_pre_soft_reset(adev);
5439 r = amdgpu_device_ip_soft_reset(adev);
5440 amdgpu_device_ip_post_soft_reset(adev);
5441 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
5442 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
5443 need_full_reset = true;
5444 }
5445 }
5446
5447 if (!test_bit(AMDGPU_SKIP_COREDUMP, &reset_context->flags)) {
5448 dev_info(tmp_adev->dev, "Dumping IP State\n");
5449 /* Trigger ip dump before we reset the asic */
5450 for (i = 0; i < tmp_adev->num_ip_blocks; i++)
5451 if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
5452 tmp_adev->ip_blocks[i].version->funcs
5453 ->dump_ip_state((void *)&tmp_adev->ip_blocks[i]);
5454 dev_info(tmp_adev->dev, "Dumping IP State Completed\n");
5455 }
5456
5457 if (need_full_reset)
5458 r = amdgpu_device_ip_suspend(adev);
5459 if (need_full_reset)
5460 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5461 else
5462 clear_bit(AMDGPU_NEED_FULL_RESET,
5463 &reset_context->flags);
5464 }
5465
5466 return r;
5467}
5468
5469int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context)
5470{
5471 struct list_head *device_list_handle;
5472 bool full_reset, vram_lost = false;
5473 struct amdgpu_device *tmp_adev;
5474 int r, init_level;
5475
5476 device_list_handle = reset_context->reset_device_list;
5477
5478 if (!device_list_handle)
5479 return -EINVAL;
5480
5481 full_reset = test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5482
5483 /**
5484 * If it's reset on init, it's default init level, otherwise keep level
5485 * as recovery level.
5486 */
5487 if (reset_context->method == AMD_RESET_METHOD_ON_INIT)
5488 init_level = AMDGPU_INIT_LEVEL_DEFAULT;
5489 else
5490 init_level = AMDGPU_INIT_LEVEL_RESET_RECOVERY;
5491
5492 r = 0;
5493 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5494 amdgpu_set_init_level(tmp_adev, init_level);
5495 if (full_reset) {
5496 /* post card */
5497 amdgpu_ras_set_fed(tmp_adev, false);
5498 r = amdgpu_device_asic_init(tmp_adev);
5499 if (r) {
5500 dev_warn(tmp_adev->dev, "asic atom init failed!");
5501 } else {
5502 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5503
5504 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5505 if (r)
5506 goto out;
5507
5508 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5509
5510 if (!test_bit(AMDGPU_SKIP_COREDUMP, &reset_context->flags))
5511 amdgpu_coredump(tmp_adev, false, vram_lost, reset_context->job);
5512
5513 if (vram_lost) {
5514 DRM_INFO("VRAM is lost due to GPU reset!\n");
5515 amdgpu_inc_vram_lost(tmp_adev);
5516 }
5517
5518 r = amdgpu_device_fw_loading(tmp_adev);
5519 if (r)
5520 return r;
5521
5522 r = amdgpu_xcp_restore_partition_mode(
5523 tmp_adev->xcp_mgr);
5524 if (r)
5525 goto out;
5526
5527 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5528 if (r)
5529 goto out;
5530
5531 if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
5532 amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
5533
5534 r = amdgpu_device_ip_resume_phase3(tmp_adev);
5535 if (r)
5536 goto out;
5537
5538 if (vram_lost)
5539 amdgpu_device_fill_reset_magic(tmp_adev);
5540
5541 /*
5542 * Add this ASIC as tracked as reset was already
5543 * complete successfully.
5544 */
5545 amdgpu_register_gpu_instance(tmp_adev);
5546
5547 if (!reset_context->hive &&
5548 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5549 amdgpu_xgmi_add_device(tmp_adev);
5550
5551 r = amdgpu_device_ip_late_init(tmp_adev);
5552 if (r)
5553 goto out;
5554
5555 drm_client_dev_resume(adev_to_drm(tmp_adev), false);
5556
5557 /*
5558 * The GPU enters bad state once faulty pages
5559 * by ECC has reached the threshold, and ras
5560 * recovery is scheduled next. So add one check
5561 * here to break recovery if it indeed exceeds
5562 * bad page threshold, and remind user to
5563 * retire this GPU or setting one bigger
5564 * bad_page_threshold value to fix this once
5565 * probing driver again.
5566 */
5567 if (!amdgpu_ras_is_rma(tmp_adev)) {
5568 /* must succeed. */
5569 amdgpu_ras_resume(tmp_adev);
5570 } else {
5571 r = -EINVAL;
5572 goto out;
5573 }
5574
5575 /* Update PSP FW topology after reset */
5576 if (reset_context->hive &&
5577 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5578 r = amdgpu_xgmi_update_topology(
5579 reset_context->hive, tmp_adev);
5580 }
5581 }
5582
5583out:
5584 if (!r) {
5585 /* IP init is complete now, set level as default */
5586 amdgpu_set_init_level(tmp_adev,
5587 AMDGPU_INIT_LEVEL_DEFAULT);
5588 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5589 r = amdgpu_ib_ring_tests(tmp_adev);
5590 if (r) {
5591 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5592 r = -EAGAIN;
5593 goto end;
5594 }
5595 }
5596
5597 if (r)
5598 tmp_adev->asic_reset_res = r;
5599 }
5600
5601end:
5602 return r;
5603}
5604
5605int amdgpu_do_asic_reset(struct list_head *device_list_handle,
5606 struct amdgpu_reset_context *reset_context)
5607{
5608 struct amdgpu_device *tmp_adev = NULL;
5609 bool need_full_reset, skip_hw_reset;
5610 int r = 0;
5611
5612 /* Try reset handler method first */
5613 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5614 reset_list);
5615
5616 reset_context->reset_device_list = device_list_handle;
5617 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5618 /* If reset handler not implemented, continue; otherwise return */
5619 if (r == -EOPNOTSUPP)
5620 r = 0;
5621 else
5622 return r;
5623
5624 /* Reset handler not implemented, use the default method */
5625 need_full_reset =
5626 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5627 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
5628
5629 /*
5630 * ASIC reset has to be done on all XGMI hive nodes ASAP
5631 * to allow proper links negotiation in FW (within 1 sec)
5632 */
5633 if (!skip_hw_reset && need_full_reset) {
5634 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5635 /* For XGMI run all resets in parallel to speed up the process */
5636 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5637 if (!queue_work(system_unbound_wq,
5638 &tmp_adev->xgmi_reset_work))
5639 r = -EALREADY;
5640 } else
5641 r = amdgpu_asic_reset(tmp_adev);
5642
5643 if (r) {
5644 dev_err(tmp_adev->dev,
5645 "ASIC reset failed with error, %d for drm dev, %s",
5646 r, adev_to_drm(tmp_adev)->unique);
5647 goto out;
5648 }
5649 }
5650
5651 /* For XGMI wait for all resets to complete before proceed */
5652 if (!r) {
5653 list_for_each_entry(tmp_adev, device_list_handle,
5654 reset_list) {
5655 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5656 flush_work(&tmp_adev->xgmi_reset_work);
5657 r = tmp_adev->asic_reset_res;
5658 if (r)
5659 break;
5660 }
5661 }
5662 }
5663 }
5664
5665 if (!r && amdgpu_ras_intr_triggered()) {
5666 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5667 amdgpu_ras_reset_error_count(tmp_adev,
5668 AMDGPU_RAS_BLOCK__MMHUB);
5669 }
5670
5671 amdgpu_ras_intr_cleared();
5672 }
5673
5674 r = amdgpu_device_reinit_after_reset(reset_context);
5675 if (r == -EAGAIN)
5676 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5677 else
5678 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5679
5680out:
5681 return r;
5682}
5683
5684static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5685{
5686
5687 switch (amdgpu_asic_reset_method(adev)) {
5688 case AMD_RESET_METHOD_MODE1:
5689 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5690 break;
5691 case AMD_RESET_METHOD_MODE2:
5692 adev->mp1_state = PP_MP1_STATE_RESET;
5693 break;
5694 default:
5695 adev->mp1_state = PP_MP1_STATE_NONE;
5696 break;
5697 }
5698}
5699
5700static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5701{
5702 amdgpu_vf_error_trans_all(adev);
5703 adev->mp1_state = PP_MP1_STATE_NONE;
5704}
5705
5706static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5707{
5708 struct pci_dev *p = NULL;
5709
5710 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5711 adev->pdev->bus->number, 1);
5712 if (p) {
5713 pm_runtime_enable(&(p->dev));
5714 pm_runtime_resume(&(p->dev));
5715 }
5716
5717 pci_dev_put(p);
5718}
5719
5720static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5721{
5722 enum amd_reset_method reset_method;
5723 struct pci_dev *p = NULL;
5724 u64 expires;
5725
5726 /*
5727 * For now, only BACO and mode1 reset are confirmed
5728 * to suffer the audio issue without proper suspended.
5729 */
5730 reset_method = amdgpu_asic_reset_method(adev);
5731 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5732 (reset_method != AMD_RESET_METHOD_MODE1))
5733 return -EINVAL;
5734
5735 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5736 adev->pdev->bus->number, 1);
5737 if (!p)
5738 return -ENODEV;
5739
5740 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5741 if (!expires)
5742 /*
5743 * If we cannot get the audio device autosuspend delay,
5744 * a fixed 4S interval will be used. Considering 3S is
5745 * the audio controller default autosuspend delay setting.
5746 * 4S used here is guaranteed to cover that.
5747 */
5748 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5749
5750 while (!pm_runtime_status_suspended(&(p->dev))) {
5751 if (!pm_runtime_suspend(&(p->dev)))
5752 break;
5753
5754 if (expires < ktime_get_mono_fast_ns()) {
5755 dev_warn(adev->dev, "failed to suspend display audio\n");
5756 pci_dev_put(p);
5757 /* TODO: abort the succeeding gpu reset? */
5758 return -ETIMEDOUT;
5759 }
5760 }
5761
5762 pm_runtime_disable(&(p->dev));
5763
5764 pci_dev_put(p);
5765 return 0;
5766}
5767
5768static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5769{
5770 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5771
5772#if defined(CONFIG_DEBUG_FS)
5773 if (!amdgpu_sriov_vf(adev))
5774 cancel_work(&adev->reset_work);
5775#endif
5776
5777 if (adev->kfd.dev)
5778 cancel_work(&adev->kfd.reset_work);
5779
5780 if (amdgpu_sriov_vf(adev))
5781 cancel_work(&adev->virt.flr_work);
5782
5783 if (con && adev->ras_enabled)
5784 cancel_work(&con->recovery_work);
5785
5786}
5787
5788static int amdgpu_device_health_check(struct list_head *device_list_handle)
5789{
5790 struct amdgpu_device *tmp_adev;
5791 int ret = 0;
5792 u32 status;
5793
5794 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5795 pci_read_config_dword(tmp_adev->pdev, PCI_COMMAND, &status);
5796 if (PCI_POSSIBLE_ERROR(status)) {
5797 dev_err(tmp_adev->dev, "device lost from bus!");
5798 ret = -ENODEV;
5799 }
5800 }
5801
5802 return ret;
5803}
5804
5805/**
5806 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5807 *
5808 * @adev: amdgpu_device pointer
5809 * @job: which job trigger hang
5810 * @reset_context: amdgpu reset context pointer
5811 *
5812 * Attempt to reset the GPU if it has hung (all asics).
5813 * Attempt to do soft-reset or full-reset and reinitialize Asic
5814 * Returns 0 for success or an error on failure.
5815 */
5816
5817int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5818 struct amdgpu_job *job,
5819 struct amdgpu_reset_context *reset_context)
5820{
5821 struct list_head device_list, *device_list_handle = NULL;
5822 bool job_signaled = false;
5823 struct amdgpu_hive_info *hive = NULL;
5824 struct amdgpu_device *tmp_adev = NULL;
5825 int i, r = 0;
5826 bool need_emergency_restart = false;
5827 bool audio_suspended = false;
5828 int retry_limit = AMDGPU_MAX_RETRY_LIMIT;
5829
5830 /*
5831 * Special case: RAS triggered and full reset isn't supported
5832 */
5833 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5834
5835 /*
5836 * Flush RAM to disk so that after reboot
5837 * the user can read log and see why the system rebooted.
5838 */
5839 if (need_emergency_restart && amdgpu_ras_get_context(adev) &&
5840 amdgpu_ras_get_context(adev)->reboot) {
5841 DRM_WARN("Emergency reboot.");
5842
5843 ksys_sync_helper();
5844 emergency_restart();
5845 }
5846
5847 dev_info(adev->dev, "GPU %s begin!\n",
5848 need_emergency_restart ? "jobs stop":"reset");
5849
5850 if (!amdgpu_sriov_vf(adev))
5851 hive = amdgpu_get_xgmi_hive(adev);
5852 if (hive)
5853 mutex_lock(&hive->hive_lock);
5854
5855 reset_context->job = job;
5856 reset_context->hive = hive;
5857 /*
5858 * Build list of devices to reset.
5859 * In case we are in XGMI hive mode, resort the device list
5860 * to put adev in the 1st position.
5861 */
5862 INIT_LIST_HEAD(&device_list);
5863 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) {
5864 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5865 list_add_tail(&tmp_adev->reset_list, &device_list);
5866 if (adev->shutdown)
5867 tmp_adev->shutdown = true;
5868 }
5869 if (!list_is_first(&adev->reset_list, &device_list))
5870 list_rotate_to_front(&adev->reset_list, &device_list);
5871 device_list_handle = &device_list;
5872 } else {
5873 list_add_tail(&adev->reset_list, &device_list);
5874 device_list_handle = &device_list;
5875 }
5876
5877 if (!amdgpu_sriov_vf(adev)) {
5878 r = amdgpu_device_health_check(device_list_handle);
5879 if (r)
5880 goto end_reset;
5881 }
5882
5883 /* We need to lock reset domain only once both for XGMI and single device */
5884 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5885 reset_list);
5886 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5887
5888 /* block all schedulers and reset given job's ring */
5889 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5890
5891 amdgpu_device_set_mp1_state(tmp_adev);
5892
5893 /*
5894 * Try to put the audio codec into suspend state
5895 * before gpu reset started.
5896 *
5897 * Due to the power domain of the graphics device
5898 * is shared with AZ power domain. Without this,
5899 * we may change the audio hardware from behind
5900 * the audio driver's back. That will trigger
5901 * some audio codec errors.
5902 */
5903 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5904 audio_suspended = true;
5905
5906 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5907
5908 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5909
5910 amdgpu_amdkfd_pre_reset(tmp_adev, reset_context);
5911
5912 /*
5913 * Mark these ASICs to be reseted as untracked first
5914 * And add them back after reset completed
5915 */
5916 amdgpu_unregister_gpu_instance(tmp_adev);
5917
5918 drm_client_dev_suspend(adev_to_drm(tmp_adev), false);
5919
5920 /* disable ras on ALL IPs */
5921 if (!need_emergency_restart &&
5922 amdgpu_device_ip_need_full_reset(tmp_adev))
5923 amdgpu_ras_suspend(tmp_adev);
5924
5925 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5926 struct amdgpu_ring *ring = tmp_adev->rings[i];
5927
5928 if (!amdgpu_ring_sched_ready(ring))
5929 continue;
5930
5931 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5932
5933 if (need_emergency_restart)
5934 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5935 }
5936 atomic_inc(&tmp_adev->gpu_reset_counter);
5937 }
5938
5939 if (need_emergency_restart)
5940 goto skip_sched_resume;
5941
5942 /*
5943 * Must check guilty signal here since after this point all old
5944 * HW fences are force signaled.
5945 *
5946 * job->base holds a reference to parent fence
5947 */
5948 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5949 job_signaled = true;
5950 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5951 goto skip_hw_reset;
5952 }
5953
5954retry: /* Rest of adevs pre asic reset from XGMI hive. */
5955 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5956 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5957 /*TODO Should we stop ?*/
5958 if (r) {
5959 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5960 r, adev_to_drm(tmp_adev)->unique);
5961 tmp_adev->asic_reset_res = r;
5962 }
5963 }
5964
5965 /* Actual ASIC resets if needed.*/
5966 /* Host driver will handle XGMI hive reset for SRIOV */
5967 if (amdgpu_sriov_vf(adev)) {
5968 if (amdgpu_ras_get_fed_status(adev) || amdgpu_virt_rcvd_ras_interrupt(adev)) {
5969 dev_dbg(adev->dev, "Detected RAS error, wait for FLR completion\n");
5970 amdgpu_ras_set_fed(adev, true);
5971 set_bit(AMDGPU_HOST_FLR, &reset_context->flags);
5972 }
5973
5974 r = amdgpu_device_reset_sriov(adev, reset_context);
5975 if (AMDGPU_RETRY_SRIOV_RESET(r) && (retry_limit--) > 0) {
5976 amdgpu_virt_release_full_gpu(adev, true);
5977 goto retry;
5978 }
5979 if (r)
5980 adev->asic_reset_res = r;
5981 } else {
5982 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5983 if (r && r == -EAGAIN)
5984 goto retry;
5985 }
5986
5987 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5988 /*
5989 * Drop any pending non scheduler resets queued before reset is done.
5990 * Any reset scheduled after this point would be valid. Scheduler resets
5991 * were already dropped during drm_sched_stop and no new ones can come
5992 * in before drm_sched_start.
5993 */
5994 amdgpu_device_stop_pending_resets(tmp_adev);
5995 }
5996
5997skip_hw_reset:
5998
5999 /* Post ASIC reset for all devs .*/
6000 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
6001
6002 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6003 struct amdgpu_ring *ring = tmp_adev->rings[i];
6004
6005 if (!amdgpu_ring_sched_ready(ring))
6006 continue;
6007
6008 drm_sched_start(&ring->sched, 0);
6009 }
6010
6011 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
6012 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
6013
6014 if (tmp_adev->asic_reset_res)
6015 r = tmp_adev->asic_reset_res;
6016
6017 tmp_adev->asic_reset_res = 0;
6018
6019 if (r) {
6020 /* bad news, how to tell it to userspace ?
6021 * for ras error, we should report GPU bad status instead of
6022 * reset failure
6023 */
6024 if (reset_context->src != AMDGPU_RESET_SRC_RAS ||
6025 !amdgpu_ras_eeprom_check_err_threshold(tmp_adev))
6026 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n",
6027 atomic_read(&tmp_adev->gpu_reset_counter));
6028 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
6029 } else {
6030 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
6031 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
6032 DRM_WARN("smart shift update failed\n");
6033 }
6034 }
6035
6036skip_sched_resume:
6037 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
6038 /* unlock kfd: SRIOV would do it separately */
6039 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
6040 amdgpu_amdkfd_post_reset(tmp_adev);
6041
6042 /* kfd_post_reset will do nothing if kfd device is not initialized,
6043 * need to bring up kfd here if it's not be initialized before
6044 */
6045 if (!adev->kfd.init_complete)
6046 amdgpu_amdkfd_device_init(adev);
6047
6048 if (audio_suspended)
6049 amdgpu_device_resume_display_audio(tmp_adev);
6050
6051 amdgpu_device_unset_mp1_state(tmp_adev);
6052
6053 amdgpu_ras_set_error_query_ready(tmp_adev, true);
6054 }
6055
6056 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
6057 reset_list);
6058 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
6059
6060end_reset:
6061 if (hive) {
6062 mutex_unlock(&hive->hive_lock);
6063 amdgpu_put_xgmi_hive(hive);
6064 }
6065
6066 if (r)
6067 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
6068
6069 atomic_set(&adev->reset_domain->reset_res, r);
6070 return r;
6071}
6072
6073/**
6074 * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner
6075 *
6076 * @adev: amdgpu_device pointer
6077 * @speed: pointer to the speed of the link
6078 * @width: pointer to the width of the link
6079 *
6080 * Evaluate the hierarchy to find the speed and bandwidth capabilities of the
6081 * first physical partner to an AMD dGPU.
6082 * This will exclude any virtual switches and links.
6083 */
6084static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
6085 enum pci_bus_speed *speed,
6086 enum pcie_link_width *width)
6087{
6088 struct pci_dev *parent = adev->pdev;
6089
6090 if (!speed || !width)
6091 return;
6092
6093 *speed = PCI_SPEED_UNKNOWN;
6094 *width = PCIE_LNK_WIDTH_UNKNOWN;
6095
6096 if (amdgpu_device_pcie_dynamic_switching_supported(adev)) {
6097 while ((parent = pci_upstream_bridge(parent))) {
6098 /* skip upstream/downstream switches internal to dGPU*/
6099 if (parent->vendor == PCI_VENDOR_ID_ATI)
6100 continue;
6101 *speed = pcie_get_speed_cap(parent);
6102 *width = pcie_get_width_cap(parent);
6103 break;
6104 }
6105 } else {
6106 /* use the current speeds rather than max if switching is not supported */
6107 pcie_bandwidth_available(adev->pdev, NULL, speed, width);
6108 }
6109}
6110
6111/**
6112 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
6113 *
6114 * @adev: amdgpu_device pointer
6115 *
6116 * Fetchs and stores in the driver the PCIE capabilities (gen speed
6117 * and lanes) of the slot the device is in. Handles APUs and
6118 * virtualized environments where PCIE config space may not be available.
6119 */
6120static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
6121{
6122 struct pci_dev *pdev;
6123 enum pci_bus_speed speed_cap, platform_speed_cap;
6124 enum pcie_link_width platform_link_width;
6125
6126 if (amdgpu_pcie_gen_cap)
6127 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
6128
6129 if (amdgpu_pcie_lane_cap)
6130 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
6131
6132 /* covers APUs as well */
6133 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
6134 if (adev->pm.pcie_gen_mask == 0)
6135 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
6136 if (adev->pm.pcie_mlw_mask == 0)
6137 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
6138 return;
6139 }
6140
6141 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
6142 return;
6143
6144 amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
6145 &platform_link_width);
6146
6147 if (adev->pm.pcie_gen_mask == 0) {
6148 /* asic caps */
6149 pdev = adev->pdev;
6150 speed_cap = pcie_get_speed_cap(pdev);
6151 if (speed_cap == PCI_SPEED_UNKNOWN) {
6152 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6153 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6154 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
6155 } else {
6156 if (speed_cap == PCIE_SPEED_32_0GT)
6157 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6158 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6159 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6160 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
6161 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
6162 else if (speed_cap == PCIE_SPEED_16_0GT)
6163 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6164 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6165 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6166 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
6167 else if (speed_cap == PCIE_SPEED_8_0GT)
6168 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6169 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6170 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
6171 else if (speed_cap == PCIE_SPEED_5_0GT)
6172 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6173 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
6174 else
6175 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
6176 }
6177 /* platform caps */
6178 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
6179 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6180 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
6181 } else {
6182 if (platform_speed_cap == PCIE_SPEED_32_0GT)
6183 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6184 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6185 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6186 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
6187 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
6188 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
6189 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6190 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6191 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
6192 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
6193 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
6194 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6195 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
6196 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
6197 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
6198 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
6199 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
6200 else
6201 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
6202
6203 }
6204 }
6205 if (adev->pm.pcie_mlw_mask == 0) {
6206 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
6207 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
6208 } else {
6209 switch (platform_link_width) {
6210 case PCIE_LNK_X32:
6211 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
6212 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6213 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6214 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6215 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6216 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6217 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6218 break;
6219 case PCIE_LNK_X16:
6220 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6221 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6222 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6223 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6224 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6225 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6226 break;
6227 case PCIE_LNK_X12:
6228 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6229 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6230 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6231 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6232 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6233 break;
6234 case PCIE_LNK_X8:
6235 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6236 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6237 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6238 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6239 break;
6240 case PCIE_LNK_X4:
6241 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6242 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6243 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6244 break;
6245 case PCIE_LNK_X2:
6246 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6247 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6248 break;
6249 case PCIE_LNK_X1:
6250 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
6251 break;
6252 default:
6253 break;
6254 }
6255 }
6256 }
6257}
6258
6259/**
6260 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
6261 *
6262 * @adev: amdgpu_device pointer
6263 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
6264 *
6265 * Return true if @peer_adev can access (DMA) @adev through the PCIe
6266 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
6267 * @peer_adev.
6268 */
6269bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
6270 struct amdgpu_device *peer_adev)
6271{
6272#ifdef CONFIG_HSA_AMD_P2P
6273 bool p2p_access =
6274 !adev->gmc.xgmi.connected_to_cpu &&
6275 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
6276 if (!p2p_access)
6277 dev_info(adev->dev, "PCIe P2P access from peer device %s is not supported by the chipset\n",
6278 pci_name(peer_adev->pdev));
6279
6280 bool is_large_bar = adev->gmc.visible_vram_size &&
6281 adev->gmc.real_vram_size == adev->gmc.visible_vram_size;
6282 bool p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev);
6283
6284 if (!p2p_addressable) {
6285 uint64_t address_mask = peer_adev->dev->dma_mask ?
6286 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
6287 resource_size_t aper_limit =
6288 adev->gmc.aper_base + adev->gmc.aper_size - 1;
6289
6290 p2p_addressable = !(adev->gmc.aper_base & address_mask ||
6291 aper_limit & address_mask);
6292 }
6293 return pcie_p2p && is_large_bar && p2p_access && p2p_addressable;
6294#else
6295 return false;
6296#endif
6297}
6298
6299int amdgpu_device_baco_enter(struct drm_device *dev)
6300{
6301 struct amdgpu_device *adev = drm_to_adev(dev);
6302 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6303
6304 if (!amdgpu_device_supports_baco(dev))
6305 return -ENOTSUPP;
6306
6307 if (ras && adev->ras_enabled &&
6308 adev->nbio.funcs->enable_doorbell_interrupt)
6309 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
6310
6311 return amdgpu_dpm_baco_enter(adev);
6312}
6313
6314int amdgpu_device_baco_exit(struct drm_device *dev)
6315{
6316 struct amdgpu_device *adev = drm_to_adev(dev);
6317 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6318 int ret = 0;
6319
6320 if (!amdgpu_device_supports_baco(dev))
6321 return -ENOTSUPP;
6322
6323 ret = amdgpu_dpm_baco_exit(adev);
6324 if (ret)
6325 return ret;
6326
6327 if (ras && adev->ras_enabled &&
6328 adev->nbio.funcs->enable_doorbell_interrupt)
6329 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
6330
6331 if (amdgpu_passthrough(adev) && adev->nbio.funcs &&
6332 adev->nbio.funcs->clear_doorbell_interrupt)
6333 adev->nbio.funcs->clear_doorbell_interrupt(adev);
6334
6335 return 0;
6336}
6337
6338/**
6339 * amdgpu_pci_error_detected - Called when a PCI error is detected.
6340 * @pdev: PCI device struct
6341 * @state: PCI channel state
6342 *
6343 * Description: Called when a PCI error is detected.
6344 *
6345 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
6346 */
6347pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6348{
6349 struct drm_device *dev = pci_get_drvdata(pdev);
6350 struct amdgpu_device *adev = drm_to_adev(dev);
6351 int i;
6352
6353 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
6354
6355 if (adev->gmc.xgmi.num_physical_nodes > 1) {
6356 DRM_WARN("No support for XGMI hive yet...");
6357 return PCI_ERS_RESULT_DISCONNECT;
6358 }
6359
6360 adev->pci_channel_state = state;
6361
6362 switch (state) {
6363 case pci_channel_io_normal:
6364 return PCI_ERS_RESULT_CAN_RECOVER;
6365 /* Fatal error, prepare for slot reset */
6366 case pci_channel_io_frozen:
6367 /*
6368 * Locking adev->reset_domain->sem will prevent any external access
6369 * to GPU during PCI error recovery
6370 */
6371 amdgpu_device_lock_reset_domain(adev->reset_domain);
6372 amdgpu_device_set_mp1_state(adev);
6373
6374 /*
6375 * Block any work scheduling as we do for regular GPU reset
6376 * for the duration of the recovery
6377 */
6378 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6379 struct amdgpu_ring *ring = adev->rings[i];
6380
6381 if (!amdgpu_ring_sched_ready(ring))
6382 continue;
6383
6384 drm_sched_stop(&ring->sched, NULL);
6385 }
6386 atomic_inc(&adev->gpu_reset_counter);
6387 return PCI_ERS_RESULT_NEED_RESET;
6388 case pci_channel_io_perm_failure:
6389 /* Permanent error, prepare for device removal */
6390 return PCI_ERS_RESULT_DISCONNECT;
6391 }
6392
6393 return PCI_ERS_RESULT_NEED_RESET;
6394}
6395
6396/**
6397 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
6398 * @pdev: pointer to PCI device
6399 */
6400pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
6401{
6402
6403 DRM_INFO("PCI error: mmio enabled callback!!\n");
6404
6405 /* TODO - dump whatever for debugging purposes */
6406
6407 /* This called only if amdgpu_pci_error_detected returns
6408 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
6409 * works, no need to reset slot.
6410 */
6411
6412 return PCI_ERS_RESULT_RECOVERED;
6413}
6414
6415/**
6416 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
6417 * @pdev: PCI device struct
6418 *
6419 * Description: This routine is called by the pci error recovery
6420 * code after the PCI slot has been reset, just before we
6421 * should resume normal operations.
6422 */
6423pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
6424{
6425 struct drm_device *dev = pci_get_drvdata(pdev);
6426 struct amdgpu_device *adev = drm_to_adev(dev);
6427 int r, i;
6428 struct amdgpu_reset_context reset_context;
6429 u32 memsize;
6430 struct list_head device_list;
6431
6432 /* PCI error slot reset should be skipped During RAS recovery */
6433 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
6434 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) &&
6435 amdgpu_ras_in_recovery(adev))
6436 return PCI_ERS_RESULT_RECOVERED;
6437
6438 DRM_INFO("PCI error: slot reset callback!!\n");
6439
6440 memset(&reset_context, 0, sizeof(reset_context));
6441
6442 INIT_LIST_HEAD(&device_list);
6443 list_add_tail(&adev->reset_list, &device_list);
6444
6445 /* wait for asic to come out of reset */
6446 msleep(500);
6447
6448 /* Restore PCI confspace */
6449 amdgpu_device_load_pci_state(pdev);
6450
6451 /* confirm ASIC came out of reset */
6452 for (i = 0; i < adev->usec_timeout; i++) {
6453 memsize = amdgpu_asic_get_config_memsize(adev);
6454
6455 if (memsize != 0xffffffff)
6456 break;
6457 udelay(1);
6458 }
6459 if (memsize == 0xffffffff) {
6460 r = -ETIME;
6461 goto out;
6462 }
6463
6464 reset_context.method = AMD_RESET_METHOD_NONE;
6465 reset_context.reset_req_dev = adev;
6466 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6467 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
6468
6469 adev->no_hw_access = true;
6470 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
6471 adev->no_hw_access = false;
6472 if (r)
6473 goto out;
6474
6475 r = amdgpu_do_asic_reset(&device_list, &reset_context);
6476
6477out:
6478 if (!r) {
6479 if (amdgpu_device_cache_pci_state(adev->pdev))
6480 pci_restore_state(adev->pdev);
6481
6482 DRM_INFO("PCIe error recovery succeeded\n");
6483 } else {
6484 DRM_ERROR("PCIe error recovery failed, err:%d", r);
6485 amdgpu_device_unset_mp1_state(adev);
6486 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6487 }
6488
6489 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
6490}
6491
6492/**
6493 * amdgpu_pci_resume() - resume normal ops after PCI reset
6494 * @pdev: pointer to PCI device
6495 *
6496 * Called when the error recovery driver tells us that its
6497 * OK to resume normal operation.
6498 */
6499void amdgpu_pci_resume(struct pci_dev *pdev)
6500{
6501 struct drm_device *dev = pci_get_drvdata(pdev);
6502 struct amdgpu_device *adev = drm_to_adev(dev);
6503 int i;
6504
6505
6506 DRM_INFO("PCI error: resume callback!!\n");
6507
6508 /* Only continue execution for the case of pci_channel_io_frozen */
6509 if (adev->pci_channel_state != pci_channel_io_frozen)
6510 return;
6511
6512 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6513 struct amdgpu_ring *ring = adev->rings[i];
6514
6515 if (!amdgpu_ring_sched_ready(ring))
6516 continue;
6517
6518 drm_sched_start(&ring->sched, 0);
6519 }
6520
6521 amdgpu_device_unset_mp1_state(adev);
6522 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6523}
6524
6525bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
6526{
6527 struct drm_device *dev = pci_get_drvdata(pdev);
6528 struct amdgpu_device *adev = drm_to_adev(dev);
6529 int r;
6530
6531 if (amdgpu_sriov_vf(adev))
6532 return false;
6533
6534 r = pci_save_state(pdev);
6535 if (!r) {
6536 kfree(adev->pci_state);
6537
6538 adev->pci_state = pci_store_saved_state(pdev);
6539
6540 if (!adev->pci_state) {
6541 DRM_ERROR("Failed to store PCI saved state");
6542 return false;
6543 }
6544 } else {
6545 DRM_WARN("Failed to save PCI state, err:%d\n", r);
6546 return false;
6547 }
6548
6549 return true;
6550}
6551
6552bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
6553{
6554 struct drm_device *dev = pci_get_drvdata(pdev);
6555 struct amdgpu_device *adev = drm_to_adev(dev);
6556 int r;
6557
6558 if (!adev->pci_state)
6559 return false;
6560
6561 r = pci_load_saved_state(pdev, adev->pci_state);
6562
6563 if (!r) {
6564 pci_restore_state(pdev);
6565 } else {
6566 DRM_WARN("Failed to load PCI state, err:%d\n", r);
6567 return false;
6568 }
6569
6570 return true;
6571}
6572
6573void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
6574 struct amdgpu_ring *ring)
6575{
6576#ifdef CONFIG_X86_64
6577 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6578 return;
6579#endif
6580 if (adev->gmc.xgmi.connected_to_cpu)
6581 return;
6582
6583 if (ring && ring->funcs->emit_hdp_flush)
6584 amdgpu_ring_emit_hdp_flush(ring);
6585 else
6586 amdgpu_asic_flush_hdp(adev, ring);
6587}
6588
6589void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
6590 struct amdgpu_ring *ring)
6591{
6592#ifdef CONFIG_X86_64
6593 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6594 return;
6595#endif
6596 if (adev->gmc.xgmi.connected_to_cpu)
6597 return;
6598
6599 amdgpu_asic_invalidate_hdp(adev, ring);
6600}
6601
6602int amdgpu_in_reset(struct amdgpu_device *adev)
6603{
6604 return atomic_read(&adev->reset_domain->in_gpu_reset);
6605}
6606
6607/**
6608 * amdgpu_device_halt() - bring hardware to some kind of halt state
6609 *
6610 * @adev: amdgpu_device pointer
6611 *
6612 * Bring hardware to some kind of halt state so that no one can touch it
6613 * any more. It will help to maintain error context when error occurred.
6614 * Compare to a simple hang, the system will keep stable at least for SSH
6615 * access. Then it should be trivial to inspect the hardware state and
6616 * see what's going on. Implemented as following:
6617 *
6618 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
6619 * clears all CPU mappings to device, disallows remappings through page faults
6620 * 2. amdgpu_irq_disable_all() disables all interrupts
6621 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
6622 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
6623 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
6624 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
6625 * flush any in flight DMA operations
6626 */
6627void amdgpu_device_halt(struct amdgpu_device *adev)
6628{
6629 struct pci_dev *pdev = adev->pdev;
6630 struct drm_device *ddev = adev_to_drm(adev);
6631
6632 amdgpu_xcp_dev_unplug(adev);
6633 drm_dev_unplug(ddev);
6634
6635 amdgpu_irq_disable_all(adev);
6636
6637 amdgpu_fence_driver_hw_fini(adev);
6638
6639 adev->no_hw_access = true;
6640
6641 amdgpu_device_unmap_mmio(adev);
6642
6643 pci_disable_device(pdev);
6644 pci_wait_for_pending_transaction(pdev);
6645}
6646
6647u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6648 u32 reg)
6649{
6650 unsigned long flags, address, data;
6651 u32 r;
6652
6653 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6654 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6655
6656 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6657 WREG32(address, reg * 4);
6658 (void)RREG32(address);
6659 r = RREG32(data);
6660 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6661 return r;
6662}
6663
6664void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6665 u32 reg, u32 v)
6666{
6667 unsigned long flags, address, data;
6668
6669 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6670 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6671
6672 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6673 WREG32(address, reg * 4);
6674 (void)RREG32(address);
6675 WREG32(data, v);
6676 (void)RREG32(data);
6677 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6678}
6679
6680/**
6681 * amdgpu_device_get_gang - return a reference to the current gang
6682 * @adev: amdgpu_device pointer
6683 *
6684 * Returns: A new reference to the current gang leader.
6685 */
6686struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev)
6687{
6688 struct dma_fence *fence;
6689
6690 rcu_read_lock();
6691 fence = dma_fence_get_rcu_safe(&adev->gang_submit);
6692 rcu_read_unlock();
6693 return fence;
6694}
6695
6696/**
6697 * amdgpu_device_switch_gang - switch to a new gang
6698 * @adev: amdgpu_device pointer
6699 * @gang: the gang to switch to
6700 *
6701 * Try to switch to a new gang.
6702 * Returns: NULL if we switched to the new gang or a reference to the current
6703 * gang leader.
6704 */
6705struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6706 struct dma_fence *gang)
6707{
6708 struct dma_fence *old = NULL;
6709
6710 do {
6711 dma_fence_put(old);
6712 old = amdgpu_device_get_gang(adev);
6713 if (old == gang)
6714 break;
6715
6716 if (!dma_fence_is_signaled(old))
6717 return old;
6718
6719 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6720 old, gang) != old);
6721
6722 dma_fence_put(old);
6723 return NULL;
6724}
6725
6726bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6727{
6728 switch (adev->asic_type) {
6729#ifdef CONFIG_DRM_AMDGPU_SI
6730 case CHIP_HAINAN:
6731#endif
6732 case CHIP_TOPAZ:
6733 /* chips with no display hardware */
6734 return false;
6735#ifdef CONFIG_DRM_AMDGPU_SI
6736 case CHIP_TAHITI:
6737 case CHIP_PITCAIRN:
6738 case CHIP_VERDE:
6739 case CHIP_OLAND:
6740#endif
6741#ifdef CONFIG_DRM_AMDGPU_CIK
6742 case CHIP_BONAIRE:
6743 case CHIP_HAWAII:
6744 case CHIP_KAVERI:
6745 case CHIP_KABINI:
6746 case CHIP_MULLINS:
6747#endif
6748 case CHIP_TONGA:
6749 case CHIP_FIJI:
6750 case CHIP_POLARIS10:
6751 case CHIP_POLARIS11:
6752 case CHIP_POLARIS12:
6753 case CHIP_VEGAM:
6754 case CHIP_CARRIZO:
6755 case CHIP_STONEY:
6756 /* chips with display hardware */
6757 return true;
6758 default:
6759 /* IP discovery */
6760 if (!amdgpu_ip_version(adev, DCE_HWIP, 0) ||
6761 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6762 return false;
6763 return true;
6764 }
6765}
6766
6767uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6768 uint32_t inst, uint32_t reg_addr, char reg_name[],
6769 uint32_t expected_value, uint32_t mask)
6770{
6771 uint32_t ret = 0;
6772 uint32_t old_ = 0;
6773 uint32_t tmp_ = RREG32(reg_addr);
6774 uint32_t loop = adev->usec_timeout;
6775
6776 while ((tmp_ & (mask)) != (expected_value)) {
6777 if (old_ != tmp_) {
6778 loop = adev->usec_timeout;
6779 old_ = tmp_;
6780 } else
6781 udelay(1);
6782 tmp_ = RREG32(reg_addr);
6783 loop--;
6784 if (!loop) {
6785 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6786 inst, reg_name, (uint32_t)expected_value,
6787 (uint32_t)(tmp_ & (mask)));
6788 ret = -ETIMEDOUT;
6789 break;
6790 }
6791 }
6792 return ret;
6793}
6794
6795ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring)
6796{
6797 ssize_t size = 0;
6798
6799 if (!ring || !ring->adev)
6800 return size;
6801
6802 if (amdgpu_device_should_recover_gpu(ring->adev))
6803 size |= AMDGPU_RESET_TYPE_FULL;
6804
6805 if (unlikely(!ring->adev->debug_disable_soft_recovery) &&
6806 !amdgpu_sriov_vf(ring->adev) && ring->funcs->soft_recovery)
6807 size |= AMDGPU_RESET_TYPE_SOFT_RESET;
6808
6809 return size;
6810}
6811
6812ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset)
6813{
6814 ssize_t size = 0;
6815
6816 if (supported_reset == 0) {
6817 size += sysfs_emit_at(buf, size, "unsupported");
6818 size += sysfs_emit_at(buf, size, "\n");
6819 return size;
6820
6821 }
6822
6823 if (supported_reset & AMDGPU_RESET_TYPE_SOFT_RESET)
6824 size += sysfs_emit_at(buf, size, "soft ");
6825
6826 if (supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
6827 size += sysfs_emit_at(buf, size, "queue ");
6828
6829 if (supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)
6830 size += sysfs_emit_at(buf, size, "pipe ");
6831
6832 if (supported_reset & AMDGPU_RESET_TYPE_FULL)
6833 size += sysfs_emit_at(buf, size, "full ");
6834
6835 size += sysfs_emit_at(buf, size, "\n");
6836 return size;
6837}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <linux/slab.h>
30#include <linux/debugfs.h>
31#include <drm/drmP.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/amdgpu_drm.h>
34#include <linux/vgaarb.h>
35#include <linux/vga_switcheroo.h>
36#include <linux/efi.h>
37#include "amdgpu.h"
38#include "amdgpu_i2c.h"
39#include "atom.h"
40#include "amdgpu_atombios.h"
41#include "amd_pcie.h"
42#ifdef CONFIG_DRM_AMDGPU_CIK
43#include "cik.h"
44#endif
45#include "vi.h"
46#include "bif/bif_4_1_d.h"
47
48static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
49static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
50
51static const char *amdgpu_asic_name[] = {
52 "BONAIRE",
53 "KAVERI",
54 "KABINI",
55 "HAWAII",
56 "MULLINS",
57 "TOPAZ",
58 "TONGA",
59 "FIJI",
60 "CARRIZO",
61 "STONEY",
62 "LAST",
63};
64
65bool amdgpu_device_is_px(struct drm_device *dev)
66{
67 struct amdgpu_device *adev = dev->dev_private;
68
69 if (adev->flags & AMD_IS_PX)
70 return true;
71 return false;
72}
73
74/*
75 * MMIO register access helper functions.
76 */
77uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
78 bool always_indirect)
79{
80 if ((reg * 4) < adev->rmmio_size && !always_indirect)
81 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
82 else {
83 unsigned long flags;
84 uint32_t ret;
85
86 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
87 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
88 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
89 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
90
91 return ret;
92 }
93}
94
95void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
96 bool always_indirect)
97{
98 if ((reg * 4) < adev->rmmio_size && !always_indirect)
99 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
100 else {
101 unsigned long flags;
102
103 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
104 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
105 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
106 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
107 }
108}
109
110u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
111{
112 if ((reg * 4) < adev->rio_mem_size)
113 return ioread32(adev->rio_mem + (reg * 4));
114 else {
115 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
116 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
117 }
118}
119
120void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
121{
122
123 if ((reg * 4) < adev->rio_mem_size)
124 iowrite32(v, adev->rio_mem + (reg * 4));
125 else {
126 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
127 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
128 }
129}
130
131/**
132 * amdgpu_mm_rdoorbell - read a doorbell dword
133 *
134 * @adev: amdgpu_device pointer
135 * @index: doorbell index
136 *
137 * Returns the value in the doorbell aperture at the
138 * requested doorbell index (CIK).
139 */
140u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
141{
142 if (index < adev->doorbell.num_doorbells) {
143 return readl(adev->doorbell.ptr + index);
144 } else {
145 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
146 return 0;
147 }
148}
149
150/**
151 * amdgpu_mm_wdoorbell - write a doorbell dword
152 *
153 * @adev: amdgpu_device pointer
154 * @index: doorbell index
155 * @v: value to write
156 *
157 * Writes @v to the doorbell aperture at the
158 * requested doorbell index (CIK).
159 */
160void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
161{
162 if (index < adev->doorbell.num_doorbells) {
163 writel(v, adev->doorbell.ptr + index);
164 } else {
165 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
166 }
167}
168
169/**
170 * amdgpu_invalid_rreg - dummy reg read function
171 *
172 * @adev: amdgpu device pointer
173 * @reg: offset of register
174 *
175 * Dummy register read function. Used for register blocks
176 * that certain asics don't have (all asics).
177 * Returns the value in the register.
178 */
179static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
180{
181 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
182 BUG();
183 return 0;
184}
185
186/**
187 * amdgpu_invalid_wreg - dummy reg write function
188 *
189 * @adev: amdgpu device pointer
190 * @reg: offset of register
191 * @v: value to write to the register
192 *
193 * Dummy register read function. Used for register blocks
194 * that certain asics don't have (all asics).
195 */
196static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
197{
198 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
199 reg, v);
200 BUG();
201}
202
203/**
204 * amdgpu_block_invalid_rreg - dummy reg read function
205 *
206 * @adev: amdgpu device pointer
207 * @block: offset of instance
208 * @reg: offset of register
209 *
210 * Dummy register read function. Used for register blocks
211 * that certain asics don't have (all asics).
212 * Returns the value in the register.
213 */
214static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
215 uint32_t block, uint32_t reg)
216{
217 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
218 reg, block);
219 BUG();
220 return 0;
221}
222
223/**
224 * amdgpu_block_invalid_wreg - dummy reg write function
225 *
226 * @adev: amdgpu device pointer
227 * @block: offset of instance
228 * @reg: offset of register
229 * @v: value to write to the register
230 *
231 * Dummy register read function. Used for register blocks
232 * that certain asics don't have (all asics).
233 */
234static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
235 uint32_t block,
236 uint32_t reg, uint32_t v)
237{
238 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
239 reg, block, v);
240 BUG();
241}
242
243static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
244{
245 int r;
246
247 if (adev->vram_scratch.robj == NULL) {
248 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
249 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
250 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
251 NULL, NULL, &adev->vram_scratch.robj);
252 if (r) {
253 return r;
254 }
255 }
256
257 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
258 if (unlikely(r != 0))
259 return r;
260 r = amdgpu_bo_pin(adev->vram_scratch.robj,
261 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
262 if (r) {
263 amdgpu_bo_unreserve(adev->vram_scratch.robj);
264 return r;
265 }
266 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
267 (void **)&adev->vram_scratch.ptr);
268 if (r)
269 amdgpu_bo_unpin(adev->vram_scratch.robj);
270 amdgpu_bo_unreserve(adev->vram_scratch.robj);
271
272 return r;
273}
274
275static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
276{
277 int r;
278
279 if (adev->vram_scratch.robj == NULL) {
280 return;
281 }
282 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
283 if (likely(r == 0)) {
284 amdgpu_bo_kunmap(adev->vram_scratch.robj);
285 amdgpu_bo_unpin(adev->vram_scratch.robj);
286 amdgpu_bo_unreserve(adev->vram_scratch.robj);
287 }
288 amdgpu_bo_unref(&adev->vram_scratch.robj);
289}
290
291/**
292 * amdgpu_program_register_sequence - program an array of registers.
293 *
294 * @adev: amdgpu_device pointer
295 * @registers: pointer to the register array
296 * @array_size: size of the register array
297 *
298 * Programs an array or registers with and and or masks.
299 * This is a helper for setting golden registers.
300 */
301void amdgpu_program_register_sequence(struct amdgpu_device *adev,
302 const u32 *registers,
303 const u32 array_size)
304{
305 u32 tmp, reg, and_mask, or_mask;
306 int i;
307
308 if (array_size % 3)
309 return;
310
311 for (i = 0; i < array_size; i +=3) {
312 reg = registers[i + 0];
313 and_mask = registers[i + 1];
314 or_mask = registers[i + 2];
315
316 if (and_mask == 0xffffffff) {
317 tmp = or_mask;
318 } else {
319 tmp = RREG32(reg);
320 tmp &= ~and_mask;
321 tmp |= or_mask;
322 }
323 WREG32(reg, tmp);
324 }
325}
326
327void amdgpu_pci_config_reset(struct amdgpu_device *adev)
328{
329 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
330}
331
332/*
333 * GPU doorbell aperture helpers function.
334 */
335/**
336 * amdgpu_doorbell_init - Init doorbell driver information.
337 *
338 * @adev: amdgpu_device pointer
339 *
340 * Init doorbell driver information (CIK)
341 * Returns 0 on success, error on failure.
342 */
343static int amdgpu_doorbell_init(struct amdgpu_device *adev)
344{
345 /* doorbell bar mapping */
346 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
347 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
348
349 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
350 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
351 if (adev->doorbell.num_doorbells == 0)
352 return -EINVAL;
353
354 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
355 if (adev->doorbell.ptr == NULL) {
356 return -ENOMEM;
357 }
358 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
359 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
360
361 return 0;
362}
363
364/**
365 * amdgpu_doorbell_fini - Tear down doorbell driver information.
366 *
367 * @adev: amdgpu_device pointer
368 *
369 * Tear down doorbell driver information (CIK)
370 */
371static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
372{
373 iounmap(adev->doorbell.ptr);
374 adev->doorbell.ptr = NULL;
375}
376
377/**
378 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
379 * setup amdkfd
380 *
381 * @adev: amdgpu_device pointer
382 * @aperture_base: output returning doorbell aperture base physical address
383 * @aperture_size: output returning doorbell aperture size in bytes
384 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
385 *
386 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
387 * takes doorbells required for its own rings and reports the setup to amdkfd.
388 * amdgpu reserved doorbells are at the start of the doorbell aperture.
389 */
390void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
391 phys_addr_t *aperture_base,
392 size_t *aperture_size,
393 size_t *start_offset)
394{
395 /*
396 * The first num_doorbells are used by amdgpu.
397 * amdkfd takes whatever's left in the aperture.
398 */
399 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
400 *aperture_base = adev->doorbell.base;
401 *aperture_size = adev->doorbell.size;
402 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
403 } else {
404 *aperture_base = 0;
405 *aperture_size = 0;
406 *start_offset = 0;
407 }
408}
409
410/*
411 * amdgpu_wb_*()
412 * Writeback is the the method by which the the GPU updates special pages
413 * in memory with the status of certain GPU events (fences, ring pointers,
414 * etc.).
415 */
416
417/**
418 * amdgpu_wb_fini - Disable Writeback and free memory
419 *
420 * @adev: amdgpu_device pointer
421 *
422 * Disables Writeback and frees the Writeback memory (all asics).
423 * Used at driver shutdown.
424 */
425static void amdgpu_wb_fini(struct amdgpu_device *adev)
426{
427 if (adev->wb.wb_obj) {
428 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
429 amdgpu_bo_kunmap(adev->wb.wb_obj);
430 amdgpu_bo_unpin(adev->wb.wb_obj);
431 amdgpu_bo_unreserve(adev->wb.wb_obj);
432 }
433 amdgpu_bo_unref(&adev->wb.wb_obj);
434 adev->wb.wb = NULL;
435 adev->wb.wb_obj = NULL;
436 }
437}
438
439/**
440 * amdgpu_wb_init- Init Writeback driver info and allocate memory
441 *
442 * @adev: amdgpu_device pointer
443 *
444 * Disables Writeback and frees the Writeback memory (all asics).
445 * Used at driver startup.
446 * Returns 0 on success or an -error on failure.
447 */
448static int amdgpu_wb_init(struct amdgpu_device *adev)
449{
450 int r;
451
452 if (adev->wb.wb_obj == NULL) {
453 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
454 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
455 &adev->wb.wb_obj);
456 if (r) {
457 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
458 return r;
459 }
460 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
461 if (unlikely(r != 0)) {
462 amdgpu_wb_fini(adev);
463 return r;
464 }
465 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
466 &adev->wb.gpu_addr);
467 if (r) {
468 amdgpu_bo_unreserve(adev->wb.wb_obj);
469 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
470 amdgpu_wb_fini(adev);
471 return r;
472 }
473 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
474 amdgpu_bo_unreserve(adev->wb.wb_obj);
475 if (r) {
476 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
477 amdgpu_wb_fini(adev);
478 return r;
479 }
480
481 adev->wb.num_wb = AMDGPU_MAX_WB;
482 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
483
484 /* clear wb memory */
485 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
486 }
487
488 return 0;
489}
490
491/**
492 * amdgpu_wb_get - Allocate a wb entry
493 *
494 * @adev: amdgpu_device pointer
495 * @wb: wb index
496 *
497 * Allocate a wb slot for use by the driver (all asics).
498 * Returns 0 on success or -EINVAL on failure.
499 */
500int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
501{
502 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
503 if (offset < adev->wb.num_wb) {
504 __set_bit(offset, adev->wb.used);
505 *wb = offset;
506 return 0;
507 } else {
508 return -EINVAL;
509 }
510}
511
512/**
513 * amdgpu_wb_free - Free a wb entry
514 *
515 * @adev: amdgpu_device pointer
516 * @wb: wb index
517 *
518 * Free a wb slot allocated for use by the driver (all asics)
519 */
520void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
521{
522 if (wb < adev->wb.num_wb)
523 __clear_bit(wb, adev->wb.used);
524}
525
526/**
527 * amdgpu_vram_location - try to find VRAM location
528 * @adev: amdgpu device structure holding all necessary informations
529 * @mc: memory controller structure holding memory informations
530 * @base: base address at which to put VRAM
531 *
532 * Function will place try to place VRAM at base address provided
533 * as parameter (which is so far either PCI aperture address or
534 * for IGP TOM base address).
535 *
536 * If there is not enough space to fit the unvisible VRAM in the 32bits
537 * address space then we limit the VRAM size to the aperture.
538 *
539 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
540 * this shouldn't be a problem as we are using the PCI aperture as a reference.
541 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
542 * not IGP.
543 *
544 * Note: we use mc_vram_size as on some board we need to program the mc to
545 * cover the whole aperture even if VRAM size is inferior to aperture size
546 * Novell bug 204882 + along with lots of ubuntu ones
547 *
548 * Note: when limiting vram it's safe to overwritte real_vram_size because
549 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
550 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
551 * ones)
552 *
553 * Note: IGP TOM addr should be the same as the aperture addr, we don't
554 * explicitly check for that thought.
555 *
556 * FIXME: when reducing VRAM size align new size on power of 2.
557 */
558void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
559{
560 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
561
562 mc->vram_start = base;
563 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
564 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
565 mc->real_vram_size = mc->aper_size;
566 mc->mc_vram_size = mc->aper_size;
567 }
568 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
569 if (limit && limit < mc->real_vram_size)
570 mc->real_vram_size = limit;
571 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
572 mc->mc_vram_size >> 20, mc->vram_start,
573 mc->vram_end, mc->real_vram_size >> 20);
574}
575
576/**
577 * amdgpu_gtt_location - try to find GTT location
578 * @adev: amdgpu device structure holding all necessary informations
579 * @mc: memory controller structure holding memory informations
580 *
581 * Function will place try to place GTT before or after VRAM.
582 *
583 * If GTT size is bigger than space left then we ajust GTT size.
584 * Thus function will never fails.
585 *
586 * FIXME: when reducing GTT size align new size on power of 2.
587 */
588void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
589{
590 u64 size_af, size_bf;
591
592 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
593 size_bf = mc->vram_start & ~mc->gtt_base_align;
594 if (size_bf > size_af) {
595 if (mc->gtt_size > size_bf) {
596 dev_warn(adev->dev, "limiting GTT\n");
597 mc->gtt_size = size_bf;
598 }
599 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
600 } else {
601 if (mc->gtt_size > size_af) {
602 dev_warn(adev->dev, "limiting GTT\n");
603 mc->gtt_size = size_af;
604 }
605 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
606 }
607 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
608 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
609 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
610}
611
612/*
613 * GPU helpers function.
614 */
615/**
616 * amdgpu_card_posted - check if the hw has already been initialized
617 *
618 * @adev: amdgpu_device pointer
619 *
620 * Check if the asic has been initialized (all asics).
621 * Used at driver startup.
622 * Returns true if initialized or false if not.
623 */
624bool amdgpu_card_posted(struct amdgpu_device *adev)
625{
626 uint32_t reg;
627
628 /* then check MEM_SIZE, in case the crtcs are off */
629 reg = RREG32(mmCONFIG_MEMSIZE);
630
631 if (reg)
632 return true;
633
634 return false;
635
636}
637
638/**
639 * amdgpu_dummy_page_init - init dummy page used by the driver
640 *
641 * @adev: amdgpu_device pointer
642 *
643 * Allocate the dummy page used by the driver (all asics).
644 * This dummy page is used by the driver as a filler for gart entries
645 * when pages are taken out of the GART
646 * Returns 0 on sucess, -ENOMEM on failure.
647 */
648int amdgpu_dummy_page_init(struct amdgpu_device *adev)
649{
650 if (adev->dummy_page.page)
651 return 0;
652 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
653 if (adev->dummy_page.page == NULL)
654 return -ENOMEM;
655 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
656 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
657 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
658 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
659 __free_page(adev->dummy_page.page);
660 adev->dummy_page.page = NULL;
661 return -ENOMEM;
662 }
663 return 0;
664}
665
666/**
667 * amdgpu_dummy_page_fini - free dummy page used by the driver
668 *
669 * @adev: amdgpu_device pointer
670 *
671 * Frees the dummy page used by the driver (all asics).
672 */
673void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
674{
675 if (adev->dummy_page.page == NULL)
676 return;
677 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
678 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
679 __free_page(adev->dummy_page.page);
680 adev->dummy_page.page = NULL;
681}
682
683
684/* ATOM accessor methods */
685/*
686 * ATOM is an interpreted byte code stored in tables in the vbios. The
687 * driver registers callbacks to access registers and the interpreter
688 * in the driver parses the tables and executes then to program specific
689 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
690 * atombios.h, and atom.c
691 */
692
693/**
694 * cail_pll_read - read PLL register
695 *
696 * @info: atom card_info pointer
697 * @reg: PLL register offset
698 *
699 * Provides a PLL register accessor for the atom interpreter (r4xx+).
700 * Returns the value of the PLL register.
701 */
702static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
703{
704 return 0;
705}
706
707/**
708 * cail_pll_write - write PLL register
709 *
710 * @info: atom card_info pointer
711 * @reg: PLL register offset
712 * @val: value to write to the pll register
713 *
714 * Provides a PLL register accessor for the atom interpreter (r4xx+).
715 */
716static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
717{
718
719}
720
721/**
722 * cail_mc_read - read MC (Memory Controller) register
723 *
724 * @info: atom card_info pointer
725 * @reg: MC register offset
726 *
727 * Provides an MC register accessor for the atom interpreter (r4xx+).
728 * Returns the value of the MC register.
729 */
730static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
731{
732 return 0;
733}
734
735/**
736 * cail_mc_write - write MC (Memory Controller) register
737 *
738 * @info: atom card_info pointer
739 * @reg: MC register offset
740 * @val: value to write to the pll register
741 *
742 * Provides a MC register accessor for the atom interpreter (r4xx+).
743 */
744static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
745{
746
747}
748
749/**
750 * cail_reg_write - write MMIO register
751 *
752 * @info: atom card_info pointer
753 * @reg: MMIO register offset
754 * @val: value to write to the pll register
755 *
756 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
757 */
758static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
759{
760 struct amdgpu_device *adev = info->dev->dev_private;
761
762 WREG32(reg, val);
763}
764
765/**
766 * cail_reg_read - read MMIO register
767 *
768 * @info: atom card_info pointer
769 * @reg: MMIO register offset
770 *
771 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
772 * Returns the value of the MMIO register.
773 */
774static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
775{
776 struct amdgpu_device *adev = info->dev->dev_private;
777 uint32_t r;
778
779 r = RREG32(reg);
780 return r;
781}
782
783/**
784 * cail_ioreg_write - write IO register
785 *
786 * @info: atom card_info pointer
787 * @reg: IO register offset
788 * @val: value to write to the pll register
789 *
790 * Provides a IO register accessor for the atom interpreter (r4xx+).
791 */
792static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
793{
794 struct amdgpu_device *adev = info->dev->dev_private;
795
796 WREG32_IO(reg, val);
797}
798
799/**
800 * cail_ioreg_read - read IO register
801 *
802 * @info: atom card_info pointer
803 * @reg: IO register offset
804 *
805 * Provides an IO register accessor for the atom interpreter (r4xx+).
806 * Returns the value of the IO register.
807 */
808static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
809{
810 struct amdgpu_device *adev = info->dev->dev_private;
811 uint32_t r;
812
813 r = RREG32_IO(reg);
814 return r;
815}
816
817/**
818 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
819 *
820 * @adev: amdgpu_device pointer
821 *
822 * Frees the driver info and register access callbacks for the ATOM
823 * interpreter (r4xx+).
824 * Called at driver shutdown.
825 */
826static void amdgpu_atombios_fini(struct amdgpu_device *adev)
827{
828 if (adev->mode_info.atom_context)
829 kfree(adev->mode_info.atom_context->scratch);
830 kfree(adev->mode_info.atom_context);
831 adev->mode_info.atom_context = NULL;
832 kfree(adev->mode_info.atom_card_info);
833 adev->mode_info.atom_card_info = NULL;
834}
835
836/**
837 * amdgpu_atombios_init - init the driver info and callbacks for atombios
838 *
839 * @adev: amdgpu_device pointer
840 *
841 * Initializes the driver info and register access callbacks for the
842 * ATOM interpreter (r4xx+).
843 * Returns 0 on sucess, -ENOMEM on failure.
844 * Called at driver startup.
845 */
846static int amdgpu_atombios_init(struct amdgpu_device *adev)
847{
848 struct card_info *atom_card_info =
849 kzalloc(sizeof(struct card_info), GFP_KERNEL);
850
851 if (!atom_card_info)
852 return -ENOMEM;
853
854 adev->mode_info.atom_card_info = atom_card_info;
855 atom_card_info->dev = adev->ddev;
856 atom_card_info->reg_read = cail_reg_read;
857 atom_card_info->reg_write = cail_reg_write;
858 /* needed for iio ops */
859 if (adev->rio_mem) {
860 atom_card_info->ioreg_read = cail_ioreg_read;
861 atom_card_info->ioreg_write = cail_ioreg_write;
862 } else {
863 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
864 atom_card_info->ioreg_read = cail_reg_read;
865 atom_card_info->ioreg_write = cail_reg_write;
866 }
867 atom_card_info->mc_read = cail_mc_read;
868 atom_card_info->mc_write = cail_mc_write;
869 atom_card_info->pll_read = cail_pll_read;
870 atom_card_info->pll_write = cail_pll_write;
871
872 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
873 if (!adev->mode_info.atom_context) {
874 amdgpu_atombios_fini(adev);
875 return -ENOMEM;
876 }
877
878 mutex_init(&adev->mode_info.atom_context->mutex);
879 amdgpu_atombios_scratch_regs_init(adev);
880 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
881 return 0;
882}
883
884/* if we get transitioned to only one device, take VGA back */
885/**
886 * amdgpu_vga_set_decode - enable/disable vga decode
887 *
888 * @cookie: amdgpu_device pointer
889 * @state: enable/disable vga decode
890 *
891 * Enable/disable vga decode (all asics).
892 * Returns VGA resource flags.
893 */
894static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
895{
896 struct amdgpu_device *adev = cookie;
897 amdgpu_asic_set_vga_state(adev, state);
898 if (state)
899 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
900 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
901 else
902 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
903}
904
905/**
906 * amdgpu_check_pot_argument - check that argument is a power of two
907 *
908 * @arg: value to check
909 *
910 * Validates that a certain argument is a power of two (all asics).
911 * Returns true if argument is valid.
912 */
913static bool amdgpu_check_pot_argument(int arg)
914{
915 return (arg & (arg - 1)) == 0;
916}
917
918/**
919 * amdgpu_check_arguments - validate module params
920 *
921 * @adev: amdgpu_device pointer
922 *
923 * Validates certain module parameters and updates
924 * the associated values used by the driver (all asics).
925 */
926static void amdgpu_check_arguments(struct amdgpu_device *adev)
927{
928 if (amdgpu_sched_jobs < 4) {
929 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
930 amdgpu_sched_jobs);
931 amdgpu_sched_jobs = 4;
932 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
933 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
934 amdgpu_sched_jobs);
935 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
936 }
937
938 if (amdgpu_gart_size != -1) {
939 /* gtt size must be power of two and greater or equal to 32M */
940 if (amdgpu_gart_size < 32) {
941 dev_warn(adev->dev, "gart size (%d) too small\n",
942 amdgpu_gart_size);
943 amdgpu_gart_size = -1;
944 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
945 dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
946 amdgpu_gart_size);
947 amdgpu_gart_size = -1;
948 }
949 }
950
951 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
952 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
953 amdgpu_vm_size);
954 amdgpu_vm_size = 8;
955 }
956
957 if (amdgpu_vm_size < 1) {
958 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
959 amdgpu_vm_size);
960 amdgpu_vm_size = 8;
961 }
962
963 /*
964 * Max GPUVM size for Cayman, SI and CI are 40 bits.
965 */
966 if (amdgpu_vm_size > 1024) {
967 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
968 amdgpu_vm_size);
969 amdgpu_vm_size = 8;
970 }
971
972 /* defines number of bits in page table versus page directory,
973 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
974 * page table and the remaining bits are in the page directory */
975 if (amdgpu_vm_block_size == -1) {
976
977 /* Total bits covered by PD + PTs */
978 unsigned bits = ilog2(amdgpu_vm_size) + 18;
979
980 /* Make sure the PD is 4K in size up to 8GB address space.
981 Above that split equal between PD and PTs */
982 if (amdgpu_vm_size <= 8)
983 amdgpu_vm_block_size = bits - 9;
984 else
985 amdgpu_vm_block_size = (bits + 3) / 2;
986
987 } else if (amdgpu_vm_block_size < 9) {
988 dev_warn(adev->dev, "VM page table size (%d) too small\n",
989 amdgpu_vm_block_size);
990 amdgpu_vm_block_size = 9;
991 }
992
993 if (amdgpu_vm_block_size > 24 ||
994 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
995 dev_warn(adev->dev, "VM page table size (%d) too large\n",
996 amdgpu_vm_block_size);
997 amdgpu_vm_block_size = 9;
998 }
999}
1000
1001/**
1002 * amdgpu_switcheroo_set_state - set switcheroo state
1003 *
1004 * @pdev: pci dev pointer
1005 * @state: vga_switcheroo state
1006 *
1007 * Callback for the switcheroo driver. Suspends or resumes the
1008 * the asics before or after it is powered up using ACPI methods.
1009 */
1010static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1011{
1012 struct drm_device *dev = pci_get_drvdata(pdev);
1013
1014 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1015 return;
1016
1017 if (state == VGA_SWITCHEROO_ON) {
1018 unsigned d3_delay = dev->pdev->d3_delay;
1019
1020 printk(KERN_INFO "amdgpu: switched on\n");
1021 /* don't suspend or resume card normally */
1022 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1023
1024 amdgpu_resume_kms(dev, true, true);
1025
1026 dev->pdev->d3_delay = d3_delay;
1027
1028 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1029 drm_kms_helper_poll_enable(dev);
1030 } else {
1031 printk(KERN_INFO "amdgpu: switched off\n");
1032 drm_kms_helper_poll_disable(dev);
1033 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1034 amdgpu_suspend_kms(dev, true, true);
1035 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1036 }
1037}
1038
1039/**
1040 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1041 *
1042 * @pdev: pci dev pointer
1043 *
1044 * Callback for the switcheroo driver. Check of the switcheroo
1045 * state can be changed.
1046 * Returns true if the state can be changed, false if not.
1047 */
1048static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1049{
1050 struct drm_device *dev = pci_get_drvdata(pdev);
1051
1052 /*
1053 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1054 * locking inversion with the driver load path. And the access here is
1055 * completely racy anyway. So don't bother with locking for now.
1056 */
1057 return dev->open_count == 0;
1058}
1059
1060static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1061 .set_gpu_state = amdgpu_switcheroo_set_state,
1062 .reprobe = NULL,
1063 .can_switch = amdgpu_switcheroo_can_switch,
1064};
1065
1066int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1067 enum amd_ip_block_type block_type,
1068 enum amd_clockgating_state state)
1069{
1070 int i, r = 0;
1071
1072 for (i = 0; i < adev->num_ip_blocks; i++) {
1073 if (adev->ip_blocks[i].type == block_type) {
1074 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1075 state);
1076 if (r)
1077 return r;
1078 }
1079 }
1080 return r;
1081}
1082
1083int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1084 enum amd_ip_block_type block_type,
1085 enum amd_powergating_state state)
1086{
1087 int i, r = 0;
1088
1089 for (i = 0; i < adev->num_ip_blocks; i++) {
1090 if (adev->ip_blocks[i].type == block_type) {
1091 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1092 state);
1093 if (r)
1094 return r;
1095 }
1096 }
1097 return r;
1098}
1099
1100const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1101 struct amdgpu_device *adev,
1102 enum amd_ip_block_type type)
1103{
1104 int i;
1105
1106 for (i = 0; i < adev->num_ip_blocks; i++)
1107 if (adev->ip_blocks[i].type == type)
1108 return &adev->ip_blocks[i];
1109
1110 return NULL;
1111}
1112
1113/**
1114 * amdgpu_ip_block_version_cmp
1115 *
1116 * @adev: amdgpu_device pointer
1117 * @type: enum amd_ip_block_type
1118 * @major: major version
1119 * @minor: minor version
1120 *
1121 * return 0 if equal or greater
1122 * return 1 if smaller or the ip_block doesn't exist
1123 */
1124int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1125 enum amd_ip_block_type type,
1126 u32 major, u32 minor)
1127{
1128 const struct amdgpu_ip_block_version *ip_block;
1129 ip_block = amdgpu_get_ip_block(adev, type);
1130
1131 if (ip_block && ((ip_block->major > major) ||
1132 ((ip_block->major == major) &&
1133 (ip_block->minor >= minor))))
1134 return 0;
1135
1136 return 1;
1137}
1138
1139static int amdgpu_early_init(struct amdgpu_device *adev)
1140{
1141 int i, r;
1142
1143 switch (adev->asic_type) {
1144 case CHIP_TOPAZ:
1145 case CHIP_TONGA:
1146 case CHIP_FIJI:
1147 case CHIP_CARRIZO:
1148 case CHIP_STONEY:
1149 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1150 adev->family = AMDGPU_FAMILY_CZ;
1151 else
1152 adev->family = AMDGPU_FAMILY_VI;
1153
1154 r = vi_set_ip_blocks(adev);
1155 if (r)
1156 return r;
1157 break;
1158#ifdef CONFIG_DRM_AMDGPU_CIK
1159 case CHIP_BONAIRE:
1160 case CHIP_HAWAII:
1161 case CHIP_KAVERI:
1162 case CHIP_KABINI:
1163 case CHIP_MULLINS:
1164 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1165 adev->family = AMDGPU_FAMILY_CI;
1166 else
1167 adev->family = AMDGPU_FAMILY_KV;
1168
1169 r = cik_set_ip_blocks(adev);
1170 if (r)
1171 return r;
1172 break;
1173#endif
1174 default:
1175 /* FIXME: not supported yet */
1176 return -EINVAL;
1177 }
1178
1179 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1180 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1181 if (adev->ip_block_status == NULL)
1182 return -ENOMEM;
1183
1184 if (adev->ip_blocks == NULL) {
1185 DRM_ERROR("No IP blocks found!\n");
1186 return r;
1187 }
1188
1189 for (i = 0; i < adev->num_ip_blocks; i++) {
1190 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1191 DRM_ERROR("disabled ip block: %d\n", i);
1192 adev->ip_block_status[i].valid = false;
1193 } else {
1194 if (adev->ip_blocks[i].funcs->early_init) {
1195 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1196 if (r == -ENOENT) {
1197 adev->ip_block_status[i].valid = false;
1198 } else if (r) {
1199 DRM_ERROR("early_init %d failed %d\n", i, r);
1200 return r;
1201 } else {
1202 adev->ip_block_status[i].valid = true;
1203 }
1204 } else {
1205 adev->ip_block_status[i].valid = true;
1206 }
1207 }
1208 }
1209
1210 return 0;
1211}
1212
1213static int amdgpu_init(struct amdgpu_device *adev)
1214{
1215 int i, r;
1216
1217 for (i = 0; i < adev->num_ip_blocks; i++) {
1218 if (!adev->ip_block_status[i].valid)
1219 continue;
1220 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1221 if (r) {
1222 DRM_ERROR("sw_init %d failed %d\n", i, r);
1223 return r;
1224 }
1225 adev->ip_block_status[i].sw = true;
1226 /* need to do gmc hw init early so we can allocate gpu mem */
1227 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1228 r = amdgpu_vram_scratch_init(adev);
1229 if (r) {
1230 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1231 return r;
1232 }
1233 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1234 if (r) {
1235 DRM_ERROR("hw_init %d failed %d\n", i, r);
1236 return r;
1237 }
1238 r = amdgpu_wb_init(adev);
1239 if (r) {
1240 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1241 return r;
1242 }
1243 adev->ip_block_status[i].hw = true;
1244 }
1245 }
1246
1247 for (i = 0; i < adev->num_ip_blocks; i++) {
1248 if (!adev->ip_block_status[i].sw)
1249 continue;
1250 /* gmc hw init is done early */
1251 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1252 continue;
1253 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1254 if (r) {
1255 DRM_ERROR("hw_init %d failed %d\n", i, r);
1256 return r;
1257 }
1258 adev->ip_block_status[i].hw = true;
1259 }
1260
1261 return 0;
1262}
1263
1264static int amdgpu_late_init(struct amdgpu_device *adev)
1265{
1266 int i = 0, r;
1267
1268 for (i = 0; i < adev->num_ip_blocks; i++) {
1269 if (!adev->ip_block_status[i].valid)
1270 continue;
1271 /* enable clockgating to save power */
1272 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1273 AMD_CG_STATE_GATE);
1274 if (r) {
1275 DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
1276 return r;
1277 }
1278 if (adev->ip_blocks[i].funcs->late_init) {
1279 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1280 if (r) {
1281 DRM_ERROR("late_init %d failed %d\n", i, r);
1282 return r;
1283 }
1284 }
1285 }
1286
1287 return 0;
1288}
1289
1290static int amdgpu_fini(struct amdgpu_device *adev)
1291{
1292 int i, r;
1293
1294 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1295 if (!adev->ip_block_status[i].hw)
1296 continue;
1297 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1298 amdgpu_wb_fini(adev);
1299 amdgpu_vram_scratch_fini(adev);
1300 }
1301 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1302 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1303 AMD_CG_STATE_UNGATE);
1304 if (r) {
1305 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1306 return r;
1307 }
1308 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1309 /* XXX handle errors */
1310 if (r) {
1311 DRM_DEBUG("hw_fini %d failed %d\n", i, r);
1312 }
1313 adev->ip_block_status[i].hw = false;
1314 }
1315
1316 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1317 if (!adev->ip_block_status[i].sw)
1318 continue;
1319 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1320 /* XXX handle errors */
1321 if (r) {
1322 DRM_DEBUG("sw_fini %d failed %d\n", i, r);
1323 }
1324 adev->ip_block_status[i].sw = false;
1325 adev->ip_block_status[i].valid = false;
1326 }
1327
1328 return 0;
1329}
1330
1331static int amdgpu_suspend(struct amdgpu_device *adev)
1332{
1333 int i, r;
1334
1335 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1336 if (!adev->ip_block_status[i].valid)
1337 continue;
1338 /* ungate blocks so that suspend can properly shut them down */
1339 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1340 AMD_CG_STATE_UNGATE);
1341 if (r) {
1342 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1343 }
1344 /* XXX handle errors */
1345 r = adev->ip_blocks[i].funcs->suspend(adev);
1346 /* XXX handle errors */
1347 if (r) {
1348 DRM_ERROR("suspend %d failed %d\n", i, r);
1349 }
1350 }
1351
1352 return 0;
1353}
1354
1355static int amdgpu_resume(struct amdgpu_device *adev)
1356{
1357 int i, r;
1358
1359 for (i = 0; i < adev->num_ip_blocks; i++) {
1360 if (!adev->ip_block_status[i].valid)
1361 continue;
1362 r = adev->ip_blocks[i].funcs->resume(adev);
1363 if (r) {
1364 DRM_ERROR("resume %d failed %d\n", i, r);
1365 return r;
1366 }
1367 }
1368
1369 return 0;
1370}
1371
1372/**
1373 * amdgpu_device_init - initialize the driver
1374 *
1375 * @adev: amdgpu_device pointer
1376 * @pdev: drm dev pointer
1377 * @pdev: pci dev pointer
1378 * @flags: driver flags
1379 *
1380 * Initializes the driver info and hw (all asics).
1381 * Returns 0 for success or an error on failure.
1382 * Called at driver startup.
1383 */
1384int amdgpu_device_init(struct amdgpu_device *adev,
1385 struct drm_device *ddev,
1386 struct pci_dev *pdev,
1387 uint32_t flags)
1388{
1389 int r, i;
1390 bool runtime = false;
1391
1392 adev->shutdown = false;
1393 adev->dev = &pdev->dev;
1394 adev->ddev = ddev;
1395 adev->pdev = pdev;
1396 adev->flags = flags;
1397 adev->asic_type = flags & AMD_ASIC_MASK;
1398 adev->is_atom_bios = false;
1399 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1400 adev->mc.gtt_size = 512 * 1024 * 1024;
1401 adev->accel_working = false;
1402 adev->num_rings = 0;
1403 adev->mman.buffer_funcs = NULL;
1404 adev->mman.buffer_funcs_ring = NULL;
1405 adev->vm_manager.vm_pte_funcs = NULL;
1406 adev->vm_manager.vm_pte_num_rings = 0;
1407 adev->gart.gart_funcs = NULL;
1408 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1409
1410 adev->smc_rreg = &amdgpu_invalid_rreg;
1411 adev->smc_wreg = &amdgpu_invalid_wreg;
1412 adev->pcie_rreg = &amdgpu_invalid_rreg;
1413 adev->pcie_wreg = &amdgpu_invalid_wreg;
1414 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1415 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1416 adev->didt_rreg = &amdgpu_invalid_rreg;
1417 adev->didt_wreg = &amdgpu_invalid_wreg;
1418 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1419 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1420
1421 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1422 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1423 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1424
1425 /* mutex initialization are all done here so we
1426 * can recall function without having locking issues */
1427 mutex_init(&adev->vm_manager.lock);
1428 atomic_set(&adev->irq.ih.lock, 0);
1429 mutex_init(&adev->pm.mutex);
1430 mutex_init(&adev->gfx.gpu_clock_mutex);
1431 mutex_init(&adev->srbm_mutex);
1432 mutex_init(&adev->grbm_idx_mutex);
1433 mutex_init(&adev->mn_lock);
1434 hash_init(adev->mn_hash);
1435
1436 amdgpu_check_arguments(adev);
1437
1438 /* Registers mapping */
1439 /* TODO: block userspace mapping of io register */
1440 spin_lock_init(&adev->mmio_idx_lock);
1441 spin_lock_init(&adev->smc_idx_lock);
1442 spin_lock_init(&adev->pcie_idx_lock);
1443 spin_lock_init(&adev->uvd_ctx_idx_lock);
1444 spin_lock_init(&adev->didt_idx_lock);
1445 spin_lock_init(&adev->audio_endpt_idx_lock);
1446
1447 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1448 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1449 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1450 if (adev->rmmio == NULL) {
1451 return -ENOMEM;
1452 }
1453 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1454 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1455
1456 /* doorbell bar mapping */
1457 amdgpu_doorbell_init(adev);
1458
1459 /* io port mapping */
1460 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1461 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1462 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1463 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1464 break;
1465 }
1466 }
1467 if (adev->rio_mem == NULL)
1468 DRM_ERROR("Unable to find PCI I/O BAR\n");
1469
1470 /* early init functions */
1471 r = amdgpu_early_init(adev);
1472 if (r)
1473 return r;
1474
1475 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1476 /* this will fail for cards that aren't VGA class devices, just
1477 * ignore it */
1478 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1479
1480 if (amdgpu_runtime_pm == 1)
1481 runtime = true;
1482 if (amdgpu_device_is_px(ddev))
1483 runtime = true;
1484 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1485 if (runtime)
1486 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1487
1488 /* Read BIOS */
1489 if (!amdgpu_get_bios(adev))
1490 return -EINVAL;
1491 /* Must be an ATOMBIOS */
1492 if (!adev->is_atom_bios) {
1493 dev_err(adev->dev, "Expecting atombios for GPU\n");
1494 return -EINVAL;
1495 }
1496 r = amdgpu_atombios_init(adev);
1497 if (r) {
1498 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1499 return r;
1500 }
1501
1502 /* See if the asic supports SR-IOV */
1503 adev->virtualization.supports_sr_iov =
1504 amdgpu_atombios_has_gpu_virtualization_table(adev);
1505
1506 /* Post card if necessary */
1507 if (!amdgpu_card_posted(adev) ||
1508 adev->virtualization.supports_sr_iov) {
1509 if (!adev->bios) {
1510 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1511 return -EINVAL;
1512 }
1513 DRM_INFO("GPU not posted. posting now...\n");
1514 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1515 }
1516
1517 /* Initialize clocks */
1518 r = amdgpu_atombios_get_clock_info(adev);
1519 if (r) {
1520 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1521 return r;
1522 }
1523 /* init i2c buses */
1524 amdgpu_atombios_i2c_init(adev);
1525
1526 /* Fence driver */
1527 r = amdgpu_fence_driver_init(adev);
1528 if (r) {
1529 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1530 return r;
1531 }
1532
1533 /* init the mode config */
1534 drm_mode_config_init(adev->ddev);
1535
1536 r = amdgpu_init(adev);
1537 if (r) {
1538 dev_err(adev->dev, "amdgpu_init failed\n");
1539 amdgpu_fini(adev);
1540 return r;
1541 }
1542
1543 adev->accel_working = true;
1544
1545 amdgpu_fbdev_init(adev);
1546
1547 r = amdgpu_ib_pool_init(adev);
1548 if (r) {
1549 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1550 return r;
1551 }
1552
1553 r = amdgpu_ib_ring_tests(adev);
1554 if (r)
1555 DRM_ERROR("ib ring test failed (%d).\n", r);
1556
1557 r = amdgpu_gem_debugfs_init(adev);
1558 if (r) {
1559 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1560 }
1561
1562 r = amdgpu_debugfs_regs_init(adev);
1563 if (r) {
1564 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1565 }
1566
1567 if ((amdgpu_testing & 1)) {
1568 if (adev->accel_working)
1569 amdgpu_test_moves(adev);
1570 else
1571 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1572 }
1573 if ((amdgpu_testing & 2)) {
1574 if (adev->accel_working)
1575 amdgpu_test_syncing(adev);
1576 else
1577 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1578 }
1579 if (amdgpu_benchmarking) {
1580 if (adev->accel_working)
1581 amdgpu_benchmark(adev, amdgpu_benchmarking);
1582 else
1583 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1584 }
1585
1586 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1587 * explicit gating rather than handling it automatically.
1588 */
1589 r = amdgpu_late_init(adev);
1590 if (r) {
1591 dev_err(adev->dev, "amdgpu_late_init failed\n");
1592 return r;
1593 }
1594
1595 return 0;
1596}
1597
1598static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1599
1600/**
1601 * amdgpu_device_fini - tear down the driver
1602 *
1603 * @adev: amdgpu_device pointer
1604 *
1605 * Tear down the driver info (all asics).
1606 * Called at driver shutdown.
1607 */
1608void amdgpu_device_fini(struct amdgpu_device *adev)
1609{
1610 int r;
1611
1612 DRM_INFO("amdgpu: finishing device.\n");
1613 adev->shutdown = true;
1614 /* evict vram memory */
1615 amdgpu_bo_evict_vram(adev);
1616 amdgpu_ib_pool_fini(adev);
1617 amdgpu_fence_driver_fini(adev);
1618 amdgpu_fbdev_fini(adev);
1619 r = amdgpu_fini(adev);
1620 kfree(adev->ip_block_status);
1621 adev->ip_block_status = NULL;
1622 adev->accel_working = false;
1623 /* free i2c buses */
1624 amdgpu_i2c_fini(adev);
1625 amdgpu_atombios_fini(adev);
1626 kfree(adev->bios);
1627 adev->bios = NULL;
1628 vga_switcheroo_unregister_client(adev->pdev);
1629 vga_client_register(adev->pdev, NULL, NULL, NULL);
1630 if (adev->rio_mem)
1631 pci_iounmap(adev->pdev, adev->rio_mem);
1632 adev->rio_mem = NULL;
1633 iounmap(adev->rmmio);
1634 adev->rmmio = NULL;
1635 amdgpu_doorbell_fini(adev);
1636 amdgpu_debugfs_regs_cleanup(adev);
1637 amdgpu_debugfs_remove_files(adev);
1638}
1639
1640
1641/*
1642 * Suspend & resume.
1643 */
1644/**
1645 * amdgpu_suspend_kms - initiate device suspend
1646 *
1647 * @pdev: drm dev pointer
1648 * @state: suspend state
1649 *
1650 * Puts the hw in the suspend state (all asics).
1651 * Returns 0 for success or an error on failure.
1652 * Called at driver suspend.
1653 */
1654int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1655{
1656 struct amdgpu_device *adev;
1657 struct drm_crtc *crtc;
1658 struct drm_connector *connector;
1659 int r;
1660
1661 if (dev == NULL || dev->dev_private == NULL) {
1662 return -ENODEV;
1663 }
1664
1665 adev = dev->dev_private;
1666
1667 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1668 return 0;
1669
1670 drm_kms_helper_poll_disable(dev);
1671
1672 /* turn off display hw */
1673 drm_modeset_lock_all(dev);
1674 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1675 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1676 }
1677 drm_modeset_unlock_all(dev);
1678
1679 /* unpin the front buffers and cursors */
1680 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1682 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1683 struct amdgpu_bo *robj;
1684
1685 if (amdgpu_crtc->cursor_bo) {
1686 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1687 r = amdgpu_bo_reserve(aobj, false);
1688 if (r == 0) {
1689 amdgpu_bo_unpin(aobj);
1690 amdgpu_bo_unreserve(aobj);
1691 }
1692 }
1693
1694 if (rfb == NULL || rfb->obj == NULL) {
1695 continue;
1696 }
1697 robj = gem_to_amdgpu_bo(rfb->obj);
1698 /* don't unpin kernel fb objects */
1699 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1700 r = amdgpu_bo_reserve(robj, false);
1701 if (r == 0) {
1702 amdgpu_bo_unpin(robj);
1703 amdgpu_bo_unreserve(robj);
1704 }
1705 }
1706 }
1707 /* evict vram memory */
1708 amdgpu_bo_evict_vram(adev);
1709
1710 amdgpu_fence_driver_suspend(adev);
1711
1712 r = amdgpu_suspend(adev);
1713
1714 /* evict remaining vram memory */
1715 amdgpu_bo_evict_vram(adev);
1716
1717 pci_save_state(dev->pdev);
1718 if (suspend) {
1719 /* Shut down the device */
1720 pci_disable_device(dev->pdev);
1721 pci_set_power_state(dev->pdev, PCI_D3hot);
1722 }
1723
1724 if (fbcon) {
1725 console_lock();
1726 amdgpu_fbdev_set_suspend(adev, 1);
1727 console_unlock();
1728 }
1729 return 0;
1730}
1731
1732/**
1733 * amdgpu_resume_kms - initiate device resume
1734 *
1735 * @pdev: drm dev pointer
1736 *
1737 * Bring the hw back to operating state (all asics).
1738 * Returns 0 for success or an error on failure.
1739 * Called at driver resume.
1740 */
1741int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1742{
1743 struct drm_connector *connector;
1744 struct amdgpu_device *adev = dev->dev_private;
1745 struct drm_crtc *crtc;
1746 int r;
1747
1748 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1749 return 0;
1750
1751 if (fbcon) {
1752 console_lock();
1753 }
1754 if (resume) {
1755 pci_set_power_state(dev->pdev, PCI_D0);
1756 pci_restore_state(dev->pdev);
1757 if (pci_enable_device(dev->pdev)) {
1758 if (fbcon)
1759 console_unlock();
1760 return -1;
1761 }
1762 }
1763
1764 /* post card */
1765 if (!amdgpu_card_posted(adev))
1766 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1767
1768 r = amdgpu_resume(adev);
1769 if (r)
1770 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1771
1772 amdgpu_fence_driver_resume(adev);
1773
1774 if (resume) {
1775 r = amdgpu_ib_ring_tests(adev);
1776 if (r)
1777 DRM_ERROR("ib ring test failed (%d).\n", r);
1778 }
1779
1780 r = amdgpu_late_init(adev);
1781 if (r)
1782 return r;
1783
1784 /* pin cursors */
1785 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1786 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1787
1788 if (amdgpu_crtc->cursor_bo) {
1789 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1790 r = amdgpu_bo_reserve(aobj, false);
1791 if (r == 0) {
1792 r = amdgpu_bo_pin(aobj,
1793 AMDGPU_GEM_DOMAIN_VRAM,
1794 &amdgpu_crtc->cursor_addr);
1795 if (r != 0)
1796 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1797 amdgpu_bo_unreserve(aobj);
1798 }
1799 }
1800 }
1801
1802 /* blat the mode back in */
1803 if (fbcon) {
1804 drm_helper_resume_force_mode(dev);
1805 /* turn on display hw */
1806 drm_modeset_lock_all(dev);
1807 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1808 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1809 }
1810 drm_modeset_unlock_all(dev);
1811 }
1812
1813 drm_kms_helper_poll_enable(dev);
1814 drm_helper_hpd_irq_event(dev);
1815
1816 if (fbcon) {
1817 amdgpu_fbdev_set_suspend(adev, 0);
1818 console_unlock();
1819 }
1820
1821 return 0;
1822}
1823
1824/**
1825 * amdgpu_gpu_reset - reset the asic
1826 *
1827 * @adev: amdgpu device pointer
1828 *
1829 * Attempt the reset the GPU if it has hung (all asics).
1830 * Returns 0 for success or an error on failure.
1831 */
1832int amdgpu_gpu_reset(struct amdgpu_device *adev)
1833{
1834 unsigned ring_sizes[AMDGPU_MAX_RINGS];
1835 uint32_t *ring_data[AMDGPU_MAX_RINGS];
1836
1837 bool saved = false;
1838
1839 int i, r;
1840 int resched;
1841
1842 atomic_inc(&adev->gpu_reset_counter);
1843
1844 /* block TTM */
1845 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1846
1847 r = amdgpu_suspend(adev);
1848
1849 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1850 struct amdgpu_ring *ring = adev->rings[i];
1851 if (!ring)
1852 continue;
1853
1854 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1855 if (ring_sizes[i]) {
1856 saved = true;
1857 dev_info(adev->dev, "Saved %d dwords of commands "
1858 "on ring %d.\n", ring_sizes[i], i);
1859 }
1860 }
1861
1862retry:
1863 r = amdgpu_asic_reset(adev);
1864 /* post card */
1865 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1866
1867 if (!r) {
1868 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1869 r = amdgpu_resume(adev);
1870 }
1871
1872 if (!r) {
1873 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1874 struct amdgpu_ring *ring = adev->rings[i];
1875 if (!ring)
1876 continue;
1877
1878 amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1879 ring_sizes[i] = 0;
1880 ring_data[i] = NULL;
1881 }
1882
1883 r = amdgpu_ib_ring_tests(adev);
1884 if (r) {
1885 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1886 if (saved) {
1887 saved = false;
1888 r = amdgpu_suspend(adev);
1889 goto retry;
1890 }
1891 }
1892 } else {
1893 amdgpu_fence_driver_force_completion(adev);
1894 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1895 if (adev->rings[i])
1896 kfree(ring_data[i]);
1897 }
1898 }
1899
1900 drm_helper_resume_force_mode(adev->ddev);
1901
1902 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1903 if (r) {
1904 /* bad news, how to tell it to userspace ? */
1905 dev_info(adev->dev, "GPU reset failed\n");
1906 }
1907
1908 return r;
1909}
1910
1911#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
1912#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1913
1914void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1915{
1916 u32 mask;
1917 int ret;
1918
1919 if (amdgpu_pcie_gen_cap)
1920 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1921
1922 if (amdgpu_pcie_lane_cap)
1923 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1924
1925 /* covers APUs as well */
1926 if (pci_is_root_bus(adev->pdev->bus)) {
1927 if (adev->pm.pcie_gen_mask == 0)
1928 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1929 if (adev->pm.pcie_mlw_mask == 0)
1930 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1931 return;
1932 }
1933
1934 if (adev->pm.pcie_gen_mask == 0) {
1935 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1936 if (!ret) {
1937 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1938 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1939 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1940
1941 if (mask & DRM_PCIE_SPEED_25)
1942 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1943 if (mask & DRM_PCIE_SPEED_50)
1944 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1945 if (mask & DRM_PCIE_SPEED_80)
1946 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1947 } else {
1948 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1949 }
1950 }
1951 if (adev->pm.pcie_mlw_mask == 0) {
1952 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1953 if (!ret) {
1954 switch (mask) {
1955 case 32:
1956 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1957 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1958 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1959 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1960 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1961 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1962 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1963 break;
1964 case 16:
1965 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1966 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1967 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1971 break;
1972 case 12:
1973 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1974 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1975 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1976 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1977 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1978 break;
1979 case 8:
1980 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1982 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1983 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1984 break;
1985 case 4:
1986 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1989 break;
1990 case 2:
1991 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1993 break;
1994 case 1:
1995 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
1996 break;
1997 default:
1998 break;
1999 }
2000 } else {
2001 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2002 }
2003 }
2004}
2005
2006/*
2007 * Debugfs
2008 */
2009int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2010 struct drm_info_list *files,
2011 unsigned nfiles)
2012{
2013 unsigned i;
2014
2015 for (i = 0; i < adev->debugfs_count; i++) {
2016 if (adev->debugfs[i].files == files) {
2017 /* Already registered */
2018 return 0;
2019 }
2020 }
2021
2022 i = adev->debugfs_count + 1;
2023 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2024 DRM_ERROR("Reached maximum number of debugfs components.\n");
2025 DRM_ERROR("Report so we increase "
2026 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2027 return -EINVAL;
2028 }
2029 adev->debugfs[adev->debugfs_count].files = files;
2030 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2031 adev->debugfs_count = i;
2032#if defined(CONFIG_DEBUG_FS)
2033 drm_debugfs_create_files(files, nfiles,
2034 adev->ddev->control->debugfs_root,
2035 adev->ddev->control);
2036 drm_debugfs_create_files(files, nfiles,
2037 adev->ddev->primary->debugfs_root,
2038 adev->ddev->primary);
2039#endif
2040 return 0;
2041}
2042
2043static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2044{
2045#if defined(CONFIG_DEBUG_FS)
2046 unsigned i;
2047
2048 for (i = 0; i < adev->debugfs_count; i++) {
2049 drm_debugfs_remove_files(adev->debugfs[i].files,
2050 adev->debugfs[i].num_files,
2051 adev->ddev->control);
2052 drm_debugfs_remove_files(adev->debugfs[i].files,
2053 adev->debugfs[i].num_files,
2054 adev->ddev->primary);
2055 }
2056#endif
2057}
2058
2059#if defined(CONFIG_DEBUG_FS)
2060
2061static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2062 size_t size, loff_t *pos)
2063{
2064 struct amdgpu_device *adev = f->f_inode->i_private;
2065 ssize_t result = 0;
2066 int r;
2067
2068 if (size & 0x3 || *pos & 0x3)
2069 return -EINVAL;
2070
2071 while (size) {
2072 uint32_t value;
2073
2074 if (*pos > adev->rmmio_size)
2075 return result;
2076
2077 value = RREG32(*pos >> 2);
2078 r = put_user(value, (uint32_t *)buf);
2079 if (r)
2080 return r;
2081
2082 result += 4;
2083 buf += 4;
2084 *pos += 4;
2085 size -= 4;
2086 }
2087
2088 return result;
2089}
2090
2091static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2092 size_t size, loff_t *pos)
2093{
2094 struct amdgpu_device *adev = f->f_inode->i_private;
2095 ssize_t result = 0;
2096 int r;
2097
2098 if (size & 0x3 || *pos & 0x3)
2099 return -EINVAL;
2100
2101 while (size) {
2102 uint32_t value;
2103
2104 if (*pos > adev->rmmio_size)
2105 return result;
2106
2107 r = get_user(value, (uint32_t *)buf);
2108 if (r)
2109 return r;
2110
2111 WREG32(*pos >> 2, value);
2112
2113 result += 4;
2114 buf += 4;
2115 *pos += 4;
2116 size -= 4;
2117 }
2118
2119 return result;
2120}
2121
2122static const struct file_operations amdgpu_debugfs_regs_fops = {
2123 .owner = THIS_MODULE,
2124 .read = amdgpu_debugfs_regs_read,
2125 .write = amdgpu_debugfs_regs_write,
2126 .llseek = default_llseek
2127};
2128
2129static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2130{
2131 struct drm_minor *minor = adev->ddev->primary;
2132 struct dentry *ent, *root = minor->debugfs_root;
2133
2134 ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
2135 adev, &amdgpu_debugfs_regs_fops);
2136 if (IS_ERR(ent))
2137 return PTR_ERR(ent);
2138 i_size_write(ent->d_inode, adev->rmmio_size);
2139 adev->debugfs_regs = ent;
2140
2141 return 0;
2142}
2143
2144static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2145{
2146 debugfs_remove(adev->debugfs_regs);
2147 adev->debugfs_regs = NULL;
2148}
2149
2150int amdgpu_debugfs_init(struct drm_minor *minor)
2151{
2152 return 0;
2153}
2154
2155void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2156{
2157}
2158#else
2159static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2160{
2161 return 0;
2162}
2163static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2164#endif