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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * GPIO interface for Intel Sodaville SoCs.
4 *
5 * Copyright (c) 2010, 2011 Intel Corporation
6 *
7 * Author: Hans J. Koch <hjk@linutronix.de>
8 */
9
10#include <linux/errno.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/kernel.h>
17#include <linux/of_irq.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#define DRV_NAME "sdv_gpio"
22#define SDV_NUM_PUB_GPIOS 12
23#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
24#define GPIO_BAR 0
25
26#define GPOUTR 0x00
27#define GPOER 0x04
28#define GPINR 0x08
29
30#define GPSTR 0x0c
31#define GPIT1R0 0x10
32#define GPIO_INT 0x14
33#define GPIT1R1 0x18
34
35#define GPMUXCTL 0x1c
36
37struct sdv_gpio_chip_data {
38 int irq_base;
39 void __iomem *gpio_pub_base;
40 struct irq_domain *id;
41 struct irq_chip_generic *gc;
42 struct gpio_chip chip;
43};
44
45static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
46{
47 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
48 struct sdv_gpio_chip_data *sd = gc->private;
49 void __iomem *type_reg;
50 u32 reg;
51
52 if (d->hwirq < 8)
53 type_reg = sd->gpio_pub_base + GPIT1R0;
54 else
55 type_reg = sd->gpio_pub_base + GPIT1R1;
56
57 reg = readl(type_reg);
58
59 switch (type) {
60 case IRQ_TYPE_LEVEL_HIGH:
61 reg &= ~BIT(4 * (d->hwirq % 8));
62 break;
63
64 case IRQ_TYPE_LEVEL_LOW:
65 reg |= BIT(4 * (d->hwirq % 8));
66 break;
67
68 default:
69 return -EINVAL;
70 }
71
72 writel(reg, type_reg);
73 return 0;
74}
75
76static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
77{
78 struct sdv_gpio_chip_data *sd = data;
79 unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
80 int irq_bit;
81
82 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
83 if (!irq_stat)
84 return IRQ_NONE;
85
86 for_each_set_bit(irq_bit, &irq_stat, 32)
87 generic_handle_domain_irq(sd->id, irq_bit);
88
89 return IRQ_HANDLED;
90}
91
92static int sdv_xlate(struct irq_domain *h, struct device_node *node,
93 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
94 u32 *out_type)
95{
96 u32 line, type;
97
98 if (node != irq_domain_get_of_node(h))
99 return -EINVAL;
100
101 if (intsize < 2)
102 return -EINVAL;
103
104 line = *intspec;
105 *out_hwirq = line;
106
107 intspec++;
108 type = *intspec;
109
110 switch (type) {
111 case IRQ_TYPE_LEVEL_LOW:
112 case IRQ_TYPE_LEVEL_HIGH:
113 *out_type = type;
114 break;
115 default:
116 return -EINVAL;
117 }
118 return 0;
119}
120
121static const struct irq_domain_ops irq_domain_sdv_ops = {
122 .xlate = sdv_xlate,
123};
124
125static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
126 struct pci_dev *pdev)
127{
128 struct irq_chip_type *ct;
129 int ret;
130
131 sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
132 SDV_NUM_PUB_GPIOS, -1);
133 if (sd->irq_base < 0)
134 return sd->irq_base;
135
136 /* mask + ACK all interrupt sources */
137 writel(0, sd->gpio_pub_base + GPIO_INT);
138 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
139
140 ret = devm_request_irq(&pdev->dev, pdev->irq,
141 sdv_gpio_pub_irq_handler, IRQF_SHARED,
142 "sdv_gpio", sd);
143 if (ret)
144 return ret;
145
146 /*
147 * This gpio irq controller latches level irqs. Testing shows that if
148 * we unmask & ACK the IRQ before the source of the interrupt is gone
149 * then the interrupt is active again.
150 */
151 sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
152 sd->irq_base,
153 sd->gpio_pub_base,
154 handle_fasteoi_irq);
155 if (!sd->gc)
156 return -ENOMEM;
157
158 sd->gc->private = sd;
159 ct = sd->gc->chip_types;
160 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
161 ct->regs.eoi = GPSTR;
162 ct->regs.mask = GPIO_INT;
163 ct->chip.irq_mask = irq_gc_mask_clr_bit;
164 ct->chip.irq_unmask = irq_gc_mask_set_bit;
165 ct->chip.irq_eoi = irq_gc_eoi;
166 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
167
168 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
169 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
170 IRQ_LEVEL | IRQ_NOPROBE);
171
172 sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
173 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
174 if (!sd->id)
175 return -ENODEV;
176
177 return 0;
178}
179
180static int sdv_gpio_probe(struct pci_dev *pdev,
181 const struct pci_device_id *pci_id)
182{
183 struct sdv_gpio_chip_data *sd;
184 int ret;
185 u32 mux_val;
186
187 sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
188 if (!sd)
189 return -ENOMEM;
190
191 ret = pcim_enable_device(pdev);
192 if (ret) {
193 dev_err(&pdev->dev, "can't enable device.\n");
194 return ret;
195 }
196
197 ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
198 if (ret) {
199 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
200 return ret;
201 }
202
203 sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
204
205 ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
206 if (!ret)
207 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
208
209 ret = bgpio_init(&sd->chip, &pdev->dev, 4,
210 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
211 NULL, sd->gpio_pub_base + GPOER, NULL, 0);
212 if (ret)
213 return ret;
214
215 sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
216
217 ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
218 if (ret < 0) {
219 dev_err(&pdev->dev, "gpiochip_add() failed.\n");
220 return ret;
221 }
222
223 ret = sdv_register_irqsupport(sd, pdev);
224 if (ret)
225 return ret;
226
227 pci_set_drvdata(pdev, sd);
228 dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
229 return 0;
230}
231
232static const struct pci_device_id sdv_gpio_pci_ids[] = {
233 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
234 { 0, },
235};
236
237static struct pci_driver sdv_gpio_driver = {
238 .driver = {
239 .suppress_bind_attrs = true,
240 },
241 .name = DRV_NAME,
242 .id_table = sdv_gpio_pci_ids,
243 .probe = sdv_gpio_probe,
244};
245builtin_pci_driver(sdv_gpio_driver);
1/*
2 * GPIO interface for Intel Sodaville SoCs.
3 *
4 * Copyright (c) 2010, 2011 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/platform_device.h>
21#include <linux/of_irq.h>
22#include <linux/gpio/driver.h>
23
24#define DRV_NAME "sdv_gpio"
25#define SDV_NUM_PUB_GPIOS 12
26#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
27#define GPIO_BAR 0
28
29#define GPOUTR 0x00
30#define GPOER 0x04
31#define GPINR 0x08
32
33#define GPSTR 0x0c
34#define GPIT1R0 0x10
35#define GPIO_INT 0x14
36#define GPIT1R1 0x18
37
38#define GPMUXCTL 0x1c
39
40struct sdv_gpio_chip_data {
41 int irq_base;
42 void __iomem *gpio_pub_base;
43 struct irq_domain *id;
44 struct irq_chip_generic *gc;
45 struct gpio_chip chip;
46};
47
48static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
49{
50 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
51 struct sdv_gpio_chip_data *sd = gc->private;
52 void __iomem *type_reg;
53 u32 reg;
54
55 if (d->hwirq < 8)
56 type_reg = sd->gpio_pub_base + GPIT1R0;
57 else
58 type_reg = sd->gpio_pub_base + GPIT1R1;
59
60 reg = readl(type_reg);
61
62 switch (type) {
63 case IRQ_TYPE_LEVEL_HIGH:
64 reg &= ~BIT(4 * (d->hwirq % 8));
65 break;
66
67 case IRQ_TYPE_LEVEL_LOW:
68 reg |= BIT(4 * (d->hwirq % 8));
69 break;
70
71 default:
72 return -EINVAL;
73 }
74
75 writel(reg, type_reg);
76 return 0;
77}
78
79static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
80{
81 struct sdv_gpio_chip_data *sd = data;
82 u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
83
84 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
85 if (!irq_stat)
86 return IRQ_NONE;
87
88 while (irq_stat) {
89 u32 irq_bit = __fls(irq_stat);
90
91 irq_stat &= ~BIT(irq_bit);
92 generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
93 }
94
95 return IRQ_HANDLED;
96}
97
98static int sdv_xlate(struct irq_domain *h, struct device_node *node,
99 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
100 u32 *out_type)
101{
102 u32 line, type;
103
104 if (node != irq_domain_get_of_node(h))
105 return -EINVAL;
106
107 if (intsize < 2)
108 return -EINVAL;
109
110 line = *intspec;
111 *out_hwirq = line;
112
113 intspec++;
114 type = *intspec;
115
116 switch (type) {
117 case IRQ_TYPE_LEVEL_LOW:
118 case IRQ_TYPE_LEVEL_HIGH:
119 *out_type = type;
120 break;
121 default:
122 return -EINVAL;
123 }
124 return 0;
125}
126
127static const struct irq_domain_ops irq_domain_sdv_ops = {
128 .xlate = sdv_xlate,
129};
130
131static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
132 struct pci_dev *pdev)
133{
134 struct irq_chip_type *ct;
135 int ret;
136
137 sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
138 if (sd->irq_base < 0)
139 return sd->irq_base;
140
141 /* mask + ACK all interrupt sources */
142 writel(0, sd->gpio_pub_base + GPIO_INT);
143 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
144
145 ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
146 "sdv_gpio", sd);
147 if (ret)
148 goto out_free_desc;
149
150 /*
151 * This gpio irq controller latches level irqs. Testing shows that if
152 * we unmask & ACK the IRQ before the source of the interrupt is gone
153 * then the interrupt is active again.
154 */
155 sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
156 sd->gpio_pub_base, handle_fasteoi_irq);
157 if (!sd->gc) {
158 ret = -ENOMEM;
159 goto out_free_irq;
160 }
161
162 sd->gc->private = sd;
163 ct = sd->gc->chip_types;
164 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
165 ct->regs.eoi = GPSTR;
166 ct->regs.mask = GPIO_INT;
167 ct->chip.irq_mask = irq_gc_mask_clr_bit;
168 ct->chip.irq_unmask = irq_gc_mask_set_bit;
169 ct->chip.irq_eoi = irq_gc_eoi;
170 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
171
172 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
173 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
174 IRQ_LEVEL | IRQ_NOPROBE);
175
176 sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
177 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
178 if (!sd->id) {
179 ret = -ENODEV;
180 goto out_free_irq;
181 }
182 return 0;
183out_free_irq:
184 free_irq(pdev->irq, sd);
185out_free_desc:
186 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
187 return ret;
188}
189
190static int sdv_gpio_probe(struct pci_dev *pdev,
191 const struct pci_device_id *pci_id)
192{
193 struct sdv_gpio_chip_data *sd;
194 unsigned long addr;
195 const void *prop;
196 int len;
197 int ret;
198 u32 mux_val;
199
200 sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
201 if (!sd)
202 return -ENOMEM;
203 ret = pci_enable_device(pdev);
204 if (ret) {
205 dev_err(&pdev->dev, "can't enable device.\n");
206 goto done;
207 }
208
209 ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
210 if (ret) {
211 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
212 goto disable_pci;
213 }
214
215 addr = pci_resource_start(pdev, GPIO_BAR);
216 if (!addr) {
217 ret = -ENODEV;
218 goto release_reg;
219 }
220 sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
221
222 prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
223 if (prop && len == 4) {
224 mux_val = of_read_number(prop, 1);
225 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
226 }
227
228 ret = bgpio_init(&sd->chip, &pdev->dev, 4,
229 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
230 NULL, sd->gpio_pub_base + GPOER, NULL, 0);
231 if (ret)
232 goto unmap;
233 sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
234
235 ret = gpiochip_add_data(&sd->chip, sd);
236 if (ret < 0) {
237 dev_err(&pdev->dev, "gpiochip_add() failed.\n");
238 goto unmap;
239 }
240
241 ret = sdv_register_irqsupport(sd, pdev);
242 if (ret)
243 goto unmap;
244
245 pci_set_drvdata(pdev, sd);
246 dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
247 return 0;
248
249unmap:
250 iounmap(sd->gpio_pub_base);
251release_reg:
252 pci_release_region(pdev, GPIO_BAR);
253disable_pci:
254 pci_disable_device(pdev);
255done:
256 kfree(sd);
257 return ret;
258}
259
260static void sdv_gpio_remove(struct pci_dev *pdev)
261{
262 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
263
264 free_irq(pdev->irq, sd);
265 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
266
267 gpiochip_remove(&sd->chip);
268 pci_release_region(pdev, GPIO_BAR);
269 iounmap(sd->gpio_pub_base);
270 pci_disable_device(pdev);
271 kfree(sd);
272}
273
274static const struct pci_device_id sdv_gpio_pci_ids[] = {
275 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
276 { 0, },
277};
278
279static struct pci_driver sdv_gpio_driver = {
280 .name = DRV_NAME,
281 .id_table = sdv_gpio_pci_ids,
282 .probe = sdv_gpio_probe,
283 .remove = sdv_gpio_remove,
284};
285
286module_pci_driver(sdv_gpio_driver);
287
288MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
289MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
290MODULE_LICENSE("GPL v2");