1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
 
 
 
 
 
 
 
  4 */
  5
  6#include <linux/clk.h>
  7#include <linux/clk-provider.h>
  8#include <linux/export.h>
  9#include <linux/slab.h>
 10#include "clk.h"
 11
 12struct clk_cpu {
 13	struct clk_hw	hw;
 14	struct clk	*div;
 15	struct clk	*mux;
 16	struct clk	*pll;
 17	struct clk	*step;
 18};
 19
 20static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
 21{
 22	return container_of(hw, struct clk_cpu, hw);
 23}
 24
 25static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
 26					 unsigned long parent_rate)
 27{
 28	struct clk_cpu *cpu = to_clk_cpu(hw);
 29
 30	return clk_get_rate(cpu->div);
 31}
 32
 33static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
 34			       unsigned long *prate)
 35{
 36	struct clk_cpu *cpu = to_clk_cpu(hw);
 37
 38	return clk_round_rate(cpu->pll, rate);
 39}
 40
 41static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
 42			    unsigned long parent_rate)
 43{
 44	struct clk_cpu *cpu = to_clk_cpu(hw);
 45	int ret;
 46
 47	/* switch to PLL bypass clock */
 48	ret = clk_set_parent(cpu->mux, cpu->step);
 49	if (ret)
 50		return ret;
 51
 52	/* reprogram PLL */
 53	ret = clk_set_rate(cpu->pll, rate);
 54	if (ret) {
 55		clk_set_parent(cpu->mux, cpu->pll);
 56		return ret;
 57	}
 58	/* switch back to PLL clock */
 59	clk_set_parent(cpu->mux, cpu->pll);
 60
 61	/* Ensure the divider is what we expect */
 62	clk_set_rate(cpu->div, rate);
 63
 64	return 0;
 65}
 66
 67static const struct clk_ops clk_cpu_ops = {
 68	.recalc_rate	= clk_cpu_recalc_rate,
 69	.round_rate	= clk_cpu_round_rate,
 70	.set_rate	= clk_cpu_set_rate,
 71};
 72
 73struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
 74		struct clk *div, struct clk *mux, struct clk *pll,
 75		struct clk *step)
 76{
 77	struct clk_cpu *cpu;
 78	struct clk_hw *hw;
 79	struct clk_init_data init;
 80	int ret;
 81
 82	cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
 83	if (!cpu)
 84		return ERR_PTR(-ENOMEM);
 85
 86	cpu->div = div;
 87	cpu->mux = mux;
 88	cpu->pll = pll;
 89	cpu->step = step;
 90
 91	init.name = name;
 92	init.ops = &clk_cpu_ops;
 93	init.flags = CLK_IS_CRITICAL;
 94	init.parent_names = &parent_name;
 95	init.num_parents = 1;
 96
 97	cpu->hw.init = &init;
 98	hw = &cpu->hw;
 99
100	ret = clk_hw_register(NULL, hw);
101	if (ret) {
102		kfree(cpu);
103		return ERR_PTR(ret);
104	}
105
106	return hw;
107}
108EXPORT_SYMBOL_GPL(imx_clk_hw_cpu);

 
  1/*
  2 * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 * http://www.opensource.org/licenses/gpl-license.html
  9 * http://www.gnu.org/copyleft/gpl.html
 10 */
 11
 12#include <linux/clk.h>
 13#include <linux/clk-provider.h>
 
 14#include <linux/slab.h>
 15#include "clk.h"
 16
 17struct clk_cpu {
 18	struct clk_hw	hw;
 19	struct clk	*div;
 20	struct clk	*mux;
 21	struct clk	*pll;
 22	struct clk	*step;
 23};
 24
 25static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
 26{
 27	return container_of(hw, struct clk_cpu, hw);
 28}
 29
 30static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
 31					 unsigned long parent_rate)
 32{
 33	struct clk_cpu *cpu = to_clk_cpu(hw);
 34
 35	return clk_get_rate(cpu->div);
 36}
 37
 38static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
 39			       unsigned long *prate)
 40{
 41	struct clk_cpu *cpu = to_clk_cpu(hw);
 42
 43	return clk_round_rate(cpu->pll, rate);
 44}
 45
 46static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
 47			    unsigned long parent_rate)
 48{
 49	struct clk_cpu *cpu = to_clk_cpu(hw);
 50	int ret;
 51
 52	/* switch to PLL bypass clock */
 53	ret = clk_set_parent(cpu->mux, cpu->step);
 54	if (ret)
 55		return ret;
 56
 57	/* reprogram PLL */
 58	ret = clk_set_rate(cpu->pll, rate);
 59	if (ret) {
 60		clk_set_parent(cpu->mux, cpu->pll);
 61		return ret;
 62	}
 63	/* switch back to PLL clock */
 64	clk_set_parent(cpu->mux, cpu->pll);
 65
 66	/* Ensure the divider is what we expect */
 67	clk_set_rate(cpu->div, rate);
 68
 69	return 0;
 70}
 71
 72static const struct clk_ops clk_cpu_ops = {
 73	.recalc_rate	= clk_cpu_recalc_rate,
 74	.round_rate	= clk_cpu_round_rate,
 75	.set_rate	= clk_cpu_set_rate,
 76};
 77
 78struct clk *imx_clk_cpu(const char *name, const char *parent_name,
 79		struct clk *div, struct clk *mux, struct clk *pll,
 80		struct clk *step)
 81{
 82	struct clk_cpu *cpu;
 83	struct clk *clk;
 84	struct clk_init_data init;
 
 85
 86	cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
 87	if (!cpu)
 88		return ERR_PTR(-ENOMEM);
 89
 90	cpu->div = div;
 91	cpu->mux = mux;
 92	cpu->pll = pll;
 93	cpu->step = step;
 94
 95	init.name = name;
 96	init.ops = &clk_cpu_ops;
 97	init.flags = 0;
 98	init.parent_names = &parent_name;
 99	init.num_parents = 1;
100
101	cpu->hw.init = &init;
 
102
103	clk = clk_register(NULL, &cpu->hw);
104	if (IS_ERR(clk))
105		kfree(cpu);
 
 
106
107	return clk;
108}