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1# SPDX-License-Identifier: GPL-2.0
2#
3# Bus Devices
4#
5
6menu "Bus devices"
7
8config ARM_CCI
9 bool
10
11config ARM_CCI400_COMMON
12 bool
13 select ARM_CCI
14
15config ARM_CCI400_PORT_CTRL
16 bool
17 depends on ARM && OF && CPU_V7
18 select ARM_CCI400_COMMON
19 help
20 Low level power management driver for CCI400 cache coherent
21 interconnect for ARM platforms.
22
23config ARM_INTEGRATOR_LM
24 bool "ARM Integrator Logic Module bus"
25 depends on HAS_IOMEM
26 depends on ARCH_INTEGRATOR || COMPILE_TEST
27 default ARCH_INTEGRATOR
28 help
29 Say y here to enable support for the ARM Logic Module bus
30 found on the ARM Integrator AP (Application Platform)
31
32config BRCMSTB_GISB_ARB
33 tristate "Broadcom STB GISB bus arbiter"
34 depends on ARCH_BRCMSTB || BMIPS_GENERIC
35 default ARCH_BRCMSTB || BMIPS_GENERIC
36 help
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
38 arbiter. This driver provides timeout and target abort error handling
39 and internal bus master decoding.
40
41config BT1_APB
42 bool "Baikal-T1 APB-bus driver"
43 depends on MIPS_BAIKAL_T1 || COMPILE_TEST
44 select REGMAP_MMIO
45 help
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
47 IO requests are routed to this bus by means of the DW AMBA 3 AXI
48 Interconnect. In case of any APB protocol collisions, slave device
49 not responding on timeout an IRQ is raised with an erroneous address
50 reported to the APB terminator (APB Errors Handler Block). This
51 driver provides the interrupt handler to detect the erroneous
52 address, prints an error message about the address fault, updates an
53 errors counter. The counter and the APB-bus operations timeout can be
54 accessed via corresponding sysfs nodes.
55
56config BT1_AXI
57 bool "Baikal-T1 AXI-bus driver"
58 depends on MIPS_BAIKAL_T1 || COMPILE_TEST
59 select MFD_SYSCON
60 help
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
64 Interconnect (so called AXI Main Interconnect) routing IO requests
65 from one SoC block to another. This driver provides a way to detect
66 any bus protocol errors and device not responding situations by
67 means of an embedded on top of the interconnect errors handler
68 block (EHB). AXI Interconnect QoS arbitration tuning is currently
69 unsupported.
70
71config MOXTET
72 tristate "CZ.NIC Turris Mox module configuration bus"
73 depends on SPI_MASTER && OF
74 help
75 Say yes here to add support for the module configuration bus found
76 on CZ.NIC's Turris Mox. This is needed for the ability to discover
77 the order in which the modules are connected and to get/set some of
78 their settings. For example the GPIOs on Mox SFP module are
79 configured through this bus.
80
81config HISILICON_LPC
82 bool "Support for ISA I/O space on HiSilicon Hip06/7"
83 depends on (ARM64 && ARCH_HISI) || (COMPILE_TEST && !ALPHA && !HEXAGON && !PARISC)
84 depends on HAS_IOPORT
85 select INDIRECT_PIO if ARM64
86 help
87 Driver to enable I/O access to devices attached to the Low Pin
88 Count bus on the HiSilicon Hip06/7 SoC.
89
90config IMX_WEIM
91 bool "Freescale EIM DRIVER"
92 depends on ARCH_MXC || COMPILE_TEST
93 help
94 Driver for i.MX WEIM controller.
95 The WEIM(Wireless External Interface Module) works like a bus.
96 You can attach many different devices on it, such as NOR, onenand.
97
98config INTEL_IXP4XX_EB
99 bool "Intel IXP4xx expansion bus interface driver"
100 depends on HAS_IOMEM
101 depends on ARCH_IXP4XX || COMPILE_TEST
102 default ARCH_IXP4XX
103 select MFD_SYSCON
104 help
105 Driver for the Intel IXP4xx expansion bus interface. The driver is
106 needed to set up various chip select configuration parameters before
107 devices on the expansion bus can be discovered.
108
109config MIPS_CDMM
110 bool "MIPS Common Device Memory Map (CDMM) Driver"
111 depends on CPU_MIPSR2 || CPU_MIPSR5
112 help
113 Driver needed for the MIPS Common Device Memory Map bus in MIPS
114 cores. This bus is for per-CPU tightly coupled devices such as the
115 Fast Debug Channel (FDC).
116
117 For this to work, either your bootloader needs to enable the CDMM
118 region at an unused physical address on the boot CPU, or else your
119 platform code needs to implement mips_cdmm_phys_base() (see
120 asm/cdmm.h).
121
122config MVEBU_MBUS
123 bool
124 depends on PLAT_ORION
125 help
126 Driver needed for the MBus configuration on Marvell EBU SoCs
127 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
128
129config OMAP_INTERCONNECT
130 tristate "OMAP INTERCONNECT DRIVER"
131 depends on ARCH_OMAP2PLUS
132
133 help
134 Driver to enable OMAP interconnect error handling driver.
135
136config OMAP_OCP2SCP
137 tristate "OMAP OCP2SCP DRIVER"
138 depends on ARCH_OMAP2PLUS
139 help
140 Driver to enable ocp2scp module which transforms ocp interface
141 protocol to scp protocol. In OMAP4, USB PHY is connected via
142 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
143 OCP2SCP.
144
145config QCOM_EBI2
146 bool "Qualcomm External Bus Interface 2 (EBI2)"
147 depends on HAS_IOMEM
148 depends on ARCH_QCOM || COMPILE_TEST
149 default ARCH_QCOM
150 help
151 Say y here to enable support for the Qualcomm External Bus
152 Interface 2, which can be used to connect things like NAND Flash,
153 SRAM, ethernet adapters, FPGAs and LCD displays.
154
155config QCOM_SSC_BLOCK_BUS
156 bool "Qualcomm SSC Block Bus Init Driver"
157 depends on ARCH_QCOM
158 help
159 Say y here to enable support for initializing the bus that connects
160 the SSC block's internal bus to the cNoC (configurantion NoC) on
161 (some) qcom SoCs.
162 The SSC (Snapdragon Sensor Core) block contains a gpio controller,
163 i2c/spi/uart controllers, a hexagon core, and a clock controller
164 which provides clocks for the above.
165
166config STM32_FIREWALL
167 bool "STM32 Firewall framework"
168 depends on (ARCH_STM32 || COMPILE_TEST) && OF
169 select OF_DYNAMIC
170 help
171 Say y to enable STM32 firewall framework and its services. Firewall
172 controllers will be able to register to the framework. Access for
173 hardware resources linked to a firewall controller can be requested
174 through this STM32 framework.
175
176config SUN50I_DE2_BUS
177 bool "Allwinner A64 DE2 Bus Driver"
178 default ARM64
179 depends on ARCH_SUNXI
180 select SUNXI_SRAM
181 help
182 Say y here to enable support for Allwinner A64 DE2 bus driver. It's
183 mostly transparent, but a SRAM region needs to be claimed in the SRAM
184 controller to make the all blocks in the DE2 part accessible.
185
186config SUNXI_RSB
187 tristate "Allwinner sunXi Reduced Serial Bus Driver"
188 default MACH_SUN8I || MACH_SUN9I || ARM64
189 depends on ARCH_SUNXI
190 select REGMAP
191 help
192 Say y here to enable support for Allwinner's Reduced Serial Bus
193 (RSB) support. This controller is responsible for communicating
194 with various RSB based devices, such as AXP223, AXP8XX PMICs,
195 and AC100/AC200 ICs.
196
197config TEGRA_ACONNECT
198 tristate "Tegra ACONNECT Bus Driver"
199 depends on ARCH_TEGRA
200 depends on OF && PM
201 help
202 Driver for the Tegra ACONNECT bus which is used to interface with
203 the devices inside the Audio Processing Engine (APE) for
204 Tegra210 and later.
205
206config TEGRA_GMI
207 tristate "Tegra Generic Memory Interface bus driver"
208 depends on ARCH_TEGRA
209 help
210 Driver for the Tegra Generic Memory Interface bus which can be used
211 to attach devices such as NOR, UART, FPGA and more.
212
213config TI_PWMSS
214 bool
215 default y if (ARCH_OMAP2PLUS) && (PWM_TIECAP || PWM_TIEHRPWM || TI_EQEP)
216 help
217 PWM Subsystem driver support for AM33xx SOC.
218
219 PWM submodules require PWM config space access from submodule
220 drivers and require common parent driver support.
221
222config TI_SYSC
223 bool "TI sysc interconnect target module driver"
224 depends on ARCH_OMAP2PLUS || ARCH_K3
225 default y
226 help
227 Generic driver for Texas Instruments interconnect target module
228 found on many TI SoCs.
229
230config TS_NBUS
231 tristate "Technologic Systems NBUS Driver"
232 depends on SOC_IMX28
233 depends on OF_GPIO && PWM
234 help
235 Driver for the Technologic Systems NBUS which is used to interface
236 with the peripherals in the FPGA of the TS-4600 SoM.
237
238config UNIPHIER_SYSTEM_BUS
239 tristate "UniPhier System Bus driver"
240 depends on ARCH_UNIPHIER && OF
241 default y
242 help
243 Support for UniPhier System Bus, a simple external bus. This is
244 needed to use on-board devices connected to UniPhier SoCs.
245
246config VEXPRESS_CONFIG
247 tristate "Versatile Express configuration bus"
248 default y if ARCH_VEXPRESS
249 depends on ARM || ARM64
250 depends on OF
251 select REGMAP
252 help
253 Platform configuration infrastructure for the ARM Ltd.
254 Versatile Express.
255
256config DA8XX_MSTPRI
257 bool "TI da8xx master peripheral priority driver"
258 depends on ARCH_DAVINCI_DA8XX
259 help
260 Driver for Texas Instruments da8xx master peripheral priority
261 configuration. Allows to adjust the priorities of all master
262 peripherals.
263
264source "drivers/bus/fsl-mc/Kconfig"
265source "drivers/bus/mhi/Kconfig"
266
267endmenu
1#
2# Bus Devices
3#
4
5menu "Bus devices"
6
7config ARM_CCI
8 bool
9
10config ARM_CCI_PMU
11 bool
12 select ARM_CCI
13
14config ARM_CCI400_COMMON
15 bool
16 select ARM_CCI
17
18config ARM_CCI400_PMU
19 bool "ARM CCI400 PMU support"
20 depends on (ARM && CPU_V7) || ARM64
21 depends on PERF_EVENTS
22 select ARM_CCI400_COMMON
23 select ARM_CCI_PMU
24 help
25 Support for PMU events monitoring on the ARM CCI-400 (cache coherent
26 interconnect). CCI-400 supports counting events related to the
27 connected slave/master interfaces.
28
29config ARM_CCI400_PORT_CTRL
30 bool
31 depends on ARM && OF && CPU_V7
32 select ARM_CCI400_COMMON
33 help
34 Low level power management driver for CCI400 cache coherent
35 interconnect for ARM platforms.
36
37config ARM_CCI5xx_PMU
38 bool "ARM CCI-500/CCI-550 PMU support"
39 depends on (ARM && CPU_V7) || ARM64
40 depends on PERF_EVENTS
41 select ARM_CCI_PMU
42 help
43 Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache
44 coherent interconnects. Both of them provide 8 independent event counters,
45 which can count events pertaining to the slave/master interfaces as well
46 as the internal events to the CCI.
47
48 If unsure, say Y
49
50config ARM_CCN
51 bool "ARM CCN driver support"
52 depends on ARM || ARM64
53 depends on PERF_EVENTS
54 help
55 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
56 interconnect.
57
58config BRCMSTB_GISB_ARB
59 bool "Broadcom STB GISB bus arbiter"
60 depends on ARM || MIPS
61 help
62 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
63 arbiter. This driver provides timeout and target abort error handling
64 and internal bus master decoding.
65
66config IMX_WEIM
67 bool "Freescale EIM DRIVER"
68 depends on ARCH_MXC
69 help
70 Driver for i.MX WEIM controller.
71 The WEIM(Wireless External Interface Module) works like a bus.
72 You can attach many different devices on it, such as NOR, onenand.
73
74config MIPS_CDMM
75 bool "MIPS Common Device Memory Map (CDMM) Driver"
76 depends on CPU_MIPSR2
77 help
78 Driver needed for the MIPS Common Device Memory Map bus in MIPS
79 cores. This bus is for per-CPU tightly coupled devices such as the
80 Fast Debug Channel (FDC).
81
82 For this to work, either your bootloader needs to enable the CDMM
83 region at an unused physical address on the boot CPU, or else your
84 platform code needs to implement mips_cdmm_phys_base() (see
85 asm/cdmm.h).
86
87config MVEBU_MBUS
88 bool
89 depends on PLAT_ORION
90 help
91 Driver needed for the MBus configuration on Marvell EBU SoCs
92 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
93
94config OMAP_INTERCONNECT
95 tristate "OMAP INTERCONNECT DRIVER"
96 depends on ARCH_OMAP2PLUS
97
98 help
99 Driver to enable OMAP interconnect error handling driver.
100
101config OMAP_OCP2SCP
102 tristate "OMAP OCP2SCP DRIVER"
103 depends on ARCH_OMAP2PLUS
104 help
105 Driver to enable ocp2scp module which transforms ocp interface
106 protocol to scp protocol. In OMAP4, USB PHY is connected via
107 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
108 OCP2SCP.
109
110config SIMPLE_PM_BUS
111 bool "Simple Power-Managed Bus Driver"
112 depends on OF && PM
113 depends on ARCH_SHMOBILE || COMPILE_TEST
114 help
115 Driver for transparent busses that don't need a real driver, but
116 where the bus controller is part of a PM domain, or under the control
117 of a functional clock, and thus relies on runtime PM for managing
118 this PM domain and/or clock.
119 An example of such a bus controller is the Renesas Bus State
120 Controller (BSC, sometimes called "LBSC within Bus Bridge", or
121 "External Bus Interface") as found on several Renesas ARM SoCs.
122
123config SUNXI_RSB
124 tristate "Allwinner sunXi Reduced Serial Bus Driver"
125 default MACH_SUN8I || MACH_SUN9I
126 depends on ARCH_SUNXI
127 select REGMAP
128 help
129 Say y here to enable support for Allwinner's Reduced Serial Bus
130 (RSB) support. This controller is responsible for communicating
131 with various RSB based devices, such as AXP223, AXP8XX PMICs,
132 and AC100/AC200 ICs.
133
134config UNIPHIER_SYSTEM_BUS
135 tristate "UniPhier System Bus driver"
136 depends on ARCH_UNIPHIER && OF
137 default y
138 help
139 Support for UniPhier System Bus, a simple external bus. This is
140 needed to use on-board devices connected to UniPhier SoCs.
141
142config VEXPRESS_CONFIG
143 bool "Versatile Express configuration bus"
144 default y if ARCH_VEXPRESS
145 depends on ARM || ARM64
146 depends on OF
147 select REGMAP
148 help
149 Platform configuration infrastructure for the ARM Ltd.
150 Versatile Express.
151endmenu