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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright IBM Corp 2000, 2011
4 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
5 * Denis Joseph Barrow,
6 */
7
8#include <linux/linkage.h>
9#include <asm/asm-offsets.h>
10#include <asm/nospec-insn.h>
11#include <asm/sigp.h>
12#include <asm/lowcore.h>
13
14 GEN_BR_THUNK %r9
15
16#
17# Issue "store status" for the current CPU to its prefix page
18# and call passed function afterwards
19#
20# r2 = Function to be called after store status
21# r3 = Parameter for function
22#
23SYM_CODE_START(store_status)
24 STMG_LC %r0,%r15,__LC_GPREGS_SAVE_AREA
25 /* General purpose registers */
26 GET_LC %r13
27 /* Control registers */
28 stctg %c0,%c15,__LC_CREGS_SAVE_AREA(%r13)
29 /* Access registers */
30 stamy %a0,%a15,__LC_AREGS_SAVE_AREA(%r13)
31 /* Floating point registers */
32 lay %r1,__LC_FPREGS_SAVE_AREA(%r13)
33 std %f0, 0x00(%r1)
34 std %f1, 0x08(%r1)
35 std %f2, 0x10(%r1)
36 std %f3, 0x18(%r1)
37 std %f4, 0x20(%r1)
38 std %f5, 0x28(%r1)
39 std %f6, 0x30(%r1)
40 std %f7, 0x38(%r1)
41 std %f8, 0x40(%r1)
42 std %f9, 0x48(%r1)
43 std %f10,0x50(%r1)
44 std %f11,0x58(%r1)
45 std %f12,0x60(%r1)
46 std %f13,0x68(%r1)
47 std %f14,0x70(%r1)
48 std %f15,0x78(%r1)
49 /* Floating point control register */
50 lay %r1,__LC_FP_CREG_SAVE_AREA(%r13)
51 stfpc 0(%r1)
52 /* CPU timer */
53 lay %r1,__LC_CPU_TIMER_SAVE_AREA(%r13)
54 stpt 0(%r1)
55 /* Store prefix register */
56 lay %r1,__LC_PREFIX_SAVE_AREA(%r13)
57 stpx 0(%r1)
58 /* Clock comparator - seven bytes */
59 larl %r4,clkcmp
60 stckc 0(%r4)
61 lay %r1,__LC_CLOCK_COMP_SAVE_AREA(%r13)
62 mvc 1(7,%r1),1(%r4)
63 /* Program status word */
64 lay %r1,__LC_PSW_SAVE_AREA(%r13)
65 epsw %r4,%r5
66 st %r4,0(%r1)
67 st %r5,4(%r1)
68 stg %r2,8(%r1)
69 lgr %r9,%r2
70 lgr %r2,%r3
71 BR_EX %r9
72SYM_CODE_END(store_status)
73
74 .section .bss
75 .balign 8
76SYM_DATA_LOCAL(clkcmp, .quad 0x0000000000000000)
77 .previous
1/*
2 * Copyright IBM Corp 2000, 2011
3 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
4 * Denis Joseph Barrow,
5 */
6
7#include <linux/linkage.h>
8#include <asm/asm-offsets.h>
9#include <asm/sigp.h>
10
11#
12# Issue "store status" for the current CPU to its prefix page
13# and call passed function afterwards
14#
15# r2 = Function to be called after store status
16# r3 = Parameter for function
17#
18ENTRY(store_status)
19 /* Save register one and load save area base */
20 stg %r1,__LC_SAVE_AREA_RESTART
21 /* General purpose registers */
22 lghi %r1,__LC_GPREGS_SAVE_AREA
23 stmg %r0,%r15,0(%r1)
24 mvc 8(8,%r1),__LC_SAVE_AREA_RESTART
25 /* Control registers */
26 lghi %r1,__LC_CREGS_SAVE_AREA
27 stctg %c0,%c15,0(%r1)
28 /* Access registers */
29 lghi %r1,__LC_AREGS_SAVE_AREA
30 stam %a0,%a15,0(%r1)
31 /* Floating point registers */
32 lghi %r1,__LC_FPREGS_SAVE_AREA
33 std %f0, 0x00(%r1)
34 std %f1, 0x08(%r1)
35 std %f2, 0x10(%r1)
36 std %f3, 0x18(%r1)
37 std %f4, 0x20(%r1)
38 std %f5, 0x28(%r1)
39 std %f6, 0x30(%r1)
40 std %f7, 0x38(%r1)
41 std %f8, 0x40(%r1)
42 std %f9, 0x48(%r1)
43 std %f10,0x50(%r1)
44 std %f11,0x58(%r1)
45 std %f12,0x60(%r1)
46 std %f13,0x68(%r1)
47 std %f14,0x70(%r1)
48 std %f15,0x78(%r1)
49 /* Floating point control register */
50 lghi %r1,__LC_FP_CREG_SAVE_AREA
51 stfpc 0(%r1)
52 /* CPU timer */
53 lghi %r1,__LC_CPU_TIMER_SAVE_AREA
54 stpt 0(%r1)
55 /* Store prefix register */
56 lghi %r1,__LC_PREFIX_SAVE_AREA
57 stpx 0(%r1)
58 /* Clock comparator - seven bytes */
59 lghi %r1,__LC_CLOCK_COMP_SAVE_AREA
60 larl %r4,.Lclkcmp
61 stckc 0(%r4)
62 mvc 1(7,%r1),1(%r4)
63 /* Program status word */
64 lghi %r1,__LC_PSW_SAVE_AREA
65 epsw %r4,%r5
66 st %r4,0(%r1)
67 st %r5,4(%r1)
68 stg %r2,8(%r1)
69 lgr %r1,%r2
70 lgr %r2,%r3
71 br %r1
72
73 .section .bss
74 .align 8
75.Lclkcmp: .quad 0x0000000000000000
76 .previous
77
78#
79# do_reipl_asm
80# Parameter: r2 = schid of reipl device
81#
82
83ENTRY(do_reipl_asm)
84 basr %r13,0
85.Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
86.Lpg1: lgr %r3,%r2
87 larl %r2,.Lstatus
88 brasl %r14,store_status
89
90.Lstatus: lctlg %c6,%c6,.Lall-.Lpg0(%r13)
91 lgr %r1,%r2
92 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
93 stsch .Lschib-.Lpg0(%r13)
94 oi .Lschib+5-.Lpg0(%r13),0x84
95.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
96 msch .Lschib-.Lpg0(%r13)
97 lghi %r0,5
98.Lssch: ssch .Liplorb-.Lpg0(%r13)
99 jz .L001
100 brct %r0,.Lssch
101 bas %r14,.Ldisab-.Lpg0(%r13)
102.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
103.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
104.Lcont: c %r1,__LC_SUBCHANNEL_ID
105 jnz .Ltpi
106 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
107 jnz .Ltpi
108 tsch .Liplirb-.Lpg0(%r13)
109 tm .Liplirb+9-.Lpg0(%r13),0xbf
110 jz .L002
111 bas %r14,.Ldisab-.Lpg0(%r13)
112.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
113 jz .L003
114 bas %r14,.Ldisab-.Lpg0(%r13)
115.L003: st %r1,__LC_SUBCHANNEL_ID
116 lhi %r1,0 # mode 0 = esa
117 slr %r0,%r0 # set cpuid to zero
118 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode
119 lpsw 0
120.Ldisab: sll %r14,1
121 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
122 st %r14,.Ldispsw+12-.Lpg0(%r13)
123 lpswe .Ldispsw-.Lpg0(%r13)
124 .align 8
125.Lall: .quad 0x00000000ff000000
126 .align 16
127/*
128 * These addresses have to be 31 bit otherwise
129 * the sigp will throw a specifcation exception
130 * when switching to ESA mode as bit 31 be set
131 * in the ESA psw.
132 * Bit 31 of the addresses has to be 0 for the
133 * 31bit lpswe instruction a fact they appear to have
134 * omitted from the pop.
135 */
136.Lnewpsw: .quad 0x0000000080000000
137 .quad .Lpg1
138.Lpcnew: .quad 0x0000000080000000
139 .quad .Lecs
140.Lionew: .quad 0x0000000080000000
141 .quad .Lcont
142.Lwaitpsw: .quad 0x0202000080000000
143 .quad .Ltpi
144.Ldispsw: .quad 0x0002000080000000
145 .quad 0x0000000000000000
146.Liplccws: .long 0x02000000,0x60000018
147 .long 0x08000008,0x20000001
148.Liplorb: .long 0x0049504c,0x0040ff80
149 .long 0x00000000+.Liplccws
150.Lschib: .long 0x00000000,0x00000000
151 .long 0x00000000,0x00000000
152 .long 0x00000000,0x00000000
153 .long 0x00000000,0x00000000
154 .long 0x00000000,0x00000000
155 .long 0x00000000,0x00000000
156.Liplirb: .long 0x00000000,0x00000000
157 .long 0x00000000,0x00000000
158 .long 0x00000000,0x00000000
159 .long 0x00000000,0x00000000
160 .long 0x00000000,0x00000000
161 .long 0x00000000,0x00000000
162 .long 0x00000000,0x00000000
163 .long 0x00000000,0x00000000