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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8195-clk.h>
9#include <dt-bindings/gce/mt8195-gce.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/memory/mt8195-memory-port.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15#include <dt-bindings/power/mt8195-power.h>
16#include <dt-bindings/reset/mt8195-resets.h>
17#include <dt-bindings/thermal/thermal.h>
18#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
19
20/ {
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases {
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
29 gce0 = &gce0;
30 gce1 = &gce1;
31 ethdr0 = ðdr0;
32 mutex0 = &mutex;
33 mutex1 = &mutex1;
34 merge1 = &merge1;
35 merge2 = &merge2;
36 merge3 = &merge3;
37 merge4 = &merge4;
38 merge5 = &merge5;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a55";
56 reg = <0x000>;
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
70 };
71
72 cpu1: cpu@100 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x100>;
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
89 };
90
91 cpu2: cpu@200 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a55";
94 reg = <0x200>;
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
108 };
109
110 cpu3: cpu@300 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a55";
113 reg = <0x300>;
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
127 };
128
129 cpu4: cpu@400 {
130 device_type = "cpu";
131 compatible = "arm,cortex-a78";
132 reg = <0x400>;
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
146 };
147
148 cpu5: cpu@500 {
149 device_type = "cpu";
150 compatible = "arm,cortex-a78";
151 reg = <0x500>;
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
165 };
166
167 cpu6: cpu@600 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a78";
170 reg = <0x600>;
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
184 };
185
186 cpu7: cpu@700 {
187 device_type = "cpu";
188 compatible = "arm,cortex-a78";
189 reg = <0x700>;
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
203 };
204
205 cpu-map {
206 cluster0 {
207 core0 {
208 cpu = <&cpu0>;
209 };
210
211 core1 {
212 cpu = <&cpu1>;
213 };
214
215 core2 {
216 cpu = <&cpu2>;
217 };
218
219 core3 {
220 cpu = <&cpu3>;
221 };
222
223 core4 {
224 cpu = <&cpu4>;
225 };
226
227 core5 {
228 cpu = <&cpu5>;
229 };
230
231 core6 {
232 cpu = <&cpu6>;
233 };
234
235 core7 {
236 cpu = <&cpu7>;
237 };
238 };
239 };
240
241 idle-states {
242 entry-method = "psci";
243
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
251 };
252
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
260 };
261
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
269 };
270
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
278 };
279 };
280
281 l2_0: l2-cache0 {
282 compatible = "cache";
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
289 };
290
291 l2_1: l2-cache1 {
292 compatible = "cache";
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
299 };
300
301 l3_0: l3-cache {
302 compatible = "cache";
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
308 };
309 };
310
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
316 status = "fail";
317 };
318
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
323 };
324
325 sound: mt8195-sound {
326 mediatek,platform = <&afe>;
327 status = "disabled";
328 };
329
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
333 clocks = <&clk26m>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
337 };
338
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
344 };
345
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
351 };
352
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
356 #performance-domain-cells = <1>;
357 };
358
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
362
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
366 };
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
370 };
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
374 };
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
378 };
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
382 };
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
386 };
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
390 };
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
394 };
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
398 };
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
402 };
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
406 };
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
410 };
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
414 };
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
418 };
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
422 };
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
426 };
427 };
428
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
433 };
434
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
439 };
440
441 psci {
442 compatible = "arm,psci-1.0";
443 method = "smc";
444 };
445
446 timer: timer {
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
453 };
454
455 soc {
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
459 ranges;
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
461
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
468 reg = <0 0x0c000000 0 0x40000>,
469 <0 0x0c040000 0 0x200000>;
470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
471
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
475 };
476
477 ppi_cluster1: interrupt-partition-1 {
478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
479 };
480 };
481 };
482
483 topckgen: syscon@10000000 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
485 reg = <0 0x10000000 0 0x1000>;
486 #clock-cells = <1>;
487 };
488
489 infracfg_ao: syscon@10001000 {
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
491 reg = <0 0x10001000 0 0x1000>;
492 #clock-cells = <1>;
493 #reset-cells = <1>;
494 };
495
496 pericfg: syscon@10003000 {
497 compatible = "mediatek,mt8195-pericfg", "syscon";
498 reg = <0 0x10003000 0 0x1000>;
499 #clock-cells = <1>;
500 };
501
502 pio: pinctrl@10005000 {
503 compatible = "mediatek,mt8195-pinctrl";
504 reg = <0 0x10005000 0 0x1000>,
505 <0 0x11d10000 0 0x1000>,
506 <0 0x11d30000 0 0x1000>,
507 <0 0x11d40000 0 0x1000>,
508 <0 0x11e20000 0 0x1000>,
509 <0 0x11eb0000 0 0x1000>,
510 <0 0x11f40000 0 0x1000>,
511 <0 0x1000b000 0 0x1000>;
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
513 "iocfg_br", "iocfg_lm", "iocfg_rb",
514 "iocfg_tl", "eint";
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
520 #interrupt-cells = <2>;
521 };
522
523 scpsys: syscon@10006000 {
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
525 reg = <0 0x10006000 0 0x1000>;
526
527 /* System Power Manager */
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
533
534 /* power domain of the SoC */
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
536 reg = <MT8195_POWER_DOMAIN_MFG0>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
540
541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
542 reg = <MT8195_POWER_DOMAIN_MFG1>;
543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
545 clock-names = "mfg", "alt";
546 mediatek,infracfg = <&infracfg_ao>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
550
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
552 reg = <MT8195_POWER_DOMAIN_MFG2>;
553 #power-domain-cells = <0>;
554 };
555
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
557 reg = <MT8195_POWER_DOMAIN_MFG3>;
558 #power-domain-cells = <0>;
559 };
560
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
562 reg = <MT8195_POWER_DOMAIN_MFG4>;
563 #power-domain-cells = <0>;
564 };
565
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
567 reg = <MT8195_POWER_DOMAIN_MFG5>;
568 #power-domain-cells = <0>;
569 };
570
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
572 reg = <MT8195_POWER_DOMAIN_MFG6>;
573 #power-domain-cells = <0>;
574 };
575 };
576 };
577
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
580 clocks = <&topckgen CLK_TOP_VPP>,
581 <&topckgen CLK_TOP_CAM>,
582 <&topckgen CLK_TOP_CCU>,
583 <&topckgen CLK_TOP_IMG>,
584 <&topckgen CLK_TOP_VENC>,
585 <&topckgen CLK_TOP_VDEC>,
586 <&topckgen CLK_TOP_WPE_VPP>,
587 <&topckgen CLK_TOP_CFG_VPP0>,
588 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
608 "vppsys4", "vppsys5", "vppsys6", "vppsys7",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
615 mediatek,infracfg = <&infracfg_ao>;
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
619
620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
621 reg = <MT8195_POWER_DOMAIN_VDEC1>;
622 clocks = <&vdecsys CLK_VDEC_LARB1>;
623 clock-names = "vdec1-0";
624 mediatek,infracfg = <&infracfg_ao>;
625 #power-domain-cells = <0>;
626 };
627
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
629 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
630 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
631 clock-names = "venc1-larb";
632 mediatek,infracfg = <&infracfg_ao>;
633 #power-domain-cells = <0>;
634 };
635
636 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
637 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
638 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
639 <&vdosys0 CLK_VDO0_SMI_GALS>,
640 <&vdosys0 CLK_VDO0_SMI_COMMON>,
641 <&vdosys0 CLK_VDO0_SMI_EMI>,
642 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
643 <&vdosys0 CLK_VDO0_SMI_LARB>,
644 <&vdosys0 CLK_VDO0_SMI_RSI>;
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
646 "vdosys0-2", "vdosys0-3",
647 "vdosys0-4", "vdosys0-5";
648 mediatek,infracfg = <&infracfg_ao>;
649 #address-cells = <1>;
650 #size-cells = <0>;
651 #power-domain-cells = <1>;
652
653 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
654 reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
655 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
656 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
657 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
658 clock-names = "vppsys1", "vppsys1-0",
659 "vppsys1-1";
660 mediatek,infracfg = <&infracfg_ao>;
661 #power-domain-cells = <0>;
662 };
663
664 power-domain@MT8195_POWER_DOMAIN_WPESYS {
665 reg = <MT8195_POWER_DOMAIN_WPESYS>;
666 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
667 <&wpesys CLK_WPE_SMI_LARB8>,
668 <&wpesys CLK_WPE_SMI_LARB7_P>,
669 <&wpesys CLK_WPE_SMI_LARB8_P>;
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
671 "wepsys-3";
672 mediatek,infracfg = <&infracfg_ao>;
673 #power-domain-cells = <0>;
674 };
675
676 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
677 reg = <MT8195_POWER_DOMAIN_VDEC0>;
678 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
679 clock-names = "vdec0-0";
680 mediatek,infracfg = <&infracfg_ao>;
681 #power-domain-cells = <0>;
682 };
683
684 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
685 reg = <MT8195_POWER_DOMAIN_VDEC2>;
686 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
687 clock-names = "vdec2-0";
688 mediatek,infracfg = <&infracfg_ao>;
689 #power-domain-cells = <0>;
690 };
691
692 power-domain@MT8195_POWER_DOMAIN_VENC {
693 reg = <MT8195_POWER_DOMAIN_VENC>;
694 clocks = <&vencsys CLK_VENC_LARB>;
695 clock-names = "venc0-larb";
696 mediatek,infracfg = <&infracfg_ao>;
697 #power-domain-cells = <0>;
698 };
699
700 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
701 reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
702 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
703 <&vdosys1 CLK_VDO1_SMI_LARB2>,
704 <&vdosys1 CLK_VDO1_SMI_LARB3>,
705 <&vdosys1 CLK_VDO1_GALS>;
706 clock-names = "vdosys1", "vdosys1-0",
707 "vdosys1-1", "vdosys1-2";
708 mediatek,infracfg = <&infracfg_ao>;
709 #address-cells = <1>;
710 #size-cells = <0>;
711 #power-domain-cells = <1>;
712
713 power-domain@MT8195_POWER_DOMAIN_DP_TX {
714 reg = <MT8195_POWER_DOMAIN_DP_TX>;
715 mediatek,infracfg = <&infracfg_ao>;
716 #power-domain-cells = <0>;
717 };
718
719 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
720 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
721 mediatek,infracfg = <&infracfg_ao>;
722 #power-domain-cells = <0>;
723 };
724
725 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
726 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
727 clocks = <&topckgen CLK_TOP_HDMI_APB>;
728 clock-names = "hdmi_tx";
729 #power-domain-cells = <0>;
730 };
731 };
732
733 power-domain@MT8195_POWER_DOMAIN_IMG {
734 reg = <MT8195_POWER_DOMAIN_IMG>;
735 clocks = <&imgsys CLK_IMG_LARB9>,
736 <&imgsys CLK_IMG_GALS>;
737 clock-names = "img-0", "img-1";
738 mediatek,infracfg = <&infracfg_ao>;
739 #address-cells = <1>;
740 #size-cells = <0>;
741 #power-domain-cells = <1>;
742
743 power-domain@MT8195_POWER_DOMAIN_DIP {
744 reg = <MT8195_POWER_DOMAIN_DIP>;
745 #power-domain-cells = <0>;
746 };
747
748 power-domain@MT8195_POWER_DOMAIN_IPE {
749 reg = <MT8195_POWER_DOMAIN_IPE>;
750 clocks = <&topckgen CLK_TOP_IPE>,
751 <&imgsys CLK_IMG_IPE>,
752 <&ipesys CLK_IPE_SMI_LARB12>;
753 clock-names = "ipe", "ipe-0", "ipe-1";
754 mediatek,infracfg = <&infracfg_ao>;
755 #power-domain-cells = <0>;
756 };
757 };
758
759 power-domain@MT8195_POWER_DOMAIN_CAM {
760 reg = <MT8195_POWER_DOMAIN_CAM>;
761 clocks = <&camsys CLK_CAM_LARB13>,
762 <&camsys CLK_CAM_LARB14>,
763 <&camsys CLK_CAM_CAM2MM0_GALS>,
764 <&camsys CLK_CAM_CAM2MM1_GALS>,
765 <&camsys CLK_CAM_CAM2SYS_GALS>;
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
767 "cam-4";
768 mediatek,infracfg = <&infracfg_ao>;
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <1>;
772
773 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
774 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
775 #power-domain-cells = <0>;
776 };
777
778 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
779 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
780 #power-domain-cells = <0>;
781 };
782
783 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
784 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
785 #power-domain-cells = <0>;
786 };
787 };
788 };
789 };
790
791 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
792 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
793 mediatek,infracfg = <&infracfg_ao>;
794 #power-domain-cells = <0>;
795 };
796
797 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
798 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
799 mediatek,infracfg = <&infracfg_ao>;
800 #power-domain-cells = <0>;
801 };
802
803 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
804 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
805 #power-domain-cells = <0>;
806 };
807
808 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
809 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
810 #power-domain-cells = <0>;
811 };
812
813 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
814 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
815 clocks = <&topckgen CLK_TOP_SENINF>,
816 <&topckgen CLK_TOP_SENINF2>;
817 clock-names = "csi_rx_top", "csi_rx_top1";
818 #power-domain-cells = <0>;
819 };
820
821 power-domain@MT8195_POWER_DOMAIN_ETHER {
822 reg = <MT8195_POWER_DOMAIN_ETHER>;
823 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
824 clock-names = "ether";
825 #power-domain-cells = <0>;
826 };
827
828 power-domain@MT8195_POWER_DOMAIN_ADSP {
829 reg = <MT8195_POWER_DOMAIN_ADSP>;
830 clocks = <&topckgen CLK_TOP_ADSP>,
831 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
832 clock-names = "adsp", "adsp1";
833 #address-cells = <1>;
834 #size-cells = <0>;
835 mediatek,infracfg = <&infracfg_ao>;
836 #power-domain-cells = <1>;
837
838 power-domain@MT8195_POWER_DOMAIN_AUDIO {
839 reg = <MT8195_POWER_DOMAIN_AUDIO>;
840 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
841 <&topckgen CLK_TOP_AUD_INTBUS>,
842 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
843 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
844 clock-names = "audio", "audio1", "audio2",
845 "audio3";
846 mediatek,infracfg = <&infracfg_ao>;
847 #power-domain-cells = <0>;
848 };
849 };
850 };
851 };
852
853 watchdog: watchdog@10007000 {
854 compatible = "mediatek,mt8195-wdt";
855 mediatek,disable-extrst;
856 reg = <0 0x10007000 0 0x100>;
857 #reset-cells = <1>;
858 };
859
860 apmixedsys: syscon@1000c000 {
861 compatible = "mediatek,mt8195-apmixedsys", "syscon";
862 reg = <0 0x1000c000 0 0x1000>;
863 #clock-cells = <1>;
864 };
865
866 systimer: timer@10017000 {
867 compatible = "mediatek,mt8195-timer",
868 "mediatek,mt6765-timer";
869 reg = <0 0x10017000 0 0x1000>;
870 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
871 clocks = <&clk13m>;
872 };
873
874 pwrap: pwrap@10024000 {
875 compatible = "mediatek,mt8195-pwrap", "syscon";
876 reg = <0 0x10024000 0 0x1000>;
877 reg-names = "pwrap";
878 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
880 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
881 clock-names = "spi", "wrap";
882 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
883 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
884 };
885
886 spmi: spmi@10027000 {
887 compatible = "mediatek,mt8195-spmi";
888 reg = <0 0x10027000 0 0x000e00>,
889 <0 0x10029000 0 0x000100>;
890 reg-names = "pmif", "spmimst";
891 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
892 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
893 <&topckgen CLK_TOP_SPMI_M_MST>;
894 clock-names = "pmif_sys_ck",
895 "pmif_tmr_ck",
896 "spmimst_clk_mux";
897 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
898 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
899 };
900
901 iommu_infra: infra-iommu@10315000 {
902 compatible = "mediatek,mt8195-iommu-infra";
903 reg = <0 0x10315000 0 0x5000>;
904 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
905 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
906 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
907 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
908 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
909 #iommu-cells = <1>;
910 };
911
912 gce0: mailbox@10320000 {
913 compatible = "mediatek,mt8195-gce";
914 reg = <0 0x10320000 0 0x4000>;
915 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
916 #mbox-cells = <2>;
917 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
918 };
919
920 gce1: mailbox@10330000 {
921 compatible = "mediatek,mt8195-gce";
922 reg = <0 0x10330000 0 0x4000>;
923 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
924 #mbox-cells = <2>;
925 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
926 };
927
928 scp: scp@10500000 {
929 compatible = "mediatek,mt8195-scp";
930 reg = <0 0x10500000 0 0x100000>,
931 <0 0x10720000 0 0xe0000>,
932 <0 0x10700000 0 0x8000>;
933 reg-names = "sram", "cfg", "l1tcm";
934 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
935 status = "disabled";
936 };
937
938 scp_adsp: clock-controller@10720000 {
939 compatible = "mediatek,mt8195-scp_adsp";
940 reg = <0 0x10720000 0 0x1000>;
941 #clock-cells = <1>;
942 };
943
944 adsp: dsp@10803000 {
945 compatible = "mediatek,mt8195-dsp";
946 reg = <0 0x10803000 0 0x1000>,
947 <0 0x10840000 0 0x40000>;
948 reg-names = "cfg", "sram";
949 clocks = <&topckgen CLK_TOP_ADSP>,
950 <&clk26m>,
951 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
952 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
953 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
954 <&topckgen CLK_TOP_AUDIO_H>;
955 clock-names = "adsp_sel",
956 "clk26m_ck",
957 "audio_local_bus",
958 "mainpll_d7_d2",
959 "scp_adsp_audiodsp",
960 "audio_h";
961 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
962 mbox-names = "rx", "tx";
963 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
964 status = "disabled";
965 };
966
967 adsp_mailbox0: mailbox@10816000 {
968 compatible = "mediatek,mt8195-adsp-mbox";
969 #mbox-cells = <0>;
970 reg = <0 0x10816000 0 0x1000>;
971 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
972 };
973
974 adsp_mailbox1: mailbox@10817000 {
975 compatible = "mediatek,mt8195-adsp-mbox";
976 #mbox-cells = <0>;
977 reg = <0 0x10817000 0 0x1000>;
978 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
979 };
980
981 afe: mt8195-afe-pcm@10890000 {
982 compatible = "mediatek,mt8195-audio";
983 reg = <0 0x10890000 0 0x10000>;
984 mediatek,topckgen = <&topckgen>;
985 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
986 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
987 resets = <&watchdog 14>;
988 reset-names = "audiosys";
989 clocks = <&clk26m>,
990 <&apmixedsys CLK_APMIXED_APLL1>,
991 <&apmixedsys CLK_APMIXED_APLL2>,
992 <&topckgen CLK_TOP_APLL12_DIV0>,
993 <&topckgen CLK_TOP_APLL12_DIV1>,
994 <&topckgen CLK_TOP_APLL12_DIV2>,
995 <&topckgen CLK_TOP_APLL12_DIV3>,
996 <&topckgen CLK_TOP_APLL12_DIV9>,
997 <&topckgen CLK_TOP_A1SYS_HP>,
998 <&topckgen CLK_TOP_AUD_INTBUS>,
999 <&topckgen CLK_TOP_AUDIO_H>,
1000 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001 <&topckgen CLK_TOP_DPTX_MCK>,
1002 <&topckgen CLK_TOP_I2SO1_MCK>,
1003 <&topckgen CLK_TOP_I2SO2_MCK>,
1004 <&topckgen CLK_TOP_I2SI1_MCK>,
1005 <&topckgen CLK_TOP_I2SI2_MCK>,
1006 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1007 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1008 clock-names = "clk26m",
1009 "apll1_ck",
1010 "apll2_ck",
1011 "apll12_div0",
1012 "apll12_div1",
1013 "apll12_div2",
1014 "apll12_div3",
1015 "apll12_div9",
1016 "a1sys_hp_sel",
1017 "aud_intbus_sel",
1018 "audio_h_sel",
1019 "audio_local_bus_sel",
1020 "dptx_m_sel",
1021 "i2so1_m_sel",
1022 "i2so2_m_sel",
1023 "i2si1_m_sel",
1024 "i2si2_m_sel",
1025 "infra_ao_audio_26m_b",
1026 "scp_adsp_audiodsp";
1027 status = "disabled";
1028 };
1029
1030 uart0: serial@11001100 {
1031 compatible = "mediatek,mt8195-uart",
1032 "mediatek,mt6577-uart";
1033 reg = <0 0x11001100 0 0x100>;
1034 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1035 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1036 clock-names = "baud", "bus";
1037 status = "disabled";
1038 };
1039
1040 uart1: serial@11001200 {
1041 compatible = "mediatek,mt8195-uart",
1042 "mediatek,mt6577-uart";
1043 reg = <0 0x11001200 0 0x100>;
1044 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1045 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1046 clock-names = "baud", "bus";
1047 status = "disabled";
1048 };
1049
1050 uart2: serial@11001300 {
1051 compatible = "mediatek,mt8195-uart",
1052 "mediatek,mt6577-uart";
1053 reg = <0 0x11001300 0 0x100>;
1054 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1055 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1056 clock-names = "baud", "bus";
1057 status = "disabled";
1058 };
1059
1060 uart3: serial@11001400 {
1061 compatible = "mediatek,mt8195-uart",
1062 "mediatek,mt6577-uart";
1063 reg = <0 0x11001400 0 0x100>;
1064 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1065 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1066 clock-names = "baud", "bus";
1067 status = "disabled";
1068 };
1069
1070 uart4: serial@11001500 {
1071 compatible = "mediatek,mt8195-uart",
1072 "mediatek,mt6577-uart";
1073 reg = <0 0x11001500 0 0x100>;
1074 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1075 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1076 clock-names = "baud", "bus";
1077 status = "disabled";
1078 };
1079
1080 uart5: serial@11001600 {
1081 compatible = "mediatek,mt8195-uart",
1082 "mediatek,mt6577-uart";
1083 reg = <0 0x11001600 0 0x100>;
1084 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1085 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1086 clock-names = "baud", "bus";
1087 status = "disabled";
1088 };
1089
1090 auxadc: auxadc@11002000 {
1091 compatible = "mediatek,mt8195-auxadc",
1092 "mediatek,mt8173-auxadc";
1093 reg = <0 0x11002000 0 0x1000>;
1094 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1095 clock-names = "main";
1096 #io-channel-cells = <1>;
1097 status = "disabled";
1098 };
1099
1100 pericfg_ao: syscon@11003000 {
1101 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1102 reg = <0 0x11003000 0 0x1000>;
1103 #clock-cells = <1>;
1104 };
1105
1106 spi0: spi@1100a000 {
1107 compatible = "mediatek,mt8195-spi",
1108 "mediatek,mt6765-spi";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 reg = <0 0x1100a000 0 0x1000>;
1112 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1113 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114 <&topckgen CLK_TOP_SPI>,
1115 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1116 clock-names = "parent-clk", "sel-clk", "spi-clk";
1117 status = "disabled";
1118 };
1119
1120 lvts_ap: thermal-sensor@1100b000 {
1121 compatible = "mediatek,mt8195-lvts-ap";
1122 reg = <0 0x1100b000 0 0xc00>;
1123 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1124 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1125 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1126 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1129 };
1130
1131 svs: svs@1100bc00 {
1132 compatible = "mediatek,mt8195-svs";
1133 reg = <0 0x1100bc00 0 0x400>;
1134 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
1135 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1136 clock-names = "main";
1137 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1138 nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1139 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
1140 reset-names = "svs_rst";
1141 };
1142
1143 disp_pwm0: pwm@1100e000 {
1144 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1145 reg = <0 0x1100e000 0 0x1000>;
1146 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1147 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148 #pwm-cells = <2>;
1149 clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1150 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1151 clock-names = "main", "mm";
1152 status = "disabled";
1153 };
1154
1155 disp_pwm1: pwm@1100f000 {
1156 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1157 reg = <0 0x1100f000 0 0x1000>;
1158 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1159 #pwm-cells = <2>;
1160 clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1161 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1162 clock-names = "main", "mm";
1163 status = "disabled";
1164 };
1165
1166 spi1: spi@11010000 {
1167 compatible = "mediatek,mt8195-spi",
1168 "mediatek,mt6765-spi";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1171 reg = <0 0x11010000 0 0x1000>;
1172 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1173 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174 <&topckgen CLK_TOP_SPI>,
1175 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1176 clock-names = "parent-clk", "sel-clk", "spi-clk";
1177 status = "disabled";
1178 };
1179
1180 spi2: spi@11012000 {
1181 compatible = "mediatek,mt8195-spi",
1182 "mediatek,mt6765-spi";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 reg = <0 0x11012000 0 0x1000>;
1186 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1187 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188 <&topckgen CLK_TOP_SPI>,
1189 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1190 clock-names = "parent-clk", "sel-clk", "spi-clk";
1191 status = "disabled";
1192 };
1193
1194 spi3: spi@11013000 {
1195 compatible = "mediatek,mt8195-spi",
1196 "mediatek,mt6765-spi";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 reg = <0 0x11013000 0 0x1000>;
1200 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1201 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202 <&topckgen CLK_TOP_SPI>,
1203 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1204 clock-names = "parent-clk", "sel-clk", "spi-clk";
1205 status = "disabled";
1206 };
1207
1208 spi4: spi@11018000 {
1209 compatible = "mediatek,mt8195-spi",
1210 "mediatek,mt6765-spi";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 reg = <0 0x11018000 0 0x1000>;
1214 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1215 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216 <&topckgen CLK_TOP_SPI>,
1217 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1218 clock-names = "parent-clk", "sel-clk", "spi-clk";
1219 status = "disabled";
1220 };
1221
1222 spi5: spi@11019000 {
1223 compatible = "mediatek,mt8195-spi",
1224 "mediatek,mt6765-spi";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227 reg = <0 0x11019000 0 0x1000>;
1228 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1229 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230 <&topckgen CLK_TOP_SPI>,
1231 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1232 clock-names = "parent-clk", "sel-clk", "spi-clk";
1233 status = "disabled";
1234 };
1235
1236 spis0: spi@1101d000 {
1237 compatible = "mediatek,mt8195-spi-slave";
1238 reg = <0 0x1101d000 0 0x1000>;
1239 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1240 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1241 clock-names = "spi";
1242 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1244 status = "disabled";
1245 };
1246
1247 spis1: spi@1101e000 {
1248 compatible = "mediatek,mt8195-spi-slave";
1249 reg = <0 0x1101e000 0 0x1000>;
1250 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1251 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1252 clock-names = "spi";
1253 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1255 status = "disabled";
1256 };
1257
1258 eth: ethernet@11021000 {
1259 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1260 reg = <0 0x11021000 0 0x4000>;
1261 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1262 interrupt-names = "macirq";
1263 clock-names = "axi",
1264 "apb",
1265 "mac_main",
1266 "ptp_ref",
1267 "rmii_internal",
1268 "mac_cg";
1269 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1270 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1271 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1272 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1273 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1274 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1275 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1276 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1277 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1278 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1279 <&topckgen CLK_TOP_ETHPLL_D8>,
1280 <&topckgen CLK_TOP_ETHPLL_D10>;
1281 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1282 mediatek,pericfg = <&infracfg_ao>;
1283 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,mtl-rx-config = <&mtl_rx_setup>;
1285 snps,mtl-tx-config = <&mtl_tx_setup>;
1286 snps,txpbl = <16>;
1287 snps,rxpbl = <16>;
1288 snps,clk-csr = <0>;
1289 status = "disabled";
1290
1291 mdio {
1292 compatible = "snps,dwmac-mdio";
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1295 };
1296
1297 stmmac_axi_setup: stmmac-axi-config {
1298 snps,wr_osr_lmt = <0x7>;
1299 snps,rd_osr_lmt = <0x7>;
1300 snps,blen = <0 0 0 0 16 8 4>;
1301 };
1302
1303 mtl_rx_setup: rx-queues-config {
1304 snps,rx-queues-to-use = <4>;
1305 snps,rx-sched-sp;
1306 queue0 {
1307 snps,dcb-algorithm;
1308 snps,map-to-dma-channel = <0x0>;
1309 };
1310 queue1 {
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1313 };
1314 queue2 {
1315 snps,dcb-algorithm;
1316 snps,map-to-dma-channel = <0x0>;
1317 };
1318 queue3 {
1319 snps,dcb-algorithm;
1320 snps,map-to-dma-channel = <0x0>;
1321 };
1322 };
1323
1324 mtl_tx_setup: tx-queues-config {
1325 snps,tx-queues-to-use = <4>;
1326 snps,tx-sched-wrr;
1327 queue0 {
1328 snps,weight = <0x10>;
1329 snps,dcb-algorithm;
1330 snps,priority = <0x0>;
1331 };
1332 queue1 {
1333 snps,weight = <0x11>;
1334 snps,dcb-algorithm;
1335 snps,priority = <0x1>;
1336 };
1337 queue2 {
1338 snps,weight = <0x12>;
1339 snps,dcb-algorithm;
1340 snps,priority = <0x2>;
1341 };
1342 queue3 {
1343 snps,weight = <0x13>;
1344 snps,dcb-algorithm;
1345 snps,priority = <0x3>;
1346 };
1347 };
1348 };
1349
1350 ssusb0: usb@11201000 {
1351 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1352 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1353 reg-names = "mac", "ippc";
1354 ranges = <0 0 0 0x11200000 0 0x3f00>;
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1357 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
1358 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1359 <&topckgen CLK_TOP_SSUSB_REF>,
1360 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1361 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1362 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
1363 wakeup-source;
1364 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1365 status = "disabled";
1366
1367 xhci0: usb@0 {
1368 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1369 reg = <0 0 0 0x1000>;
1370 reg-names = "mac";
1371 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1372 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1373 <&topckgen CLK_TOP_SSUSB_XHCI>;
1374 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1375 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1376 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1377 <&topckgen CLK_TOP_SSUSB_REF>,
1378 <&apmixedsys CLK_APMIXED_USB1PLL>,
1379 <&clk26m>,
1380 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1381 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1382 status = "disabled";
1383 };
1384 };
1385
1386 mmc0: mmc@11230000 {
1387 compatible = "mediatek,mt8195-mmc",
1388 "mediatek,mt8183-mmc";
1389 reg = <0 0x11230000 0 0x10000>,
1390 <0 0x11f50000 0 0x1000>;
1391 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1392 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1393 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1394 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1395 clock-names = "source", "hclk", "source_cg";
1396 status = "disabled";
1397 };
1398
1399 mmc1: mmc@11240000 {
1400 compatible = "mediatek,mt8195-mmc",
1401 "mediatek,mt8183-mmc";
1402 reg = <0 0x11240000 0 0x1000>,
1403 <0 0x11c70000 0 0x1000>;
1404 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1405 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1406 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1407 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1408 clock-names = "source", "hclk", "source_cg";
1409 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1410 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1411 status = "disabled";
1412 };
1413
1414 mmc2: mmc@11250000 {
1415 compatible = "mediatek,mt8195-mmc",
1416 "mediatek,mt8183-mmc";
1417 reg = <0 0x11250000 0 0x1000>,
1418 <0 0x11e60000 0 0x1000>;
1419 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1420 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1421 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1422 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1423 clock-names = "source", "hclk", "source_cg";
1424 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1425 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1426 status = "disabled";
1427 };
1428
1429 lvts_mcu: thermal-sensor@11278000 {
1430 compatible = "mediatek,mt8195-lvts-mcu";
1431 reg = <0 0x11278000 0 0x1000>;
1432 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1433 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1434 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1435 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1436 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1437 #thermal-sensor-cells = <1>;
1438 };
1439
1440 xhci1: usb@11290000 {
1441 compatible = "mediatek,mt8195-xhci",
1442 "mediatek,mtk-xhci";
1443 reg = <0 0x11290000 0 0x1000>,
1444 <0 0x11293e00 0 0x0100>;
1445 reg-names = "mac", "ippc";
1446 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1447 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
1448 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1449 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1451 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1452 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1453 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1454 <&apmixedsys CLK_APMIXED_USB1PLL>,
1455 <&clk26m>,
1456 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1457 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1458 "xhci_ck";
1459 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1460 wakeup-source;
1461 status = "disabled";
1462 };
1463
1464 ssusb2: usb@112a1000 {
1465 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1466 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
1467 reg-names = "mac", "ippc";
1468 ranges = <0 0 0 0x112a0000 0 0x3f00>;
1469 #address-cells = <2>;
1470 #size-cells = <2>;
1471 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
1472 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
1473 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1474 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1475 <&topckgen CLK_TOP_SSUSB_P2_REF>,
1476 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1477 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1478 phys = <&u2port2 PHY_TYPE_USB2>;
1479 wakeup-source;
1480 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1481 status = "disabled";
1482
1483 xhci2: usb@0 {
1484 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1485 reg = <0 0 0 0x1000>;
1486 reg-names = "mac";
1487 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1488 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1489 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1490 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1491 clock-names = "sys_ck";
1492 status = "disabled";
1493 };
1494 };
1495
1496 ssusb3: usb@112b1000 {
1497 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3";
1498 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
1499 reg-names = "mac", "ippc";
1500 ranges = <0 0 0 0x112b0000 0 0x3f00>;
1501 #address-cells = <2>;
1502 #size-cells = <2>;
1503 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
1504 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
1505 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1506 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1507 <&topckgen CLK_TOP_SSUSB_P3_REF>,
1508 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1509 clock-names = "sys_ck", "ref_ck", "mcu_ck";
1510 phys = <&u2port3 PHY_TYPE_USB2>;
1511 wakeup-source;
1512 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1513 status = "disabled";
1514
1515 xhci3: usb@0 {
1516 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
1517 reg = <0 0 0 0x1000>;
1518 reg-names = "mac";
1519 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1520 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1521 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1522 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1523 clock-names = "sys_ck";
1524 status = "disabled";
1525 };
1526 };
1527
1528 pcie0: pcie@112f0000 {
1529 compatible = "mediatek,mt8195-pcie",
1530 "mediatek,mt8192-pcie";
1531 device_type = "pci";
1532 #address-cells = <3>;
1533 #size-cells = <2>;
1534 reg = <0 0x112f0000 0 0x4000>;
1535 reg-names = "pcie-mac";
1536 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1537 bus-range = <0x00 0xff>;
1538 ranges = <0x81000000 0 0x20000000
1539 0x0 0x20000000 0 0x200000>,
1540 <0x82000000 0 0x20200000
1541 0x0 0x20200000 0 0x3e00000>;
1542
1543 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1544 iommu-map-mask = <0x0>;
1545
1546 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1547 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1548 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1549 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1550 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1551 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1552 clock-names = "pl_250m", "tl_26m", "tl_96m",
1553 "tl_32k", "peri_26m", "peri_mem";
1554 assigned-clocks = <&topckgen CLK_TOP_TL>;
1555 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1556
1557 phys = <&pciephy>;
1558 phy-names = "pcie-phy";
1559
1560 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1561
1562 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1563 reset-names = "mac";
1564
1565 #interrupt-cells = <1>;
1566 interrupt-map-mask = <0 0 0 7>;
1567 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1568 <0 0 0 2 &pcie_intc0 1>,
1569 <0 0 0 3 &pcie_intc0 2>,
1570 <0 0 0 4 &pcie_intc0 3>;
1571 status = "disabled";
1572
1573 pcie_intc0: interrupt-controller {
1574 interrupt-controller;
1575 #address-cells = <0>;
1576 #interrupt-cells = <1>;
1577 };
1578 };
1579
1580 pcie1: pcie@112f8000 {
1581 compatible = "mediatek,mt8195-pcie",
1582 "mediatek,mt8192-pcie";
1583 device_type = "pci";
1584 #address-cells = <3>;
1585 #size-cells = <2>;
1586 reg = <0 0x112f8000 0 0x4000>;
1587 reg-names = "pcie-mac";
1588 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1589 bus-range = <0x00 0xff>;
1590 ranges = <0x81000000 0 0x24000000
1591 0x0 0x24000000 0 0x200000>,
1592 <0x82000000 0 0x24200000
1593 0x0 0x24200000 0 0x3e00000>;
1594
1595 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1596 iommu-map-mask = <0x0>;
1597
1598 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1599 <&clk26m>,
1600 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1601 <&clk26m>,
1602 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1603 /* Designer has connect pcie1 with peri_mem_p0 clock */
1604 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1605 clock-names = "pl_250m", "tl_26m", "tl_96m",
1606 "tl_32k", "peri_26m", "peri_mem";
1607 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1608 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1609
1610 phys = <&u3port1 PHY_TYPE_PCIE>;
1611 phy-names = "pcie-phy";
1612 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1613
1614 #interrupt-cells = <1>;
1615 interrupt-map-mask = <0 0 0 7>;
1616 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1617 <0 0 0 2 &pcie_intc1 1>,
1618 <0 0 0 3 &pcie_intc1 2>,
1619 <0 0 0 4 &pcie_intc1 3>;
1620 status = "disabled";
1621
1622 pcie_intc1: interrupt-controller {
1623 interrupt-controller;
1624 #address-cells = <0>;
1625 #interrupt-cells = <1>;
1626 };
1627 };
1628
1629 nor_flash: spi@1132c000 {
1630 compatible = "mediatek,mt8195-nor",
1631 "mediatek,mt8173-nor";
1632 reg = <0 0x1132c000 0 0x1000>;
1633 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1634 clocks = <&topckgen CLK_TOP_SPINOR>,
1635 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1636 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1637 clock-names = "spi", "sf", "axi";
1638 #address-cells = <1>;
1639 #size-cells = <0>;
1640 status = "disabled";
1641 };
1642
1643 efuse: efuse@11c10000 {
1644 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1645 reg = <0 0x11c10000 0 0x1000>;
1646 #address-cells = <1>;
1647 #size-cells = <1>;
1648 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1649 reg = <0x184 0x1>;
1650 bits = <0 5>;
1651 };
1652 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1653 reg = <0x184 0x2>;
1654 bits = <5 5>;
1655 };
1656 u3_intr_p0: usb3-intr@185 {
1657 reg = <0x185 0x1>;
1658 bits = <2 6>;
1659 };
1660 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1661 reg = <0x186 0x1>;
1662 bits = <0 5>;
1663 };
1664 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1665 reg = <0x186 0x2>;
1666 bits = <5 5>;
1667 };
1668 comb_intr_p1: usb3-intr@187 {
1669 reg = <0x187 0x1>;
1670 bits = <2 6>;
1671 };
1672 u2_intr_p0: usb2-intr-p0@188,1 {
1673 reg = <0x188 0x1>;
1674 bits = <0 5>;
1675 };
1676 u2_intr_p1: usb2-intr-p1@188,2 {
1677 reg = <0x188 0x2>;
1678 bits = <5 5>;
1679 };
1680 u2_intr_p2: usb2-intr-p2@189,1 {
1681 reg = <0x189 0x1>;
1682 bits = <2 5>;
1683 };
1684 u2_intr_p3: usb2-intr-p3@189,2 {
1685 reg = <0x189 0x2>;
1686 bits = <7 5>;
1687 };
1688 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1689 reg = <0x190 0x1>;
1690 bits = <0 4>;
1691 };
1692 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1693 reg = <0x190 0x1>;
1694 bits = <4 4>;
1695 };
1696 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1697 reg = <0x191 0x1>;
1698 bits = <0 4>;
1699 };
1700 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1701 reg = <0x191 0x1>;
1702 bits = <4 4>;
1703 };
1704 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1705 reg = <0x192 0x1>;
1706 bits = <0 4>;
1707 };
1708 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1709 reg = <0x192 0x1>;
1710 bits = <4 4>;
1711 };
1712 pciephy_glb_intr: pciephy-glb-intr@193 {
1713 reg = <0x193 0x1>;
1714 bits = <0 4>;
1715 };
1716 dp_calibration: dp-data@1ac {
1717 reg = <0x1ac 0x10>;
1718 };
1719 lvts_efuse_data1: lvts1-calib@1bc {
1720 reg = <0x1bc 0x14>;
1721 };
1722 lvts_efuse_data2: lvts2-calib@1d0 {
1723 reg = <0x1d0 0x38>;
1724 };
1725 svs_calib_data: svs-calib@580 {
1726 reg = <0x580 0x64>;
1727 };
1728 socinfo-data1@7a0 {
1729 reg = <0x7a0 0x4>;
1730 };
1731 };
1732
1733 u3phy2: t-phy@11c40000 {
1734 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1735 #address-cells = <1>;
1736 #size-cells = <1>;
1737 ranges = <0 0 0x11c40000 0x700>;
1738 status = "disabled";
1739
1740 u2port2: usb-phy@0 {
1741 reg = <0x0 0x700>;
1742 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1743 clock-names = "ref";
1744 #phy-cells = <1>;
1745 };
1746 };
1747
1748 u3phy3: t-phy@11c50000 {
1749 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1750 #address-cells = <1>;
1751 #size-cells = <1>;
1752 ranges = <0 0 0x11c50000 0x700>;
1753 status = "disabled";
1754
1755 u2port3: usb-phy@0 {
1756 reg = <0x0 0x700>;
1757 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1758 clock-names = "ref";
1759 #phy-cells = <1>;
1760 };
1761 };
1762
1763 mipi_tx0: dsi-phy@11c80000 {
1764 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1765 reg = <0 0x11c80000 0 0x1000>;
1766 clocks = <&clk26m>;
1767 clock-output-names = "mipi_tx0_pll";
1768 #clock-cells = <0>;
1769 #phy-cells = <0>;
1770 status = "disabled";
1771 };
1772
1773 mipi_tx1: dsi-phy@11c90000 {
1774 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1775 reg = <0 0x11c90000 0 0x1000>;
1776 clocks = <&clk26m>;
1777 clock-output-names = "mipi_tx1_pll";
1778 #clock-cells = <0>;
1779 #phy-cells = <0>;
1780 status = "disabled";
1781 };
1782
1783 i2c5: i2c@11d00000 {
1784 compatible = "mediatek,mt8195-i2c",
1785 "mediatek,mt8192-i2c";
1786 reg = <0 0x11d00000 0 0x1000>,
1787 <0 0x10220580 0 0x80>;
1788 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1789 clock-div = <1>;
1790 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1791 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1792 clock-names = "main", "dma";
1793 #address-cells = <1>;
1794 #size-cells = <0>;
1795 status = "disabled";
1796 };
1797
1798 i2c6: i2c@11d01000 {
1799 compatible = "mediatek,mt8195-i2c",
1800 "mediatek,mt8192-i2c";
1801 reg = <0 0x11d01000 0 0x1000>,
1802 <0 0x10220600 0 0x80>;
1803 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1804 clock-div = <1>;
1805 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1806 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1807 clock-names = "main", "dma";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1810 status = "disabled";
1811 };
1812
1813 i2c7: i2c@11d02000 {
1814 compatible = "mediatek,mt8195-i2c",
1815 "mediatek,mt8192-i2c";
1816 reg = <0 0x11d02000 0 0x1000>,
1817 <0 0x10220680 0 0x80>;
1818 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1819 clock-div = <1>;
1820 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1821 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1822 clock-names = "main", "dma";
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1825 status = "disabled";
1826 };
1827
1828 imp_iic_wrap_s: clock-controller@11d03000 {
1829 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1830 reg = <0 0x11d03000 0 0x1000>;
1831 #clock-cells = <1>;
1832 };
1833
1834 i2c0: i2c@11e00000 {
1835 compatible = "mediatek,mt8195-i2c",
1836 "mediatek,mt8192-i2c";
1837 reg = <0 0x11e00000 0 0x1000>,
1838 <0 0x10220080 0 0x80>;
1839 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1840 clock-div = <1>;
1841 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1842 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1843 clock-names = "main", "dma";
1844 #address-cells = <1>;
1845 #size-cells = <0>;
1846 status = "disabled";
1847 };
1848
1849 i2c1: i2c@11e01000 {
1850 compatible = "mediatek,mt8195-i2c",
1851 "mediatek,mt8192-i2c";
1852 reg = <0 0x11e01000 0 0x1000>,
1853 <0 0x10220200 0 0x80>;
1854 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1855 clock-div = <1>;
1856 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1857 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1858 clock-names = "main", "dma";
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1861 status = "disabled";
1862 };
1863
1864 i2c2: i2c@11e02000 {
1865 compatible = "mediatek,mt8195-i2c",
1866 "mediatek,mt8192-i2c";
1867 reg = <0 0x11e02000 0 0x1000>,
1868 <0 0x10220380 0 0x80>;
1869 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1870 clock-div = <1>;
1871 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1872 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1873 clock-names = "main", "dma";
1874 #address-cells = <1>;
1875 #size-cells = <0>;
1876 status = "disabled";
1877 };
1878
1879 i2c3: i2c@11e03000 {
1880 compatible = "mediatek,mt8195-i2c",
1881 "mediatek,mt8192-i2c";
1882 reg = <0 0x11e03000 0 0x1000>,
1883 <0 0x10220480 0 0x80>;
1884 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1885 clock-div = <1>;
1886 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1887 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1888 clock-names = "main", "dma";
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1891 status = "disabled";
1892 };
1893
1894 i2c4: i2c@11e04000 {
1895 compatible = "mediatek,mt8195-i2c",
1896 "mediatek,mt8192-i2c";
1897 reg = <0 0x11e04000 0 0x1000>,
1898 <0 0x10220500 0 0x80>;
1899 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1900 clock-div = <1>;
1901 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1902 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1903 clock-names = "main", "dma";
1904 #address-cells = <1>;
1905 #size-cells = <0>;
1906 status = "disabled";
1907 };
1908
1909 imp_iic_wrap_w: clock-controller@11e05000 {
1910 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1911 reg = <0 0x11e05000 0 0x1000>;
1912 #clock-cells = <1>;
1913 };
1914
1915 u3phy1: t-phy@11e30000 {
1916 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1917 #address-cells = <1>;
1918 #size-cells = <1>;
1919 ranges = <0 0 0x11e30000 0xe00>;
1920 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1921 status = "disabled";
1922
1923 u2port1: usb-phy@0 {
1924 reg = <0x0 0x700>;
1925 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1926 <&clk26m>;
1927 clock-names = "ref", "da_ref";
1928 #phy-cells = <1>;
1929 };
1930
1931 u3port1: usb-phy@700 {
1932 reg = <0x700 0x700>;
1933 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1934 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1935 clock-names = "ref", "da_ref";
1936 nvmem-cells = <&comb_intr_p1>,
1937 <&comb_rx_imp_p1>,
1938 <&comb_tx_imp_p1>;
1939 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1940 #phy-cells = <1>;
1941 };
1942 };
1943
1944 u3phy0: t-phy@11e40000 {
1945 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1946 #address-cells = <1>;
1947 #size-cells = <1>;
1948 ranges = <0 0 0x11e40000 0xe00>;
1949 status = "disabled";
1950
1951 u2port0: usb-phy@0 {
1952 reg = <0x0 0x700>;
1953 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1954 <&clk26m>;
1955 clock-names = "ref", "da_ref";
1956 #phy-cells = <1>;
1957 };
1958
1959 u3port0: usb-phy@700 {
1960 reg = <0x700 0x700>;
1961 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1962 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1963 clock-names = "ref", "da_ref";
1964 nvmem-cells = <&u3_intr_p0>,
1965 <&u3_rx_imp_p0>,
1966 <&u3_tx_imp_p0>;
1967 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1968 #phy-cells = <1>;
1969 };
1970 };
1971
1972 pciephy: phy@11e80000 {
1973 compatible = "mediatek,mt8195-pcie-phy";
1974 reg = <0 0x11e80000 0 0x10000>;
1975 reg-names = "sif";
1976 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1977 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1978 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1979 <&pciephy_rx_ln1>;
1980 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1981 "tx_ln0_nmos", "rx_ln0",
1982 "tx_ln1_pmos", "tx_ln1_nmos",
1983 "rx_ln1";
1984 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1985 #phy-cells = <0>;
1986 status = "disabled";
1987 };
1988
1989 ufsphy: ufs-phy@11fa0000 {
1990 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1991 reg = <0 0x11fa0000 0 0xc000>;
1992 clocks = <&clk26m>, <&clk26m>;
1993 clock-names = "unipro", "mp";
1994 #phy-cells = <0>;
1995 status = "disabled";
1996 };
1997
1998 gpu: gpu@13000000 {
1999 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
2000 "arm,mali-valhall-jm";
2001 reg = <0 0x13000000 0 0x4000>;
2002
2003 clocks = <&mfgcfg CLK_MFG_BG3D>;
2004 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
2005 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
2006 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
2007 interrupt-names = "job", "mmu", "gpu";
2008 operating-points-v2 = <&gpu_opp_table>;
2009 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
2010 <&spm MT8195_POWER_DOMAIN_MFG3>,
2011 <&spm MT8195_POWER_DOMAIN_MFG4>,
2012 <&spm MT8195_POWER_DOMAIN_MFG5>,
2013 <&spm MT8195_POWER_DOMAIN_MFG6>;
2014 power-domain-names = "core0", "core1", "core2", "core3", "core4";
2015 status = "disabled";
2016 };
2017
2018 mfgcfg: clock-controller@13fbf000 {
2019 compatible = "mediatek,mt8195-mfgcfg";
2020 reg = <0 0x13fbf000 0 0x1000>;
2021 #clock-cells = <1>;
2022 };
2023
2024 vppsys0: syscon@14000000 {
2025 compatible = "mediatek,mt8195-vppsys0", "syscon";
2026 reg = <0 0x14000000 0 0x1000>;
2027 #clock-cells = <1>;
2028 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2029 };
2030
2031 dma-controller@14001000 {
2032 compatible = "mediatek,mt8195-mdp3-rdma";
2033 reg = <0 0x14001000 0 0x1000>;
2034 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2035 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2036 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
2037 mediatek,scp = <&scp>;
2038 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2039 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
2040 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2041 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
2042 <&gce1 13 CMDQ_THR_PRIO_1>,
2043 <&gce1 14 CMDQ_THR_PRIO_1>,
2044 <&gce1 21 CMDQ_THR_PRIO_1>,
2045 <&gce1 22 CMDQ_THR_PRIO_1>;
2046 #dma-cells = <1>;
2047 };
2048
2049 display@14002000 {
2050 compatible = "mediatek,mt8195-mdp3-fg";
2051 reg = <0 0x14002000 0 0x1000>;
2052 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2053 clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
2054 };
2055
2056 display@14003000 {
2057 compatible = "mediatek,mt8195-mdp3-stitch";
2058 reg = <0 0x14003000 0 0x1000>;
2059 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2060 clocks = <&vppsys0 CLK_VPP0_STITCH>;
2061 };
2062
2063 display@14004000 {
2064 compatible = "mediatek,mt8195-mdp3-hdr";
2065 reg = <0 0x14004000 0 0x1000>;
2066 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2067 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2068 };
2069
2070 display@14005000 {
2071 compatible = "mediatek,mt8195-mdp3-aal";
2072 reg = <0 0x14005000 0 0x1000>;
2073 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
2074 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2075 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
2076 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2077 };
2078
2079 display@14006000 {
2080 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2081 reg = <0 0x14006000 0 0x1000>;
2082 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2083 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2084 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
2085 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2086 };
2087
2088 display@14007000 {
2089 compatible = "mediatek,mt8195-mdp3-tdshp";
2090 reg = <0 0x14007000 0 0x1000>;
2091 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2092 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2093 };
2094
2095 display@14008000 {
2096 compatible = "mediatek,mt8195-mdp3-color";
2097 reg = <0 0x14008000 0 0x1000>;
2098 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
2099 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2100 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
2101 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2102 };
2103
2104 display@14009000 {
2105 compatible = "mediatek,mt8195-mdp3-ovl";
2106 reg = <0 0x14009000 0 0x1000>;
2107 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
2108 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2109 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
2110 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2111 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
2112 };
2113
2114 display@1400a000 {
2115 compatible = "mediatek,mt8195-mdp3-padding";
2116 reg = <0 0x1400a000 0 0x1000>;
2117 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2118 clocks = <&vppsys0 CLK_VPP0_PADDING>;
2119 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2120 };
2121
2122 display@1400b000 {
2123 compatible = "mediatek,mt8195-mdp3-tcc";
2124 reg = <0 0x1400b000 0 0x1000>;
2125 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2126 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2127 };
2128
2129 dma-controller@1400c000 {
2130 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2131 reg = <0 0x1400c000 0 0x1000>;
2132 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2133 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2134 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
2135 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
2136 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
2137 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2138 #dma-cells = <1>;
2139 };
2140
2141 mutex@1400f000 {
2142 compatible = "mediatek,mt8195-vpp-mutex";
2143 reg = <0 0x1400f000 0 0x1000>;
2144 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
2145 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2146 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
2147 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2148 };
2149
2150 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
2151 compatible = "mediatek,mt8195-smi-sub-common";
2152 reg = <0 0x14010000 0 0x1000>;
2153 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2154 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2155 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2156 clock-names = "apb", "smi", "gals0";
2157 mediatek,smi = <&smi_common_vpp>;
2158 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2159 };
2160
2161 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
2162 compatible = "mediatek,mt8195-smi-sub-common";
2163 reg = <0 0x14011000 0 0x1000>;
2164 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2165 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2166 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2167 clock-names = "apb", "smi", "gals0";
2168 mediatek,smi = <&smi_common_vpp>;
2169 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2170 };
2171
2172 smi_common_vpp: smi@14012000 {
2173 compatible = "mediatek,mt8195-smi-common-vpp";
2174 reg = <0 0x14012000 0 0x1000>;
2175 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2176 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2177 <&vppsys0 CLK_VPP0_SMI_RSI>,
2178 <&vppsys0 CLK_VPP0_SMI_RSI>;
2179 clock-names = "apb", "smi", "gals0", "gals1";
2180 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2181 };
2182
2183 larb4: larb@14013000 {
2184 compatible = "mediatek,mt8195-smi-larb";
2185 reg = <0 0x14013000 0 0x1000>;
2186 mediatek,larb-id = <4>;
2187 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2188 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2189 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2190 clock-names = "apb", "smi";
2191 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2192 };
2193
2194 iommu_vpp: iommu@14018000 {
2195 compatible = "mediatek,mt8195-iommu-vpp";
2196 reg = <0 0x14018000 0 0x1000>;
2197 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2198 &larb12 &larb14 &larb16 &larb18
2199 &larb20 &larb22 &larb23 &larb26
2200 &larb27>;
2201 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2202 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2203 clock-names = "bclk";
2204 #iommu-cells = <1>;
2205 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2206 };
2207
2208 wpesys: clock-controller@14e00000 {
2209 compatible = "mediatek,mt8195-wpesys";
2210 reg = <0 0x14e00000 0 0x1000>;
2211 #clock-cells = <1>;
2212 };
2213
2214 wpesys_vpp0: clock-controller@14e02000 {
2215 compatible = "mediatek,mt8195-wpesys_vpp0";
2216 reg = <0 0x14e02000 0 0x1000>;
2217 #clock-cells = <1>;
2218 };
2219
2220 wpesys_vpp1: clock-controller@14e03000 {
2221 compatible = "mediatek,mt8195-wpesys_vpp1";
2222 reg = <0 0x14e03000 0 0x1000>;
2223 #clock-cells = <1>;
2224 };
2225
2226 larb7: larb@14e04000 {
2227 compatible = "mediatek,mt8195-smi-larb";
2228 reg = <0 0x14e04000 0 0x1000>;
2229 mediatek,larb-id = <7>;
2230 mediatek,smi = <&smi_common_vdo>;
2231 clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2232 <&wpesys CLK_WPE_SMI_LARB7>;
2233 clock-names = "apb", "smi";
2234 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2235 };
2236
2237 larb8: larb@14e05000 {
2238 compatible = "mediatek,mt8195-smi-larb";
2239 reg = <0 0x14e05000 0 0x1000>;
2240 mediatek,larb-id = <8>;
2241 mediatek,smi = <&smi_common_vpp>;
2242 clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2243 <&wpesys CLK_WPE_SMI_LARB8>,
2244 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2245 clock-names = "apb", "smi", "gals";
2246 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2247 };
2248
2249 vppsys1: syscon@14f00000 {
2250 compatible = "mediatek,mt8195-vppsys1", "syscon";
2251 reg = <0 0x14f00000 0 0x1000>;
2252 #clock-cells = <1>;
2253 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2254 };
2255
2256 mutex@14f01000 {
2257 compatible = "mediatek,mt8195-vpp-mutex";
2258 reg = <0 0x14f01000 0 0x1000>;
2259 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2260 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2261 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
2262 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2263 };
2264
2265 larb5: larb@14f02000 {
2266 compatible = "mediatek,mt8195-smi-larb";
2267 reg = <0 0x14f02000 0 0x1000>;
2268 mediatek,larb-id = <5>;
2269 mediatek,smi = <&smi_common_vdo>;
2270 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2271 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2272 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2273 clock-names = "apb", "smi", "gals";
2274 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2275 };
2276
2277 larb6: larb@14f03000 {
2278 compatible = "mediatek,mt8195-smi-larb";
2279 reg = <0 0x14f03000 0 0x1000>;
2280 mediatek,larb-id = <6>;
2281 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2282 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2283 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2284 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2285 clock-names = "apb", "smi", "gals";
2286 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2287 };
2288
2289 display@14f06000 {
2290 compatible = "mediatek,mt8195-mdp3-split";
2291 reg = <0 0x14f06000 0 0x1000>;
2292 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2293 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
2294 <&vppsys1 CLK_VPP1_HDMI_META>,
2295 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
2296 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2297 };
2298
2299 display@14f07000 {
2300 compatible = "mediatek,mt8195-mdp3-tcc";
2301 reg = <0 0x14f07000 0 0x1000>;
2302 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2303 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
2304 };
2305
2306 dma-controller@14f08000 {
2307 compatible = "mediatek,mt8195-mdp3-rdma";
2308 reg = <0 0x14f08000 0 0x1000>;
2309 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2310 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2311 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
2312 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
2313 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
2314 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2315 #dma-cells = <1>;
2316 };
2317
2318 dma-controller@14f09000 {
2319 compatible = "mediatek,mt8195-mdp3-rdma";
2320 reg = <0 0x14f09000 0 0x1000>;
2321 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2322 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2323 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
2324 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
2325 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
2326 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2327 #dma-cells = <1>;
2328 };
2329
2330 dma-controller@14f0a000 {
2331 compatible = "mediatek,mt8195-mdp3-rdma";
2332 reg = <0 0x14f0a000 0 0x1000>;
2333 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2334 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2335 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
2336 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
2337 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
2338 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2339 #dma-cells = <1>;
2340 };
2341
2342 display@14f0b000 {
2343 compatible = "mediatek,mt8195-mdp3-fg";
2344 reg = <0 0x14f0b000 0 0x1000>;
2345 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2346 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
2347 };
2348
2349 display@14f0c000 {
2350 compatible = "mediatek,mt8195-mdp3-fg";
2351 reg = <0 0x14f0c000 0 0x1000>;
2352 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2353 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
2354 };
2355
2356 display@14f0d000 {
2357 compatible = "mediatek,mt8195-mdp3-fg";
2358 reg = <0 0x14f0d000 0 0x1000>;
2359 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2360 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
2361 };
2362
2363 display@14f0e000 {
2364 compatible = "mediatek,mt8195-mdp3-hdr";
2365 reg = <0 0x14f0e000 0 0x1000>;
2366 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2367 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
2368 };
2369
2370 display@14f0f000 {
2371 compatible = "mediatek,mt8195-mdp3-hdr";
2372 reg = <0 0x14f0f000 0 0x1000>;
2373 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2374 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
2375 };
2376
2377 display@14f10000 {
2378 compatible = "mediatek,mt8195-mdp3-hdr";
2379 reg = <0 0x14f10000 0 0x1000>;
2380 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2381 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
2382 };
2383
2384 display@14f11000 {
2385 compatible = "mediatek,mt8195-mdp3-aal";
2386 reg = <0 0x14f11000 0 0x1000>;
2387 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
2388 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2389 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
2390 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2391 };
2392
2393 display@14f12000 {
2394 compatible = "mediatek,mt8195-mdp3-aal";
2395 reg = <0 0x14f12000 0 0x1000>;
2396 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
2397 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2398 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
2399 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2400 };
2401
2402 display@14f13000 {
2403 compatible = "mediatek,mt8195-mdp3-aal";
2404 reg = <0 0x14f13000 0 0x1000>;
2405 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
2406 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2407 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
2408 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2409 };
2410
2411 display@14f14000 {
2412 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2413 reg = <0 0x14f14000 0 0x1000>;
2414 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2415 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2416 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
2417 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
2418 };
2419
2420 display@14f15000 {
2421 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2422 reg = <0 0x14f15000 0 0x1000>;
2423 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2424 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2425 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
2426 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
2427 };
2428
2429 display@14f16000 {
2430 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2431 reg = <0 0x14f16000 0 0x1000>;
2432 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2433 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2434 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
2435 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
2436 };
2437
2438 display@14f17000 {
2439 compatible = "mediatek,mt8195-mdp3-tdshp";
2440 reg = <0 0x14f17000 0 0x1000>;
2441 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2442 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
2443 };
2444
2445 display@14f18000 {
2446 compatible = "mediatek,mt8195-mdp3-tdshp";
2447 reg = <0 0x14f18000 0 0x1000>;
2448 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2449 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
2450 };
2451
2452 display@14f19000 {
2453 compatible = "mediatek,mt8195-mdp3-tdshp";
2454 reg = <0 0x14f19000 0 0x1000>;
2455 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2456 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
2457 };
2458
2459 display@14f1a000 {
2460 compatible = "mediatek,mt8195-mdp3-merge";
2461 reg = <0 0x14f1a000 0 0x1000>;
2462 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2463 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
2464 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2465 };
2466
2467 display@14f1b000 {
2468 compatible = "mediatek,mt8195-mdp3-merge";
2469 reg = <0 0x14f1b000 0 0x1000>;
2470 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2471 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
2472 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2473 };
2474
2475 display@14f1c000 {
2476 compatible = "mediatek,mt8195-mdp3-color";
2477 reg = <0 0x14f1c000 0 0x1000>;
2478 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
2479 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2480 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
2481 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2482 };
2483
2484 display@14f1d000 {
2485 compatible = "mediatek,mt8195-mdp3-color";
2486 reg = <0 0x14f1d000 0 0x1000>;
2487 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2488 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
2489 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
2490 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2491 };
2492
2493 display@14f1e000 {
2494 compatible = "mediatek,mt8195-mdp3-color";
2495 reg = <0 0x14f1e000 0 0x1000>;
2496 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
2497 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2498 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
2499 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2500 };
2501
2502 display@14f1f000 {
2503 compatible = "mediatek,mt8195-mdp3-ovl";
2504 reg = <0 0x14f1f000 0 0x1000>;
2505 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
2506 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2507 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
2508 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2509 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
2510 };
2511
2512 display@14f20000 {
2513 compatible = "mediatek,mt8195-mdp3-padding";
2514 reg = <0 0x14f20000 0 0x1000>;
2515 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2516 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
2517 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2518 };
2519
2520 display@14f21000 {
2521 compatible = "mediatek,mt8195-mdp3-padding";
2522 reg = <0 0x14f21000 0 0x1000>;
2523 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2524 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
2525 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2526 };
2527
2528 display@14f22000 {
2529 compatible = "mediatek,mt8195-mdp3-padding";
2530 reg = <0 0x14f22000 0 0x1000>;
2531 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2532 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
2533 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2534 };
2535
2536 dma-controller@14f23000 {
2537 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2538 reg = <0 0x14f23000 0 0x1000>;
2539 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2540 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2541 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
2542 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
2543 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
2544 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2545 #dma-cells = <1>;
2546 };
2547
2548 dma-controller@14f24000 {
2549 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2550 reg = <0 0x14f24000 0 0x1000>;
2551 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2552 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2553 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
2554 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
2555 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
2556 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2557 #dma-cells = <1>;
2558 };
2559
2560 dma-controller@14f25000 {
2561 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2562 reg = <0 0x14f25000 0 0x1000>;
2563 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2564 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2565 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
2566 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
2567 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
2568 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2569 #dma-cells = <1>;
2570 };
2571
2572 imgsys: clock-controller@15000000 {
2573 compatible = "mediatek,mt8195-imgsys";
2574 reg = <0 0x15000000 0 0x1000>;
2575 #clock-cells = <1>;
2576 };
2577
2578 larb9: larb@15001000 {
2579 compatible = "mediatek,mt8195-smi-larb";
2580 reg = <0 0x15001000 0 0x1000>;
2581 mediatek,larb-id = <9>;
2582 mediatek,smi = <&smi_sub_common_img1_3x1>;
2583 clocks = <&imgsys CLK_IMG_LARB9>,
2584 <&imgsys CLK_IMG_LARB9>,
2585 <&imgsys CLK_IMG_GALS>;
2586 clock-names = "apb", "smi", "gals";
2587 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2588 };
2589
2590 smi_sub_common_img0_3x1: smi@15002000 {
2591 compatible = "mediatek,mt8195-smi-sub-common";
2592 reg = <0 0x15002000 0 0x1000>;
2593 clocks = <&imgsys CLK_IMG_IPE>,
2594 <&imgsys CLK_IMG_IPE>,
2595 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2596 clock-names = "apb", "smi", "gals0";
2597 mediatek,smi = <&smi_common_vpp>;
2598 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2599 };
2600
2601 smi_sub_common_img1_3x1: smi@15003000 {
2602 compatible = "mediatek,mt8195-smi-sub-common";
2603 reg = <0 0x15003000 0 0x1000>;
2604 clocks = <&imgsys CLK_IMG_LARB9>,
2605 <&imgsys CLK_IMG_LARB9>,
2606 <&imgsys CLK_IMG_GALS>;
2607 clock-names = "apb", "smi", "gals0";
2608 mediatek,smi = <&smi_common_vdo>;
2609 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2610 };
2611
2612 imgsys1_dip_top: clock-controller@15110000 {
2613 compatible = "mediatek,mt8195-imgsys1_dip_top";
2614 reg = <0 0x15110000 0 0x1000>;
2615 #clock-cells = <1>;
2616 };
2617
2618 larb10: larb@15120000 {
2619 compatible = "mediatek,mt8195-smi-larb";
2620 reg = <0 0x15120000 0 0x1000>;
2621 mediatek,larb-id = <10>;
2622 mediatek,smi = <&smi_sub_common_img1_3x1>;
2623 clocks = <&imgsys CLK_IMG_DIP0>,
2624 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2625 clock-names = "apb", "smi";
2626 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2627 };
2628
2629 imgsys1_dip_nr: clock-controller@15130000 {
2630 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2631 reg = <0 0x15130000 0 0x1000>;
2632 #clock-cells = <1>;
2633 };
2634
2635 imgsys1_wpe: clock-controller@15220000 {
2636 compatible = "mediatek,mt8195-imgsys1_wpe";
2637 reg = <0 0x15220000 0 0x1000>;
2638 #clock-cells = <1>;
2639 };
2640
2641 larb11: larb@15230000 {
2642 compatible = "mediatek,mt8195-smi-larb";
2643 reg = <0 0x15230000 0 0x1000>;
2644 mediatek,larb-id = <11>;
2645 mediatek,smi = <&smi_sub_common_img1_3x1>;
2646 clocks = <&imgsys CLK_IMG_WPE0>,
2647 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2648 clock-names = "apb", "smi";
2649 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2650 };
2651
2652 ipesys: clock-controller@15330000 {
2653 compatible = "mediatek,mt8195-ipesys";
2654 reg = <0 0x15330000 0 0x1000>;
2655 #clock-cells = <1>;
2656 };
2657
2658 larb12: larb@15340000 {
2659 compatible = "mediatek,mt8195-smi-larb";
2660 reg = <0 0x15340000 0 0x1000>;
2661 mediatek,larb-id = <12>;
2662 mediatek,smi = <&smi_sub_common_img0_3x1>;
2663 clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2664 <&ipesys CLK_IPE_SMI_LARB12>;
2665 clock-names = "apb", "smi";
2666 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2667 };
2668
2669 camsys: clock-controller@16000000 {
2670 compatible = "mediatek,mt8195-camsys";
2671 reg = <0 0x16000000 0 0x1000>;
2672 #clock-cells = <1>;
2673 };
2674
2675 larb13: larb@16001000 {
2676 compatible = "mediatek,mt8195-smi-larb";
2677 reg = <0 0x16001000 0 0x1000>;
2678 mediatek,larb-id = <13>;
2679 mediatek,smi = <&smi_sub_common_cam_4x1>;
2680 clocks = <&camsys CLK_CAM_LARB13>,
2681 <&camsys CLK_CAM_LARB13>,
2682 <&camsys CLK_CAM_CAM2MM0_GALS>;
2683 clock-names = "apb", "smi", "gals";
2684 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2685 };
2686
2687 larb14: larb@16002000 {
2688 compatible = "mediatek,mt8195-smi-larb";
2689 reg = <0 0x16002000 0 0x1000>;
2690 mediatek,larb-id = <14>;
2691 mediatek,smi = <&smi_sub_common_cam_7x1>;
2692 clocks = <&camsys CLK_CAM_LARB14>,
2693 <&camsys CLK_CAM_LARB14>;
2694 clock-names = "apb", "smi";
2695 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2696 };
2697
2698 smi_sub_common_cam_4x1: smi@16004000 {
2699 compatible = "mediatek,mt8195-smi-sub-common";
2700 reg = <0 0x16004000 0 0x1000>;
2701 clocks = <&camsys CLK_CAM_LARB13>,
2702 <&camsys CLK_CAM_LARB13>,
2703 <&camsys CLK_CAM_CAM2MM0_GALS>;
2704 clock-names = "apb", "smi", "gals0";
2705 mediatek,smi = <&smi_common_vdo>;
2706 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2707 };
2708
2709 smi_sub_common_cam_7x1: smi@16005000 {
2710 compatible = "mediatek,mt8195-smi-sub-common";
2711 reg = <0 0x16005000 0 0x1000>;
2712 clocks = <&camsys CLK_CAM_LARB14>,
2713 <&camsys CLK_CAM_CAM2MM1_GALS>,
2714 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2715 clock-names = "apb", "smi", "gals0";
2716 mediatek,smi = <&smi_common_vpp>;
2717 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2718 };
2719
2720 larb16: larb@16012000 {
2721 compatible = "mediatek,mt8195-smi-larb";
2722 reg = <0 0x16012000 0 0x1000>;
2723 mediatek,larb-id = <16>;
2724 mediatek,smi = <&smi_sub_common_cam_7x1>;
2725 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2726 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2727 clock-names = "apb", "smi";
2728 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2729 };
2730
2731 larb17: larb@16013000 {
2732 compatible = "mediatek,mt8195-smi-larb";
2733 reg = <0 0x16013000 0 0x1000>;
2734 mediatek,larb-id = <17>;
2735 mediatek,smi = <&smi_sub_common_cam_4x1>;
2736 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2737 <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2738 clock-names = "apb", "smi";
2739 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2740 };
2741
2742 larb27: larb@16014000 {
2743 compatible = "mediatek,mt8195-smi-larb";
2744 reg = <0 0x16014000 0 0x1000>;
2745 mediatek,larb-id = <27>;
2746 mediatek,smi = <&smi_sub_common_cam_7x1>;
2747 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2748 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2749 clock-names = "apb", "smi";
2750 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2751 };
2752
2753 larb28: larb@16015000 {
2754 compatible = "mediatek,mt8195-smi-larb";
2755 reg = <0 0x16015000 0 0x1000>;
2756 mediatek,larb-id = <28>;
2757 mediatek,smi = <&smi_sub_common_cam_4x1>;
2758 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2759 <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2760 clock-names = "apb", "smi";
2761 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2762 };
2763
2764 camsys_rawa: clock-controller@1604f000 {
2765 compatible = "mediatek,mt8195-camsys_rawa";
2766 reg = <0 0x1604f000 0 0x1000>;
2767 #clock-cells = <1>;
2768 };
2769
2770 camsys_yuva: clock-controller@1606f000 {
2771 compatible = "mediatek,mt8195-camsys_yuva";
2772 reg = <0 0x1606f000 0 0x1000>;
2773 #clock-cells = <1>;
2774 };
2775
2776 camsys_rawb: clock-controller@1608f000 {
2777 compatible = "mediatek,mt8195-camsys_rawb";
2778 reg = <0 0x1608f000 0 0x1000>;
2779 #clock-cells = <1>;
2780 };
2781
2782 camsys_yuvb: clock-controller@160af000 {
2783 compatible = "mediatek,mt8195-camsys_yuvb";
2784 reg = <0 0x160af000 0 0x1000>;
2785 #clock-cells = <1>;
2786 };
2787
2788 camsys_mraw: clock-controller@16140000 {
2789 compatible = "mediatek,mt8195-camsys_mraw";
2790 reg = <0 0x16140000 0 0x1000>;
2791 #clock-cells = <1>;
2792 };
2793
2794 larb25: larb@16141000 {
2795 compatible = "mediatek,mt8195-smi-larb";
2796 reg = <0 0x16141000 0 0x1000>;
2797 mediatek,larb-id = <25>;
2798 mediatek,smi = <&smi_sub_common_cam_4x1>;
2799 clocks = <&camsys CLK_CAM_LARB13>,
2800 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2801 <&camsys CLK_CAM_CAM2MM0_GALS>;
2802 clock-names = "apb", "smi", "gals";
2803 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2804 };
2805
2806 larb26: larb@16142000 {
2807 compatible = "mediatek,mt8195-smi-larb";
2808 reg = <0 0x16142000 0 0x1000>;
2809 mediatek,larb-id = <26>;
2810 mediatek,smi = <&smi_sub_common_cam_7x1>;
2811 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2812 <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2813 clock-names = "apb", "smi";
2814 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2815
2816 };
2817
2818 ccusys: clock-controller@17200000 {
2819 compatible = "mediatek,mt8195-ccusys";
2820 reg = <0 0x17200000 0 0x1000>;
2821 #clock-cells = <1>;
2822 };
2823
2824 larb18: larb@17201000 {
2825 compatible = "mediatek,mt8195-smi-larb";
2826 reg = <0 0x17201000 0 0x1000>;
2827 mediatek,larb-id = <18>;
2828 mediatek,smi = <&smi_sub_common_cam_7x1>;
2829 clocks = <&ccusys CLK_CCU_LARB18>,
2830 <&ccusys CLK_CCU_LARB18>;
2831 clock-names = "apb", "smi";
2832 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2833 };
2834
2835 video-codec@18000000 {
2836 compatible = "mediatek,mt8195-vcodec-dec";
2837 mediatek,scp = <&scp>;
2838 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
2839 #address-cells = <2>;
2840 #size-cells = <2>;
2841 reg = <0 0x18000000 0 0x1000>,
2842 <0 0x18004000 0 0x1000>;
2843 ranges = <0 0 0 0x18000000 0 0x26000>;
2844
2845 video-codec@2000 {
2846 compatible = "mediatek,mtk-vcodec-lat-soc";
2847 reg = <0 0x2000 0 0x800>;
2848 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
2849 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
2850 clocks = <&topckgen CLK_TOP_VDEC>,
2851 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2852 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2853 <&topckgen CLK_TOP_UNIVPLL_D4>;
2854 clock-names = "sel", "vdec", "lat", "top";
2855 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2856 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2857 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2858 };
2859
2860 video-codec@10000 {
2861 compatible = "mediatek,mtk-vcodec-lat";
2862 reg = <0 0x10000 0 0x800>;
2863 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
2864 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
2865 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
2866 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
2867 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
2868 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
2869 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
2870 clocks = <&topckgen CLK_TOP_VDEC>,
2871 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2872 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2873 <&topckgen CLK_TOP_UNIVPLL_D4>;
2874 clock-names = "sel", "vdec", "lat", "top";
2875 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2876 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2877 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2878 };
2879
2880 video-codec@25000 {
2881 compatible = "mediatek,mtk-vcodec-core";
2882 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */
2883 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
2884 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
2885 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
2886 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
2887 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
2888 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
2889 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
2890 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
2891 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
2892 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
2893 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
2894 clocks = <&topckgen CLK_TOP_VDEC>,
2895 <&vdecsys CLK_VDEC_VDEC>,
2896 <&vdecsys CLK_VDEC_LAT>,
2897 <&topckgen CLK_TOP_UNIVPLL_D4>;
2898 clock-names = "sel", "vdec", "lat", "top";
2899 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2900 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2901 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2902 };
2903 };
2904
2905 larb24: larb@1800d000 {
2906 compatible = "mediatek,mt8195-smi-larb";
2907 reg = <0 0x1800d000 0 0x1000>;
2908 mediatek,larb-id = <24>;
2909 mediatek,smi = <&smi_common_vdo>;
2910 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2911 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2912 clock-names = "apb", "smi";
2913 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2914 };
2915
2916 larb23: larb@1800e000 {
2917 compatible = "mediatek,mt8195-smi-larb";
2918 reg = <0 0x1800e000 0 0x1000>;
2919 mediatek,larb-id = <23>;
2920 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2921 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2922 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2923 clock-names = "apb", "smi";
2924 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2925 };
2926
2927 vdecsys_soc: clock-controller@1800f000 {
2928 compatible = "mediatek,mt8195-vdecsys_soc";
2929 reg = <0 0x1800f000 0 0x1000>;
2930 #clock-cells = <1>;
2931 };
2932
2933 larb21: larb@1802e000 {
2934 compatible = "mediatek,mt8195-smi-larb";
2935 reg = <0 0x1802e000 0 0x1000>;
2936 mediatek,larb-id = <21>;
2937 mediatek,smi = <&smi_common_vdo>;
2938 clocks = <&vdecsys CLK_VDEC_LARB1>,
2939 <&vdecsys CLK_VDEC_LARB1>;
2940 clock-names = "apb", "smi";
2941 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2942 };
2943
2944 vdecsys: clock-controller@1802f000 {
2945 compatible = "mediatek,mt8195-vdecsys";
2946 reg = <0 0x1802f000 0 0x1000>;
2947 #clock-cells = <1>;
2948 };
2949
2950 larb22: larb@1803e000 {
2951 compatible = "mediatek,mt8195-smi-larb";
2952 reg = <0 0x1803e000 0 0x1000>;
2953 mediatek,larb-id = <22>;
2954 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2955 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2956 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2957 clock-names = "apb", "smi";
2958 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2959 };
2960
2961 vdecsys_core1: clock-controller@1803f000 {
2962 compatible = "mediatek,mt8195-vdecsys_core1";
2963 reg = <0 0x1803f000 0 0x1000>;
2964 #clock-cells = <1>;
2965 };
2966
2967 apusys_pll: clock-controller@190f3000 {
2968 compatible = "mediatek,mt8195-apusys_pll";
2969 reg = <0 0x190f3000 0 0x1000>;
2970 #clock-cells = <1>;
2971 };
2972
2973 vencsys: clock-controller@1a000000 {
2974 compatible = "mediatek,mt8195-vencsys";
2975 reg = <0 0x1a000000 0 0x1000>;
2976 #clock-cells = <1>;
2977 };
2978
2979 larb19: larb@1a010000 {
2980 compatible = "mediatek,mt8195-smi-larb";
2981 reg = <0 0x1a010000 0 0x1000>;
2982 mediatek,larb-id = <19>;
2983 mediatek,smi = <&smi_common_vdo>;
2984 clocks = <&vencsys CLK_VENC_VENC>,
2985 <&vencsys CLK_VENC_GALS>;
2986 clock-names = "apb", "smi";
2987 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2988 };
2989
2990 venc: video-codec@1a020000 {
2991 compatible = "mediatek,mt8195-vcodec-enc";
2992 reg = <0 0x1a020000 0 0x10000>;
2993 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2994 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2995 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2996 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
2997 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
2998 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
2999 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
3000 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
3001 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
3002 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
3003 mediatek,scp = <&scp>;
3004 clocks = <&vencsys CLK_VENC_VENC>;
3005 clock-names = "venc_sel";
3006 assigned-clocks = <&topckgen CLK_TOP_VENC>;
3007 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3008 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3009 #address-cells = <2>;
3010 #size-cells = <2>;
3011 };
3012
3013 jpgdec-master {
3014 compatible = "mediatek,mt8195-jpgdec";
3015 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3016 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3017 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3018 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3019 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3020 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3021 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3022 #address-cells = <2>;
3023 #size-cells = <2>;
3024 ranges;
3025
3026 jpgdec@1a040000 {
3027 compatible = "mediatek,mt8195-jpgdec-hw";
3028 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
3029 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3030 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3031 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3032 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3033 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3034 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3035 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
3036 clocks = <&vencsys CLK_VENC_JPGDEC>;
3037 clock-names = "jpgdec";
3038 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3039 };
3040
3041 jpgdec@1a050000 {
3042 compatible = "mediatek,mt8195-jpgdec-hw";
3043 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
3044 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3045 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3046 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3047 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3048 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3049 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3050 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
3051 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
3052 clock-names = "jpgdec";
3053 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3054 };
3055
3056 jpgdec@1b040000 {
3057 compatible = "mediatek,mt8195-jpgdec-hw";
3058 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
3059 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
3060 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
3061 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
3062 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
3063 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
3064 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
3065 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
3066 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
3067 clock-names = "jpgdec";
3068 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3069 };
3070 };
3071
3072 vencsys_core1: clock-controller@1b000000 {
3073 compatible = "mediatek,mt8195-vencsys_core1";
3074 reg = <0 0x1b000000 0 0x1000>;
3075 #clock-cells = <1>;
3076 };
3077
3078 vdosys0: syscon@1c01a000 {
3079 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3080 reg = <0 0x1c01a000 0 0x1000>;
3081 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3082 #clock-cells = <1>;
3083 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3084 };
3085
3086
3087 jpgenc-master {
3088 compatible = "mediatek,mt8195-jpgenc";
3089 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3090 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3091 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3092 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3093 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3094 #address-cells = <2>;
3095 #size-cells = <2>;
3096 ranges;
3097
3098 jpgenc@1a030000 {
3099 compatible = "mediatek,mt8195-jpgenc-hw";
3100 reg = <0 0x1a030000 0 0x10000>;
3101 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
3102 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
3103 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
3104 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
3105 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
3106 clocks = <&vencsys CLK_VENC_JPGENC>;
3107 clock-names = "jpgenc";
3108 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3109 };
3110
3111 jpgenc@1b030000 {
3112 compatible = "mediatek,mt8195-jpgenc-hw";
3113 reg = <0 0x1b030000 0 0x10000>;
3114 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3115 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3116 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3117 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3118 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
3119 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
3120 clock-names = "jpgenc";
3121 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3122 };
3123 };
3124
3125 larb20: larb@1b010000 {
3126 compatible = "mediatek,mt8195-smi-larb";
3127 reg = <0 0x1b010000 0 0x1000>;
3128 mediatek,larb-id = <20>;
3129 mediatek,smi = <&smi_common_vpp>;
3130 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
3131 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
3132 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3133 clock-names = "apb", "smi", "gals";
3134 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3135 };
3136
3137 ovl0: ovl@1c000000 {
3138 compatible = "mediatek,mt8195-disp-ovl";
3139 reg = <0 0x1c000000 0 0x1000>;
3140 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
3141 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3142 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
3143 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
3144 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3145 };
3146
3147 rdma0: rdma@1c002000 {
3148 compatible = "mediatek,mt8195-disp-rdma";
3149 reg = <0 0x1c002000 0 0x1000>;
3150 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
3151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3152 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
3153 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
3154 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3155 };
3156
3157 color0: color@1c003000 {
3158 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3159 reg = <0 0x1c003000 0 0x1000>;
3160 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
3161 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3162 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
3163 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3164 };
3165
3166 ccorr0: ccorr@1c004000 {
3167 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3168 reg = <0 0x1c004000 0 0x1000>;
3169 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
3170 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3171 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
3172 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3173 };
3174
3175 aal0: aal@1c005000 {
3176 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3177 reg = <0 0x1c005000 0 0x1000>;
3178 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
3179 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3180 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
3181 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3182 };
3183
3184 gamma0: gamma@1c006000 {
3185 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3186 reg = <0 0x1c006000 0 0x1000>;
3187 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
3188 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3189 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
3190 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3191 };
3192
3193 dither0: dither@1c007000 {
3194 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3195 reg = <0 0x1c007000 0 0x1000>;
3196 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
3197 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3198 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
3199 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3200 };
3201
3202 dsi0: dsi@1c008000 {
3203 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3204 reg = <0 0x1c008000 0 0x1000>;
3205 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
3206 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3207 clocks = <&vdosys0 CLK_VDO0_DSI0>,
3208 <&vdosys0 CLK_VDO0_DSI0_DSI>,
3209 <&mipi_tx0>;
3210 clock-names = "engine", "digital", "hs";
3211 phys = <&mipi_tx0>;
3212 phy-names = "dphy";
3213 status = "disabled";
3214 };
3215
3216 dsc0: dsc@1c009000 {
3217 compatible = "mediatek,mt8195-disp-dsc";
3218 reg = <0 0x1c009000 0 0x1000>;
3219 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
3220 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3221 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
3222 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3223 };
3224
3225 dsi1: dsi@1c012000 {
3226 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3227 reg = <0 0x1c012000 0 0x1000>;
3228 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
3229 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3230 clocks = <&vdosys0 CLK_VDO0_DSI1>,
3231 <&vdosys0 CLK_VDO0_DSI1_DSI>,
3232 <&mipi_tx1>;
3233 clock-names = "engine", "digital", "hs";
3234 phys = <&mipi_tx1>;
3235 phy-names = "dphy";
3236 status = "disabled";
3237 };
3238
3239 merge0: merge@1c014000 {
3240 compatible = "mediatek,mt8195-disp-merge";
3241 reg = <0 0x1c014000 0 0x1000>;
3242 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
3243 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3244 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3245 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3246 };
3247
3248 dp_intf0: dp-intf@1c015000 {
3249 compatible = "mediatek,mt8195-dp-intf";
3250 reg = <0 0x1c015000 0 0x1000>;
3251 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
3252 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3253 <&vdosys0 CLK_VDO0_DP_INTF0>,
3254 <&apmixedsys CLK_APMIXED_TVDPLL1>;
3255 clock-names = "pixel", "engine", "pll";
3256 status = "disabled";
3257 };
3258
3259 mutex: mutex@1c016000 {
3260 compatible = "mediatek,mt8195-disp-mutex";
3261 reg = <0 0x1c016000 0 0x1000>;
3262 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3263 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3264 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
3265 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3266 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3267 };
3268
3269 larb0: larb@1c018000 {
3270 compatible = "mediatek,mt8195-smi-larb";
3271 reg = <0 0x1c018000 0 0x1000>;
3272 mediatek,larb-id = <0>;
3273 mediatek,smi = <&smi_common_vdo>;
3274 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3275 <&vdosys0 CLK_VDO0_SMI_LARB>,
3276 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3277 clock-names = "apb", "smi", "gals";
3278 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3279 };
3280
3281 larb1: larb@1c019000 {
3282 compatible = "mediatek,mt8195-smi-larb";
3283 reg = <0 0x1c019000 0 0x1000>;
3284 mediatek,larb-id = <1>;
3285 mediatek,smi = <&smi_common_vpp>;
3286 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3287 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3288 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3289 clock-names = "apb", "smi", "gals";
3290 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3291 };
3292
3293 vdosys1: syscon@1c100000 {
3294 compatible = "mediatek,mt8195-vdosys1", "syscon";
3295 reg = <0 0x1c100000 0 0x1000>;
3296 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
3297 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3298 #clock-cells = <1>;
3299 #reset-cells = <1>;
3300 };
3301
3302 smi_common_vdo: smi@1c01b000 {
3303 compatible = "mediatek,mt8195-smi-common-vdo";
3304 reg = <0 0x1c01b000 0 0x1000>;
3305 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
3306 <&vdosys0 CLK_VDO0_SMI_EMI>,
3307 <&vdosys0 CLK_VDO0_SMI_RSI>,
3308 <&vdosys0 CLK_VDO0_SMI_GALS>;
3309 clock-names = "apb", "smi", "gals0", "gals1";
3310 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3311
3312 };
3313
3314 iommu_vdo: iommu@1c01f000 {
3315 compatible = "mediatek,mt8195-iommu-vdo";
3316 reg = <0 0x1c01f000 0 0x1000>;
3317 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
3318 &larb10 &larb11 &larb13 &larb17
3319 &larb19 &larb21 &larb24 &larb25
3320 &larb28>;
3321 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
3322 #iommu-cells = <1>;
3323 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
3324 clock-names = "bclk";
3325 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3326 };
3327
3328 mutex1: mutex@1c101000 {
3329 compatible = "mediatek,mt8195-disp-mutex";
3330 reg = <0 0x1c101000 0 0x1000>;
3331 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3332 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3333 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3334 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3335 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3336 };
3337
3338 larb2: larb@1c102000 {
3339 compatible = "mediatek,mt8195-smi-larb";
3340 reg = <0 0x1c102000 0 0x1000>;
3341 mediatek,larb-id = <2>;
3342 mediatek,smi = <&smi_common_vdo>;
3343 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3344 <&vdosys1 CLK_VDO1_SMI_LARB2>,
3345 <&vdosys1 CLK_VDO1_GALS>;
3346 clock-names = "apb", "smi", "gals";
3347 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3348 };
3349
3350 larb3: larb@1c103000 {
3351 compatible = "mediatek,mt8195-smi-larb";
3352 reg = <0 0x1c103000 0 0x1000>;
3353 mediatek,larb-id = <3>;
3354 mediatek,smi = <&smi_common_vpp>;
3355 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3356 <&vdosys1 CLK_VDO1_GALS>,
3357 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3358 clock-names = "apb", "smi", "gals";
3359 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3360 };
3361
3362 vdo1_rdma0: dma-controller@1c104000 {
3363 compatible = "mediatek,mt8195-vdo1-rdma";
3364 reg = <0 0x1c104000 0 0x1000>;
3365 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
3366 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
3367 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3368 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
3369 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3370 #dma-cells = <1>;
3371 };
3372
3373 vdo1_rdma1: dma-controller@1c105000 {
3374 compatible = "mediatek,mt8195-vdo1-rdma";
3375 reg = <0 0x1c105000 0 0x1000>;
3376 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
3377 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
3378 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3379 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
3380 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3381 #dma-cells = <1>;
3382 };
3383
3384 vdo1_rdma2: dma-controller@1c106000 {
3385 compatible = "mediatek,mt8195-vdo1-rdma";
3386 reg = <0 0x1c106000 0 0x1000>;
3387 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
3388 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
3389 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3390 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
3391 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3392 #dma-cells = <1>;
3393 };
3394
3395 vdo1_rdma3: dma-controller@1c107000 {
3396 compatible = "mediatek,mt8195-vdo1-rdma";
3397 reg = <0 0x1c107000 0 0x1000>;
3398 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
3399 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
3400 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3401 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
3402 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3403 #dma-cells = <1>;
3404 };
3405
3406 vdo1_rdma4: dma-controller@1c108000 {
3407 compatible = "mediatek,mt8195-vdo1-rdma";
3408 reg = <0 0x1c108000 0 0x1000>;
3409 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
3410 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
3411 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3412 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
3413 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3414 #dma-cells = <1>;
3415 };
3416
3417 vdo1_rdma5: dma-controller@1c109000 {
3418 compatible = "mediatek,mt8195-vdo1-rdma";
3419 reg = <0 0x1c109000 0 0x1000>;
3420 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
3421 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
3422 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3423 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
3424 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3425 #dma-cells = <1>;
3426 };
3427
3428 vdo1_rdma6: dma-controller@1c10a000 {
3429 compatible = "mediatek,mt8195-vdo1-rdma";
3430 reg = <0 0x1c10a000 0 0x1000>;
3431 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
3432 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
3433 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3434 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
3435 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3436 #dma-cells = <1>;
3437 };
3438
3439 vdo1_rdma7: dma-controller@1c10b000 {
3440 compatible = "mediatek,mt8195-vdo1-rdma";
3441 reg = <0 0x1c10b000 0 0x1000>;
3442 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
3443 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
3444 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3445 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
3446 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3447 #dma-cells = <1>;
3448 };
3449
3450 merge1: vpp-merge@1c10c000 {
3451 compatible = "mediatek,mt8195-disp-merge";
3452 reg = <0 0x1c10c000 0 0x1000>;
3453 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
3454 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
3455 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
3456 clock-names = "merge","merge_async";
3457 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3458 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3459 mediatek,merge-mute;
3460 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
3461 };
3462
3463 merge2: vpp-merge@1c10d000 {
3464 compatible = "mediatek,mt8195-disp-merge";
3465 reg = <0 0x1c10d000 0 0x1000>;
3466 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
3467 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
3468 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
3469 clock-names = "merge","merge_async";
3470 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3471 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3472 mediatek,merge-mute;
3473 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
3474 };
3475
3476 merge3: vpp-merge@1c10e000 {
3477 compatible = "mediatek,mt8195-disp-merge";
3478 reg = <0 0x1c10e000 0 0x1000>;
3479 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
3480 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
3481 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
3482 clock-names = "merge","merge_async";
3483 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3484 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3485 mediatek,merge-mute;
3486 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
3487 };
3488
3489 merge4: vpp-merge@1c10f000 {
3490 compatible = "mediatek,mt8195-disp-merge";
3491 reg = <0 0x1c10f000 0 0x1000>;
3492 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
3493 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
3494 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
3495 clock-names = "merge","merge_async";
3496 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3497 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3498 mediatek,merge-mute;
3499 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3500 };
3501
3502 merge5: vpp-merge@1c110000 {
3503 compatible = "mediatek,mt8195-disp-merge";
3504 reg = <0 0x1c110000 0 0x1000>;
3505 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3506 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3507 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3508 clock-names = "merge","merge_async";
3509 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3510 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3511 mediatek,merge-fifo-en;
3512 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3513 };
3514
3515 dp_intf1: dp-intf@1c113000 {
3516 compatible = "mediatek,mt8195-dp-intf";
3517 reg = <0 0x1c113000 0 0x1000>;
3518 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3519 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3520 clocks = <&vdosys1 CLK_VDO1_DPINTF>,
3521 <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3522 <&apmixedsys CLK_APMIXED_TVDPLL2>;
3523 clock-names = "pixel", "engine", "pll";
3524 status = "disabled";
3525 };
3526
3527 ethdr0: hdr-engine@1c114000 {
3528 compatible = "mediatek,mt8195-disp-ethdr";
3529 reg = <0 0x1c114000 0 0x1000>,
3530 <0 0x1c115000 0 0x1000>,
3531 <0 0x1c117000 0 0x1000>,
3532 <0 0x1c119000 0 0x1000>,
3533 <0 0x1c11a000 0 0x1000>,
3534 <0 0x1c11b000 0 0x1000>,
3535 <0 0x1c11c000 0 0x1000>;
3536 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3537 "vdo_be", "adl_ds";
3538 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3539 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
3540 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
3541 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
3542 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
3543 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
3544 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
3545 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3546 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3547 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3548 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3549 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3550 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3551 <&vdosys1 CLK_VDO1_26M_SLOW>,
3552 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3553 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3554 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3555 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3556 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3557 <&topckgen CLK_TOP_ETHDR>;
3558 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3559 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
3560 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
3561 "ethdr_top";
3562 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3563 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
3564 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
3565 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
3566 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3567 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3568 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3569 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3570 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
3571 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3572 "gfx_fe1_async", "vdo_be_async";
3573 };
3574
3575 edp_tx: edp-tx@1c500000 {
3576 compatible = "mediatek,mt8195-edp-tx";
3577 reg = <0 0x1c500000 0 0x8000>;
3578 nvmem-cells = <&dp_calibration>;
3579 nvmem-cell-names = "dp_calibration_data";
3580 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3581 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3582 max-linkrate-mhz = <8100>;
3583 status = "disabled";
3584 };
3585
3586 dp_tx: dp-tx@1c600000 {
3587 compatible = "mediatek,mt8195-dp-tx";
3588 reg = <0 0x1c600000 0 0x8000>;
3589 nvmem-cells = <&dp_calibration>;
3590 nvmem-cell-names = "dp_calibration_data";
3591 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3592 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3593 max-linkrate-mhz = <8100>;
3594 status = "disabled";
3595 };
3596 };
3597
3598 thermal_zones: thermal-zones {
3599 cpu0-thermal {
3600 polling-delay = <1000>;
3601 polling-delay-passive = <250>;
3602 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3603
3604 trips {
3605 cpu0_alert: trip-alert {
3606 temperature = <85000>;
3607 hysteresis = <2000>;
3608 type = "passive";
3609 };
3610
3611 cpu0_crit: trip-crit {
3612 temperature = <100000>;
3613 hysteresis = <2000>;
3614 type = "critical";
3615 };
3616 };
3617
3618 cooling-maps {
3619 map0 {
3620 trip = <&cpu0_alert>;
3621 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3622 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3623 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3624 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3625 };
3626 };
3627 };
3628
3629 cpu1-thermal {
3630 polling-delay = <1000>;
3631 polling-delay-passive = <250>;
3632 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3633
3634 trips {
3635 cpu1_alert: trip-alert {
3636 temperature = <85000>;
3637 hysteresis = <2000>;
3638 type = "passive";
3639 };
3640
3641 cpu1_crit: trip-crit {
3642 temperature = <100000>;
3643 hysteresis = <2000>;
3644 type = "critical";
3645 };
3646 };
3647
3648 cooling-maps {
3649 map0 {
3650 trip = <&cpu1_alert>;
3651 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3652 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3653 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3654 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3655 };
3656 };
3657 };
3658
3659 cpu2-thermal {
3660 polling-delay = <1000>;
3661 polling-delay-passive = <250>;
3662 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3663
3664 trips {
3665 cpu2_alert: trip-alert {
3666 temperature = <85000>;
3667 hysteresis = <2000>;
3668 type = "passive";
3669 };
3670
3671 cpu2_crit: trip-crit {
3672 temperature = <100000>;
3673 hysteresis = <2000>;
3674 type = "critical";
3675 };
3676 };
3677
3678 cooling-maps {
3679 map0 {
3680 trip = <&cpu2_alert>;
3681 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3682 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3683 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3684 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3685 };
3686 };
3687 };
3688
3689 cpu3-thermal {
3690 polling-delay = <1000>;
3691 polling-delay-passive = <250>;
3692 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3693
3694 trips {
3695 cpu3_alert: trip-alert {
3696 temperature = <85000>;
3697 hysteresis = <2000>;
3698 type = "passive";
3699 };
3700
3701 cpu3_crit: trip-crit {
3702 temperature = <100000>;
3703 hysteresis = <2000>;
3704 type = "critical";
3705 };
3706 };
3707
3708 cooling-maps {
3709 map0 {
3710 trip = <&cpu3_alert>;
3711 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3712 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3713 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3714 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3715 };
3716 };
3717 };
3718
3719 cpu4-thermal {
3720 polling-delay = <1000>;
3721 polling-delay-passive = <250>;
3722 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3723
3724 trips {
3725 cpu4_alert: trip-alert {
3726 temperature = <85000>;
3727 hysteresis = <2000>;
3728 type = "passive";
3729 };
3730
3731 cpu4_crit: trip-crit {
3732 temperature = <100000>;
3733 hysteresis = <2000>;
3734 type = "critical";
3735 };
3736 };
3737
3738 cooling-maps {
3739 map0 {
3740 trip = <&cpu4_alert>;
3741 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3742 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3743 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3744 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3745 };
3746 };
3747 };
3748
3749 cpu5-thermal {
3750 polling-delay = <1000>;
3751 polling-delay-passive = <250>;
3752 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3753
3754 trips {
3755 cpu5_alert: trip-alert {
3756 temperature = <85000>;
3757 hysteresis = <2000>;
3758 type = "passive";
3759 };
3760
3761 cpu5_crit: trip-crit {
3762 temperature = <100000>;
3763 hysteresis = <2000>;
3764 type = "critical";
3765 };
3766 };
3767
3768 cooling-maps {
3769 map0 {
3770 trip = <&cpu5_alert>;
3771 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3772 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3773 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3774 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3775 };
3776 };
3777 };
3778
3779 cpu6-thermal {
3780 polling-delay = <1000>;
3781 polling-delay-passive = <250>;
3782 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3783
3784 trips {
3785 cpu6_alert: trip-alert {
3786 temperature = <85000>;
3787 hysteresis = <2000>;
3788 type = "passive";
3789 };
3790
3791 cpu6_crit: trip-crit {
3792 temperature = <100000>;
3793 hysteresis = <2000>;
3794 type = "critical";
3795 };
3796 };
3797
3798 cooling-maps {
3799 map0 {
3800 trip = <&cpu6_alert>;
3801 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3802 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3803 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3804 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3805 };
3806 };
3807 };
3808
3809 cpu7-thermal {
3810 polling-delay = <1000>;
3811 polling-delay-passive = <250>;
3812 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3813
3814 trips {
3815 cpu7_alert: trip-alert {
3816 temperature = <85000>;
3817 hysteresis = <2000>;
3818 type = "passive";
3819 };
3820
3821 cpu7_crit: trip-crit {
3822 temperature = <100000>;
3823 hysteresis = <2000>;
3824 type = "critical";
3825 };
3826 };
3827
3828 cooling-maps {
3829 map0 {
3830 trip = <&cpu7_alert>;
3831 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3832 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3833 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3834 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3835 };
3836 };
3837 };
3838
3839 vpu0-thermal {
3840 polling-delay = <1000>;
3841 polling-delay-passive = <250>;
3842 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3843
3844 trips {
3845 vpu0_alert: trip-alert {
3846 temperature = <85000>;
3847 hysteresis = <2000>;
3848 type = "passive";
3849 };
3850
3851 vpu0_crit: trip-crit {
3852 temperature = <100000>;
3853 hysteresis = <2000>;
3854 type = "critical";
3855 };
3856 };
3857 };
3858
3859 vpu1-thermal {
3860 polling-delay = <1000>;
3861 polling-delay-passive = <250>;
3862 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3863
3864 trips {
3865 vpu1_alert: trip-alert {
3866 temperature = <85000>;
3867 hysteresis = <2000>;
3868 type = "passive";
3869 };
3870
3871 vpu1_crit: trip-crit {
3872 temperature = <100000>;
3873 hysteresis = <2000>;
3874 type = "critical";
3875 };
3876 };
3877 };
3878
3879 gpu-thermal {
3880 polling-delay = <1000>;
3881 polling-delay-passive = <250>;
3882 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3883
3884 trips {
3885 gpu0_alert: trip-alert {
3886 temperature = <85000>;
3887 hysteresis = <2000>;
3888 type = "passive";
3889 };
3890
3891 gpu0_crit: trip-crit {
3892 temperature = <100000>;
3893 hysteresis = <2000>;
3894 type = "critical";
3895 };
3896 };
3897 };
3898
3899 gpu1-thermal {
3900 polling-delay = <1000>;
3901 polling-delay-passive = <250>;
3902 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3903
3904 trips {
3905 gpu1_alert: trip-alert {
3906 temperature = <85000>;
3907 hysteresis = <2000>;
3908 type = "passive";
3909 };
3910
3911 gpu1_crit: trip-crit {
3912 temperature = <100000>;
3913 hysteresis = <2000>;
3914 type = "critical";
3915 };
3916 };
3917 };
3918
3919 vdec-thermal {
3920 polling-delay = <1000>;
3921 polling-delay-passive = <250>;
3922 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3923
3924 trips {
3925 vdec_alert: trip-alert {
3926 temperature = <85000>;
3927 hysteresis = <2000>;
3928 type = "passive";
3929 };
3930
3931 vdec_crit: trip-crit {
3932 temperature = <100000>;
3933 hysteresis = <2000>;
3934 type = "critical";
3935 };
3936 };
3937 };
3938
3939 img-thermal {
3940 polling-delay = <1000>;
3941 polling-delay-passive = <250>;
3942 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3943
3944 trips {
3945 img_alert: trip-alert {
3946 temperature = <85000>;
3947 hysteresis = <2000>;
3948 type = "passive";
3949 };
3950
3951 img_crit: trip-crit {
3952 temperature = <100000>;
3953 hysteresis = <2000>;
3954 type = "critical";
3955 };
3956 };
3957 };
3958
3959 infra-thermal {
3960 polling-delay = <1000>;
3961 polling-delay-passive = <250>;
3962 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3963
3964 trips {
3965 infra_alert: trip-alert {
3966 temperature = <85000>;
3967 hysteresis = <2000>;
3968 type = "passive";
3969 };
3970
3971 infra_crit: trip-crit {
3972 temperature = <100000>;
3973 hysteresis = <2000>;
3974 type = "critical";
3975 };
3976 };
3977 };
3978
3979 cam0-thermal {
3980 polling-delay = <1000>;
3981 polling-delay-passive = <250>;
3982 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3983
3984 trips {
3985 cam0_alert: trip-alert {
3986 temperature = <85000>;
3987 hysteresis = <2000>;
3988 type = "passive";
3989 };
3990
3991 cam0_crit: trip-crit {
3992 temperature = <100000>;
3993 hysteresis = <2000>;
3994 type = "critical";
3995 };
3996 };
3997 };
3998
3999 cam1-thermal {
4000 polling-delay = <1000>;
4001 polling-delay-passive = <250>;
4002 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
4003
4004 trips {
4005 cam1_alert: trip-alert {
4006 temperature = <85000>;
4007 hysteresis = <2000>;
4008 type = "passive";
4009 };
4010
4011 cam1_crit: trip-crit {
4012 temperature = <100000>;
4013 hysteresis = <2000>;
4014 type = "critical";
4015 };
4016 };
4017 };
4018 };
4019};