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1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2
3#include <dt-bindings/clock/mediatek,mt7988-clk.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/phy/phy.h>
6
7/ {
8 compatible = "mediatek,mt7988a";
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 compatible = "arm,cortex-a73";
19 reg = <0x0>;
20 device_type = "cpu";
21 enable-method = "psci";
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a73";
26 reg = <0x1>;
27 device_type = "cpu";
28 enable-method = "psci";
29 };
30
31 cpu@2 {
32 compatible = "arm,cortex-a73";
33 reg = <0x2>;
34 device_type = "cpu";
35 enable-method = "psci";
36 };
37
38 cpu@3 {
39 compatible = "arm,cortex-a73";
40 reg = <0x3>;
41 device_type = "cpu";
42 enable-method = "psci";
43 };
44 };
45
46 oscillator-40m {
47 compatible = "fixed-clock";
48 clock-frequency = <40000000>;
49 #clock-cells = <0>;
50 clock-output-names = "clkxtal";
51 };
52
53 pmu {
54 compatible = "arm,cortex-a73-pmu";
55 interrupt-parent = <&gic>;
56 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
57 };
58
59 psci {
60 compatible = "arm,psci-0.2";
61 method = "smc";
62 };
63
64 soc {
65 compatible = "simple-bus";
66 ranges;
67 #address-cells = <2>;
68 #size-cells = <2>;
69
70 gic: interrupt-controller@c000000 {
71 compatible = "arm,gic-v3";
72 reg = <0 0x0c000000 0 0x40000>, /* GICD */
73 <0 0x0c080000 0 0x200000>, /* GICR */
74 <0 0x0c400000 0 0x2000>, /* GICC */
75 <0 0x0c410000 0 0x1000>, /* GICH */
76 <0 0x0c420000 0 0x2000>; /* GICV */
77 interrupt-parent = <&gic>;
78 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-controller;
80 #interrupt-cells = <3>;
81 };
82
83 infracfg: clock-controller@10001000 {
84 compatible = "mediatek,mt7988-infracfg", "syscon";
85 reg = <0 0x10001000 0 0x1000>;
86 #clock-cells = <1>;
87 };
88
89 topckgen: clock-controller@1001b000 {
90 compatible = "mediatek,mt7988-topckgen", "syscon";
91 reg = <0 0x1001b000 0 0x1000>;
92 #clock-cells = <1>;
93 };
94
95 watchdog: watchdog@1001c000 {
96 compatible = "mediatek,mt7988-wdt";
97 reg = <0 0x1001c000 0 0x1000>;
98 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
99 #reset-cells = <1>;
100 };
101
102 clock-controller@1001e000 {
103 compatible = "mediatek,mt7988-apmixedsys";
104 reg = <0 0x1001e000 0 0x1000>;
105 #clock-cells = <1>;
106 };
107
108 pwm@10048000 {
109 compatible = "mediatek,mt7988-pwm";
110 reg = <0 0x10048000 0 0x1000>;
111 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
112 <&infracfg CLK_INFRA_66M_PWM_HCK>,
113 <&infracfg CLK_INFRA_66M_PWM_CK1>,
114 <&infracfg CLK_INFRA_66M_PWM_CK2>,
115 <&infracfg CLK_INFRA_66M_PWM_CK3>,
116 <&infracfg CLK_INFRA_66M_PWM_CK4>,
117 <&infracfg CLK_INFRA_66M_PWM_CK5>,
118 <&infracfg CLK_INFRA_66M_PWM_CK6>,
119 <&infracfg CLK_INFRA_66M_PWM_CK7>,
120 <&infracfg CLK_INFRA_66M_PWM_CK8>;
121 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
122 "pwm4", "pwm5", "pwm6", "pwm7", "pwm8";
123 #pwm-cells = <2>;
124 status = "disabled";
125 };
126
127 serial@11000000 {
128 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
129 reg = <0 0x11000000 0 0x100>;
130 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-names = "uart", "wakeup";
132 clocks = <&topckgen CLK_TOP_UART_SEL>,
133 <&infracfg CLK_INFRA_52M_UART0_CK>;
134 clock-names = "baud", "bus";
135 status = "disabled";
136 };
137
138 serial@11000100 {
139 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
140 reg = <0 0x11000100 0 0x100>;
141 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
142 interrupt-names = "uart", "wakeup";
143 clocks = <&topckgen CLK_TOP_UART_SEL>,
144 <&infracfg CLK_INFRA_52M_UART1_CK>;
145 clock-names = "baud", "bus";
146 status = "disabled";
147 };
148
149 serial@11000200 {
150 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
151 reg = <0 0x11000200 0 0x100>;
152 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-names = "uart", "wakeup";
154 clocks = <&topckgen CLK_TOP_UART_SEL>,
155 <&infracfg CLK_INFRA_52M_UART2_CK>;
156 clock-names = "baud", "bus";
157 status = "disabled";
158 };
159
160 i2c@11003000 {
161 compatible = "mediatek,mt7981-i2c";
162 reg = <0 0x11003000 0 0x1000>,
163 <0 0x10217080 0 0x80>;
164 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
165 clock-div = <1>;
166 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
167 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
168 clock-names = "main", "dma";
169 #address-cells = <1>;
170 #size-cells = <0>;
171 status = "disabled";
172 };
173
174 i2c@11004000 {
175 compatible = "mediatek,mt7981-i2c";
176 reg = <0 0x11004000 0 0x1000>,
177 <0 0x10217100 0 0x80>;
178 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
179 clock-div = <1>;
180 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
181 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
182 clock-names = "main", "dma";
183 #address-cells = <1>;
184 #size-cells = <0>;
185 status = "disabled";
186 };
187
188 i2c@11005000 {
189 compatible = "mediatek,mt7981-i2c";
190 reg = <0 0x11005000 0 0x1000>,
191 <0 0x10217180 0 0x80>;
192 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
193 clock-div = <1>;
194 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
195 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
196 clock-names = "main", "dma";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 status = "disabled";
200 };
201
202 usb@11190000 {
203 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
204 reg = <0 0x11190000 0 0x2e00>,
205 <0 0x11193e00 0 0x0100>;
206 reg-names = "mac", "ippc";
207 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&infracfg CLK_INFRA_USB_SYS>,
209 <&infracfg CLK_INFRA_USB_REF>,
210 <&infracfg CLK_INFRA_66M_USB_HCK>,
211 <&infracfg CLK_INFRA_133M_USB_HCK>,
212 <&infracfg CLK_INFRA_USB_XHCI>;
213 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
214 };
215
216 usb@11200000 {
217 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
218 reg = <0 0x11200000 0 0x2e00>,
219 <0 0x11203e00 0 0x0100>;
220 reg-names = "mac", "ippc";
221 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
223 <&infracfg CLK_INFRA_USB_CK_P1>,
224 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
225 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
226 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
227 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
228 };
229
230 clock-controller@11f40000 {
231 compatible = "mediatek,mt7988-xfi-pll";
232 reg = <0 0x11f40000 0 0x1000>;
233 resets = <&watchdog 16>;
234 #clock-cells = <1>;
235 };
236
237 efuse@11f50000 {
238 compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
239 reg = <0 0x11f50000 0 0x1000>;
240 #address-cells = <1>;
241 #size-cells = <1>;
242 };
243
244 clock-controller@15000000 {
245 compatible = "mediatek,mt7988-ethsys", "syscon";
246 reg = <0 0x15000000 0 0x1000>;
247 #clock-cells = <1>;
248 #reset-cells = <1>;
249 };
250
251 clock-controller@15031000 {
252 compatible = "mediatek,mt7988-ethwarp";
253 reg = <0 0x15031000 0 0x1000>;
254 #clock-cells = <1>;
255 #reset-cells = <1>;
256 };
257 };
258
259 timer {
260 compatible = "arm,armv8-timer";
261 interrupt-parent = <&gic>;
262 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
263 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
264 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
265 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
266 };
267};