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1// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2/*
3 * Copyright 2024 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx93.dtsi"
10
11/ {
12 model = "NXP i.MX93 9x9 Quick Start Board";
13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93";
14
15 bt_sco_codec: bt-sco-codec {
16 #sound-dai-cells = <1>;
17 compatible = "linux,bt-sco";
18 };
19
20 chosen {
21 stdout-path = &lpuart1;
22 };
23
24 reserved-memory {
25 #address-cells = <2>;
26 #size-cells = <2>;
27 ranges;
28
29 linux,cma {
30 compatible = "shared-dma-pool";
31 reusable;
32 size = <0 0x10000000>;
33 linux,cma-default;
34 };
35
36 vdev0vring0: vdev0vring0@a4000000 {
37 reg = <0 0xa4000000 0 0x8000>;
38 no-map;
39 };
40
41 vdev0vring1: vdev0vring1@a4008000 {
42 reg = <0 0xa4008000 0 0x8000>;
43 no-map;
44 };
45
46 vdev1vring0: vdev1vring0@a4010000 {
47 reg = <0 0xa4010000 0 0x8000>;
48 no-map;
49 };
50
51 vdev1vring1: vdev1vring1@a4018000 {
52 reg = <0 0xa4018000 0 0x8000>;
53 no-map;
54 };
55
56 rsc_table: rsc-table@2021e000 {
57 reg = <0 0x2021e000 0 0x1000>;
58 no-map;
59 };
60
61 vdevbuffer: vdevbuffer@a4020000 {
62 compatible = "shared-dma-pool";
63 reg = <0 0xa4020000 0 0x100000>;
64 no-map;
65 };
66
67 };
68
69 reg_vref_1v8: regulator-adc-vref {
70 compatible = "regulator-fixed";
71 regulator-name = "VREF_1V8";
72 regulator-min-microvolt = <1800000>;
73 regulator-max-microvolt = <1800000>;
74 };
75
76 reg_audio_pwr: regulator-audio-pwr {
77 compatible = "regulator-fixed";
78 regulator-name = "audio-pwr";
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
81 gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>;
82 enable-active-high;
83 };
84
85 reg_rpi_3v3: regulator-rpi {
86 compatible = "regulator-fixed";
87 regulator-name = "VDD_RPI_3V3";
88 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>;
90 gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>;
91 enable-active-high;
92 };
93
94 reg_usdhc2_vmmc: regulator-usdhc2 {
95 compatible = "regulator-fixed";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
98 regulator-name = "VSD_3V3";
99 regulator-min-microvolt = <3300000>;
100 regulator-max-microvolt = <3300000>;
101 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
102 enable-active-high;
103 off-on-delay-us = <12000>;
104 };
105
106 sound-bt-sco {
107 compatible = "simple-audio-card";
108 simple-audio-card,name = "bt-sco-audio";
109 simple-audio-card,format = "dsp_a";
110 simple-audio-card,bitclock-inversion;
111 simple-audio-card,frame-master = <&btcpu>;
112 simple-audio-card,bitclock-master = <&btcpu>;
113
114 btcpu: simple-audio-card,cpu {
115 sound-dai = <&sai1>;
116 dai-tdm-slot-num = <2>;
117 dai-tdm-slot-width = <16>;
118 };
119
120 simple-audio-card,codec {
121 sound-dai = <&bt_sco_codec 1>;
122 };
123 };
124
125 sound-micfil {
126 compatible = "fsl,imx-audio-card";
127 model = "micfil-audio";
128
129 pri-dai-link {
130 link-name = "micfil hifi";
131 format = "i2s";
132
133 cpu {
134 sound-dai = <&micfil>;
135 };
136 };
137 };
138
139 sound-wm8962 {
140 compatible = "fsl,imx-audio-wm8962";
141 model = "wm8962-audio";
142 audio-cpu = <&sai3>;
143 audio-codec = <&wm8962>;
144 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>;
145 audio-routing =
146 "Headphone Jack", "HPOUTL",
147 "Headphone Jack", "HPOUTR",
148 "Ext Spk", "SPKOUTL",
149 "Ext Spk", "SPKOUTR",
150 "AMIC", "MICBIAS",
151 "IN3R", "AMIC",
152 "IN1R", "AMIC";
153 };
154};
155
156&adc1 {
157 vref-supply = <®_vref_1v8>;
158 status = "okay";
159};
160
161&cm33 {
162 mbox-names = "tx", "rx", "rxdb";
163 mboxes = <&mu1 0 1>,
164 <&mu1 1 1>,
165 <&mu1 3 1>;
166 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
167 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
168 status = "okay";
169};
170
171&eqos {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_eqos>;
174 phy-mode = "rgmii-id";
175 phy-handle = <ðphy1>;
176 status = "okay";
177
178 mdio {
179 compatible = "snps,dwmac-mdio";
180 #address-cells = <1>;
181 #size-cells = <0>;
182 clock-frequency = <5000000>;
183
184 ethphy1: ethernet-phy@1 {
185 compatible = "ethernet-phy-ieee802.3-c22";
186 reg = <1>;
187 eee-broken-1000t;
188 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
189 reset-assert-us = <10000>;
190 reset-deassert-us = <80000>;
191 realtek,clkout-disable;
192 };
193 };
194};
195
196&lpi2c1 {
197 clock-frequency = <400000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_lpi2c1>;
200 status = "okay";
201
202 wm8962: audio-codec@1a {
203 compatible = "wlf,wm8962";
204 reg = <0x1a>;
205 clocks = <&clk IMX93_CLK_SAI3_GATE>;
206 DCVDD-supply = <®_audio_pwr>;
207 DBVDD-supply = <®_audio_pwr>;
208 AVDD-supply = <®_audio_pwr>;
209 CPVDD-supply = <®_audio_pwr>;
210 MICVDD-supply = <®_audio_pwr>;
211 PLLVDD-supply = <®_audio_pwr>;
212 SPKVDD1-supply = <®_audio_pwr>;
213 SPKVDD2-supply = <®_audio_pwr>;
214 gpio-cfg = <
215 0x0000 /* 0:Default */
216 0x0000 /* 1:Default */
217 0x0000 /* 2:FN_DMICCLK */
218 0x0000 /* 3:Default */
219 0x0000 /* 4:FN_DMICCDAT */
220 0x0000 /* 5:Default */
221 >;
222 };
223
224 ptn5110: tcpc@50 {
225 compatible = "nxp,ptn5110", "tcpci";
226 reg = <0x50>;
227 interrupt-parent = <&gpio3>;
228 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
229
230 typec1_con: connector {
231 compatible = "usb-c-connector";
232 label = "USB-C";
233 power-role = "dual";
234 data-role = "dual";
235 try-power-role = "sink";
236 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
237 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
238 PDO_VAR(5000, 20000, 3000)>;
239 op-sink-microwatt = <15000000>;
240 self-powered;
241
242 ports {
243 #address-cells = <1>;
244 #size-cells = <0>;
245
246 port@0 {
247 reg = <0>;
248
249 typec1_dr_sw: endpoint {
250 remote-endpoint = <&usb1_drd_sw>;
251 };
252 };
253 };
254 };
255 };
256
257 rtc@53 {
258 compatible = "nxp,pcf2131";
259 reg = <0x53>;
260 interrupt-parent = <&pcal6524>;
261 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
262 };
263};
264
265&lpi2c2 {
266 clock-frequency = <400000>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_lpi2c2>;
269 status = "okay";
270
271 pcal6524: gpio@22 {
272 compatible = "nxp,pcal6524";
273 reg = <0x22>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 interrupt-parent = <&gpio3>;
279 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_pcal6524>;
282
283 exp-sel-hog {
284 gpio-hog;
285 gpios = <22 GPIO_ACTIVE_HIGH>;
286 output-low;
287 };
288
289 mic-can-sel-hog {
290 gpio-hog;
291 gpios = <17 GPIO_ACTIVE_HIGH>;
292 output-low;
293 };
294 };
295
296 pmic@25 {
297 compatible = "nxp,pca9451a";
298 reg = <0x25>;
299 interrupt-parent = <&pcal6524>;
300 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
301
302 regulators {
303 buck1: BUCK1 {
304 regulator-name = "BUCK1";
305 regulator-min-microvolt = <650000>;
306 regulator-max-microvolt = <2237500>;
307 regulator-boot-on;
308 regulator-always-on;
309 regulator-ramp-delay = <3125>;
310 };
311
312 buck2: BUCK2 {
313 regulator-name = "BUCK2";
314 regulator-min-microvolt = <600000>;
315 regulator-max-microvolt = <2187500>;
316 regulator-boot-on;
317 regulator-always-on;
318 regulator-ramp-delay = <3125>;
319 };
320
321 buck4: BUCK4 {
322 regulator-name = "BUCK4";
323 regulator-min-microvolt = <600000>;
324 regulator-max-microvolt = <3400000>;
325 regulator-boot-on;
326 regulator-always-on;
327 };
328
329 buck5: BUCK5 {
330 regulator-name = "BUCK5";
331 regulator-min-microvolt = <600000>;
332 regulator-max-microvolt = <3400000>;
333 regulator-boot-on;
334 regulator-always-on;
335 };
336
337 buck6: BUCK6 {
338 regulator-name = "BUCK6";
339 regulator-min-microvolt = <600000>;
340 regulator-max-microvolt = <3400000>;
341 regulator-boot-on;
342 regulator-always-on;
343 };
344
345 ldo1: LDO1 {
346 regulator-name = "LDO1";
347 regulator-min-microvolt = <1600000>;
348 regulator-max-microvolt = <3300000>;
349 regulator-boot-on;
350 regulator-always-on;
351 };
352
353 ldo4: LDO4 {
354 regulator-name = "LDO4";
355 regulator-min-microvolt = <800000>;
356 regulator-max-microvolt = <3300000>;
357 regulator-boot-on;
358 regulator-always-on;
359 };
360
361 ldo5: LDO5 {
362 regulator-name = "LDO5";
363 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <3300000>;
365 regulator-boot-on;
366 regulator-always-on;
367 };
368 };
369 };
370};
371
372&lpuart1 { /* console */
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_uart1>;
375 status = "okay";
376};
377
378&micfil {
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_pdm>;
381 assigned-clocks = <&clk IMX93_CLK_PDM>;
382 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
383 assigned-clock-rates = <49152000>;
384 status = "okay";
385};
386
387&mu1 {
388 status = "okay";
389};
390
391&mu2 {
392 status = "okay";
393};
394
395&sai1 {
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_sai1>;
398 assigned-clocks = <&clk IMX93_CLK_SAI1>;
399 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
400 assigned-clock-rates = <12288000>;
401 fsl,sai-mclk-direction-output;
402 status = "okay";
403};
404
405&sai3 {
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_sai3>;
408 assigned-clocks = <&clk IMX93_CLK_SAI3>;
409 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
410 assigned-clock-rates = <12288000>;
411 fsl,sai-mclk-direction-output;
412 fsl,sai-synchronous-rx;
413 status = "okay";
414};
415
416&usbotg1 {
417 dr_mode = "otg";
418 hnp-disable;
419 srp-disable;
420 adp-disable;
421 usb-role-switch;
422 disable-over-current;
423 samsung,picophy-pre-emp-curr-control = <3>;
424 samsung,picophy-dc-vol-level-adjust = <7>;
425 status = "okay";
426
427 port {
428 usb1_drd_sw: endpoint {
429 remote-endpoint = <&typec1_dr_sw>;
430 };
431 };
432};
433
434&usdhc1 {
435 pinctrl-names = "default", "state_100mhz", "state_200mhz";
436 pinctrl-0 = <&pinctrl_usdhc1>;
437 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
438 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
439 bus-width = <8>;
440 non-removable;
441 status = "okay";
442};
443
444&usdhc2 {
445 pinctrl-names = "default", "state_100mhz", "state_200mhz";
446 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
447 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
448 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
449 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
450 vmmc-supply = <®_usdhc2_vmmc>;
451 bus-width = <4>;
452 no-mmc;
453 status = "okay";
454};
455
456&wdog3 {
457 status = "okay";
458};
459
460&iomuxc {
461 pinctrl_eqos: eqosgrp {
462 fsl,pins = <
463 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
464 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
465 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
466 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
467 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
468 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
469 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
470 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
471 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
472 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
473 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
474 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
475 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
476 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
477 >;
478 };
479
480 pinctrl_lpi2c1: lpi2c1grp {
481 fsl,pins = <
482 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
483 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
484 >;
485 };
486
487 pinctrl_lpi2c2: lpi2c2grp {
488 fsl,pins = <
489 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
490 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
491 >;
492 };
493
494 pinctrl_pcal6524: pcal6524grp {
495 fsl,pins = <
496 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
497 >;
498 };
499
500 pinctrl_pdm: pdmgrp {
501 fsl,pins = <
502 MX93_PAD_PDM_CLK__PDM_CLK 0x31e
503 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e
504 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e
505 >;
506 };
507
508 pinctrl_uart1: uart1grp {
509 fsl,pins = <
510 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
511 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
512 >;
513 };
514
515 pinctrl_uart5: uart5grp {
516 fsl,pins = <
517 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
518 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
519 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
520 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
521 >;
522 };
523
524 /* need to config the SION for data and cmd pad, refer to ERR052021 */
525 pinctrl_usdhc1: usdhc1grp {
526 fsl,pins = <
527 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
528 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
529 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
530 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
531 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
532 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
533 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
534 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
535 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
536 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
537 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
538 >;
539 };
540
541 /* need to config the SION for data and cmd pad, refer to ERR052021 */
542 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
543 fsl,pins = <
544 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
545 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
546 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
547 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
548 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
549 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
550 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
551 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
552 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
553 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
554 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
555 >;
556 };
557
558 /* need to config the SION for data and cmd pad, refer to ERR052021 */
559 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
560 fsl,pins = <
561 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
562 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
563 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
564 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
565 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
566 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
567 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
568 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
569 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
570 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
571 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
572 >;
573 };
574
575 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
576 fsl,pins = <
577 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
578 >;
579 };
580
581 pinctrl_sai1: sai1grp {
582 fsl,pins = <
583 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
584 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
585 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
586 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
587 >;
588 };
589
590 pinctrl_sai3: sai3grp {
591 fsl,pins = <
592 MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e
593 MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e
594 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
595 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e
596 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
597 >;
598 };
599
600 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
601 fsl,pins = <
602 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
603 >;
604 };
605
606 /* need to config the SION for data and cmd pad, refer to ERR052021 */
607 pinctrl_usdhc2: usdhc2grp {
608 fsl,pins = <
609 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
610 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
611 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
612 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
613 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
614 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
615 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
616 >;
617 };
618
619 /* need to config the SION for data and cmd pad, refer to ERR052021 */
620 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
621 fsl,pins = <
622 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
623 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
624 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
625 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
626 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
627 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
628 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
629 >;
630 };
631
632 /* need to config the SION for data and cmd pad, refer to ERR052021 */
633 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
634 fsl,pins = <
635 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
636 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
637 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
638 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
639 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
640 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
641 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
642 >;
643 };
644};