Loading...
Note: File does not exist in v4.6.
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/pads-imx8qm.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 mmc0 = &usdhc1;
21 mmc1 = &usdhc2;
22 mmc2 = &usdhc3;
23 serial0 = &lpuart0;
24 serial1 = &lpuart1;
25 serial2 = &lpuart2;
26 serial3 = &lpuart3;
27 spi0 = &lpspi0;
28 spi1 = &lpspi1;
29 spi2 = &lpspi2;
30 spi3 = &lpspi3;
31 vpu-core0 = &vpu_core0;
32 vpu-core1 = &vpu_core1;
33 vpu-core2 = &vpu_core2;
34 };
35
36 cpus {
37 #address-cells = <2>;
38 #size-cells = <0>;
39
40 cpu-map {
41 cluster0 {
42 core0 {
43 cpu = <&A53_0>;
44 };
45 core1 {
46 cpu = <&A53_1>;
47 };
48 core2 {
49 cpu = <&A53_2>;
50 };
51 core3 {
52 cpu = <&A53_3>;
53 };
54 };
55
56 cluster1 {
57 core0 {
58 cpu = <&A72_0>;
59 };
60 core1 {
61 cpu = <&A72_1>;
62 };
63 };
64 };
65
66 A53_0: cpu@0 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a53";
69 reg = <0x0 0x0>;
70 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
71 enable-method = "psci";
72 i-cache-size = <0x8000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <256>;
75 d-cache-size = <0x8000>;
76 d-cache-line-size = <64>;
77 d-cache-sets = <128>;
78 next-level-cache = <&A53_L2>;
79 operating-points-v2 = <&a53_opp_table>;
80 #cooling-cells = <2>;
81 };
82
83 A53_1: cpu@1 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a53";
86 reg = <0x0 0x1>;
87 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 #cooling-cells = <2>;
98 };
99
100 A53_2: cpu@2 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x0 0x2>;
104 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
105 enable-method = "psci";
106 i-cache-size = <0x8000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <256>;
109 d-cache-size = <0x8000>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&A53_L2>;
113 operating-points-v2 = <&a53_opp_table>;
114 #cooling-cells = <2>;
115 };
116
117 A53_3: cpu@3 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a53";
120 reg = <0x0 0x3>;
121 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
122 enable-method = "psci";
123 i-cache-size = <0x8000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <256>;
126 d-cache-size = <0x8000>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <128>;
129 next-level-cache = <&A53_L2>;
130 operating-points-v2 = <&a53_opp_table>;
131 #cooling-cells = <2>;
132 };
133
134 A72_0: cpu@100 {
135 device_type = "cpu";
136 compatible = "arm,cortex-a72";
137 reg = <0x0 0x100>;
138 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
139 enable-method = "psci";
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
146 next-level-cache = <&A72_L2>;
147 operating-points-v2 = <&a72_opp_table>;
148 #cooling-cells = <2>;
149 };
150
151 A72_1: cpu@101 {
152 device_type = "cpu";
153 compatible = "arm,cortex-a72";
154 reg = <0x0 0x101>;
155 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
156 enable-method = "psci";
157 next-level-cache = <&A72_L2>;
158 operating-points-v2 = <&a72_opp_table>;
159 #cooling-cells = <2>;
160 };
161
162 A53_L2: l2-cache0 {
163 compatible = "cache";
164 cache-level = <2>;
165 cache-unified;
166 cache-size = <0x100000>;
167 cache-line-size = <64>;
168 cache-sets = <1024>;
169 };
170
171 A72_L2: l2-cache1 {
172 compatible = "cache";
173 cache-level = <2>;
174 cache-unified;
175 cache-size = <0x100000>;
176 cache-line-size = <64>;
177 cache-sets = <1024>;
178 };
179 };
180
181 a53_opp_table: opp-table-0 {
182 compatible = "operating-points-v2";
183 opp-shared;
184
185 opp-600000000 {
186 opp-hz = /bits/ 64 <600000000>;
187 opp-microvolt = <900000>;
188 clock-latency-ns = <150000>;
189 };
190
191 opp-896000000 {
192 opp-hz = /bits/ 64 <896000000>;
193 opp-microvolt = <1000000>;
194 clock-latency-ns = <150000>;
195 };
196
197 opp-1104000000 {
198 opp-hz = /bits/ 64 <1104000000>;
199 opp-microvolt = <1100000>;
200 clock-latency-ns = <150000>;
201 };
202
203 opp-1200000000 {
204 opp-hz = /bits/ 64 <1200000000>;
205 opp-microvolt = <1100000>;
206 clock-latency-ns = <150000>;
207 opp-suspend;
208 };
209 };
210
211 a72_opp_table: opp-table-1 {
212 compatible = "operating-points-v2";
213 opp-shared;
214
215 opp-600000000 {
216 opp-hz = /bits/ 64 <600000000>;
217 opp-microvolt = <1000000>;
218 clock-latency-ns = <150000>;
219 };
220
221 opp-1056000000 {
222 opp-hz = /bits/ 64 <1056000000>;
223 opp-microvolt = <1000000>;
224 clock-latency-ns = <150000>;
225 };
226
227 opp-1296000000 {
228 opp-hz = /bits/ 64 <1296000000>;
229 opp-microvolt = <1100000>;
230 clock-latency-ns = <150000>;
231 };
232
233 opp-1596000000 {
234 opp-hz = /bits/ 64 <1596000000>;
235 opp-microvolt = <1100000>;
236 clock-latency-ns = <150000>;
237 opp-suspend;
238 };
239 };
240
241 gic: interrupt-controller@51a00000 {
242 compatible = "arm,gic-v3";
243 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
244 <0x0 0x51b00000 0 0xC0000>, /* GICR */
245 <0x0 0x52000000 0 0x2000>, /* GICC */
246 <0x0 0x52010000 0 0x1000>, /* GICH */
247 <0x0 0x52020000 0 0x20000>; /* GICV */
248 #interrupt-cells = <3>;
249 interrupt-controller;
250 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-parent = <&gic>;
252 };
253
254 pmu {
255 compatible = "arm,armv8-pmuv3";
256 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
257 };
258
259 psci {
260 compatible = "arm,psci-1.0";
261 method = "smc";
262 };
263
264 timer {
265 compatible = "arm,armv8-timer";
266 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
267 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
268 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
269 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
270 };
271
272 smmu: iommu@51400000 {
273 compatible = "arm,mmu-500";
274 interrupt-parent = <&gic>;
275 reg = <0 0x51400000 0 0x40000>;
276 #global-interrupts = <1>;
277 #iommu-cells = <2>;
278 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
311 };
312
313 system-controller {
314 compatible = "fsl,imx-scu";
315 mbox-names = "tx0",
316 "rx0",
317 "gip3";
318 mboxes = <&lsio_mu1 0 0
319 &lsio_mu1 1 0
320 &lsio_mu1 3 3>;
321
322 pd: power-controller {
323 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
324 #power-domain-cells = <1>;
325 };
326
327 clk: clock-controller {
328 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
329 #clock-cells = <2>;
330 };
331
332 iomuxc: pinctrl {
333 compatible = "fsl,imx8qm-iomuxc";
334 };
335
336 rtc: rtc {
337 compatible = "fsl,imx8qxp-sc-rtc";
338 };
339
340 ocotp: ocotp {
341 compatible = "fsl,imx8qm-scu-ocotp";
342 #address-cells = <1>;
343 #size-cells = <1>;
344 read-only;
345
346 fec_mac0: mac@1c4 {
347 reg = <0x1c4 6>;
348 };
349
350 fec_mac1: mac@1c6 {
351 reg = <0x1c6 6>;
352 };
353 };
354
355 tsens: thermal-sensor {
356 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
357 #thermal-sensor-cells = <1>;
358 };
359 };
360
361 thermal-zones {
362 cpu0-thermal {
363 polling-delay-passive = <250>;
364 polling-delay = <2000>;
365 thermal-sensors = <&tsens IMX_SC_R_A53>;
366
367 trips {
368 cpu_alert0: trip0 {
369 temperature = <107000>;
370 hysteresis = <2000>;
371 type = "passive";
372 };
373
374 cpu_crit0: trip1 {
375 temperature = <127000>;
376 hysteresis = <2000>;
377 type = "critical";
378 };
379 };
380
381 cooling-maps {
382 map0 {
383 trip = <&cpu_alert0>;
384 cooling-device =
385 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
386 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
387 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
388 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
389 };
390 };
391 };
392
393 cpu1-thermal {
394 polling-delay-passive = <250>;
395 polling-delay = <2000>;
396 thermal-sensors = <&tsens IMX_SC_R_A72>;
397
398 trips {
399 cpu_alert1: trip0 {
400 temperature = <107000>;
401 hysteresis = <2000>;
402 type = "passive";
403 };
404
405 cpu_crit1: trip1 {
406 temperature = <127000>;
407 hysteresis = <2000>;
408 type = "critical";
409 };
410 };
411
412 cooling-maps {
413 map0 {
414 trip = <&cpu_alert1>;
415 cooling-device =
416 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
417 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
418 };
419 };
420 };
421
422 gpu0-thermal {
423 polling-delay-passive = <250>;
424 polling-delay = <2000>;
425 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
426
427 trips {
428 gpu_alert0: trip0 {
429 temperature = <107000>;
430 hysteresis = <2000>;
431 type = "passive";
432 };
433
434 gpu_crit0: trip1 {
435 temperature = <127000>;
436 hysteresis = <2000>;
437 type = "critical";
438 };
439 };
440 };
441
442 gpu1-thermal {
443 polling-delay-passive = <250>;
444 polling-delay = <2000>;
445 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
446
447 trips {
448 gpu_alert1: trip0 {
449 temperature = <107000>;
450 hysteresis = <2000>;
451 type = "passive";
452 };
453
454 gpu_crit1: trip1 {
455 temperature = <127000>;
456 hysteresis = <2000>;
457 type = "critical";
458 };
459 };
460 };
461
462 drc0-thermal {
463 polling-delay-passive = <250>;
464 polling-delay = <2000>;
465 thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
466
467 trips {
468 drc_alert0: trip0 {
469 temperature = <107000>;
470 hysteresis = <2000>;
471 type = "passive";
472 };
473
474 drc_crit0: trip1 {
475 temperature = <127000>;
476 hysteresis = <2000>;
477 type = "critical";
478 };
479 };
480 };
481 };
482
483 clk_dummy: clock-dummy {
484 compatible = "fixed-clock";
485 #clock-cells = <0>;
486 clock-frequency = <0>;
487 clock-output-names = "clk_dummy";
488 };
489
490 clk_esai1_rx_clk: clock-esai1-rx {
491 compatible = "fixed-clock";
492 #clock-cells = <0>;
493 clock-frequency = <0>;
494 clock-output-names = "esai1_rx_clk";
495 };
496
497 clk_esai1_rx_hf_clk: clock-esai1-rx-hf {
498 compatible = "fixed-clock";
499 #clock-cells = <0>;
500 clock-frequency = <0>;
501 clock-output-names = "esai1_rx_hf_clk";
502 };
503
504 clk_esai1_tx_clk: clock-esai1-tx {
505 compatible = "fixed-clock";
506 #clock-cells = <0>;
507 clock-frequency = <0>;
508 clock-output-names = "esai1_tx_clk";
509 };
510
511 clk_esai1_tx_hf_clk: clock-esai1-tx-hf {
512 compatible = "fixed-clock";
513 #clock-cells = <0>;
514 clock-frequency = <0>;
515 clock-output-names = "esai1_tx_hf_clk";
516 };
517
518 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk {
519 compatible = "fixed-clock";
520 #clock-cells = <0>;
521 clock-frequency = <0>;
522 clock-output-names = "hdmi-rx-mclk";
523 };
524
525 clk_mlb_clk: clock-mlb-clk {
526 compatible = "fixed-clock";
527 #clock-cells = <0>;
528 clock-frequency = <0>;
529 clock-output-names = "mlb_clk";
530 };
531
532 clk_sai5_rx_bclk: clock-sai5-rx-bclk {
533 compatible = "fixed-clock";
534 #clock-cells = <0>;
535 clock-frequency = <0>;
536 clock-output-names = "sai5_rx_bclk";
537 };
538
539 clk_sai5_tx_bclk: clock-sai5-tx-bclk {
540 compatible = "fixed-clock";
541 #clock-cells = <0>;
542 clock-frequency = <0>;
543 clock-output-names = "sai5_tx_bclk";
544 };
545
546 clk_sai6_rx_bclk: clock-sai6-rx-bclk {
547 compatible = "fixed-clock";
548 #clock-cells = <0>;
549 clock-frequency = <0>;
550 clock-output-names = "sai6_rx_bclk";
551 };
552
553 clk_sai6_tx_bclk: clock-sai6-tx-bclk {
554 compatible = "fixed-clock";
555 #clock-cells = <0>;
556 clock-frequency = <0>;
557 clock-output-names = "sai6_tx_bclk";
558 };
559
560 clk_spdif1_rx: clock-spdif1-rx {
561 compatible = "fixed-clock";
562 #clock-cells = <0>;
563 clock-frequency = <0>;
564 clock-output-names = "spdif1_rx";
565 };
566
567 lvds_ipg_clk: clock-controller-lvds-ipg {
568 compatible = "fixed-clock";
569 #clock-cells = <0>;
570 clock-frequency = <24000000>;
571 clock-output-names = "lvds0_ipg_clk";
572 };
573
574 dsi_ipg_clk: clock-controller-dsi-ipg {
575 compatible = "fixed-clock";
576 #clock-cells = <0>;
577 clock-frequency = <120000000>;
578 clock-output-names = "dsi_ipg_clk";
579 };
580
581 mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
582 compatible = "fixed-clock";
583 #clock-cells = <0>;
584 clock-frequency = <432000000>;
585 clock-output-names = "mipi_pll_div2_clk";
586 };
587
588 vpu_subsys_dsp: bus@55000000 {
589 compatible = "simple-bus";
590 #address-cells = <1>;
591 #size-cells = <1>;
592 ranges = <0x55000000 0x0 0x55000000 0x1000000>;
593
594 vpu_dsp: dsp@556e8000 {
595 compatible = "fsl,imx8qm-hifi4";
596 reg = <0x556e8000 0x88000>;
597 clocks = <&clk_dummy>,
598 <&clk_dummy>,
599 <&clk_dummy>;
600 clock-names = "ipg", "ocram", "core";
601 power-domains = <&pd IMX_SC_R_MU_13B>,
602 <&pd IMX_SC_R_DSP>,
603 <&pd IMX_SC_R_DSP_RAM>,
604 <&pd IMX_SC_R_MU_2A>;
605 mboxes = <&lsio_mu13 0 0>,
606 <&lsio_mu13 1 0>,
607 <&lsio_mu13 3 0>;
608 mbox-names = "tx", "rx", "rxdb";
609 firmware-name = "imx/dsp/hifi4.bin";
610 status = "disabled";
611 };
612 };
613
614 /* sorted in register address */
615 #include "imx8-ss-cm41.dtsi"
616 #include "imx8-ss-audio.dtsi"
617 #include "imx8-ss-vpu.dtsi"
618 #include "imx8-ss-gpu0.dtsi"
619 #include "imx8-ss-mipi0.dtsi"
620 #include "imx8-ss-lvds0.dtsi"
621 #include "imx8-ss-mipi1.dtsi"
622 #include "imx8-ss-lvds1.dtsi"
623 #include "imx8-ss-img.dtsi"
624 #include "imx8-ss-dma.dtsi"
625 #include "imx8-ss-conn.dtsi"
626 #include "imx8-ss-lsio.dtsi"
627 #include "imx8-ss-hsio.dtsi"
628};
629
630#include "imx8qm-ss-img.dtsi"
631#include "imx8qm-ss-dma.dtsi"
632#include "imx8qm-ss-conn.dtsi"
633#include "imx8qm-ss-lsio.dtsi"
634#include "imx8qm-ss-audio.dtsi"
635#include "imx8qm-ss-lvds.dtsi"
636#include "imx8qm-ss-mipi.dtsi"
637#include "imx8qm-ss-hsio.dtsi"
638
639/delete-node/ &dsp;