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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/phy/phy-imx8-pcie.h>
10#include <dt-bindings/leds/leds-pca9532.h>
11#include <dt-bindings/pwm/pwm.h>
12#include <dt-bindings/thermal/thermal.h>
13#include "imx8mp-phycore-som.dtsi"
14
15/ {
16 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
17 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
18 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
19
20 chosen {
21 stdout-path = &uart1;
22 };
23
24 backlight_lvds: backlight {
25 compatible = "pwm-backlight";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_lvds1>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
29 default-brightness-level = <11>;
30 enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
31 num-interpolated-steps = <2>;
32 power-supply = <®_lvds1_reg_en>;
33 pwms = <&pwm3 0 50000 0>;
34 };
35
36 fan0: fan {
37 compatible = "gpio-fan";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_fan>;
40 gpio-fan,speed-map = <0 0
41 13000 1>;
42 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
43 #cooling-cells = <2>;
44 };
45
46 panel1_lvds: panel-lvds {
47 compatible = "edt,etml1010g3dra";
48 backlight = <&backlight_lvds>;
49 power-supply = <®_vcc_3v3_sw>;
50
51 port {
52 panel1_in: endpoint {
53 remote-endpoint = <&ldb_lvds_ch1>;
54 };
55 };
56 };
57
58 reg_vcc_5v_sw: regulator-vcc-5v-sw {
59 compatible = "regulator-fixed";
60 regulator-always-on;
61 regulator-boot-on;
62 regulator-max-microvolt = <5000000>;
63 regulator-min-microvolt = <5000000>;
64 regulator-name = "VCC_5V_SW";
65 };
66
67 reg_can1_stby: regulator-can1-stby {
68 compatible = "regulator-fixed";
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_flexcan1_reg>;
71 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
72 regulator-max-microvolt = <3300000>;
73 regulator-min-microvolt = <3300000>;
74 regulator-name = "can1-stby";
75 };
76
77 reg_can2_stby: regulator-can2-stby {
78 compatible = "regulator-fixed";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_flexcan2_reg>;
81 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
82 regulator-max-microvolt = <3300000>;
83 regulator-min-microvolt = <3300000>;
84 regulator-name = "can2-stby";
85 };
86
87 reg_lvds1_reg_en: regulator-lvds1 {
88 compatible = "regulator-fixed";
89 enable-active-high;
90 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
91 regulator-max-microvolt = <1200000>;
92 regulator-min-microvolt = <1200000>;
93 regulator-name = "lvds1_reg_en";
94 };
95
96 reg_usb1_vbus: regulator-usb1-vbus {
97 compatible = "regulator-fixed";
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_usb1_vbus>;
100 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
101 regulator-max-microvolt = <5000000>;
102 regulator-min-microvolt = <5000000>;
103 regulator-name = "usb1_host_vbus";
104 };
105
106 reg_usdhc2_vmmc: regulator-usdhc2 {
107 compatible = "regulator-fixed";
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
110 regulator-name = "VSD_3V3";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
114 enable-active-high;
115 startup-delay-us = <100>;
116 off-on-delay-us = <12000>;
117 };
118
119 reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
120 compatible = "regulator-fixed";
121 regulator-name = "VCC_3V3_SW";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 };
125
126 thermal-zones {
127 soc-thermal {
128 trips {
129 active1: trip2 {
130 temperature = <60000>;
131 hysteresis = <2000>;
132 type = "active";
133 };
134 };
135
136 cooling-maps {
137 map1 {
138 trip = <&active1>;
139 cooling-device = <&fan0 1 THERMAL_NO_LIMIT>;
140 };
141 };
142 };
143 };
144};
145
146/* TPM */
147&ecspi1 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_ecspi1>;
153 status = "okay";
154
155 tpm: tpm@0 {
156 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
157 reg = <0>;
158 spi-max-frequency = <38000000>;
159 };
160};
161
162&eqos {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_eqos>;
165 phy-mode = "rgmii-id";
166 phy-handle = <ðphy0>;
167 status = "okay";
168
169 mdio {
170 compatible = "snps,dwmac-mdio";
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 ethphy0: ethernet-phy@1 {
175 compatible = "ethernet-phy-ieee802.3-c22";
176 reg = <0x1>;
177 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
178 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
179 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
180 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
181 enet-phy-lane-no-swap;
182 };
183 };
184};
185
186/* CAN FD */
187&flexcan1 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_flexcan1>;
190 xceiver-supply = <®_can1_stby>;
191 status = "okay";
192};
193
194&flexcan2 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_flexcan2>;
197 xceiver-supply = <®_can2_stby>;
198 status = "okay";
199};
200
201&i2c2 {
202 clock-frequency = <400000>;
203 pinctrl-names = "default", "gpio";
204 pinctrl-0 = <&pinctrl_i2c2>;
205 pinctrl-1 = <&pinctrl_i2c2_gpio>;
206 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
207 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
208 status = "okay";
209
210 eeprom@51 {
211 compatible = "atmel,24c02";
212 reg = <0x51>;
213 pagesize = <16>;
214 vcc-supply = <®_vcc_3v3_sw>;
215 };
216
217 leds@62 {
218 compatible = "nxp,pca9533";
219 reg = <0x62>;
220
221 led-1 {
222 type = <PCA9532_TYPE_LED>;
223 };
224
225 led-2 {
226 type = <PCA9532_TYPE_LED>;
227 };
228
229 led-3 {
230 type = <PCA9532_TYPE_LED>;
231 };
232 };
233};
234
235&lcdif2 {
236 status = "okay";
237};
238
239&lvds_bridge {
240 status = "okay";
241
242 ports {
243 port@2 {
244 ldb_lvds_ch1: endpoint {
245 remote-endpoint = <&panel1_in>;
246 };
247 };
248 };
249};
250
251&media_blk_ctrl {
252 /*
253 * The LVDS panel on this device uses 72.4 MHz pixel clock,
254 * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
255 * serializer and LCDIFv3 scanout engine can reach accurate
256 * pixel clock of exactly 72.4 MHz.
257 */
258 assigned-clock-rates = <500000000>, <200000000>,
259 <0>, <0>, <500000000>,
260 <506800000>;
261};
262
263&snvs_pwrkey {
264 status = "okay";
265};
266
267&pcie_phy {
268 clocks = <&hsio_blk_ctrl>;
269 clock-names = "ref";
270 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
271 fsl,clkreq-unsupported;
272 status = "okay";
273};
274
275/* Mini PCIe */
276&pcie {
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_pcie0>;
279 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
280 vpcie-supply = <®_vcc_3v3_sw>;
281 status = "okay";
282};
283
284&pwm3 {
285 status = "okay";
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_pwm3>;
288};
289
290&rv3028 {
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_rtc>;
293 interrupt-parent = <&gpio4>;
294 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
295 aux-voltage-chargeable = <1>;
296 wakeup-source;
297 trickle-resistor-ohms = <3000>;
298};
299
300/* debug console */
301&uart1 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_uart1>;
304 status = "okay";
305};
306
307/* USB1 Host mode Type-A */
308&usb3_phy0 {
309 vbus-supply = <®_usb1_vbus>;
310 status = "okay";
311};
312
313&usb3_0 {
314 status = "okay";
315};
316
317&usb_dwc3_0 {
318 dr_mode = "host";
319 status = "okay";
320};
321
322/* USB2 4-port USB3.0 HUB */
323&usb3_phy1 {
324 vbus-supply = <®_vcc_5v_sw>;
325 status = "okay";
326};
327
328&usb3_1 {
329 fsl,permanently-attached;
330 fsl,disable-port-power-control;
331 status = "okay";
332};
333
334&usb_dwc3_1 {
335 dr_mode = "host";
336 status = "okay";
337};
338
339/* RS232/RS485 */
340&uart2 {
341 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
342 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_uart2>;
345 uart-has-rtscts;
346 status = "okay";
347};
348
349/* SD-Card */
350&usdhc2 {
351 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
352 assigned-clock-rates = <200000000>;
353 pinctrl-names = "default", "state_100mhz", "state_200mhz";
354 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
355 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
356 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
357 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
358 disable-wp;
359 vmmc-supply = <®_usdhc2_vmmc>;
360 vqmmc-supply = <&ldo5>;
361 bus-width = <4>;
362 status = "okay";
363};
364
365&gpio1 {
366 gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
367 "PMIC_SD_VSEL", "", "", "", "PCIe_nPERST", "LVDS1REG_EN",
368 "PCIe_nWAKE", "PCIe_nCLKREQ", "USB1_OTG_PWR", "",
369 "PCIe_nW_DISABLE";
370};
371
372&gpio2 {
373 gpio-line-names = "", "", "", "",
374 "", "", "", "", "", "",
375 "", "", "X_SD2_CD_B", "", "", "",
376 "", "", "", "SD2_RESET_B", "LVDS1_BL_EN";
377};
378
379&gpio3 {
380 gpio-line-names = "", "", "", "",
381 "", "", "", "", "", "",
382 "", "", "", "", "", "",
383 "", "", "", "", "nCAN1_EN", "nCAN2_EN";
384};
385
386&gpio4 {
387 gpio-line-names = "", "", "", "",
388 "", "", "", "", "", "",
389 "", "", "", "", "", "",
390 "", "", "X_PMIC_IRQ_B", "nRTC_INT", "nENET0_INT_PWDN";
391};
392
393&gpio5 {
394 gpio-line-names = "", "", "", "",
395 "", "", "", "", "", "X_ECSPI1_SSO";
396};
397
398&iomuxc {
399 pinctrl_ecspi1: ecspi1grp {
400 fsl,pins = <
401 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80
402 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80
403 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80
404 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00
405 >;
406 };
407
408 pinctrl_eqos: eqosgrp {
409 fsl,pins = <
410 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
411 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
412 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
413 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
414 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
415 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
416 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
417 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
418 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12
419 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12
420 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12
421 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12
422 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
423 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12
424 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
425 >;
426 };
427
428 pinctrl_fan: fan0grp {
429 fsl,pins = <
430 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16
431 >;
432 };
433
434 pinctrl_flexcan1: flexcan1grp {
435 fsl,pins = <
436 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
437 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
438 >;
439 };
440
441 pinctrl_flexcan2: flexcan2grp {
442 fsl,pins = <
443 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
444 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
445 >;
446 };
447
448 pinctrl_flexcan1_reg: flexcan1reggrp {
449 fsl,pins = <
450 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
451 >;
452 };
453
454 pinctrl_flexcan2_reg: flexcan2reggrp {
455 fsl,pins = <
456 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
457 >;
458 };
459
460 pinctrl_i2c2: i2c2grp {
461 fsl,pins = <
462 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
463 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
464 >;
465 };
466
467 pinctrl_i2c2_gpio: i2c2gpiogrp {
468 fsl,pins = <
469 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
470 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
471 >;
472 };
473
474 pinctrl_lvds1: lvds1grp {
475 fsl,pins = <
476 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
477 >;
478 };
479
480 pinctrl_pcie0: pcie0grp {
481 fsl,pins = <
482 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40
483 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60
484 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */
485 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40
486 >;
487 };
488
489 pinctrl_pwm3: pwm3grp {
490 fsl,pins = <
491 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
492 >;
493 };
494
495 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
496 fsl,pins = <
497 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
498 >;
499 };
500
501 pinctrl_rtc: rtcgrp {
502 fsl,pins = <
503 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
504 >;
505 };
506
507 pinctrl_uart1: uart1grp {
508 fsl,pins = <
509 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
510 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
511 >;
512 };
513
514 pinctrl_usb1_vbus: usb1vbusgrp {
515 fsl,pins = <
516 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
517 >;
518 };
519
520 pinctrl_uart2: uart2grp {
521 fsl,pins = <
522 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
523 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
524 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
525 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
526 >;
527 };
528
529 pinctrl_usdhc2_pins: usdhc2-gpiogrp {
530 fsl,pins = <
531 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40
532 >;
533 };
534
535 pinctrl_usdhc2: usdhc2grp {
536 fsl,pins = <
537 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
538 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
539 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
540 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
541 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
542 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
543 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
544 >;
545 };
546
547 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
548 fsl,pins = <
549 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
550 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
551 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
552 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
553 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
554 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
555 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
556 >;
557 };
558
559 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
560 fsl,pins = <
561 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
562 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
563 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
564 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
565 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
566 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
567 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
568 >;
569 };
570};